ICMIC X84160E-2.5

Preliminary Information
ICmic
TM
This X84160/640/128 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
IC MICROSYSTEMS
MPSTM EEPROM
X84160/640/128
16K/64K/128K
Advanced MPS™ Micro Port Saver EEPROM with Block Lock™ Protection
FEATURES
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the µPort Saver provides all the
serial benefits, such as low cost, low power, low voltage,
and small package size while releasing I/Os for more
important uses.
•Up to 15MHz data transfer rate
•20ns Read Access Time
•Direct Interface to Microprocessors and
Microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
•Low Power CMOS
—1.8V–3.6V, 2.5V–5.5V and 5V ± 10% Versions
—Standby Current Less than 1µA
The µPort Saver memory outputs data within 20ns of an
active read signal. This is less than the read access time
of most hosts and provides “no-wait-state” operation. This
prevents bottlenecks on the bus. With rates to
15MHz, the µPort Saver supplies data faster than
required by most host read cycle specifications. This
eliminates the need for software NOPs.
—Active Current Less than 1mA
•Byte or Page Write Capable
—32-Byte Page Write Mode
•New Programmable Block Lock™ Protection
—Software Write Protection
—Programmable Hardware Write Protection
•Block Lock (0, 1/4, 1/2, or all of the array)
•Typical Nonvolatile Write Cycle Time: 3ms
•High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
•Small Package Options
—8-Lead Mini-DIP Package
—8, 14-Lead SOIC Packages
—8, 20, 28-Lead TSSOP Packages
—8-Lead XBGA Packages
The µPort Saver memories communicate over one line of the
data bus using a sequence of standard bus read and
write operations. This “bit serial” interface allows the
µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
The X84160/640/128 provide additional data security
features through Block Lock and programmable Hardware
Write Protection. These allow some or all of the array to
be write protected by software command or by hardware.
System Configuration, Company ID, calibration information,
or other critical data can be secured against unexpected
or inadvertent program operations, leaving the remainder
of the memory available for the system or user access
A Write Protect (WP) pin prevents inadvertent writes to the
memory.
DESCRIPTION
Xicor EEPROMs are designed and tested for
applications requiring extended endurance. Inherent data
retention is greater than 100 years.
The µPort Saver memories need no serial ports or special
hardware and connect to the processor memory bus.
Replacing bytewide data memory, the µPort Saver uses
BLOCK DIAGRAM
Internal Block Diagram MPS
System Connection
Ports
Saved
µP
µC
A15
WP
DSP
ASIC
RISC
A0
D7
CE
P0/CS
P1/CLK
P2/DI
P3/DO
D0
OE
H.V. GENERATION
TIMING & CONTROL
I/O
COMMAND
DECODE
OE
AND
CONTROL
WE
LOGIC
X
DEC
EEPROM
ARRAY
16K x 8
8K x 8
2K x 8
WE
Y DECODE
DATA REGISTER
© Xicor, Inc. 1998 Patents Pending
7067 1.1 6/10/98 T10/C0/D3
1
Characteristics subject to change without notice
X84160/640/128
PIN CONFIGURATIONS: Drawings are to the same scale, actual package sizes are shown in inches:
WP
V SS
8
V CC
2 X84160
3 X84640
7
6
NC
OE
4
5
WE
.190 in.
NC
VCC
CE
I/O
1
2
3
4
8
7
6
5
X84160
OE
WE
WP
VSS
.114 in.
.252 in.
.230 in.
20-LEAD TSSOP
CE
1
14
V CC
I/O
2
13
NC
NC
3
12
NC
NC
4
11
NC
NC
5
10
WP
V SS
6
NC
OE
9
8
7
.390 in.
1
2
3
4
5
6
7
8
9
10
WE
28-LEAD TSSOP
.238 in.
VCC 1 8 I/O
2 7 CE
3 6 VSS
OE
4 5 WP
NC
NC
CE
CE
CE
I/O
NC
NC
NC
WP
VSS
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X84128
e
8-LEAD XBGA: Top View
NC
X84640
.252 in.
.230 in.
WE
20
19
18
17
16
15
14
13
12
11
. 252 in.
PIN DESCRIPTIONS
Chip Enable (CE)
et
.078 in.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
VCC
NC
NC
NC
NC
OE
WE
NC
.250 in.
NC
NC
NC
NC
VCC
NC
NC .394 in.
NC
NC
OE
WE
NC
NC
NC
P
X84128
NC
NC
CE
I/O
NC
NC
NC
WP
VSS
NC
Data Input/Output
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
WP
Write Protect Input
VCC
Supply Voltage
VSS
Ground
NC
No Connect
PACKAGE
SELECTION GUIDE
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14-LEAD SOIC
I/O
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CE
I/O
PIN NAMES
8-LEAD TSSOP
1
t
8-LEAD PDIP
8-LEAD SOIC
84160
8-Lead PDIP
8-Lead SOIC
8-Lead TSSOP
84640
8-Lead CSP/BGA
8-Lead PDIP
8-Lead SOIC
20-Lead TSSOP
84128
8-Lead CSP/BGA
8-Lead PDIP
14-Lead SOIC
28-Lead TSSOP
Write Protect (WP)
The Write Protect input controls the Hardware Write Protect feature. When WP is LOW and the nonvoltaile bit
WPEN is “1”, nonvolatile writes of the X84160/640/128
control register is disabled, but the part otherwise functions normally. When WP is held HIGH, all functions,
including nonvolatile write operate normally. WP going
LOW while CS is still LOW will interrupt a write to the
X84160/640/128 control register. If the internal Write
cycle has already been initiated, WP going LOW will
have no effect on write.
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The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is deselected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the output buffer and to read data from the device on the I/O line.
The WP pin function is blocked when the WPEN bit in the
control register is “0”. This allows the user to install the
X84160/640/128 in a system with WP pin grounded and
still be able to write to the control register. The WP pin
functions will be enabled when the WPEN bit is set “1”.
O
Write Enable (WE)
The Write Enable input must be LOW to write either data
or command sequences to the device.
Data In/Data Out (I/O)
Data and command sequences are serially written to or
serially read from the device through the I/O pin.
2
X84160/640/128
sequence and enter the low power standby state, otherwise the device will await further reads in the sequential
read mode.
DEVICE OPERATION
The X84160/640/128 are serial EEPROMs designed to
interface directly with most microprocessor buses. Standard CE, OE, and WE signals control the read and write
operations, and a single l/O line is used to send and
receive data and commands serially.
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Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read. The
data stored in the memory at the next address can be
read sequentially by continuing to issue read cycles.
When the highest address in the array is reached, the
address counter rolls over to address 0000h and reading
may be continued indefinitely.
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Data Timing
Data input on the l/O line is latched on the rising edge of
either WE or CE, whichever occurs first. Data output on
the l/O line is active whenever both OE and CE are LOW.
Care should be taken to ensure that WE and OE are
never both LOW while CE is LOW.
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CE
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Figure 1. Read Sequence
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Read Sequence
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and CE
LOW, OE HIGH) to the part without a read cycle between
the write cycles. The address is sent serially, most significant bit first, over the I/O line. Note that this sequence is
fully static, with no special timing restrictions, and the processor is free to perform other tasks on the bus whenever the device CE pin is HIGH. Once the 16 address
bits are sent, a byte of data can be read on the I/O line by
issuing 8 separate read cycles (OE and CE LOW, WE
HIGH). At this point, writing a ‘1’ will terminate the read
Reset Sequence
The reset sequence resets the device and sets an internal write enable latch. A reset sequence can be sent at
any time by performing a read/write “0”/read operation
(see Figs. 1 and 2). This breaks the multiple read or write
cycle sequences that are normally used to read from or
write to the part. The reset sequence can be used at any
time to interrupt or end a sequential read or page load.
As soon as the write “0” cycle is complete, the part is
reset (unless a nonvolatile write cycle is in progress). The
second read cycle in this sequence, and any further read
cycles, will read a HIGH on the l/O pin until a valid read
sequence (which includes the address) is issued. The
reset sequence must be issued at the beginning of both
read and write sequences to be sure the device initiates
these operations properly.
OE
O
WE
I/O (IN)
"0"
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2
I/O (OUT)
A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
RESET
LOAD ADDRESS
WHEN ACCESSING: X84160 ARRAY: A15–A11=0
X84640 ARRAY: A15–A13=0
X84128 ARRAY: A15–A14=0
READ DATA
7008 FRM F04.1
3
X84160/640/128
Figure 2: Write Sequence
t
CE
WE
"0"
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
I/O (OUT)
X84160 ARRAY: A15–A11=0
X84640 ARRAY: A15–A13=0
X84128 ARRAY: A15–A14=0
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WHEN ACCESSING:
LOAD ADDRESS
LOAD DATA
P
RESET
et
Write Sequence
A nonvolatile write sequence consists of sending a reset
sequence, a 16-bit address, up to 32 bytes of data, and
then a special “start nonvolatile write cycle” command
sequence.
D7 D6 D5 D4 D3 D2 D1 D0
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I/O (IN)
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OE
"1"
"0"
START
NONVOLATILE
WRITE
7008 FRM F05.1
page, where data loading can continue. For this reason,
sending more than 256 consecutive data bits will result in
overwriting previous data.
A nonvolatile write cycle will not start if a partial or incomplete write sequence is issued. The internal write enable
latch is reset when the nonvolatile write cycle is completed and after an invalid write to prevent inadvertent
writes. Note that this sequence is fully static, with no special timing restrictions. The processor is free to perform
other tasks on the bus whenever the chip enable pin (CE)
is HIGH.
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ol
The reset sequence is issued first (as described in the
Reset Sequence section) to set an internal write enable
latch. The address is written serially by issuing 16
separate write cycles (WE and CE LOW, OE HIGH) to
the part without any read cycles between the writes. The
address is sent serially, most significant bit first, on the
l/O pin. Up to 32 bytes of data are written by issuing a
multiple of 8 write cycles. Again, no read cycles are
allowed between writes.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be determined
at any time by simply reading the state of the l/O pin on
the device. This pin is read when OE and CE are LOW
and WE is HIGH. During a nonvolatile write cycle the l/O
pin is LOW. When the nonvolatile write cycle is complete,
the l/O pin goes HIGH. A reset sequence can also be
issued during a nonvolatile write cycle with the same
result: I/O is LOW as long as a nonvolatile write cycle is
in progress, and l/O is HIGH when the nonvolatile write
cycle is done.
O
The nonvolatile write cycle is initiated by issuing a special
read/write “1”/read sequence. The first read cycle ends
the page load, then the write “1” followed by a read starts
the nonvolatile write cycle. The device recognizes 32byte pages (e.g., beginning at addresses XXXXXX00000
for X84160).
When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the first address on the
4
X84160/640/128
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register control
the programmable hardware write protect feature.
Hardware write protection is enabled when WP pin is
LOW, and the WPEN bit is “1”. Hardware write protection
is disabled when either the WP pin is HIGH or the WPEN
bit is “0”. When the chip is hardware write protected,
nonvolatile write is disabled to the Control Register,
including the Block Protect bits and the WPEN bit itself,
as well as the block-protected sections in the memory
array. Only the sections of the memory array that are not
block-protected can be written.
CONTROL REGISTER
A read from FFFFh returns the one byte contents of the
control register unused bits return 0. Continued reads
return undefined data. A write to address FFFFh changes
the value of the bits. Unused bits are written as “0”.
Writing more than one byte to the control register is a
violation and the operation will be aborted. After sending
one byte to the control register, a start nonvolatile write
cycle will latch in the new state.
Table 1
5
4
3
2
1
0
WPEN
0
0
0
BP1
BP0
0
0
BP1, BP0: Block Protect Bits
The Block Protect (BP0 and BP1) bits are nonvolatile and
allow the user to select one of four levels of protection.
The X84160/640/128 is divided into four segments. One,
two, or all four of the segments may be protected. That is,
the user may read the segments but will be unable to
alter (write) data within the selected segments. The
partitioning is controlled as illustrated in table 3 below.
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6
When the WP pin is tied to VSS and the WPEN bit is HIGH, the
WPEN bit is write protected. It cannot be changed back to a
“0”, as long as the WP pin is held LOW.
P
7
Note:
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The X84160/640/128 has one register that contains
control bits for the devices. The control bits, WPEN, BP1,
and BP0, are shown in Table 1. To read or change the
contents of this register requires a one byte operation to
address FFFFh.
Protected
Blocks
0
X
Protected
1
LOW
Protected
X
HIGH
Protected
Unprotected
Blocks
Status
Register
et
WP
Writable
Writable
Writable
Protected
Writable
Writable
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WPEN
e
WPEN: Write Protect Enable Bit
The Write-Protect-Enable (WPEN) bit is an enable bit for
the WP pin.
Table 2
Table 3. Block Lock Protection
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Control Register Bits
Array Address Protected
BP0
X84160
X84640
X84128
0
0
None
None
None
0
1
0600h–07FFh
1800h–1FFFh
3000h–3FFFh
upper 1/4
1
0
0400h–07FFh
1000h–1FFFh
2000h–3FFFh
upper 1/2
1
1
0000–07FFh
0000–1FFFh
0000h–3FFFh
Full Array
(Not including the
control register.)
O
BP1
5
Array
X84160/640/128
—A reset sequence must be issued to set the internal
write enable latch before starting a write sequence.
Low Power Operation
The device enters an idle state, which draws minimal current when:
—A special “start nonvolatile write” command sequence
is required to start a nonvolatile write cycle.
—an illegal sequence is entered. The following are the
more common illegal sequences:
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—The internal Write Enable latch is reset automatically
at the end of a nonvolatile write cycle.
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• Read/Write/Write—any time
—The internal Write Enable latch is reset and remains
reset as long as the WP pin is LOW, which blocks all
nonvolatile write cycles.
• Read/Write ‘1’—When writing the address or
writing data.
• Write ‘1’—when reading data
—The internal Write Enable latch resets on an invalid
write operation.
• Read/Read/Write ‘1’—after data is written to
device, but before entering the NV write sequence.
SYMBOL TABLE
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—the device powers-up;
—a nonvolatile write operation completes.
WAVEFORM
P
While a sequential read is in progress, the device
remains in an active state. This state draws more current
than the idle state, but not as much as during a read
itself. To go back to the lowest power condition, an invalid
condition is created by writing a ‘1’ after the last bit of a
read operation.
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Write Protection
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
O
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—The internal Write Enable latch is reset upon
power-up.
6
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
Will change
from LOW to
HIGH
May change
from HIGH to
LOW
Will change
from HIGH to
LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
X84160/640/128
*COMMENT
Temperature under Bias ...................... –65°C to +135°C
Storage Temperature ........................... –65°C to +150°C
Terminal Voltage with
Respect to VSS .......................................–1V to +7V
DC Output Current................................................... 5mA
Lead Temperature (Soldering, 10 seconds)..........300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
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ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED OPERATING CONDITIONS
Min.
Max.
Supply Voltage
Limits
Commercial
0°C
+70°C
X84160/640/128
4.5V to 5.5V
Industrial
–40°C
+85°C
X84160/640/128 – 2.5
2.5V to 5.5V
+125°C
X84160/640/128 – 1.8
1.8V to 3.6V
Military†
–55°C
Notes: † Contact factory for Military availability
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Temperature
D.C. OPERATING CHARACTERISTICS (VCC = 5V ±10%)
(Over the recommended operating conditions, unless otherwise specified.)
Symbol
Parameter
Min.
P
Limits
Max.
Units
Test Conditions
1
mA
OE = VIL, WE = VIH, I/O = Open,
CE clocking = VCC x 0.1/VCC x 0.9
@ 10 MHz
2
mA
ICC During Nonvolatile Write Cycle
All Inputs at CMOS Levels
VCC Supply Current (Read)
ICC2
VCC Supply Current (Write)
ISB1
VCC Standby Current
1
µA
CE = VCC, Other Inputs = VCC or VSS
ILI
Input Leakage Current
10
µA
VIN = VSS to VCC
ILO
Output Leakage Current
10
µA
VOUT = VSS to VCC
VlL (1)
Input LOW Voltage
–0.5
VCC x 0.3
V
VIH (1)
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output LOW Voltage
0.4
V
IOL = 2.1mA
V
IOH = –1mA
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bs
VOH
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ICC1
Output HIGH Voltage
VCC – 0.8
O
Notes: (1) VIL Min. and VIH Max. are for reference only and are not tested.
7
X84160/640/128
D.C. OPERATING CHARACTERISTICS (VCC = 2.5V to 5.5V)
(Over the recommended operating conditions, unless otherwise specified.)
Parameter
Limits
Min.
Max.
Units
Test Conditions
OE = VIL, WE = VIH, I/O = Open,
CE clocking = VCC x 0.1/VCC x 0.9 @
VCC = 2.5, 5 MHz
t
Symbol
VCC Supply Current (Read)
300
µA
ICC2
VCC Supply Current (Write)
2
mA
ISB1
VCC Standby Current
1
µA
ILI
Input Leakage Current
10
µA
ILO
Output Leakage Current
10
µA
VlL(1)
Input LOW Voltage
–0.5
VCC x 0.3
V
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
0.4
V
IOL = 1mA, VCC = 3V
V
IOH = –400µA, VCC = 3V
Output LOW Voltage
VOH
Output HIGH Voltage
VCC – 0.4
ICC During Nonvolatile Write Cycle
All Inputs at CMOS Levels
CE = VCC, Other Inputs = VCC or VSS
VIN = VSS to VCC
VOUT = VSS to VCC
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VOL
P
VIH
(1)
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ICC1
Parameter
Limits
et
Symbol
e
D.C. OPERATING CHARACTERISTICS (VCC = 1.8V to 3.6V)
(Over the recommended operating conditions, unless otherwise specified.)
Min.
Units
Test Conditions
200
µA
OE = VIL, WE = VIH, I/O = Open,
CE clocking = VCC x 0.1/VCC x 0.9 @
VCC = 1.8V, 4 MHz
Max.
VCC Supply Current (Read)
ICC2
VCC Supply Current (Write)
1
mA
ICC During Nonvolatile Write Cycle
All Inputs at CMOS Levels
ISB1
VCC Standby Current
1
µA
CE = VCC, Other Inputs = VCC or VSS
ILI
Input Leakage Current
10
µA
VIN = VSS to VCC
Output Leakage Current
10
µA
VOUT = VSS to VCC
bs
ILO
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ICC1
VlL(1)
–0.5
VCC x 0.3
V
VIH(1)
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output LOW Voltage
0.4
V
IOL = 0.5mA, VCC = 2V
VOH
Output HIGH Voltage
V
IOH = –250µA, VCC = 2V
O
Input LOW Voltage
VCC – 0.2
Notes: (1) VIL Min. and VIH Max. are for reference only and are not tested.
8
X84160/640/128
CAPACITANCE
TA = +25°C, f = 1MHz, VCC = 5V
CI/O
Parameter
(2)
CIN(2)
Max.
Units
Test Conditions
Input/Output Capacitance
8
pF
VI/O = 0V
Input Capacitance
6
pF
VIN = 0V
t
Symbol
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Notes: (2) Periodically sampled, but not 100% tested.
POWER-UP TIMING
Symbol
Parameter
(3)
Power-up to Read Operation
tPUW(3)
Power-up to Write Operation
tPUR
Max.
Units
2
ms
5
ms
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Notes: (3) Time delays required from the time the VCC is stable until the specific operation can be initiated.
Periodically sampled, but not 100% tested.
A.C. CONDITIONS OF TEST
VCC x 0.1 to VCC x 0.9
P
Input Pulse Levels
Input Rise and Fall Times
5ns
VCC x 0.5
e
Input and Output Timing Levels
et
EQUIVALENT A.C. LOAD CIRCUITS
5V
OUTPUT
OUTPUT
OUTPUT
30pF
4.58KΩ
30pF
O
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3.03KΩ
2.8K Ω
2.39KΩ
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2.06KΩ
2V
3V
9
5.6K Ω
30pF
X84160/640/128
A.C. CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits – X84160/640/128
Min.
Max
Min.
tRC
Read Cycle Time
tCE
CE Access Time
20
tOE
OE Access Time
20
tOEL
OE Pulse Width
20
35
tOEH
OE High Recovery Time
50
90
tLOW
CE LOW Time
20
35
tHIGH
CE HIGH Time
50
tLZ(4)
CE LOW to Output In Low Z
0
tHZ(4)
CE HIGH to Output In High Z
0
15
tOLZ(4)
OE LOW to Output In Low Z
0
tOHZ(4)
OE HIGH to Output In High Z
0
tOH
Output Hold from CE or OE HIGH
0
tWES
WE HIGH Setup Time
tWEH
WE HIGH Hold Time
125
Min.
250
Max.
Units
ns
25
70
ns
25
70
ns
70
ns
180
ns
70
ns
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70
Max.
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Parameter
P
Symbol
t
VCC = 4.5V – 5.5V VCC = 2.5V – 5.5V VCC = 1.8V – 3.6V
90
180
ns
0
0
ns
0
0
0
15
25
0
25
0
0
30
ns
ns
30
ns
0
ns
25
25
25
ns
25
25
25
ns
et
e
0
ol
Notes: (4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes HIGH (whichever occurs
first) to the time when I/O is no longer being driven into a 5pF load.
tRC
tLOW
tHIGH
tCE
bs
CE
WE
tWES
t OEL
tOE
O
OE
t OEH
tWEH
t OHZ
I/O
DATA
t OLZ
t LZ
10
HIGH Z
tOH
t HZ
X84160/640/128
Write Cycle Limits – X84160/640/128
VCC = 4.5V – 5.5V VCC = 2.5V – 5.5V VCC = 1.8V – 3.6V
Parameter
tNVWC(5)
Nonvolatile Write Cycle Time
tWC
Write Cycle Time
70
125
tWP
WE Pulse Width
20
35
tWPH
WE HIGH Recovery Time
50
90
tCS
Write Setup Time
0
0
tCH
Write Hold Time
0
0
tCP
CE Pulse Width
20
35
tCPH
CE HIGH Recovery Time
50
90
tOES
OE HIGH Setup Time
25
tOEH
OE HIGH Hold Time
25
tDS(6)
Data Setup Time
12
Data Hold Time
5
tWPSU
WP HIGH Setup
100
tWPHD(7)
WP HIGH Hold
100
Min.
Max.
Min.
5
250
Max.
Units
5
ms
du
c
5
ns
ns
180
ns
0
ns
0
ns
70
ns
180
ns
25
50
ns
25
50
ns
20
30
ns
5
5
ns
100
150
ns
100
150
ns
ro
50
P
(7)
Max.
e
tDH(6)
Min.
t
Symbol
O
bs
ol
et
Notes: (5) tNVWC is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the “start nonvolatile write cycle”
sequence until the self-timed, internal nonvolatile write cycle is completed.
(6) Data is latched into the X84160/640/128 on the rising edge of CE or WE, whichever occurs first.
(7) Periodically sampled, but not 100% tested.
11
X84160/640/128
CE Controlled Write Cycle
tCPH
tCP
tOEH
OE
tCS
tCH
WE
tWP
tWPH
tWPSU
tWPHD
tDS
I/O
ro
WP
du
c
tOES
t
CE
tDH
DATA
HIGH Z
P
tWC
e
WE Controlled Write Cycle
tCPH
CE
et
tCP
tOES
ol
OE
bs
WE
WP
tCH
tOEH
tWPH
tWP
t WPHD
tWPSU
tDS
t DH
DATA
O
I/O
t CS
HIGH Z
tWC
12
X84160/640/128
1200±30
VSS
WE
WP
3912±30
NC
P
CE
3912±30
ro
280±20
VCC
OE
e
1000±30
500±20
I/O
du
c
140±20
X84640Z: Bottom View
t
8-LEAD XBGA TYPE
1982±30
140±20
NOTE: ALL DIMENSIONS IN µM
ALL DIMENSIONS ARE TYPICAL VALUES
O
bs
ol
430±20
et
1982±30
13
X84160/640/128
ro
VCC
280±20
P
e
O
430±30
bs
ol
1500±30
et
VSS
WE
6046±30
NC
CE
6046±30
500±20
1200±30
I/O
du
c
140±20
X84128: Bottom View
t
8-LEAD XBGA TYPE
OE
WP
1982±30
1982±30
140±20
NOTE: ALL DIMENSIONS IN µM
ALL DIMENSIONS ARE TYPICAL VALUES
14
X84160/640/128
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
du
c
t
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
ro
PIN 1
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
e
SEATING
PLANE
P
0.300
(7.62) REF.
et
0.150 (3.81)
0.125 (3.18)
ol
bs
O
0.145 (3.68)
0.128 (3.25)
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.020 (0.51)
0.016 (0.41)
0.110 (2.79)
0.090 (2.29)
.073 (1.84)
MAX.
0.060 (1.52)
0.020 (0.51)
0.325 (8.25)
0.300 (7.62)
0°
15°
TYP .0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
15
X84160/640/128
du
c
t
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
PIN 1 INDEX
0.014 (0.35)
0.019 (0.49)
P
0.188 (4.78)
0.197 (5.00)
et
e
(4X) 7°
0.050 (1.27)
ro
PIN 1
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050" TYPICAL
0.050"
TYPICAL
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
O
bs
ol
0.010 (0.25)
0.020 (0.50) X 45°
0° – 8°
0.228 (5.80)
0.244 (6.20)
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
16
0.030"
TYPICAL
8 PLACES
X84160/640/128
PACKAGING INFORMATION
du
c
t
14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
ro
PIN 1
P
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
et
e
(4X) 7°
0.004 (0.10)
0.010 (0.25)
ol
0.050 (1.27)
0.053 (1.35)
0.069 (1.75)
0.050" Typical
bs
0.010 (0.25)
X 45°
0.020 (0.50)
0.050" T ypical
O
0° – 8°
0.250"
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
FOO TPRINT
0.030" Typical
14 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
17
X84160/640/128
PACKAGING INFORMATION
t
8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
du
c
.025 (.65) BSC
P
.114 (2.9)
.122 (3.1)
ro
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
e
.047 (1.20)
.0075 (.19)
.0118 (.30)
ol
et
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
O
bs
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
18
X84160/640/128
PACKAGING INFORMATION
t
20-LEAD PLASTIC, TSSOP P ACKAGE TYPE V
du
c
.025 (.65) BSC
ro
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
P
.252 (6.4)
.300 (6.6)
e
.047 (1.20)
.002 (.05)
.006 (.15)
ol
et
.0075 (.19)
.0118 (.30)
.010 (.25)
Gage Plane
O
bs
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
19
X84160/640/128
PACKAGING INFORMATION
t
28-LEAD PLASTIC, TSSOP P ACKAGE TYPE V
du
c
.025 (.65) BSC
P
.394 (10.0)
ro
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
e
.047 (1.20)
.002 (.05)
.006 (.15)
et
.0075 (.19)
.0118 (.30)
.010 (.25)
Gage Plane
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
O
bs
ol
0° – 8°
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
20
X84160/640/128
ORDERING INFORMATION
X84160/640/128 P
T
G –V
Device
VCC Range
Blank = 4.5V to 5.5V, 10 MHz
2.5 = 2.5V to 5.5V, 5 MHz
1.8 = 1.8V to 3.6V, 4 MHz
G = RoHS Compliant Lead Free package
Blank = Standard package. Non lead free
Temperature Range
Blank = Commercial = 0°C to +70°C
E = Extended = –20°C to +85°C
I = Industrial = –40°C to +85°C
Military = –55°C to +125°C (contact factory)
Packages:
X84160
P = 8-Lead PDIP
S8 = 8-Lead SOIC
*PART MARK CONVENTION
8-Lead TSSOP
EYWW
8160XXG
G = RoHS compliant
lead free
AG = 1.8 to 3.6V, 0 to +70°C
AH = 1.8 to 3.6V, -40 to +85°C
F = 2.5 to 5.5V, 0 to +70°C
G = 2.5 to 5.5V, -40 to +85°C
Blank = 4.5 to 5.5V, 0 to +70°C
I = 4.5 to 5.5V, -40 to +85°C
8-Lead XBGA PACKAGE
Complete Part Number
X84640ZE-2.5
X84640ZI-2.5
X84128ZE-2.5
X84128 ZI-2.5
V8 = 8-Lead TSSOP
8-Lead SOIC/PDIP
Blank = 8-Lead SOIC
P = 8-Lead PDIP
G = RoHS compliant lead free
AG = 1.8 to 3.6V, 0 to +70°C
AH = 1.8 to 3.6V, -40 to +85°C
F = 2.5 to 5.5V, 0 to +70°C
G = 2.5 to 5.5V, -40 to +85°C
X84160G
XXX
Blank = 4.5 to 5.5V, 0 to +70°C
I = 4.5 to 5.5V, -40 to +85°C
Top Mark
XAP
XAR
XAN
XAO
*All parts and package types not included will receive standard marking.
21
X84640
P = 8-Lead PDIP
S8 = 8-Lead SOIC
V20 = 20-Lead TSSOP
Z = 8-Lead XBGA
X84128
P = 8-Lead PDIP
S14 = 14-Lead SOIC
V28 = 28-Lead TSSOP
Z = 8-Lead XBGA
X84160/640/128
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from
patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production
and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses
are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign
patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.
22