ICMIC X25160G

ICmic
TM
This X25160 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
IC MICROSYSTEMS
X25160
16K
2K x 8 Bit
2
SPI Serial E PROM With Block LockTM Protection
FEATURES
DESCRIPTION
•2MHz Clock Rate
•SPI Modes (0,0 & 1,1)
•2K X 8 Bits
The X25160 is a CMOS 16384-bit serial E PROM,
internally organized as 2K x 8. The X25160 features a
2
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
— 32 Byte Page Mode
•Low Power CMOS
signals are a clock input (SCK) plus separate data in (SI) and
data out (SO) lines. Access to the device is con-
— <1µA Standby Current
— <5mA Active Current
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
•2.7V To 5.5V Power Supply
•Block Lock Protection
2
— Protect 1/4, 1/2 or all of E PROM Array
•Built-in Inadvertent Write Protection
The X25160 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25160 will ignore transitions on its
inputs, thus allowing the host to service higher priority
— Power-Up/Power-Down protection circuitry
— Write Enable Latch
interrupts. The WP input can be used as a hardwire input to
the X25160 disabling all write attempts to the status
— Write Protect Pin
•Self-Timed Write Cycle
register, thus providing a mechanism for limiting end user
capability of altering 0, 1/4, 1/2 or all of the memory.
— 5ms Write Cycle Time (Typical)
•High Reliability
— Endurance: 100,000 cycles
— Data Retention: 100 Years
The X25160 utilizes Xicor’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
— ESD protection: 2000V on all pins
•8-Lead PDlP Package
•8-Lead SOIC Package
•14-Lead TSSOP Package
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
2K BYTE
ARRAY
16
16 X 256
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
16
16 X 256
32
32 X 256
WP
WRITE
CONTROL
AND
TIMING
LOGIC
32
8
Y DECODE
DATA REGISTER
3064 ILL F01
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3064-3.9 6/11/96 T4/C1/D0 NS
1
Characteristics subject to change without notice
X25160
PIN DESCRIPTIONS
Hold (HOLD)
Serial Output (SO)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence
is underway, HOLD may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
PIN CONFIGURATION
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
DIP/SOIC
Chip Select (CS)
CS
1
8
VCC
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
When CS is HIGH, the X25160 is deselected and the SO
output pin is at high impedance and unless an internal
write operation is underway, the X25160 will be in the
standby power mode. CS LOW enables the X25160,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
X25160
TSSOP
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25160 status register are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25160 status
register. If the internal write cycle has already been
initiated, WP going LOW will have no effect on a write.
CS
1
14
VCC
SO
2
13
HOLD
NC
3
12
NC
NC
4
X25160 11
NC
NC
5
10
NC
WP
6
9
SCK
VSS
7
8
SI
3064 ILL F02.2
PIN NAMES
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install the
X25160 in a system with WP pin grounded and still be
able to write to the status register. The WP pin functions
will be enabled when the WPEN bit is set “1”.
SYMBOL
DESCRIPTION
CS
SO
SI
SCK
WP
VSS
VCC
HOLD
NC
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
3064 PGM T01
2
X25160
PRINCIPLES OF OPERATION
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is formatted as follows:
E2PROM
The X25160 is a 2K x 8
designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25160 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and WP
inputs must be HIGH during the entire operation. The
WP input is “Don’t Care” if WPEN is set “0”.
7
6
WPEN X
5
X
4
X
3
BP1
2
BP0
1
WEL
0
WIP
3064 PGM T02
WPEN, BP0 and BP1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are transferred MSB first.
The Write-In-Process (WIP) bit indicates whether the
X25160 is busy with a write operation. When set to a “1”,
a write is in progress, when set to a “0”, no write is in
progress. During a write, all other bits are set to “1”.
Data input is sampled on the first rising edge of SCK after
CS goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
user can assert the HOLD input to place the X25160 into
a “PAUSE” condition. After releasing HOLD, the X25160
will resume operation from the point when HOLD was
first asserted.
The Write Enable Latch (WEL) bit indicates the status of
the “write enable” latch. When set to a “1”, the latch is set,
when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protection. The X25160 is divided into four 4096-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unable to alter (write) data within the selected segments.
The partitioning is controlled as illustrated below.
Write Enable Latch
The X25160 contains a “write enable” latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte, page, or status register write
cycle.
Status Register Bits
BP1
BP0
0
0
1
1
0
1
0
1
Array Addresses
Protected
None
$0600–$07FF
$0400–$07FF
$0000–$07FF
3064 PGM T03
Table 1. Instruction Set
Instruction Name
WREN
WRDI
RDSR
WRSR
Instruction Format*
0000 0110
0000 0100
0000 0101
0000 0001
READ
0000 0011
WRITE
0000 0010
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
Write Status Register
Read Data from Memory Array beginning at selected
address
Write Data to Memory Array beginning at Selected Address
(1 to 32 Bytes)
3064 PGM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25160
To read the status register the CS line is first pulled LOW
to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the
status register are shifted out on the SO line. The read
status register sequence is illustrated in Figure 2.
Write-Protect Enable
The Write-Protect-Enable (WPEN) is available for the
X25160 as a nonvolatile enable bit for the WP pin.
WPEN WP WEL
0
0
1
1
X
X
X
X
LOW
LOW
HIGH
HIGH
0
1
0
1
0
1
Protected Unprotected Status
Blocks
Blocks
Register
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Write Sequence
Protected
Writable
Protected
Protected
Protected
Writable
Prior to any attempt to write data into the X25160, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the X25160.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.
3064 PGM T05.1
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register control
the programmable hardware write protect feature. Hardware write protection is enabled when WP pin is LOW,
and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is HIGH or the WPEN
bit is “0”. When the chip is hardware write protected,
nonvolatile writes are disabled to the Status Register,
including the Block Protect bits and the WPEN bit itself,
as well as the block-protected sections in the memory
array. Only the sections of the memory array that are not
block-protected can be written.
Note:
To write data to the E2PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go LOW and remain
LOW for the duration of the operation. The host may
continue to write up to 32 bytes of data to the X25160.
The only restriction is the 32 bytes must reside on the
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written.
Since the WPEN bit is write protected, it
cannot be changed back to a “0”, as long as
the WP pin is held LOW.
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
data byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
Clock and Data Timing
Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.
Read Sequence
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5 and
6 must be “0”. This sequence is shown in Figure 6.
When reading from the
memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25160, followed by the
16-bit address of which the last 11 are used. After the
READ opcode and address are sent, the data stored in
the memory at the selected address is shifted out on the
SO line. The data stored in memory at the next address
can be read sequentially by continuing to provide clock
pulses. The address is automatically incremented to the
next higher address after each byte of data is shifted out.
When the highest address is reached ($07FF) the
address counter rolls over to address $0000 allowing
the read cycle to be continued indefinitely. The read
operation is terminated by taking CS HIGH. Refer to the
read E2PROM array operation sequence illustrated in
Figure 1.
E2PROM
While the write is in progress following a status register or
E2PROM write sequence, the status register may be read to
check the WIP bit. During this time the WIP bit will be HIGH.
Hold Operation
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can be
resumed. The only restriction is the SCK input must be
LOW when HOLD is first pulled LOW and SCK must also
be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to VCC
or tied to VCC through a resistor.
4
X25160
Operational Notes
Data Protection
The X25160 powers-up in the following state:
The following circuitry has been included to prevent
inadvertent writes:
• The device is in the low power standby state.
• The “write enable” latch is reset upon power-up.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• A WREN instruction must be issued to set the “write
enable” latch.
• SO pin is high impedance.
• CS must come HIGH at the proper clock count in
order to start a write cycle.
• The “write enable” latch is reset.
Figure 1. Read E2PROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
INSTRUCTION
16 BIT ADDRESS
15 14 13
SI
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
SO
6
5
4
MSB
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14
7
6
5
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
SO
MSB
5
4
3
2
2
1
0
3064 ILL F03
Figure 2. Read Status Register Operation Sequence
0
3
1
0
3064 ILL F04
X25160
Figure 3. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
SO
3064 ILL F05
Figure 4. Byte Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30 31
10
SCK
INSTRUCTION
DATA BYTE
16 BIT ADDRESS
15 14 13
SI
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3064 ILL F06
6
X25160
Figure 5. Page Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30 31
10
SCK
INSTRUCTION
DATA BYTE 1
16 BIT ADDRESS
15 14 13
SI
3
2
1
7
0
6
5
4
3
2
1
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
DATA BYTE 2
SI
7
6
5
4
3
DATA BYTE 3
2
1
0
7
6
5
4
3
DATA BYTE N
2
1
0
6
5
4
3
2
1
0
3064 ILL F07
Figure 6. Write Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
DATA BYTE
INSTRUCTION
7
SI
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3064 ILL F08
7
0
X25160
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with Respect to VSS ......... –1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Military
Min.
0°C
–40°C
–55°C
Supply Voltage
X25160
X25160-2.7
Max.
+70°C
+85°C
+125°C
Limits
5V ±10%
2.7V to 5.5V
3064 PGM T07.1
3064 PGM T06.1
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
5
mA
ICC
VCC Supply Current (Active)
ISB
ILI
ILO
VIL(1)
VIH(1)
VOL1
VOH1
VOL2
VOH2
VCC Supply Current (Standby)
1
Input Leakage Current
10
Output Leakage Current
10
Input LOW Voltage
–1
VCC x 0.3
Input HIGH Voltage
VCC x 0.7 VCC + 0.5
Output LOW Voltage
0.4
Output HIGH Voltage
VCC – 0.8
Output LOW Voltage
0.4
Output HIGH Voltage
VCC – 0.3
Test Conditions
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open, CS = VSS
CS = VCC, VIN = VSS or VCC
VIN = VSS to VCC
VOUT = VSS to VCC
µA
µA
µA
V
V
V
V
V
V
VCC = 5V, IOL = 3mA
VCC = 5V, IOH = -1.6mA
VCC = 3V, IOL = 1.5mA
VCC = 3V, IOH = -0.4mA
3064 PGM T08.3
POWER-UP TIMING
Symbol
tPUR(3)
Parameter
Power-up to Read Operation
tPUW(3)
Power-up to Write Operation
Min.
Max.
1
Units
ms
5
ms
3064 PGM T09
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.
Symbol
COUT(2)
CIN(2)
Notes:
Test
Output Capacitance (SO)
Input Capacitance (SCK, SI, CS, WP, HOLD)
Max.
8
6
Units
pF
pF
Conditions
VOUT = 0V
VIN = 0V
3064 PGM T10.1
(1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
8
X25160
EQUIVALENT A.C. LOAD CIRCUIT
5V
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing Level
VCC x 0.5
3V
1.44KΩ
1.64KΩ
OUTPUT
1.95KΩ
A.C. TEST CONDITIONS
3064 PGM T11
OUTPUT
100pF
4.63KΩ
100pF
3064 ILL F09.1
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
fSCK
tCYC
tLEAD
tLAG
tWH
tWL
tSU
tH
tRI(4)
tFI(4)
tHD
tCD
tCS
tWC(5)
Parameter
Clock Frequency
Cycle Time
CS Lead Time
CS Lag Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Data In Rise Time
Data In Fall Time
HOLD Setup Time
HOLD Hold Time
CS Deselect Time
Write Cycle Time
Min.
0
500
250
250
200
200
50
50
Max.
2
2
2
100
100
2.0
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
ms
3064 PGM T12.2
Data Output Timing
Symbol
fSCK
tDIS
tV
tHO
tRO(4)
tFO(4)
tLZ(4)
tHZ(4)
Parameter
Clock Frequency
Output Disable Time
Output Valid from Clock LOW
Output Hold Time
Output Rise Time
Output Fall Time
HOLD HIGH to Output in Low Z
HOLD LOW to Output in High Z
Min.
Max.
Units
0
2
250
200
MHz
ns
ns
ns
ns
ns
ns
ns
0
100
100
100
100
3064 PGM T13.2
2Notes: (4) This parameter is periodically sampled and not 100% tested.
(5) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
nonvolatile write cycle.
9
X25160
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
SO
SI
tHO
MSB OUT
tWL
tDIS
MSB–1 OUT
LSB OUT
ADDR
LSB IN
3064 ILL F10.1
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
SI
tH
tRI
MSB IN
tFI
LSB IN
HIGH IMPEDANCE
SO
3064 ILL F11
10
X25160
Hold Timing
CS
tHD
tCD
tCD
tHD
SCK
tHZ
tLZ
SO
SI
HOLD
3064 ILL F12.1
SYMBOL TABLE
WAVEFORM
11
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
X25160
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.150 (3.81)
0.125 (3.18)
0.020 (0.51)
0.016 (0.41)
0.110 (2.79)
0.090 (2.29)
0.015 (0.38)
MAX.
0.060 (1.52)
0.020 (0.51)
0.325 (8.25)
0.300 (7.62)
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
12
X25160
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050" TYPICAL
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
13
X25160
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F32
14
X25160
ORDERING INFORMATION
X25160
P
T
G
-V
VCC Limits
Blank = 5V ±10%
2.7 = 2.7V to 5.5V
Device
G = RoHS Compliant Lead Free package
Blank = Standard package. Non lead free
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
V = 14-Lead TSSOP
Part Mark Convention
X25160
XG
G = RoHS compliant lead-free
X
Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP
V = 14-Lead TSSOP
Blank = 5V ±10%, 0°C to +70°C
I = 5V ±10%, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no
warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without
notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402;
4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents
pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to
the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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