X9261 ® Single Supply/Low Power/256-Tap/SPI Bus Data Sheet October 12, 2006 FN8171.4 DESCRIPTION Dual Digitally-Controlled (XDCP™) Potentiometers The X9261 integrates 2 digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. FEATURES • Dual–Two Separate Potentiometers • 256 Resistor Taps/pot–0.4% Resolution • SPI Serial Interface for Write, Read, and Transfer Operations of the Potentiometer Single Supply Device • Wiper Resistance, 100Ω typical @ VCC = 5V • 4 Nonvolatile Data Registers for Each Potentiometer • Nonvolatile Storage of Multiple Wiper Positions • Power-on Recall Loads Saved Wiper Position on Power-up. • Standby Current < 5µA Max • 50kΩ, 100kΩ Versions of End to End Resistance • 100 yr. Data Retention • Endurance: 100,000 Data Changes per Bit per Register • 24 Ld SOIC, 24 Ld TSSOP • Low Power CMOS • Power Supply VCC = 5V ±10% • Pb-Free Plus Anneal Available (RoHS Compliant) The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default Data Register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM VCC SPI Bus Interface Address Data Status Write Read Transfer Inc/Dec Bus Interface and Control Power-on Recall Wiper Counter Register (WCR) Control VSS RH1 RH0 Data Registers (DR0-DR3) RW0 RL0 RW1 RL1 50kΩ or 100kΩ versions 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9261 Ordering Information PART NUMBER PART MARKING X9261US24 X9261US X9261US24Z (Note) VCC LIMITS (V) RTOTAL (kΩ) TEMP RANGE (°C) 5 ±10% 50 PACKAGE PKG. DWG. # 0 to 70 24 Ld SOIC (300 mil) M24.3 X9261US Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9261UV24 X9261UV 0 to 70 24 Ld TSSOP (4.4mm) MDP0044 X9261UV24Z (Note) X9261UV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. DETAILED FUNCTIONAL DIAGRAM RH0 RL0 RW0 VCC Power-on Recall R0 R1 HOLD CS SCK SO SI A0 A1 INTERFACE AND CONTROL CIRCUITRY R2 R3 Wiper Counter Register (WCR) 50kΩ and 100kΩ 256-taps 8 Data WP Power-on Recall R0 R1 R2 R3 VSS Pot 0 Wiper Counter Register (WCR) Resistor Array Pot 1 RL1 RH1 RW1 CIRCUIT LEVEL APPLICATIONS • Vary the frequency and duty cycle of timer ICs • Vary the gain of a voltage amplifier • Vary the dc biasing of a pin diode attenuator in RF circuits • Provide programmable dc reference voltages for comparators and detectors • Control the volume in audio circuits • Provide a control variable (I, V, or R) in feedback circuits • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, characteristic frequency and Q-factor in filter circuits • Set the scale factor and zero point in sensor signal conditioning circuits 2 FN8171.4 October 12, 2006 X9261 PIN ASSIGNMENTS SYSTEM LEVEL APPLICATIONS • Adjust the contrast in LCD displays • Control the power level of LED transmitters in communication systems • Set and regulate the DC biasing point in an RF power amplifier in wireless systems • Control the gain in audio and home entertainment systems • Provide the variable DC bias for tuners in RF wireless systems Pin (SOIC/ TSSOP) Symbol 1 SO Function Serial Data Output for SPI bus 2 A0 Device Address for SPI bus. 3 NC No Connect. 4 NC No Connect. 5 NC No Connect. 6 NC No Connect. • Set the operating points in temperature control systems 7 VCC System Supply Voltage 8 RL0 Low Terminal for Potentiometer 0. • Control the operating point for sensors in industrial systems 9 RH0 High Terminal for Potentiometer 0. 10 RW0 Wiper Terminal for Potentiometer 0. • Trim offset and gain errors in artificial intelligent systems 11 CS Device Address for SPI bus. 12 WP Hardware Write Protect 13 SI Serial Data Input for SPI bus PIN CONFIGURATION 14 A1 Device Address for SPI bus. 15 RL1 Low Terminal for Potentiometer 1. 16 RH1 High Terminal for Potentiometer 1. HOLD 17 RW1 Wiper Terminal for Potentiometer 1. VSS System Ground SOIC/TSSOP SO A0 NC 1 24 2 23 SCK 18 3 22 NC 19 NC No Connect NC No Connect NC 4 21 NC 20 NC 5 20 NC 21 NC No Connect 19 NC 22 NC No Connect NC 6 VCC 7 18 VSS 23 SCK RL0 8 17 RW1 24 HOLD RH0 9 16 RH1 RW0 10 15 RL1 CS 11 14 A1 WP 12 13 SI X9261 Serial Clock for SPI bus Device select. Pause the SPI serial bus. PIN DESCRIPTIONS Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9261. 3 FN8171.4 October 12, 2006 X9261 HOLD (HOLD) Other Pins HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A1 - A0) The address inputs are used to set the 4-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9261. CHIP SELECT (CS) When CS is HIGH, the X9261 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9261, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of RH and RL such that RH0 and RL0 are the terminals of POT 0 and so on. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of RW such that RW0 is the terminals of POT 0 and so on. Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. 4 NO CONNECT No connect pins should be left floating. This pins are used for Intersil manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. PRINCIPLES OF OPERATION Serial Interface The X9261 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9261 is comprised of a resistor array (See Figure 1). The array contains the equivalent of 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (See Table 1). Power-up and Down Requirements. There are no restrictions on the power-up or powerdown conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC, VH, VL, VW. The VCC ramp rate specification is always in effect. FN8171.4 October 12, 2006 X9261 Figure 1. Detailed Potentiometer Block Diagram One of Two Potentiometers SERIAL BUS INPUT SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 1 (DR1) REGISTER 0 (DR0) 8 REGISTER 2 (DR2) 8 PARALLEL BUS INPUT REGISTER 3 (DR3) WIPER COUNTER REGISTER (WCR) RH C O U N T E R D E C O D E INC/DEC LOGIC IF WCR = 00[H] THEN RW = RL IF WCR = FF[H] THEN RW = RH UP/DN MODIFIED SCK UP/DN CLK RL RW DEVICE DESCRIPTION Wiper Counter Register (WCR) The X9261 contains two Wiper Counter Registers, one for each DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (See Instruction section for more details). Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9261 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR. 5 Data Registers (DR) Each potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bits [7:0] are used to store one of the 256 wiper positions or data (0~255). Status Register (SR) This 1-bit Status Register is used to store the system status. WIP: Write In Progress status bit, read only. – When WIP=1, indicates that high-voltage write cycle is in progress. – When WIP=0, indicates that no high-voltage write cycle is in progress. FN8171.4 October 12, 2006 X9261 Table 1. Wiper Counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V). WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 V V V V V V V V (MSB) (LSB) Table 2. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NV NV NV NV NV NV NV NV MSB LSB DEVICE DESCRIPTION Instructions IDENTIFICATION BYTE ( ID AND A ) The first byte sent to the X9261 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device id for the X9261; this is fixed as 0101[B] (refer to Table 3). The AD[3:0] bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A3 - A0 input pins. The slave address is externally specified by the user. The X9261 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9261 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3-A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE ( I[3:0] ) The next byte sent to the X9261 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[3:0]). The RB and RA bits point to one of the four Data Registers of each associated XDCP. The least significant bit points to one of two Wiper Counter Registers or Pots.The format is shown below in Table 4. Table 3. Identification Byte Format Device Type Identifier Slave Address ID3 ID2 ID1 ID0 0 1 0 1 A3 A2 A1 (MSB) A0 (LSB) Table 4. Instruction Byte Format Data Register Selection Instruction Opcode I3 I2 I1 (MSB) I0 RB Pot Selection (WCR Selection) RA 0 P0 (LSB) 6 FN8171.4 October 12, 2006 X9261 Register Selection Register Selected RB RA DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1 DEVICE DESCRIPTION Instructions Four of the ten instructions are three bytes in length. These instructions are: – Read Wiper Counter Register – read the current wiper position of the selected potentiometer, – Write Wiper Counter Register – change current wiper position of the selected potentiometer, – Read Data Register – read the contents of the selected Data Register; – Write Data Register – write a new value to the selected Data Register. – Read Status - This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the three byte instructions is illustrated in Figure 3. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (See Figure 5). – XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. – Global XFR Data Register to Wiper Counter Register – This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. – Global XFR Wiper Counter Register to Data Register – This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (See Figures 6 and 7). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9261 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the RL terminal. A detailed illustration of the sequence and timing for this operation are shown. See Instruction format for more details. Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9261; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: 7 FN8171.4 October 12, 2006 X9261 Figure 2. Two-Byte Instruction Sequence CS SCK SI 1 0 0 ID3 ID2 ID1 ID0 0 0 0 1 0 0 A1 A0 Internal Address Device ID I3 I2 RB RA I0 I1 Instruction Opcode P0 Register Pot/WCR Address Address Figure 3. Three-Byte Instruction Sequence (Write) CS SCL SI 0 1 0 1 ID3 ID2 ID1 ID0 0 0 0 0 0 A1 A0 I3 I2 I0 Instruction Opcode Internal Address Device ID I1 RB RA P0 D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register Bit [7:0] Register Pot/WCR Address Address Figure 4. Three-Byte Instruction Sequence (Read) CS SCL SI 0 1 0 1 ID3 ID2 ID1 ID0 0 0 0 0 Internal Address Device ID X 0 A1 A0 I3 I2 I1 I0 Instruction Opcode RB RA P0 X X X X X X X Don’t Care Register Pot/WCR Address Address S0 D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register Bit [7:0] 8 FN8171.4 October 12, 2006 X9261 Figure 5. Three-Byte Instruction Sequence (Read Status Register) CS SCL SI 0 1 0 1 ID3 ID2 ID1 ID0 0 0 0 0 1 A1 A0 I3 Internal Address Device ID 0 I2 1 0 1 I1 I0 Instruction Opcode RB RA 0 0 0 0 0 0 P0 0 WIP Register Pot/WCR Address Address Status Bit Figure 6. Increment/Decrement Instruction Sequence CS SCL SI 0 1 0 1 ID3 ID2 ID1 ID0 0 0 0 0 Device ID 0 A1 A0 I2 Internal Address I3 I1 I0 Instruction Opcode RB RA P0 Register Pot/WCR Address Address I N C 1 I N C 2 I N C n D E C 1 D E C n Figure 7. Increment/Decrement Timing Limits tWRID SCK SI VOLTAGE OUT RW INC/DEC CMD ISSUED 9 FN8171.4 October 12, 2006 X9261 Table 5. Instruction Set I3 1 I2 0 Instruction Set I1 I0 RB RA 0 1 0 0 1 0 1 0 0 0 0 1/0 1 0 1 1 1/0 1/0 0 1/0 Write Data Register 1 1 0 0 1/0 1/0 0 1/0 XFR Data Register to Wiper Counter Register 1 1 0 1 1/0 1/0 0 1/0 XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 0 1/0 Global XFR Data Registers to Wiper Counter Registers 0 0 0 1 1/0 1/0 0 0 Global XFR Wiper Counter Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 0 1/0 Instruction Read Wiper Counter Register Write Wiper Counter Register Read Data Register Note: 0 0 P0 Operation 1/0 Read the contents of the Wiper Counter Register pointed to by P0 Write new value to the Wiper Counter Register pointed to by P0 Read the contents of the Data Register pointed to by P0 and RB - RA Write new value to the Data Register pointed to by P0 and RB - RA Transfer the contents of the Data Register pointed to by P0 and RB - RA to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P0 to the Data Register pointed to by RB - RA Transfer the contents of the Data Registers pointed to by RB - RA of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by RB - RA of all four pots Enable Increment/decrement of the Control Latch pointed to by P0 1/0 = data is one or zero INSTRUCTION FORMAT Read Wiper Counter Register (WCR) CS Falling Edge Device Type Identifier 0 1 0 1 Device Addresses Instruction Opcode 0 0 A1 A0 1 0 0 1 WCR Addresses 0 0 Wiper Position (Sent by X9261 on SO) W C 0 P0 R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 CS W Rising C Edge R 0 Write Wiper Counter Register (WCR) Device Type Identifier CS Falling Edge 0 1 0 1 Device Addresses Instruction Opcode 0 0 A1 A0 1 0 1 0 WCR Addresses 0 0 W C 0 P0 R 7 Data Byte (Sent by Host on SI) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 CS W Rising C Edge R 0 Read Data Register (DR) Device Type Device Instruction DR and WCR Data Byte CS CS Identifier Addresses Opcode Addresses (Sent by X9271 on SO) Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA 0 P0 D D D D D D D D Edge 7 6 5 4 3 2 1 0 10 FN8171.4 October 12, 2006 X9261 Device Type Identifier Device Addresses Instruction Opcode DR and WCR Addresses CS Falling Edge 0 1 0 1 0 0 A1 A0 1 1 0 0 RB RA 0 Data Byte (Sent by Host on SI) CS Rising D D D D D D D D Edge P0 7 6 5 4 3 2 1 0 HIGH-VOLTAGE WRITE CYCLE Write Data Register (DR) Global Transfer Data Register (DR) to Wiper Counter Register (WCR) Device Type CS Identifier Falling Edge 0 1 0 1 Device Addresses 0 Instruction Opcode DR Addresses CS Rising 0 A1 A0 0 0 0 1 RB RA 0 0 Edge Global Transfer Wiper Counter Register (WCR) to Data Register (DR) Device Type Device Instruction DR CS CS Identifier Addresses Opcode Addresses Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 0 0 0 RB RA 0 0 Edge HIGH-VOLTAGE WRITE CYCLE Transfer Wiper Counter Register (WCR) to Data Register (DR) Device Type Device Instruction DR and WCR CS CS Identifier Addresses Opcode Addresses Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 1 1 0 RB RA 0 P0 Edge HIGH-VOLTAGE WRITE CYCLE Transfer Data Register (DR) to Wiper Counter Register (WCR) Device Type Device Instruction DR and WCR CS CS Identifier Addresses Opcode Addresses Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 1 0 1 RB RA 0 P0 Edge Increment/Decrement Wiper Counter Register (WCR) Device Type Device Instruction WCR Increment/Decrement CS CS Identifier Addresses Opcode Addresses (Sent by Master on SDA) Falling Rising Edge 0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 P0 I/D I/D . . . . I/D I/D Edge Read Status Register (SR) Device Type Device Instruction WCR Data Byte CS Identifier Addresses Opcode Addresses (Sent by X9261 on SO) Falling Edge 0 1 0 1 0 0 A1 A0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 WIP Notes: (1) (2) (2) (3) CS Rising Edge “A1 ~ A0”: stands for the device addresses sent by the master. WPx refers to wiper position data in the Counter Register “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). 11 FN8171.4 October 12, 2006 X9261 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on SCK any address input with respect to VSS ................................. -1V to +7V ΔV = | (VH - VL) |................................................... 5.5V Lead temperature (soldering, 10s) .................... 300°C IW (10s) ..............................................................±6mA Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial Min. 0°C -40°C Max. +70°C +85°C Supply Voltage (VCC)(4) Limits 5V ± 10% Device X9261 POTENTIOMETER CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.) Parameter Symbol RTOTAL RTOTAL Limits Min. Typ. End to End Resistance 100 End to End Resistance 50 Max. Units Test Conditions kΩ T version kΩ U version End to End Resistance Tolerance ±20 % Power Rating 50 mW 25°C, each pot IW Wiper Current ±3 mA RW Wiper Resistance 300 Ω IW = ±3mA @ V+ = 3V RW Wiper Resistance 150 Ω IW = ±3mA @ V+ = 5V VTERM Voltage on any RH or RL Pin VCC V VSS = 0V Noise VSS -120 Resolution dBV 0.4 Ref: 1V % Absolute Linearity (1) ±1 MI(3) Rw(n)(actual) - Rw(n)(expected)(5) Relative Linearity (2) ±0.6 MI(3) Rw(n + 1) - [Rw(n) + MI](5) Temperature Coefficient of RTOTAL ±300 Ratiometric Temp. Coefficient CH/CL/CW Potentiometer Capacitances Ial RW, RH, RL Leakage ppm/°C 20 10/10/25 0.1 10.0 ppm/°C pF See Macro model µA Device in stand by. Vin = VSS to VCC Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH - RL) / 255, single pot (4) During power-up VCC > VH, VL, and VW. (5) n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254. 12 FN8171.4 October 12, 2006 X9261 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions 400 μA fSCK = 2.5 MHz, SO = Open, VCC = 6V Other Inputs = VSS 5 mA fSCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS ICC1 VCC supply current (active) ICC2 VCC supply current (nonvolatile write) ISB VCC current (standby) 5 μA SCK = SI = VSS, Addr. = VSS, CS = VCC = 6V ILI Input leakage current 10 μA VIN = VSS to VCC ILO Output leakage current 10 μA VOUT = VSS to VCC VIH Input HIGH voltage VCC x 0.7 VCC + 1 V VIL Input LOW voltage -1 VCC x 0.3 V VOL Output LOW voltage 0.4 V IOL = 3mA VOH Output HIGH voltage VCC - 0.8 V IOH = -1mA, VCC ≥ +3V VOH Output HIGH voltage VCC - 0.4 V IOH = -0.4mA, VCC ≤ +3V 1 ENDURANCE AND DATA RETENTION Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years CAPACITANCE Symbol COUT(6) CIN(6) Max. Units Output capacitance (SO) Test 8 pF VOUT = 0V Test Conditions Input capacitance (A0, A1, SI, CS, WP, HOLD, and SCK) 6 pF VIN = 0V POWER-UP TIMING Symbol tr VCC (6) tPUR(7) Parameter VCC Power-up rate Power-up to initiation of read operation Min. Max. Units 0.2 50 V/ms 1 ms POWER-UP AND DOWN REQUIREMENTS The are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC power-up timing spec is always in effect. A.C. TEST CONDITIONS Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 Notes: (6) This parameter is not 100% tested (7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. 13 FN8171.4 October 12, 2006 X9261 EQUIVALENT A.C. LOAD CIRCUIT 5V 3V 1462Ω SPICE Macromodel 1382Ω RTOTAL SO pin SO pin 2714Ω CW CL 1217Ω 100pF RL RH 100pF CL 10pF 25pF 10pF RW AC TIMING Symbol Parameter Min. Max. Units 2 MHz fSCK SSI/SPI clock frequency tCYC SSI/SPI clock cycle rime tWH SSI/SPI clock high rime 200 ns tWL SSI/SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 μs tFI SI, SCK, HOLD and CS input fall time 2 μs tDIS SO output disable time tV SO output valid time tHO SO output hold time tRO SO output rise time 100 ns tFO SO output fall time 100 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns tCS CS deselect time 2 μs tWPASU WP, A0, A1 setup time 0 ns tWPAH WP, A0, A1 hold time 0 ns 14 500 0 ns 250 ns 200 ns 0 ns FN8171.4 October 12, 2006 X9261 HIGH-VOLTAGE WRITE CYCLE TIMING Symbol Parameter tWR High-voltage write cycle time (store instructions) Typ. Max. Units 5 10 ms XDCP TIMING Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 μs tWRL Wiper response time after instruction issued (all load instructions) 5 10 μs SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance TIMING DIAGRAMS Input Timing tCS CS SCK tSU SI SO tH tLAG tCYC tLEAD tWL ... tWH ... MSB tRI tFI LSB High Impedance 15 FN8171.4 October 12, 2006 X9261 Output Timing CS SCK tV tDIS ... MSB SO SI ... tHO LSB ADDR Hold Timing CS tHSU tHH SCK ... tRO tFO SO tHZ tLZ SI tHOLD HOLD XDCP Timing (for All Load Instructions) CS SCK SI ... tWRL ... MSB LSB VWx SO High Impedance Write Protect and Device Address Pins Timing (Any Instruction) CS tWPASU WP tWPAH A0 A1 16 FN8171.4 October 12, 2006 X9261 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers +VR VR RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier VS Voltage Regulator + VO – VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 Comparator with Hysterisis R2 VS VS – + 100kΩ – VO + +12V 10kΩ } 10kΩ } TL072 10kΩ VO R1 R2 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) -12V 17 FN8171.4 October 12, 2006 X9261 Application Circuits (continued) Attenuator Filter C VS R2 R1 VO – – VS + R VO + R3 R4 R2 R1 = R2 = R3 = R4 = 10kΩ R1 GO = 1 + R2/R1 fc = 1/(2πRC) V O = G VS -1/2 ≤ G ≤ +1/2 R2 } VS R1 } Inverting Amplifier Equivalent L-R Circuit R2 C1 – VS VO + + – R1 ZIN V O = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C R2 – + R1 – } RA + } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB 18 FN8171.4 October 12, 2006 X9261 Small Outline Plastic Packages (SOIC) M24.3 (JEDEC MS-013-AD ISSUE C) N 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e α B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 24 0° 24 8° 0° 7 8° Rev. 1 4/06 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 19 FN8171.4 October 12, 2006 X9261 Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE (N/2)+1 N PIN #1 I.D. E E1 0.20 C B A 1 (N/2) B 2X N/2 LEAD TIPS TOP VIEW 0.05 e C H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. E 12/02 NOTES: SEATING PLANE 0.10 M C A B b 0.10 C N LEADS SIDE VIEW 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. SEE DETAIL “X” c 4. Dimensioning and tolerancing per ASME Y14.5M-1994. END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN8171.4 October 12, 2006