INFINEON XC2268M

16/32-Bit
Architecture
XC2268M/67M,
XC2265M/64M/63M
16/32-Bit Single-Chip Microcontroller with
32-Bit Performance
XC2000 Family Derivatives / Base Line
Data Sheet
V2.0 2009-03
M ic r o co n t ro l l e r s
Edition 2009-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
16/32-Bit
Architecture
XC2268M/67M,
XC2265M/64M/63M
16/32-Bit Single-Chip Microcontroller with
32-Bit Performance
XC2000 Family Derivatives / Base Line
Data Sheet
V2.0 2009-03
M ic r o co n t ro l l e r s
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
XC226xM
Revision History: V2.0, 2009-03
Previous Version(s):
V1.3, 2008-11
V1.2, 2008-09
V1.1, 2008-06 Preliminary
V1.0, 2008-06 (Intermediate version)
Page
Subjects (major changes since last revision)
19ff
Overlaid analog input channels specified (ADC0/ADC1)
86, 88
Current through power domain DMP_A specified
94
Specification of wakeup clock frequencies improved
106f
Section “Pad Properties” added
116f
SSC interface timing improved
119ff
Debug interface timing detailled
Trademarks
C166™, TriCore™, and DAVE™ are trademarks of Infineon Technologies AG.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
Data Sheet
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Table of Contents
Table of Contents
1
1.1
1.2
1.3
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Basic Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Special Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
2.1
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Checker Module (MCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capture/Compare Unit (CAPCOM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capture/Compare Units CCU6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Serial Interface Channel Modules (USIC) . . . . . . . . . . . . . . . . .
MultiCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
40
43
44
46
46
47
53
54
56
58
62
64
65
67
68
69
69
70
71
72
4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.4
4.5
4.6
4.6.1
4.6.2
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters for Upper Voltage Area . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters for Lower Voltage Area . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
75
79
81
83
85
90
94
96
98
98
99
Data Sheet
5
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Table of Contents
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
5
5.1
5.2
Data Sheet
External Clock Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pad Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
104
106
108
116
119
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Summary of Features
16/32-Bit Single-Chip Microcontroller with 32-Bit Performance
XC226xM (XC2000 Family)
1
Summary of Features
For a quick overview and easy reference, the features of the XC226xM are summarized
here.
•
•
•
•
•
•
•
High-performance CPU with five-stage pipeline and MPU
– 12.5 ns instruction cycle at 80 MHz CPU clock (single-cycle execution)
– One-cycle 32-bit addition and subtraction with 40-bit result
– One-cycle multiplication (16 × 16 bit)
– Background division (32 / 16 bit) in 21 cycles
– One-cycle multiply-and-accumulate (MAC) instructions
– Enhanced Boolean bit manipulation facilities
– Zero-cycle jump execution
– Additional instructions to support HLL and operating systems
– Register-based design with multiple variable register banks
– Fast context switching support with two additional local register banks
– 16 Mbytes total linear address space for code and data
– 1024 Bytes on-chip special function register area (C166 Family compatible)
– Integrated Memory Protection Unit (MPU)
Interrupt system with 16 priority levels for up to 96 sources
– Selectable external inputs for interrupt generation and wake-up
– Fastest sample-rate 12.5 ns
Eight-channel interrupt-driven single-cycle data transfer with
Peripheral Event Controller (PEC), 24-bit pointers cover total address space
Clock generation from internal or external clock sources,
using on-chip PLL or prescaler
Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip
Memory Areas
On-chip memory modules
– 8 Kbytes on-chip stand-by RAM (SBRAM)
– 2 Kbytes on-chip dual-port RAM (DPRAM)
– 16 Kbytes on-chip data SRAM (DSRAM)
– Up to 32 Kbytes on-chip program/data SRAM (PSRAM)
– Up to 832 Kbytes on-chip program memory (Flash memory)
– Memory content protection through Error Correction Code (ECC)
On-Chip Peripheral Modules
– Multi-functional general purpose timer unit with 5 timers
– 16-channel general purpose capture/compare unit (CAPCOM2)
Data Sheet
7
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Summary of Features
•
•
•
•
•
•
•
•
•
– Up to four capture/compare units for flexible PWM signal generation (CCU6x)
– Two Synchronizable A/D Converters with up to 16 channels, 10-bit resolution,
conversion time below 1 μs, optional data preprocessing (data reduction, range
check), broken wire detection
– Up to 8 serial interface channels to be used as UART, LIN, high-speed
synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s),
IIS interface
– On-chip MultiCAN interface (Rev. 2.0B active) with up to 256 message objects
(Full CAN/Basic CAN) on up to 6 CAN nodes and gateway functionality
– On-chip system timer and on-chip real time clock
Up to 12 Mbytes external address space for code and data
– Programmable external bus characteristics for different address ranges
– Multiplexed or demultiplexed external address/data buses
– Selectable address bus width
– 16-bit or 8-bit data bus width
– Four programmable chip-select signals
Single power supply from 3.0 V to 5.5 V
Power reduction and wake-up modes with flexible power management
Programmable watchdog timer and oscillator watchdog
Up to 76 general purpose I/O lines
On-chip bootstrap loaders
Supported by a full range of development tools including C compilers, macroassembler packages, emulators, evaluation boards, HLL debuggers, simulators,
logic analyzer disassemblers, programming boards
On-chip debug support via Device Access Port (DAP) or JTAG interface
100-pin Green LQFP package, 0.5 mm (19.7 mil) pitch
Data Sheet
8
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Summary of Features
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. This ordering code identifies:
•
•
•
the function set of the corresponding product type
the temperature range:
– SAF-…: -40°C to 85°C
– SAK-…: -40°C to 125°C
the package and the type of delivery.
For ordering codes for the XC226xM please contact your sales representative or local
distributor.
This document describes several derivatives of the XC226xM group:
Basic Device Types are readily available and
Special Device Types are only available on request.
As this document refers to all of these derivatives, some descriptions may not apply to a
specific product, in particular to the special device types.
For simplicity the term XC226xM is used for all derivatives throughout this document.
1.1
Basic Device Types
Basic device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1
Synopsis of XC226xM Basic Device Types
Derivative1)
Program
Memory2)
PSRAM3)
Capt./Comp. ADC4) Interfaces4)
Modules
Chan.
SAK-XC2267M104FxxL
832 Kbytes 32/16
Flash
Kbytes
CC2
11 + 5 6 CAN Nodes,
CCU60/1/2/3
8 Serial Chan.
SAK-XC2267M72FxxL
576 Kbytes 32/16
Flash
Kbytes
CC2
11 + 5 6 CAN Nodes,
CCU60/1/2/3
8 Serial Chan.
1) This Data Sheet is valid for devices starting with and including design step AA.
xx is a placeholder for the available speed grade (in MHz).
2) Specific information about the on-chip Flash memory in Table 3.
3) All derivatives additionally provide 8 Kbytes SBRAM, 2 Kbytes DPRAM, and 16 Kbytes DSRAM.
4) Specific information about the available channels in Table 4.
Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1).
Data Sheet
9
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Summary of Features
1.2
Special Device Types
Special device types are only available for high-volume applications on request.
Table 2
Synopsis of XC226xM Special Device Types
Derivative1)
Program
Memory2)
SAK-XC2268M104FxxL
832 Kbytes 32/16
Flash
Kbytes
CC2
4
6 CAN Nodes,
6 Serial Chan.
SAF-XC2268M104FxxL
832 Kbytes 32/16
Flash
Kbytes
CC2
4
6 CAN Nodes,
6 Serial Chan.
SAK-XC2268M72FxxL
576 Kbytes 32/16
Flash
Kbytes
CC2
4
6 CAN Nodes,
6 Serial Chan.
SAF-XC2268M72FxxL
576 Kbytes 32/16
Flash
Kbytes
CC2
4
6 CAN Nodes,
6 Serial Chan.
SAK-XC2268M56FxxL
448 Kbytes 16/8
Flash
Kbytes
CC2
4
6 CAN Nodes,
6 Serial Chan.
SAF-XC2268M56FxxL
448 Kbytes 16/8
Flash
Kbytes
CC2
4
6 CAN Nodes,
6 Serial Chan.
SAF-XC2267M104FxxL
832 Kbytes 32/16
Flash
Kbytes
CC2
11 + 5 6 CAN Nodes,
CCU60/1/2/3
8 Serial Chan.
SAF-XC2267M72FxxL
576 Kbytes 32/16
Flash
Kbytes
CC2
11 + 5 6 CAN Nodes,
CCU60/1/2/3
8 Serial Chan.
SAK-XC2267M56FxxL
448 Kbytes 16/8
Flash
Kbytes
CC2
11 + 5 6 CAN Nodes,
CCU60/1/2/3
8 Serial Chan.
SAF-XC2267M56FxxL
448 Kbytes 16/8
Flash
Kbytes
CC2
11 + 5 6 CAN Nodes,
CCU60/1/2/3
8 Serial Chan.
SAK-XC2265M104FxxL
832 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
11 + 5 3 CAN Nodes,
8 Serial Chan.
SAF-XC2265M104FxxL
832 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
11 + 5 3 CAN Nodes,
8 Serial Chan.
SAK-XC2265M72FxxL
576 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
11 + 5 3 CAN Nodes,
8 Serial Chan.
SAF-XC2265M72FxxL
576 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
11 + 5 3 CAN Nodes,
8 Serial Chan.
SAK-XC2265M56FxxL
448 Kbytes 16/8
Flash
Kbytes
CC2
CCU60/1
11 + 5 3 CAN Nodes,
8 Serial Chan.
Data Sheet
PSRAM3)
Capt./Comp. ADC4) Interfaces4)
Modules
Chan.
10
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Summary of Features
Table 2
Derivative
Synopsis of XC226xM Special Device Types (cont’d)
1)
Program
Memory2)
PSRAM3)
Capt./Comp. ADC4) Interfaces4)
Modules
Chan.
SAF-XC2265M56FxxL
448 Kbytes 16/8
Flash
Kbytes
CC2
CCU60/1
11 + 5 3 CAN Nodes,
8 Serial Chan.
SAK-XC2264M104FxxL
832 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
8
2 CAN Nodes,
4 Serial Chan.
SAF-XC2264M104FxxL
832 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
8
2 CAN Nodes,
4 Serial Chan.
SAK-XC2264M72FxxL
576 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
8
2 CAN Nodes,
4 Serial Chan.
SAF-XC2264M72FxxL
576 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
8
2 CAN Nodes,
4 Serial Chan.
SAK-XC2264M56FxxL
448 Kbytes 16/8
Flash
Kbytes
CC2
CCU60/1
8
2 CAN Nodes,
4 Serial Chan.
SAF-XC2264M56FxxL
448 Kbytes 16/8
Flash
Kbytes
CC2
CCU60/1
8
2 CAN Nodes,
4 Serial Chan.
SAK-XC2263M104FxxL
832 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
11 + 5 1 CAN Node,
4 Serial Chan.
SAF-XC2263M104FxxL
832 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
11 + 5 1 CAN Node,
4 Serial Chan.
SAK-XC2263M72FxxL
576 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
11 + 5 1 CAN Node,
4 Serial Chan.
SAF-XC2263M72FxxL
576 Kbytes 32/16
Flash
Kbytes
CC2
CCU60/1
11 + 5 1 CAN Node,
4 Serial Chan.
SAK-XC2263M56FxxL
448 Kbytes 16/8
Flash
Kbytes
CC2
CCU60/1
11 + 5 1 CAN Node,
4 Serial Chan.
SAF-XC2263M56FxxL
448 Kbytes 16/8
Flash
Kbytes
CC2
CCU60/1
11 + 5 1 CAN Node,
4 Serial Chan.
1) This Data Sheet is valid for devices starting with and including design step AA.
xx is a placeholder for the available speed grade (in MHz).
2) Specific information about the on-chip Flash memory in Table 3.
3) All derivatives additionally provide 8 Kbytes SBRAM, 2 Kbytes DPRAM, and 16 Kbytes DSRAM.
4) Specific information about the available channels in Table 4.
Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1).
Data Sheet
11
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Summary of Features
1.3
Definition of Feature Variants
The XC226xM types are offered with several Flash memory sizes. Table 3 describes the
location of the available memory areas for each Flash memory size.
Table 3
Flash Memory Allocation
Total Flash Size
Flash Area A1)
Flash Area B
Flash Area C
832 Kbytes
C0’0000H …
C0’EFFFH
C1’0000H …
CC’FFFFH
n.a.
576 Kbytes
C0’0000H …
C0’EFFFH
C1’0000H …
C7’FFFFH
CC’0000H …
CC’FFFFH
448 Kbytes
C0’0000H …
C0’EFFFH
C1’0000H …
C5’FFFFH
CC’0000H …
CC’FFFFH
1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH).
The XC226xM types are offered with different interface options. Table 4 lists the
available channels for each option.
Table 4
Interface Channel Association
Total Number
Available Channels
11 ADC0 channels
CH0, CH2 … CH5, CH8 … CH11, CH13, CH15
8 ADC0 channels
CH0, CH2 … CH5, CH8 … CH10
4 ADC0 channels
CH0, CH2, CH3, CH4
5 ADC1 channels
CH0, CH2, CH4, CH5, CH6 (overlay: CH8 … CH11)
6 CAN nodes
CAN0, CAN1, CAN2, CAN3, CAN4, CAN5
3 CAN nodes
CAN0, CAN1, CAN2
2 CAN nodes
CAN0, CAN1
1 CAN node
CAN0
8 serial channels
U0C0, U0C1, U1C0, U1C1, U2C0, U2C1, U3C0, U3C1
6 serial channels
U0C0, U0C1, U1C0, U1C1, U2C0, U2C1
4 serial channels
U0C0, U0C1, U1C0, U1C1
Data Sheet
12
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
2
General Device Information
The XC226xM series (16/32-Bit Single-Chip Microcontroller with 32-Bit Performance) is
a part of the Infineon XC2000 Family of full-feature single-chip CMOS microcontrollers.
These devices extend the functionality and performance of the C166 Family in terms of
instructions (MAC unit), peripherals, and speed. They combine high CPU performance
(up to 80 million instructions per second) with extended peripheral functionality and
enhanced IO capabilities. Optimized peripherals can be adapted flexibly to meet the
application requirements. These derivatives utilize clock generation via PLL and internal
or external clock sources. On-chip memory modules include program Flash, program
RAM, and data RAM.
VAREF VAGND
(1)
VDDI VDDP VSS
(1)
(4)
(9)
(4)
Port 0
8 bit
XTAL1
XTAL2
Port 1
8 bit
ESR0
ESR1
Port 2
14 bit
Port 4
4 bit
Port 10
16 bit
Port 6
3 bit
Port 7
5 bit
Port 15
5 bit
Port 5
11 bit
PORST
TRST DAP/JTAG Debug
2 / 4 bit
2 bit
via Port Pins
TESTM
MC_XY_LOGSYMB100
Figure 1
Data Sheet
Logic Symbol
13
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
2.1
Pin Configuration and Definition
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDDPB
ESR0
ESR1
PORST
XTAL1
XTAL2
P1.7
P1.6
P1.5
P10.15
P1.4
P10.14
VDDI1
P1.3
P10.13
P10.12
P1.2
P10.11
P10.10
P1.1
P10.9
P10.8
P1.0
VDDPB
VS S
The pins of the XC226xM are described in detail in Table 5, which includes all alternate
functions. For further explanations please refer to the footnotes at the end of the table.
Figure 2 summarizes all pins, showing their locations on the four sides of the package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP-100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDPB
P0.7
P10.7
P10.6
P0.6
P10.5
P10.4
P0.5
P10.3
P2.10
P2.13
VDDI1
P0.4
P10.2
P0.3
P10.1
P10.0
P0.2
P2.9
P2.8
P0.1
P2.7
P0.0
VDDPB
VSS
VSS
VDDPB
P5.4
P5.5
P5.8
P5.9
P5.10
P5.11
P5.13
P5.15
P2.12
P2.11
VDDI1
P2.0
P2.1
P2.2
P4.0
P2.3
P4.1
P2.4
P2.5
P4.2
P2.6
P4.3
VDDPB
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDDPB
TESTM
P7.2
TRST
P7.0
P7.3
P7.1
P7.4
VDDIM
P6.0
P6.1
P6.2
VDDPA
P15.0
P15.2
P15.4
P15.5
P15.6
VAREF
VAGND
P5.0
P5.2
P5.3
VDDPB
MC_XY_PIN100
Figure 2
Data Sheet
Pin Configuration (top view)
14
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Key to Pin Definitions
•
•
Ctrl.: The output signal for a port pin is selected by bitfield PC in the associated
register Px_IOCRy. Output O0 is selected by setting the respective bitfield PC to
1x00B, output O1 is selected by 1x01B, etc.
Output signal OH is controlled by hardware.
Type: Indicates the pad type and its power supply domain (A, B, M, 1)
– St: Standard pad
– Sp: Special pad
– DP: Double pad - can be used as standard or high-speed pad
– In: Input only pad
– PS: Power supply pad
Table 5
Pin Definitions and Functions
Pin
Symbol
Ctrl.
Type Function
3
TESTM
I
In/B
4
P7.2
O0 / I St/B
Bit 2 of Port 7, General Purpose Input/Output
EMUX0
O1
St/B
External Analog MUX Control Output 0 (ADC1)
TxDC4
O2
St/B
CAN Node 4 Transmit Data Output
TxDC5
O3
St/B
CAN Node 5 Transmit Data Output
CCU62_CCP I
OS0A
St/B
CCU62 Position Input 0
TDI_C
I
St/B
JTAG Test Data Input
TRST
I
In/B
Test-System Reset Input
For normal system operation, pin TRST should be
held low. A high level at this pin at the rising edge
of PORST activates the XC226xM’s debug
system. In this case, pin TRST must be driven low
once to reset the debug system.
An internal pulldown device will hold this pin low
when nothing is driving it.
5
Data Sheet
Testmode Enable
Enables factory test modes, must be held HIGH for
normal operation (connect to VDDPB).
An internal pullup device will hold this pin high
when nothing is driving it.
15
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
6
P7.0
O0 / I St/B
Bit 0 of Port 7, General Purpose Input/Output
T3OUT
O1
St/B
GPT12E Timer T3 Toggle Latch Output
T6OUT
O2
St/B
GPT12E Timer T6 Toggle Latch Output
TDO_A
OH / I St/B
JTAG Test Data Output / DAP1 Input/Output
ESR2_1
I
St/B
ESR2 Trigger Input 1
RxDC4B
I
St/B
CAN Node 4 Receive Data Input
P7.3
O0 / I St/B
Bit 3 of Port 7, General Purpose Input/Output
EMUX1
O1
St/B
External Analog MUX Control Output 1 (ADC1)
U0C1_DOUT O2
St/B
USIC0 Channel 1 Shift Data Output
U0C0_DOUT O3
St/B
USIC0 Channel 0 Shift Data Output
CCU62_CCP I
OS1A
St/B
CCU62 Position Input 1
TMS_C
I
St/B
JTAG Test Mode Selection Input
U0C1_DX0F
I
St/B
USIC0 Channel 1 Shift Data Input
P7.1
O0 / I St/B
Bit 1 of Port 7, General Purpose Input/Output
EXTCLK
O1
St/B
Programmable Clock Signal Output
TXDC4
O2
St/B
CAN Node 4 Transmit Data Output
CCU62_CTR
APA
I
St/B
CCU62 Emergency Trap Input
BRKIN_C
I
St/B
OCDS Break Signal Input
P7.4
O0 / I St/B
Bit 4 of Port 7, General Purpose Input/Output
EMUX2
O1
St/B
External Analog MUX Control Output 2 (ADC1)
U0C1_DOUT O2
St/B
USIC0 Channel 1 Shift Data Output
U0C1_SCLK
OUT
St/B
USIC0 Channel 1 Shift Clock Output
CCU62_CCP I
OS2A
St/B
CCU62 Position Input 2
TCK_C
I
St/B
DAP0/JTAG Clock Input
U0C0_DX0D
I
St/B
USIC0 Channel 0 Shift Data Input
U0C1_DX1E
I
St/B
USIC0 Channel 1 Shift Clock Input
7
8
9
Data Sheet
O3
Type Function
16
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
11
P6.0
O0 / I St/A
Bit 0 of Port 6, General Purpose Input/Output
EMUX0
O1
St/A
External Analog MUX Control Output 0 (ADC0)
TxDC2
O2
St/A
CAN Node 2 Transmit Data Output
BRKOUT
O3
St/A
OCDS Break Signal Output
ADCx_REQG I
TyG
St/A
External Request Gate Input for ADC0/1
U1C1_DX0E
I
St/A
USIC1 Channel 1 Shift Data Input
P6.1
O0 / I St/A
Bit 1 of Port 6, General Purpose Input/Output
EMUX1
O1
St/A
External Analog MUX Control Output 1 (ADC0)
T3OUT
O2
St/A
GPT12E Timer T3 Toggle Latch Output
U1C1_DOUT O3
St/A
USIC1 Channel 1 Shift Data Output
ADCx_REQT I
RyE
St/A
External Request Trigger Input for ADC0/1
RxDC2E
I
St/A
CAN Node 2 Receive Data Input
ESR1_6
I
St/A
ESR1 Trigger Input 6
P6.2
O0 / I St/A
Bit 2 of Port 6, General Purpose Input/Output
EMUX2
O1
St/A
External Analog MUX Control Output 2 (ADC0)
T6OUT
O2
St/A
GPT12E Timer T6 Toggle Latch Output
U1C1_SCLK
OUT
O3
St/A
USIC1 Channel 1 Shift Clock Output
U1C1_DX1C
I
St/A
USIC1 Channel 1 Shift Clock Input
P15.0
I
In/A
Bit 0 of Port 15, General Purpose Input
ADC1_CH0
I
In/A
Analog Input Channel 0 for ADC1
P15.2
I
In/A
Bit 2 of Port 15, General Purpose Input
ADC1_CH2
I
In/A
Analog Input Channel 2 for ADC1
T5INA
I
In/A
GPT12E Timer T5 Count/Gate Input
P15.4
I
In/A
Bit 4 of Port 15, General Purpose Input
ADC1_CH4
I
In/A
Analog Input Channel 4 for ADC1
T6INA
I
In/A
GPT12E Timer T6 Count/Gate Input
12
13
15
16
17
Data Sheet
Type Function
17
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
Type Function
18
P15.5
I
In/A
Bit 5 of Port 15, General Purpose Input
ADC1_CH5
I
In/A
Analog Input Channel 5 for ADC1
T6EUDA
I
In/A
GPT12E Timer T6 External Up/Down Control
Input
P15.6
I
In/A
Bit 6 of Port 15, General Purpose Input
ADC1_CH6
I
In/A
Analog Input Channel 6 for ADC1
20
VAREF
-
PS/A Reference Voltage for A/D Converters ADC0/1
21
VAGND
-
PS/A Reference Ground for A/D Converters ADC0/1
22
P5.0
I
In/A
Bit 0 of Port 5, General Purpose Input
ADC0_CH0
I
In/A
Analog Input Channel 0 for ADC0
P5.2
I
In/A
Bit 2 of Port 5, General Purpose Input
ADC0_CH2
I
In/A
Analog Input Channel 2 for ADC0
TDI_A
I
In/A
JTAG Test Data Input
P5.3
I
In/A
Bit 3 of Port 5, General Purpose Input
ADC0_CH3
I
In/A
Analog Input Channel 3 for ADC0
T3INA
I
In/A
GPT12E Timer T3 Count/Gate Input
P5.4
I
In/A
Bit 4 of Port 5, General Purpose Input
ADC0_CH4
I
In/A
Analog Input Channel 4 for ADC0
CCU63_T12
HRB
I
In/A
External Run Control Input for T12 of CCU63
T3EUDA
I
In/A
GPT12E Timer T3 External Up/Down Control
Input
TMS_A
I
In/A
JTAG Test Mode Selection Input
P5.5
I
In/A
Bit 5 of Port 5, General Purpose Input
ADC0_CH5
I
In/A
Analog Input Channel 5 for ADC0
CCU60_T12
HRB
I
In/A
External Run Control Input for T12 of CCU60
19
23
24
28
29
Data Sheet
18
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
Type Function
30
P5.8
I
In/A
Bit 8 of Port 5, General Purpose Input
ADC0_CH8
I
In/A
Analog Input Channel 8 for ADC0
ADC1_CH8
I
In/A
Analog Input Channel 8 for ADC1
CCU6x_T12H I
RC
In/A
External Run Control Input for T12 of
CCU60/1/2/3
CCU6x_T13H I
RC
In/A
External Run Control Input for T13 of
CCU60/1/2/3
U2C0_DX0F
I
In/A
USIC2 Channel 0 Shift Data Input
P5.9
I
In/A
Bit 9 of Port 5, General Purpose Input
ADC0_CH9
I
In/A
Analog Input Channel 9 for ADC0
ADC1_CH9
I
In/A
Analog Input Channel 9 for ADC1
CC2_T7IN
I
In/A
CAPCOM2 Timer T7 Count Input
P5.10
I
In/A
Bit 10 of Port 5, General Purpose Input
ADC0_CH10
I
In/A
Analog Input Channel 10 for ADC0
ADC1_CH10
I
In/A
Analog Input Channel 10 for ADC1
BRKIN_A
I
In/A
OCDS Break Signal Input
U2C1_DX0F
I
In/A
USIC2 Channel 1 Shift Data Input
CCU61_T13
HRA
I
In/A
External Run Control Input for T13 of CCU61
P5.11
I
In/A
Bit 11 of Port 5, General Purpose Input
ADC0_CH11
I
In/A
Analog Input Channel 11 for ADC0
ADC1_CH11
I
In/A
Analog Input Channel 11 for ADC1
P5.13
I
In/A
Bit 13 of Port 5, General Purpose Input
ADC0_CH13
I
In/A
Analog Input Channel 13 for ADC0
CCU63_T13
HRF
I
In/A
External Run Control Input for T13 of CCU63
P5.15
I
In/A
Bit 15 of Port 5, General Purpose Input
ADC0_CH15
I
In/A
Analog Input Channel 15 for ADC0
RxDC2F
I
In/A
CAN Node 2 Receive Data Input
31
32
33
34
35
Data Sheet
19
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
36
P2.12
O0 / I St/B
Bit 12 of Port 2, General Purpose Input/Output
U0C0_SELO
4
O1
St/B
USIC0 Channel 0 Select/Control 4 Output
U0C1_SELO
3
O2
St/B
USIC0 Channel 1 Select/Control 3 Output
TXDC2
O3
St/B
CAN Node 2 Transmit Data Output
READY
I
St/B
External Bus Interface READY Input
P2.11
O0 / I St/B
Bit 11 of Port 2, General Purpose Input/Output
U0C0_SELO
2
O1
St/B
USIC0 Channel 0 Select/Control 2 Output
U0C1_SELO
2
O2
St/B
USIC0 Channel 1 Select/Control 2 Output
U3C1_DOUT O3
St/B
USIC3 Channel 1 Shift Data Output
BHE/WRH
OH
St/B
External Bus Interf. High-Byte Control Output
Can operate either as Byte High Enable (BHE) or
as Write strobe for High Byte (WRH).
P2.0
O0 / I St/B
Bit 0 of Port 2, General Purpose Input/Output
TxDC5
O1
St/B
CAN Node 5 Transmit Data Output
CCU63_CC6
0
O2
St/B
CCU63 Channel 0 Output
AD13
OH / I St/B
External Bus Interface Address/Data Line 13
RxDC0C
I
St/B
CAN Node 0 Receive Data Input
CCU63_CC6
0INB
I
St/B
CCU63 Channel 0 Input
T5INB
I
St/B
GPT12E Timer T5 Count/Gate Input
37
39
Data Sheet
Type Function
20
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
40
P2.1
O0 / I St/B
Bit 1 of Port 2, General Purpose Input/Output
TxDC0
O1
St/B
CAN Node 0 Transmit Data Output
CCU63_CC6
1
O2
St/B
CCU63 Channel 1 Output
AD14
OH / I St/B
External Bus Interface Address/Data Line 14
RxDC5C
I
St/B
CAN Node 5 Receive Data Input
CCU63_CC6
1INB
I
St/B
CCU63 Channel 1 Input
T5EUDB
I
St/B
GPT12E Timer T5 External Up/Down Control
Input
ESR1_5
I
St/B
ESR1 Trigger Input 5
P2.2
O0 / I St/B
Bit 2 of Port 2, General Purpose Input/Output
TxDC1
O1
St/B
CAN Node 1 Transmit Data Output
CCU63_CC6
2
O2
St/B
CCU63 Channel 2 Output
AD15
OH / I St/B
External Bus Interface Address/Data Line 15
CCU63_CC6
2INB
I
St/B
CCU63 Channel 2 Input
ESR2_5
I
St/B
ESR2 Trigger Input 5
P4.0
O0 / I St/B
Bit 0 of Port 4, General Purpose Input/Output
CC2_CC24
O3 / I St/B
CAPCOM2 CC24IO Capture Inp./ Compare Out.
CS0
OH
External Bus Interface Chip Select 0 Output
P2.3
O0 / I St/B
41
42
43
Type Function
St/B
Bit 3 of Port 2, General Purpose Input/Output
U0C0_DOUT O1
St/B
USIC0 Channel 0 Shift Data Output
CCU63_COU O2
T63
St/B
CCU63 Channel 3 Output
CC2_CC16
O3 / I St/B
CAPCOM2 CC16IO Capture Inp./ Compare Out.
A16
OH
St/B
External Bus Interface Address Line 16
ESR2_0
I
St/B
ESR2 Trigger Input 0
U0C0_DX0E
I
St/B
USIC0 Channel 0 Shift Data Input
U0C1_DX0D
I
St/B
USIC0 Channel 1 Shift Data Input
RxDC0A
I
St/B
CAN Node 0 Receive Data Input
Data Sheet
21
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
44
P4.1
O0 / I St/B
Bit 1 of Port 4, General Purpose Input/Output
U3C0_SELO
3
O1
St/B
USIC3 Channel Select/Control 3 Output
TxDC2
O2
St/B
CAN Node 2 Transmit Data Output
CC2_CC25
O3 / I St/B
CAPCOM2 CC25IO Capture Inp./ Compare Out.
CS1
OH
St/B
External Bus Interface Chip Select 1 Output
CCU62_CCP I
OS0B
St/B
CCU62 Position Input 0
T4EUDB
I
St/B
GPT12E Timer T4 External Up/Down Control
Input
ESR1_8
I
St/B
ESR1 Trigger Input 8
P2.4
O0 / I St/B
45
46
Type Function
Bit 4 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
TxDC0
O2
St/B
CAN Node 0 Transmit Data Output
CC2_CC17
O3 / I St/B
CAPCOM2 CC17IO Capture Inp./ Compare Out.
A17
OH
St/B
External Bus Interface Address Line 17
ESR1_0
I
St/B
ESR1 Trigger Input 0
U0C0_DX0F
I
St/B
USIC0 Channel 0 Shift Data Input
RxDC1A
I
St/B
CAN Node 1 Receive Data Input
P2.5
O0 / I St/B
Bit 5 of Port 2, General Purpose Input/Output
U0C0_SCLK
OUT
O1
St/B
USIC0 Channel 0 Shift Clock Output
TxDC0
O2
St/B
CAN Node 0 Transmit Data Output
CC2_CC18
O3 / I St/B
CAPCOM2 CC18IO Capture Inp./ Compare Out.
A18
OH
St/B
External Bus Interface Address Line 18
U0C0_DX1D
I
St/B
USIC0 Channel 0 Shift Clock Input
ESR1_10
I
St/B
ESR1 Trigger Input 10
Data Sheet
22
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
47
P4.2
O0 / I St/B
Bit 2 of Port 4, General Purpose Input/Output
U3C0_SCLK
OUT
O1
St/B
USIC3 Channel 0 Shift Clock Output
TxDC2
O2
St/B
CAN Node 2 Transmit Data Output
CC2_CC26
O3 / I St/B
CAPCOM2 CC26IO Capture Inp./ Compare Out.
CS2
OH
St/B
External Bus Interface Chip Select 2 Output
T2INA
I
St/B
GPT12E Timer T2 Count/Gate Input
CCU62_CCP I
OS1B
St/B
CCU62 Position Input 1
U3C0_DX1B
I
St/B
USIC3 Channel 0 Shift Clock Input
P2.6
O0 / I St/B
Bit 6 of Port 2, General Purpose Input/Output
U0C0_SELO
0
O1
St/B
USIC0 Channel 0 Select/Control 0 Output
U0C1_SELO
1
O2
St/B
USIC0 Channel 1 Select/Control 1 Output
CC2_CC19
O3 / I St/B
CAPCOM2 CC19IO Capture Inp./ Compare Out.
A19
OH
St/B
External Bus Interface Address Line 19
U0C0_DX2D
I
St/B
USIC0 Channel 0 Shift Control Input
RxDC0D
I
St/B
CAN Node 0 Receive Data Input
ESR2_6
I
St/B
ESR2 Trigger Input 6
P4.3
O0 / I St/B
48
49
U0C1_DOUT O1
Type Function
St/B
Bit 3 of Port 4, General Purpose Input/Output
USIC0 Channel 1 Shift Data Output
CC2_CC27
O3 / I St/B
CAPCOM2 CC27IO Capture Inp./ Compare Out.
CS3
OH
St/B
External Bus Interface Chip Select 3 Output
RxDC2A
I
St/B
CAN Node 2 Receive Data Input
T2EUDA
I
St/B
GPT12E Timer T2 External Up/Down Control
Input
CCU62_CCP I
OS2B
St/B
CCU62 Position Input 2
Data Sheet
23
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
53
P0.0
O0 / I St/B
54
55
Type Function
Bit 0 of Port 0, General Purpose Input/Output
U1C0_DOUT O1
St/B
USIC1 Channel 0 Shift Data Output
CCU61_CC6
0
O3
St/B
CCU61 Channel 0 IOutput
A0
OH
St/B
External Bus Interface Address Line 0
U1C0_DX0A
I
St/B
USIC1 Channel 0 Shift Data Input
CCU61_CC6
0INA
I
St/B
CCU61 Channel 0 Input
ESR1_11
I
St/B
ESR1 Trigger Input 11
P2.7
O0 / I St/B
Bit 7 of Port 2, General Purpose Input/Output
U0C1_SELO
0
O1
St/B
USIC0 Channel 1 Select/Control 0 Output
U0C0_SELO
1
O2
St/B
USIC0 Channel 0 Select/Control 1 Output
CC2_CC20
O3 / I St/B
CAPCOM2 CC20IO Capture Inp./ Compare Out.
A20
OH
St/B
External Bus Interface Address Line 20
U0C1_DX2C
I
St/B
USIC0 Channel 1 Shift Control Input
RxDC1C
I
St/B
CAN Node 1 Receive Data Input
ESR2_7
I
St/B
ESR2 Trigger Input 7
P0.1
O0 / I St/B
Bit 1 of Port 0, General Purpose Input/Output
U1C0_DOUT O1
St/B
USIC1 Channel 0 Shift Data Output
TxDC0
O2
St/B
CAN Node 0 Transmit Data Output
CCU61_CC6
1
O3
St/B
CCU61 Channel 1 Output
A1
OH
St/B
External Bus Interface Address Line 1
U1C0_DX0B
I
St/B
USIC1 Channel 0 Shift Data Input
CCU61_CC6
1INA
I
St/B
CCU61 Channel 1 Input
U1C0_DX1A
I
St/B
USIC1 Channel 0 Shift Clock Input
Data Sheet
24
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
Type Function
56
P2.8
O0 / I DP/B Bit 8 of Port 2, General Purpose Input/Output
U0C1_SCLK
OUT
O1
DP/B USIC0 Channel 1 Shift Clock Output
EXTCLK
O2
DP/B Programmable Clock Signal Output
1)
57
58
CC2_CC21
O3 / I DP/B CAPCOM2 CC21IO Capture Inp./ Compare Out.
A21
OH
DP/B External Bus Interface Address Line 21
U0C1_DX1D
I
DP/B USIC0 Channel 1 Shift Clock Input
P2.9
O0 / I St/B
Bit 9 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
TxDC1
O2
St/B
CAN Node 1 Transmit Data Output
CC2_CC22
O3 / I St/B
CAPCOM2 CC22IO Capture Inp./ Compare Out.
A22
OH
St/B
External Bus Interface Address Line 22
CLKIN1
I
St/B
Clock Signal Input 1
TCK_A
I
St/B
DAP0/JTAG Clock Input
P0.2
O0 / I St/B
Bit 2 of Port 0, General Purpose Input/Output
U1C0_SCLK
OUT
O1
St/B
USIC1 Channel 0 Shift Clock Output
TxDC0
O2
St/B
CAN Node 0 Transmit Data Output
CCU61_CC6
2
O3
St/B
CCU61 Channel 2 Output
A2
OH
St/B
External Bus Interface Address Line 2
U1C0_DX1B
I
St/B
USIC1 Channel 0 Shift Clock Input
CCU61_CC6
2INA
I
St/B
CCU61 Channel 2 Input
Data Sheet
25
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
59
P10.0
O0 / I St/B
60
61
Type Function
Bit 0 of Port 10, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
CCU60_CC6
0
O2
St/B
CCU60 Channel 0 Output
AD0
OH / I St/B
External Bus Interface Address/Data Line 0
CCU60_CC6
0INA
I
St/B
CCU60 Channel 0 Input
ESR1_2
I
St/B
ESR1 Trigger Input 2
U0C0_DX0A
I
St/B
USIC0 Channel 0 Shift Data Input
U0C1_DX0A
I
St/B
USIC0 Channel 1 Shift Data Input
P10.1
O0 / I St/B
Bit 1 of Port 10, General Purpose Input/Output
U0C0_DOUT O1
St/B
USIC0 Channel 0 Shift Data Output
CCU60_CC6
1
O2
St/B
CCU60 Channel 1 Output
AD1
OH / I St/B
External Bus Interface Address/Data Line 1
CCU60_CC6
1INA
I
St/B
CCU60 Channel 1 Input
U0C0_DX1A
I
St/B
USIC0 Channel 0 Shift Clock Input
U0C0_DX0B
I
St/B
USIC0 Channel 0 Shift Data Input
P0.3
O0 / I St/B
Bit 3 of Port 0, General Purpose Input/Output
U1C0_SELO
0
O1
St/B
USIC1 Channel 0 Select/Control 0 Output
U1C1_SELO
1
O2
St/B
USIC1 Channel 1 Select/Control 1 Output
CCU61_COU O3
T60
St/B
CCU61 Channel 0 Output
A3
OH
St/B
External Bus Interface Address Line 3
U1C0_DX2A
I
St/B
USIC1 Channel 0 Shift Control Input
RxDC0B
I
St/B
CAN Node 0 Receive Data Input
Data Sheet
26
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
62
P10.2
O0 / I St/B
Bit 2 of Port 10, General Purpose Input/Output
U0C0_SCLK
OUT
O1
St/B
USIC0 Channel 0 Shift Clock Output
CCU60_CC6
2
O2
St/B
CCU60 Channel 2 Output
U3C0_SELO
1
O3
St/B
USIC3 Channel 0 Select/Control 1 Output
AD2
OH / I St/B
External Bus Interface Address/Data Line 2
CCU60_CC6
2INA
I
St/B
CCU60 Channel 2 Input
U0C0_DX1B
I
St/B
USIC0 Channel 0 Shift Clock Input
U3C0_DX2B
I
St/B
USIC3 Channel 0 Shift Control Input
P0.4
O0 / I St/B
Bit 4 of Port 0, General Purpose Input/Output
U1C1_SELO
0
O1
St/B
USIC1 Channel 1 Select/Control 0 Output
U1C0_SELO
1
O2
St/B
USIC1 Channel 0 Select/Control 1 Output
CCU61_COU O3
T61
St/B
CCU61 Channel 1 Output
A4
OH
St/B
External Bus Interface Address Line 4
U1C1_DX2A
I
St/B
USIC1 Channel 1 Shift Control Input
RxDC1B
I
St/B
CAN Node 1 Receive Data Input
ESR2_8
I
St/B
ESR2 Trigger Input 8
P2.13
O0 / I St/B
Bit 13 of Port 2, General Purpose Input/Output
U2C1_SELO
2
O1
St/B
USIC2 Channel 1 Select/Control 2 Output
RxDC2D
I
St/B
CAN Node 2 Receive Data Input
63
65
Data Sheet
Type Function
27
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
66
P2.10
O0 / I St/B
67
Bit 10 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
U0C0_SELO
3
O2
St/B
USIC0 Channel 0 Select/Control 3 Output
CC2_CC23
O3 / I St/B
CAPCOM2 CC23IO Capture Inp./ Compare Out.
A23
OH
St/B
External Bus Interface Address Line 23
U0C1_DX0E
I
St/B
USIC0 Channel 1 Shift Data Input
CAPINA
I
St/B
GPT12E Register CAPREL Capture Input
U3C1_DX0A
I
St/B
USIC3 Channel 1 Shift Data Input
P10.3
O0 / I St/B
CCU60_COU O2
T60
68
Type Function
St/B
Bit 3 of Port 10, General Purpose Input/Output
CCU60 Channel 0 Output
AD3
OH / I St/B
External Bus Interface Address/Data Line 3
U0C0_DX2A
I
St/B
USIC0 Channel 0 Shift Control Input
U0C1_DX2A
I
St/B
USIC0 Channel 1 Shift Control Input
U3C0_DX0A
I
St/B
USIC3 Channel 0 Shift Data Input
P0.5
O0 / I St/B
Bit 5 of Port 0, General Purpose Input/Output
U1C1_SCLK
OUT
O1
St/B
USIC1 Channel 1 Shift Clock Output
U1C0_SELO
2
O2
St/B
USIC1 Channel 0 Select/Control 2 Output
CCU61_COU O3
T62
St/B
CCU61 Channel 2 Output
A5
OH
St/B
External Bus Interface Address Line 5
U1C1_DX1A
I
St/B
USIC1 Channel 1 Shift Clock Input
U1C0_DX1C
I
St/B
USIC1 Channel 0 Shift Clock Input
RXDC3E
I
St/B
CAN Node 3 Receive Data Input
Data Sheet
28
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
69
P10.4
O0 / I St/B
Bit 4 of Port 10, General Purpose Input/Output
U0C0_SELO
3
O1
St/B
USIC0 Channel 0 Select/Control 3 Output
CCU60_COU O2
T61
St/B
CCU60 Channel 1 Output
U3C0_DOUT O3
St/B
USIC3 Channel 0 Shift Data Output
70
71
Type Function
AD4
OH / I St/B
External Bus Interface Address/Data Line 4
U0C0_DX2B
I
St/B
USIC0 Channel 0 Shift Control Input
U0C1_DX2B
I
St/B
USIC0 Channel 1 Shift Control Input
ESR1_9
I
St/B
ESR1 Trigger Input 9
P10.5
O0 / I St/B
Bit 5 of Port 10, General Purpose Input/Output
U0C1_SCLK
OUT
O1
St/B
USIC0 Channel 1 Shift Clock Output
CCU60_COU O2
T62
St/B
CCU60 Channel 2 Output
U2C0_DOUT O3
St/B
USIC2 Channel 0 Shift Data Output
AD5
OH / I St/B
External Bus Interface Address/Data Line 5
U0C1_DX1B
I
USIC0 Channel 1 Shift Clock Input
P0.6
O0 / I St/B
St/B
Bit 6 of Port 0, General Purpose Input/Output
U1C1_DOUT O1
St/B
USIC1 Channel 1 Shift Data Output
TxDC1
O2
St/B
CAN Node 1 Transmit Data Output
CCU61_COU O3
T63
St/B
CCU61 Channel 3 Output
A6
OH
St/B
External Bus Interface Address Line 6
U1C1_DX0A
I
St/B
USIC1 Channel 1 Shift Data Input
CCU61_CTR
APA
I
St/B
CCU61 Emergency Trap Input
U1C1_DX1B
I
St/B
USIC1 Channel 1 Shift Clock Input
Data Sheet
29
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
72
P10.6
O0 / I St/B
73
74
Type Function
Bit 6 of Port 10, General Purpose Input/Output
U0C0_DOUT O1
St/B
USIC0 Channel 0 Shift Data Output
TxDC4
O2
St/B
CAN Node 4 Transmit Data Output
U1C0_SELO
0
O3
St/B
USIC1 Channel 0 Select/Control 0 Output
AD6
OH / I St/B
External Bus Interface Address/Data Line 6
U0C0_DX0C
I
St/B
USIC0 Channel 0 Shift Data Input
U1C0_DX2D
I
St/B
USIC1 Channel 0 Shift Control Input
CCU60_CTR
APA
I
St/B
CCU60 Emergency Trap Input
P10.7
O0 / I St/B
Bit 7 of Port 10, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
CCU60_COU O2
T63
St/B
CCU60 Channel 3 Output
AD7
OH / I St/B
External Bus Interface Address/Data Line 7
U0C1_DX0B
I
St/B
USIC0 Channel 1 Shift Data Input
CCU60_CCP I
OS0A
St/B
CCU60 Position Input 0
RxDC4C
I
St/B
CAN Node 4 Receive Data Input
T4INB
I
St/B
GPT12E Timer T4 Count/Gate Input
P0.7
O0 / I St/B
Bit 7 of Port 0, General Purpose Input/Output
U1C1_DOUT O1
St/B
USIC1 Channel 1 Shift Data Output
U1C0_SELO
3
O2
St/B
USIC1 Channel 0 Select/Control 3 Output
TxDC3
O3
St/B
CAN Node 3 Transmit Data Output
A7
OH
St/B
External Bus Interface Address Line 7
U1C1_DX0B
I
St/B
USIC1 Channel 1 Shift Data Input
CCU61_CTR
APB
I
St/B
CCU61 Emergency Trap Input
Data Sheet
30
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
78
P1.0
O0 / I St/B
Bit 0 of Port 1, General Purpose Input/Output
U1C0_MCLK
OUT
O1
St/B
USIC1 Channel 0 Master Clock Output
U1C0_SELO
4
O2
St/B
USIC1 Channel 0 Select/Control 4 Output
A8
OH
St/B
External Bus Interface Address Line 8
ESR1_3
I
St/B
ESR1 Trigger Input 3
CCU62_CTR
APB
I
St/B
CCU62 Emergency Trap Input
T6INB
I
St/B
GPT12E Timer T6 Count/Gate Input
P10.8
O0 / I St/B
Bit 8 of Port 10, General Purpose Input/Output
U0C0_MCLK
OUT
O1
St/B
USIC0 Channel 0 Master Clock Output
U0C1_SELO
0
O2
St/B
USIC0 Channel 1 Select/Control 0 Output
U2C1_DOUT O3
St/B
USIC2 Channel 1 Shift Data Output
79
AD8
80
Type Function
OH / I St/B
External Bus Interface Address/Data Line 8
CCU60_CCP I
OS1A
St/B
CCU60 Position Input 1
U0C0_DX1C
I
St/B
USIC0 Channel 0 Shift Clock Input
BRKIN_B
I
St/B
OCDS Break Signal Input
T3EUDB
I
St/B
GPT12E Timer T3 External Up/Down Control
Input
P10.9
O0 / I St/B
Bit 9 of Port 10, General Purpose Input/Output
U0C0_SELO
4
O1
St/B
USIC0 Channel 0 Select/Control 4 Output
U0C1_MCLK
OUT
O2
St/B
USIC0 Channel 1 Master Clock Output
AD9
OH / I St/B
External Bus Interface Address/Data Line 9
CCU60_CCP I
OS2A
St/B
CCU60 Position Input 2
TCK_B
I
St/B
DAP0/JTAG Clock Input
T3INB
I
St/B
GPT12E Timer T3 Count/Gate Input
Data Sheet
31
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
81
P1.1
O0 / I St/B
82
83
Type Function
Bit 1 of Port 1, General Purpose Input/Output
CCU62_COU O1
T62
St/B
CCU62 Channel 2 Output
U1C0_SELO
5
O2
St/B
USIC1 Channel 0 Select/Control 5 Output
U2C1_DOUT O3
St/B
USIC2 Channel 1 Shift Data Output
A9
OH
St/B
External Bus Interface Address Line 9
ESR2_3
I
St/B
ESR2 Trigger Input 3
U2C1_DX0C
I
St/B
USIC2 Channel 1 Shift Data Input
P10.10
O0 / I St/B
Bit 10 of Port 10, General Purpose Input/Output
U0C0_SELO
0
O1
St/B
USIC0 Channel 0 Select/Control 0 Output
CCU60_COU O2
T63
St/B
CCU60 Channel 3 Output
AD10
OH / I St/B
External Bus Interface Address/Data Line 10
U0C0_DX2C
I
St/B
USIC0 Channel 0 Shift Control Input
U0C1_DX1A
I
St/B
USIC0 Channel 1 Shift Clock Input
TDI_B
I
St/B
JTAG Test Data Input
P10.11
O0 / I St/B
Bit 11 of Port 10, General Purpose Input/Output
U1C0_SCLK
OUT
O1
St/B
USIC1 Channel 0 Shift Clock Output
BRKOUT
O2
St/B
OCDS Break Signal Output
U3C0_SELO
0
O3
St/B
USIC3 Channel 0 Select/Control 0 Output
AD11
OH / I St/B
External Bus Interface Address/Data Line 11
U1C0_DX1D
I
St/B
USIC1 Channel 0 Shift Clock Input
RxDC2B
I
St/B
CAN Node 2 Receive Data Input
TMS_B
I
St/B
JTAG Test Mode Selection Input
U3C0_DX2A
I
St/B
USIC3 Channel 0 Shift Control Input
Data Sheet
32
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
84
P1.2
O0 / I St/B
Bit 2 of Port 1, General Purpose Input/Output
CCU62_CC6
2
O1
St/B
CCU62 Channel 2 Output
U1C0_SELO
6
O2
St/B
USIC1 Channel 0 Select/Control 6 Output
U2C1_SCLK
OUT
O3
St/B
USIC2 Channel 1 Shift Clock Output
A10
OH
St/B
External Bus Interface Address Line 10
ESR1_4
I
St/B
ESR1 Trigger Input 4
CCU61_T12
HRB
I
St/B
External Run Control Input for T12 of CCU61
CCU62_CC6
2INA
I
St/B
CCU62 Channel 2 Input
U2C1_DX0D
I
St/B
USIC2 Channel 1 Shift Data Input
U2C1_DX1C
I
St/B
USIC2 Channel 1 Shift Clock Input
P10.12
O0 / I St/B
85
86
Type Function
Bit 12 of Port 10, General Purpose Input/Output
U1C0_DOUT O1
St/B
USIC1 Channel 0 Shift Data Output
TxDC2
O2
St/B
CAN Node 2 Transmit Data Output
TDO_B
OH / I St/B
JTAG Test Data Output / DAP1 Input/Output
AD12
OH / I St/B
External Bus Interface Address/Data Line 12
U1C0_DX0C
I
St/B
USIC1 Channel 0 Shift Data Input
U1C0_DX1E
I
St/B
USIC1 Channel 0 Shift Clock Input
P10.13
O0 / I St/B
Bit 13 of Port 10, General Purpose Input/Output
U1C0_DOUT O1
St/B
USIC1 Channel 0 Shift Data Output
TxDC3
O2
St/B
CAN Node 3 Transmit Data Output
U1C0_SELO
3
O3
St/B
USIC1 Channel 0 Select/Control 3 Output
WR/WRL
OH
St/B
External Bus Interface Write Strobe Output
Active for each external write access, when WR,
active for ext. writes to the low byte, when WRL.
U1C0_DX0D
I
St/B
USIC1 Channel 0 Shift Data Input
Data Sheet
33
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
87
P1.3
O0 / I St/B
89
90
Type Function
Bit 3 of Port 1, General Purpose Input/Output
CCU62_COU O1
T63
St/B
CCU62 Channel 3 Output
U1C0_SELO
7
O2
St/B
USIC1 Channel 0 Select/Control 7 Output
U2C0_SELO
4
O3
St/B
USIC2 Channel 0 Select/Control 4 Output
A11
OH
St/B
External Bus Interface Address Line 11
ESR2_4
I
St/B
ESR2 Trigger Input 4
CCU62_T12
HRB
I
St/B
External Run Control Input for T12 of CCU62
P10.14
O0 / I St/B
Bit 14 of Port 10, General Purpose Input/Output
U1C0_SELO
1
O1
St/B
USIC1 Channel 0 Select/Control 1 Output
U0C1_DOUT O2
St/B
USIC0 Channel 1 Shift Data Output
U3C0_SCLK
OUT
O3
St/B
USIC3 Channel 0 Shift Clock Output
RD
OH
St/B
External Bus Interface Read Strobe Output
ESR2_2
I
St/B
ESR2 Trigger Input 2
U0C1_DX0C
I
St/B
USIC0 Channel 1 Shift Data Input
RxDC3C
I
St/B
CAN Node 3 Receive Data Input
U3C0_DX1A
I
St/B
USIC3 Channel 0 Shift Clock Input
P1.4
O0 / I St/B
Bit 4 of Port 1, General Purpose Input/Output
CCU62_COU O1
T61
St/B
CCU62 Channel 1 Output
U1C1_SELO
4
O2
St/B
USIC1 Channel 1 Select/Control 4 Output
U2C0_SELO
5
O3
St/B
USIC2 Channel 0 Select/Control 5 Output
A12
OH
St/B
External Bus Interface Address Line 12
U2C0_DX2B
I
St/B
USIC2 Channel 0 Shift Control Input
RxDC5A
I
St/B
CAN Node 5 Receive Data Input
Data Sheet
34
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
91
P10.15
O0 / I St/B
Bit 15 of Port 10, General Purpose Input/Output
U1C0_SELO
2
O1
St/B
USIC1 Channel 0 Select/Control 2 Output
U0C1_DOUT O2
St/B
USIC0 Channel 1 Shift Data Output
U1C0_DOUT O3
St/B
USIC1 Channel 0 Shift Data Output
ALE
OH
St/B
External Bus Interf. Addr. Latch Enable Output
U0C1_DX1C
I
St/B
USIC0 Channel 1 Shift Clock Input
P1.5
O0 / I St/B
92
93
Type Function
Bit 5 of Port 1, General Purpose Input/Output
CCU62_COU O1
T60
St/B
CCU62 Channel 0 Output
U1C1_SELO
3
O2
St/B
USIC1 Channel 1 Select/Control 3 Output
BRKOUT
O3
St/B
OCDS Break Signal Output
A13
OH
St/B
External Bus Interface Address Line 13
U2C0_DX0C
I
St/B
USIC2 Channel 0 Shift Data Input
P1.6
O0 / I St/B
Bit 6 of Port 1, General Purpose Input/Output
CCU62_CC6
1
O1 / I St/B
CCU62 Channel 1 Output
U1C1_SELO
2
O2
St/B
USIC1 Channel 1 Select/Control 2 Output
U2C0_DOUT O3
St/B
USIC2 Channel 0 Shift Data Output
A14
OH
St/B
External Bus Interface Address Line 14
U2C0_DX0D
I
St/B
USIC2 Channel 0 Shift Data Input
CCU62_CC6
1INA
I
St/B
CCU62 Channel 1 Input
Data Sheet
35
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
94
P1.7
O0 / I St/B
Bit 7 of Port 1, General Purpose Input/Output
CCU62_CC6
0
O1
St/B
CCU62 Channel 0 Output
U1C1_MCLK
OUT
O2
St/B
USIC1 Channel 1 Master Clock Output
U2C0_SCLK
OUT
O3
St/B
USIC2 Channel 0 Shift Clock Output
A15
OH
St/B
External Bus Interface Address Line 15
U2C0_DX1C
I
St/B
USIC2 Channel 0 Shift Clock Input
CCU62_CC6
0INA
I
St/B
CCU62 Channel 0 Input
RxDC4E
I
St/B
CAN Node 4 Receive Data Input
95
XTAL2
O
Sp/M Crystal Oscillator Amplifier Output
96
XTAL1
I
Sp/M Crystal Oscillator Amplifier Input
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Voltages on XTAL1 must comply to the core
supply voltage VDDIM.
ESR2_9
I
St/B
ESR2 Trigger Input 9
97
PORST
I
In/B
Power On Reset Input
A low level at this pin resets the XC226xM
completely. A spike filter suppresses input pulses
<10 ns. Input pulses >100 ns safely pass the filter.
The minimum duration for a safe recognition
should be 120 ns.
An internal pullup device will hold this pin high
when nothing is driving it.
98
ESR1
O0 / I St/B
External Service Request 1
RxDC0E
I
St/B
CAN Node 0 Receive Data Input
U1C0_DX0F
I
St/B
USIC1 Channel 0 Shift Data Input
U1C0_DX2C
I
St/B
USIC1 Channel 0 Shift Control Input
U1C1_DX0C
I
St/B
USIC1 Channel 1 Shift Data Input
U1C1_DX2B
I
St/B
USIC1 Channel 1 Shift Control Input
U2C1_DX2C
I
St/B
USIC2 Channel 1 Shift Control Input
Data Sheet
Type Function
36
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
Type Function
99
ESR0
O0 / I St/B
External Service Request 0
Note: After power-up, ESR0 operates as opendrain bidirectional reset with a weak pull-up.
U1C0_DX0E
I
St/B
USIC1 Channel 0 Shift Data Input
U1C0_DX2B
I
St/B
USIC1 Channel 0 Shift Control Input
10
VDDIM
-
PS/M Digital Core Supply Voltage for Domain M
Decouple with a ceramic capacitor, see Table 13
for details.
38,
64,
88
VDDI1
-
PS/1 Digital Core Supply Voltage for Domain 1
Decouple with a ceramic capacitor, see Table 13
for details.
All VDDI1 pins must be connected to each other.
14
VDDPA
-
PS/A Digital Pad Supply Voltage for Domain A
Connect decoupling capacitors to adjacent VDDP/
VSS pin pairs as close as possible to the pins.
Note: The A/D_Converters and ports P5, P6 and
P15 are fed from supply voltage VDDPA.
2,
25,
27,
50,
52,
75,
77,
100
VDDPB
1,
26,
51,
76
VSS
-
PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent VDDP/
VSS pin pairs as close as possible to the pins.
Note: The on-chip voltage regulators and all ports
except P5, P6 and P15 are fed from supply
voltage VDDPB.
Data Sheet
-
PS/-- Digital Ground
All VSS pins must be connected to the ground-line
or ground-plane.
Note: Also the exposed pad is connected
internally to VSS. To improve the EMC
behavior, it is recommended to connect the
exposed pad to the board ground.
For thermal aspects, please refer to
Section 5.1. Board layout examples are
given in an application note.
37
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
General Device Information
1) To generate the reference clock output for bus timing measurement, fSYS must be selected as source for
EXTCLK and P2.8 must be selected as output pin. Also the high-speed clock pad must be enabled. This
configuration is referred to as reference clock output signal CLKOUT.
Data Sheet
38
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3
Functional Description
The architecture of the XC226xM combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 3). This bus structure enhances overall system performance by
enabling the concurrent operation of several subsystems of the XC226xM.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XC226xM.
DPRAM
EBC
LXBus Control
External Bus
Control
CPU
DMU
Flash Memory
OCDS
Debug Support
DSRAM
PMU
IMB
PSRAM
MAC Unit
System Functions
Clock, Reset, Power
Control, StandBy RAM
MPU
WDT
Interrupt & PEC
LXBus
MCHK
RTC
ADC1 ADC0
8-Bit
8-Bit
10-Bit 10-Bit
GPT
T2
T3
T4
..
CC2
CCU6x
CCU60
T7
T12
T12
T8
T13
T13
T5
T6
BRGen
..
Periph eral Data Bu s
Interrupt Bus
USICx
2 Ch.,
64 x
Buffer
RS232,
LIN,
SPI,
IIC, IIS
..
..
USIC0
2 Ch.,
64 x
Buffer
Multi
CAN
RS232,
LIN,
SPI,
IIC , IIS
Analog and Digital General Purpose IO (GPIO) Ports
MC_XY_BLOCKDIAGRAM
Figure 3
Data Sheet
Block Diagram
39
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC226xM is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
Table 6
XC226xM Memory Map
Address Area
Start Loc.
End Loc.
Area Size1)
Notes
IMB register space
FF’FF00H
FF’FFFFH
256 Bytes
–
Reserved (Access trap) F0’0000H
FF’FEFFH
<1 Mbyte
Minus IMB registers
Reserved for EPSRAM E8’8000H
EF’FFFFH
480 Kbytes
Mirrors EPSRAM
Emulated PSRAM
E8’0000H
E8’7FFFH
32 Kbytes
Flash timing
Reserved for PSRAM
E0’8000H
E7’FFFFH
480 Kbytes
Mirrors PSRAM
Program SRAM
E0’0000H
E0’7FFFH
32 Kbytes
Maximum speed
Reserved for Flash
CD’0000H
DF’FFFFH
<1.25 Mbytes –
Program Flash 3
CC’0000H
CC’FFFFH
64 Kbytes
–
Program Flash 2
C8’0000H
CB’FFFFH
256 Kbytes
–
Program Flash 1
C4’0000H
C7’FFFFH
256 Kbytes
–
Program Flash 0
C0’0000H
C3’FFFFH
256 Kbytes
2)
External memory area
40’0000H
BF’FFFFH
8 Mbytes
–
Available Ext. IO area3) 21’0000H
3F’FFFFH
< 2 Mbytes
Minus USIC/CAN
Data Sheet
40
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
Table 6
XC226xM Memory Map (cont’d)
Address Area
Start Loc.
End Loc.
Area Size1)
Notes
Reserved
20’C000H
20’FFFFH
16 Kbytes
–
MultiCAN/USIC regs.
20’8000H
20’BFFFH
16 Kbytes
Alternate location4)
Reserved
20’6000H
20’7FFFH
8 Kbytes
–
USIC registers
20’4000H
20’5FFFH
8 Kbytes
Accessed via EBC
MultiCAN registers
20’0000H
20’3FFFH
16 Kbytes
Accessed via EBC
External memory area
01’0000H
1F’FFFFH
< 2 Mbytes
Minus segment 0
SFR area
00’FE00H
00’FFFFH
0.5 Kbyte
–
Dual-Port RAM
00’F600H
00’FDFFH
2 Kbytes
–
Reserved for DPRAM
00’F200H
00’F5FFH
1 Kbyte
–
ESFR area
00’F000H
00’F1FFH
0.5 Kbyte
–
XSFR area
00’E000H
00’EFFFH
4 Kbytes
–
Data SRAM
00’A000H
00’DFFFH
16 Kbytes
–
Reserved for DSRAM
00’8000H
00’9FFFH
8 Kbytes
–
External memory area
00’0000H
00’7FFFH
32 Kbytes
–
1) The areas marked with “<” are slightly smaller than indicated. See column “Notes”.
2) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH).
3) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
4) The alternate location for USIC and MultiCAN registers allows access to these modules using the same data
page pointer.
Up to 32 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code
or data. The PSRAM is accessed via the PMU and is optimized for code fetches. A
section of the PSRAM with programmable size can be write-protected.
Note: The actual size of the PSRAM depends on the quoted device type.
16 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data.
The DSRAM is accessed via a separate interface and is optimized for data access.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined
variables, for the system stack, and for general purpose register banks. A register bank
can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7,
RH7) General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR,
any location in the DPRAM is bit addressable.
Data Sheet
41
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
8 Kbytes of on-chip Stand-By SRAM (SBRAM) provide storage for system-relevant
user data that must be preserved while the major part of the device is powered down.
The SBRAM is accessed via a specific interface and is powered in domain M.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are word-wide registers which are
used to control and monitor functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC2000 Family. In order to to ensure
upward compatibility they should either not be accessed or written with zeros.
In order to meet the requirements of designs where more memory is required than is
available on chip, up to 12 Mbytes (approximately, see Table 6) of external RAM and/or
ROM can be connected to the microcontroller. The External Bus Interface also provides
access to external peripherals.
The on-chip Flash memory stores code, constant data, and control data. The on-chip
Flash memory consists of one 64-Kbyte module (preferably for data storage) and
modules with a maximum capacity of 256 Kbytes each. Each module is organized in
sectors of 4 Kbytes.
The uppermost 4-Kbyte sector of segment 0 (located in Flash module 0) is used
internally to store operation control parameters and protection information.
Note: The actual size of the Flash memory depends on the chosen device type.
Each sector can be separately write protected1), erased and programmed (in blocks of
128 Bytes). The complete Flash area can be read-protected. A user-defined password
sequence temporarily unlocks protected areas. The Flash modules combine 128-bit
read access with protected and efficient writing algorithms for programming and erasing.
Dynamic error correction provides extremely high read data security for all read access
operations. Access to different Flash modules can be executed in parallel.
For Flash parameters, please see Section 4.5.
Memory Content Protection
The contents of on-chip memories can be protected against soft errors (induced e.g. by
radiation) by activating the parity mechanism or the Error Correction Code (ECC).
The parity mechanism can detect a single-bit error and prevent the software from using
incorrect data or executing incorrect instructions.
The ECC mechanism can detect and automatically correct single-bit errors. This
supports the stable operation of the system.
It is strongly recommended to activate the ECC mechanism wherever possible because
this dramatically increases the robustness of an application against such soft errors.
1) To save control bits, sectors are clustered for protection purposes, they remain separate for
programming/erasing.
Data Sheet
42
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.2
External Bus Controller
All external memory access operations are performed by a special on-chip External Bus
Controller (EBC). The EBC also controls access to resources connected to the on-chip
LXBus (MultiCAN and the USIC modules). The LXBus is an internal representation of
the external bus that allows access to integrated peripherals and modules in the same
way as to external components.
The EBC can be programmed either to Single Chip Mode, when no external memory is
required, or to an external bus mode with the following selections1):
•
•
•
Address Bus Width with a range of 0 … 24-bit
Data Bus Width 8-bit or 16-bit
Bus Operation Multiplexed or Demultiplexed
The bus interface uses Port 10 and Port 2 for addresses and data. In the demultiplexed
bus modes, the lower addresses are output separately on Port 0 and Port 1. The number
of active segment address lines is selectable, restricting the external address space to
8 Mbytes … 64 Kbytes. This is required when interface lines shall be assigned to Port 2.
External CS signals (address windows plus default) can be generated and output on
Port 4 in order to save external glue logic. External modules can be directly connected
to the common address/data bus and their individual select lines.
Important timing characteristics of the external bus interface are programmable (with
registers TCONCSx/FCONCSx) to allow the user to adapt it to a wide range of different
types of memories and external peripherals.
Access to very slow memories or modules with varying access times is supported by a
special ‘Ready’ function. The active level of the control input signal is selectable.
In addition, up to four independent address windows may be defined (using registers
ADDRSELx) to control access to resources with different bus characteristics. These
address windows are arranged hierarchically where window 4 overrides window 3, and
window 2 overrides window 1. All accesses to locations not covered by these four
address windows are controlled by TCONCS0/FCONCS0. The currently active window
can generate a chip select signal.
The external bus timing is based on the rising edge of the reference clock output
CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.
1) Bus modes are switched dynamically if several address windows with different mode settings are used.
Data Sheet
43
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.3
Central Processing Unit (CPU)
The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instructionfetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and
accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply-and-divide unit, a bit-mask generator, and a barrel
shifter.
PSRAM
Flash/ROM
PMU
CPU
Prefetch
Unit
Branch
Unit
FIFO
CSP
IP
VECSEG
CPUCON1
CPUCON2
Return
Stack
IDX0
IDX1
QX0
QX1
QR0
QR1
+/-
+/-
Multiply
Unit
MRW
+/-
MCW
MSW
MAH
MAL
2-Stage
Prefetch
Pipeline
TFR
Injection/
Exception
Handler
5-Stage
Pipeline
IFU
DPP0
DPP1
DPP2
DPP3
DPRAM
IPIP
SPSEG
SP
STKOV
STKUN
ADU
Division Unit
Bit-Mask-Gen.
Multiply Unit
Barrel-Shifter
MDC
R15
R15
R14
R15
R14
R14
R15
R14
GPRs
GPRs
GPRs
GPRs
R1
R1
R0
R0R1
R0
R1
R0
RF
PSW
+/-
MDH
MDL
ZEROS
ONES
MAC
CP
Buffer
ALU
WB
DSRAM
EBC
Peripherals
DMU
mca04917_x.vsd
Figure 4
Data Sheet
CPU Block Diagram
44
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
With this hardware most XC226xM instructions can be executed in a single machine
cycle of 12.5 ns with an 80-MHz CPU clock. For example, shift and rotate instructions
are always processed during one machine cycle, no matter how many bits are shifted.
Also, multiplication and most MAC instructions execute in one cycle. All multiple-cycle
instructions have been optimized so that they can be executed very fast; for example, a
32-/16-bit division is started within 4 cycles while the remaining cycles are executed in
the background. Another pipeline optimization, the branch target prediction, eliminates
the execution time of branch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 wordwide GPRs each at its disposal. One of these register banks is physically allocated within
the on-chip DPRAM area. A Context Pointer (CP) register determines the base address
of the active register bank accessed by the CPU at any time. The number of these
register bank copies is only restricted by the available internal RAM space. For easy
parameter passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided for storage of temporary data. The system
stack can be allocated to any location within the address space (preferably in the on-chip
RAM area); it is accessed by the CPU with the stack pointer (SP) register. Two separate
SFRs, STKOV and STKUN, are implicitly compared with the stack pointer value during
each stack access to detect stack overflow or underflow.
The high performance of the CPU hardware implementation can be best utilized by the
programmer with the highly efficient XC226xM instruction set. This includes the following
instruction classes:
•
•
•
•
•
•
•
•
•
•
•
•
•
Standard Arithmetic Instructions
DSP-Oriented Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
45
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.4
Memory Protection Unit (MPU)
The XC226xM’s Memory Protection Unit (MPU) protects user-specified memory areas
from unauthorized read, write, or instruction fetch accesses. The MPU can protect the
whole address space including the peripheral area. This completes establisched
mechanisms such as the register security mechanism or stack overrun/underrun
detection.
Four Protection Levels support flexible system programming where operating system,
low level drivers, and applications run on separate levels. Each protection level permits
different access restrictions for instructions and/or data.
Every access is checked (if the MPU is enabled) and an access violating the permission
rules will be marked as invalid and leads to a protection trap.
A set of protection registers for each protection level specifies the address ranges and
the access permissions. Applications requiring more than 4 protection levels can
dynamically re-program the protection registers.
3.5
Memory Checker Module (MCHK)
The XC226xM’s Memory Checker Module calculates a checksum (fractional polynomial
division) on a block of data, often called Cyclic Redundancy Code (CRC). It is based on
a 32-bit linear feedback shift register and may, therefore, also be used to generate
pseudo-random numbers.
The Memory Checker Module is a 16-bit parallel input signature compression circuitry
which enables error detection within a block of data stored in memory, registers, or
communicated e.g. via serial communication lines. It reduces the probability of error
masking due to repeated error patterns by calculating the signature of blocks of data.
The polynomial used for operation is configurable, so most of the commonly used
polynomials may be used. Also, the block size for generating a CRC result is
configurable via a local counter. An interrupt may be generated if testing the current data
block reveals an error.
An autonomous CRC compare circuitry is included to enable redundant error detection,
e.g. to enable higher safety integrity levels.
The Memory Checker Module provides enhanced fault detection (beyond parity or ECC)
for data and instructions in volatile and non volatile memories. This is especially
important for the safety and reliability of embedded systems.
Data Sheet
46
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.6
Interrupt System
With a minimum interrupt response time of 7/111) CPU clocks (in the case of internal
program execution), the XC226xM can react quickly to the occurrence of nondeterministic events.
The architecture of the XC226xM supports several mechanisms for fast and flexible
response to service requests; these can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to be
serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
Where in a standard interrupt service the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the
current CPU activity to perform a PEC service. A PEC service implies a single byte or
word data transfer between any two memory locations with an additional increment of
either the PEC source pointer, the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source-related vector location. PEC services are
particularly well suited to supporting the transmission or reception of blocks of data. The
XC226xM has eight PEC channels, each whith fast interrupt-driven data transfer
capabilities.
Each of the possible interrupt nodes has a separate control register containing an
interrupt request flag, an interrupt enable flag and an interrupt priority bitfield. Each node
can be programmed by its related register to one of sixteen interrupt priority levels. Once
accepted by the CPU, an interrupt service can only be interrupted by a higher-priority
service request. For standard interrupt processing, each possible interrupt node has a
dedicated vector location.
Fast external interrupt inputs can service external interrupts with high-precision
requirements. These fast interrupt inputs feature programmable edge detection (rising
edge, falling edge, or both edges).
Software interrupts are supported by the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
Table 7 shows all of the possible XC226xM interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes) may be
used to generate software-controlled interrupt requests by setting the respective
interrupt request bit (xIR).
1) Depending if the jump cache is used or not.
Data Sheet
47
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
Table 7
XC226xM Interrupt Nodes
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
CAPCOM Register 16
CC2_CC16IC
xx’0040H
10H / 16D
CAPCOM Register 17
CC2_CC17IC
xx’0044H
11H / 17D
CAPCOM Register 18, or
USIC3 Channel 0, Request 3
CC2_CC18IC
xx’0048H
12H / 18D
CAPCOM Register 19, or
USIC3 Channel 1, Request 3
CC2_CC19IC
xx’004CH
13H / 19D
CAPCOM Register 20, or
USIC0 Channel 0, Request 3
CC2_CC20IC
xx’0050H
14H / 20D
CAPCOM Register 21, or
USIC0 Channel 1, Request 3
CC2_CC21IC
xx’0054H
15H / 21D
CAPCOM Register 22, or
USIC1 Channel 0, Request 3
CC2_CC22IC
xx’0058H
16H / 22D
CAPCOM Register 23, or
USIC1 Channel 1, Request 3
CC2_CC23IC
xx’005CH
17H / 23D
CAPCOM Register 24
CC2_CC24IC
xx’0060H
18H / 24D
CAPCOM Register 25
CC2_CC25IC
xx’0064H
19H / 25D
CAPCOM Register 26
CC2_CC26IC
xx’0068H
1AH / 26D
CAPCOM Register 27
CC2_CC27IC
xx’006CH
1BH / 27D
CAPCOM Register 28, or
USIC2 Channel 0, Request 3
CC2_CC28IC
xx’0070H
1CH / 28D
CAPCOM Register 29, or
USIC2 Channel 1, Request 3
CC2_CC29IC
xx’0074H
1DH / 29D
CAPCOM Register 30, or
SCU Request 2
CC2_CC30IC
xx’0078H
1EH / 30D
CAPCOM Register 31, or
SCU Request 3
CC2_CC31IC
xx’007CH
1FH / 31D
GPT1 Timer 2
GPT12E_T2IC
xx’0080H
20H / 32D
GPT1 Timer 3
GPT12E_T3IC
xx’0084H
21H / 33D
GPT1 Timer 4
GPT12E_T4IC
xx’0088H
22H / 34D
GPT2 Timer 5
GPT12E_T5IC
xx’008CH
23H / 35D
GPT2 Timer 6
GPT12E_T6IC
xx’0090H
24H / 36D
GPT2 CAPREL Register
GPT12E_CRIC
xx’0094H
25H / 37D
Data Sheet
48
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
Table 7
XC226xM Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
CAPCOM Timer 7
CC2_T7IC
xx’0098H
26H / 38D
CAPCOM Timer 8
CC2_T8IC
xx’009CH
27H / 39D
A/D Converter Request 0
ADC_0IC
xx’00A0H
28H / 40D
A/D Converter Request 1
ADC_1IC
xx’00A4H
29H / 41D
A/D Converter Request 2
ADC_2IC
xx’00A8H
2AH / 42D
A/D Converter Request 3
ADC_3IC
xx’00ACH
2BH / 43D
A/D Converter Request 4
ADC_4IC
xx’00B0H
2CH / 44D
A/D Converter Request 5
ADC_5IC
xx’00B4H
2DH / 45D
A/D Converter Request 6
ADC_6IC
xx’00B8H
2EH / 46D
A/D Converter Request 7
ADC_7IC
xx’00BCH
2FH / 47D
CCU60 Request 0
CCU60_0IC
xx’00C0H
30H / 48D
CCU60 Request 1
CCU60_1IC
xx’00C4H
31H / 49D
CCU60 Request 2
CCU60_2IC
xx’00C8H
32H / 50D
CCU60 Request 3
CCU60_3IC
xx’00CCH
33H / 51D
CCU61 Request 0
CCU61_0IC
xx’00D0H
34H / 52D
CCU61 Request 1
CCU61_1IC
xx’00D4H
35H / 53D
CCU61 Request 2
CCU61_2IC
xx’00D8H
36H / 54D
CCU61 Request 3
CCU61_3IC
xx’00DCH
37H / 55D
CCU62 Request 0
CCU62_0IC
xx’00E0H
38H / 56D
CCU62 Request 1
CCU62_1IC
xx’00E4H
39H / 57D
CCU62 Request 2
CCU62_2IC
xx’00E8H
3AH / 58D
CCU62 Request 3
CCU62_3IC
xx’00ECH
3BH / 59D
CCU63 Request 0
CCU63_0IC
xx’00F0H
3CH / 60D
CCU63 Request 1
CCU63_1IC
xx’00F4H
3DH / 61D
CCU63 Request 2
CCU63_2IC
xx’00F8H
3EH / 62D
CCU63 Request 3
CCU63_3IC
xx’00FCH
3FH / 63D
CAN Request 0
CAN_0IC
xx’0100H
40H / 64D
CAN Request 1
CAN_1IC
xx’0104H
41H / 65D
CAN Request 2
CAN_2IC
xx’0108H
42H / 66D
CAN Request 3
CAN_3IC
xx’010CH
43H / 67D
Data Sheet
49
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
Table 7
XC226xM Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
CAN Request 4
CAN_4IC
xx’0110H
44H / 68D
CAN Request 5
CAN_5IC
xx’0114H
45H / 69D
CAN Request 6
CAN_6IC
xx’0118H
46H / 70D
CAN Request 7
CAN_7IC
xx’011CH
47H / 71D
CAN Request 8
CAN_8IC
xx’0120H
48H / 72D
CAN Request 9
CAN_9IC
xx’0124H
49H / 73D
CAN Request 10
CAN_10IC
xx’0128H
4AH / 74D
CAN Request 11
CAN_11IC
xx’012CH
4BH / 75D
CAN Request 12
CAN_12IC
xx’0130H
4CH / 76D
CAN Request 13
CAN_13IC
xx’0134H
4DH / 77D
CAN Request 14
CAN_14IC
xx’0138H
4EH / 78D
CAN Request 15
CAN_15IC
xx’013CH
4FH / 79D
USIC0 Channel 0, Request 0
U0C0_0IC
xx’0140H
50H / 80D
USIC0 Channel 0, Request 1
U0C0_1IC
xx’0144H
51H / 81D
USIC0 Channel 0, Request 2
U0C0_2IC
xx’0148H
52H / 82D
USIC0 Channel 1, Request 0
U0C1_0IC
xx’014CH
53H / 83D
USIC0 Channel 1, Request 1
U0C1_1IC
xx’0150H
54H / 84D
USIC0 Channel 1, Request 2
U0C1_2IC
xx’0154H
55H / 85D
USIC1 Channel 0, Request 0
U1C0_0IC
xx’0158H
56H / 86D
USIC1 Channel 0, Request 1
U1C0_1IC
xx’015CH
57H / 87D
USIC1 Channel 0, Request 2
U1C0_2IC
xx’0160H
58H / 88D
USIC1 Channel 1, Request 0
U1C1_0IC
xx’0164H
59H / 89D
USIC1 Channel 1, Request 1
U1C1_1IC
xx’0168H
5AH / 90D
USIC1 Channel 1, Request 2
U1C1_2IC
xx’016CH
5BH / 91D
USIC2 Channel 0, Request 0
U2C0_0IC
xx’0170H
5CH / 92D
USIC2 Channel 0, Request 1
U2C0_1IC
xx’0174H
5DH / 93D
USIC2 Channel 0, Request 2
U2C0_2IC
xx’0178H
5EH / 94D
USIC2 Channel 1, Request 0
U2C1_0IC
xx’017CH
5FH / 95D
USIC2 Channel 1, Request 1
U2C1_1IC
xx’0180H
60H / 96D
USIC2 Channel 1, Request 2
U2C1_2IC
xx’0184H
61H / 97D
Data Sheet
50
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
Table 7
XC226xM Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
USIC3 Channel 0, Request 0
U3C0_0IC
xx’0188H
62H / 98D
USIC3 Channel 0, Request 1
U3C0_1IC
xx’018CH
63H / 99D
USIC3 Channel 0, Request 2
U3C0_2IC
xx’0190H
64H / 100D
USIC3 Channel 1, Request 0
U3C1_0IC
xx’0194H
65H / 101D
USIC3 Channel 1, Request 1
U3C1_1IC
xx’0198H
66H / 102D
USIC3 Channel 1, Request 2
U3C1_2IC
xx’019CH
67H / 103D
SCU External Request 0
SCU_ERU_0IC xx’01A0H
68H / 104D
SCU External Request 1
SCU_ERU_1IC xx’01A4H
69H / 105D
SCU External Request 2
SCU_ERU_2IC xx’01A8H
6AH / 106D
SCU Request 1
SCU_1IC
xx’01ACH
6BH / 107D
SCU Request 0
SCU_0IC
xx’01B0H
6CH / 108D
SCU External Request 3
SCU_ERU_3IC xx’01B4H
6DH / 109D
RTC
RTC_IC
xx’01B8H
6EH / 110D
End of PEC Subchannel
EOPIC
xx’01BCH
6FH / 111D
1) Register VECSEG defines the segment where the vector table is located.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting with a distance of 4 (two words) between two vectors.
Note: Vector locations without an associated interrupt control register are not assigned
and are reserved.
Data Sheet
51
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
The XC226xM includes an excellent mechanism to identify and process exceptions or
error conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware
trap causes an immediate non-maskable system reaction similar to a standard interrupt
service (branching to a dedicated vector table location). The occurrence of a hardware
trap is also indicated by a single bit in the trap flag register (TFR). Unless another higherpriority trap service is in progress, a hardware trap will interrupt any ongoing program
execution. In turn, hardware trap services can normally not be interrupted by standard
or PEC interrupts.
Table 8 shows all possible exceptions or error conditions that can arise during runtime:
Table 8
Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector
Trap
Trap
1)
Number Priority
Location
Reset Functions
–
RESET
xx’0000H
00H
III
Class A Hardware Traps:
• System Request 0
• Stack Overflow
• Stack Underflow
• Software Break
SR0
STKOF
STKUF
SOFTBRK
SR0TRAP
STOTRAP
STUTRAP
SBRKTRAP
xx’0008H
xx’0010H
xx’0018H
xx’0020H
02H
04H
06H
08H
II
II
II
II
SR1
MPR/W/X
UNDOPC
ACER
PRTFLT
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
xx’0028H
xx’0028H
xx’0028H
xx’0028H
xx’0028H
0AH
0AH
0AH
0AH
0AH
I
I
I
I
I
ILLOPA
BTRAP
xx’0028H
0AH
I
Reserved
–
–
[2CH - 3CH] [0BH 0FH]
–
Software Traps:
• TRAP Instruction
–
–
Any
Any
[xx’0000H - [00H xx’01FCH] 7FH]
in steps of
4H
Current
CPU
Priority
Class B Hardware Traps:
• System Request 1
• Memory Protection
• Undefined Opcode
• Memory Access Error
• Protected Instruction
Fault
• Illegal Word Operand
Access
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet
52
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.7
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system built into the XC226xM provides a broad range of
debug and emulation features. User software running on the XC226xM can be debugged
within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface. This
either consists of the 2-pin Device Access Port (DAP) or of the JTAG port conforming to
IEEE-1149. The debug interface can be completed with an optional break interface.
The debugger controls the OCDS with a set of dedicated registers accessible via the
debug interface (DAP or JTAG). In addition the OCDS system can be controlled by the
CPU, e.g. by a monitor program. An injection interface allows the execution of OCDSgenerated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported, as is the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing data can be obtained via the debug interface, or via the external bus interface
for increased performance.
The DAP interface uses two interface signals, the JTAG interface uses four interface
signals, to communicate with external circuitry. The debug interface can be amended
with two optional break lines.
Data Sheet
53
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.8
Capture/Compare Unit (CAPCOM2)
The CAPCOM2 unit supports generation and control of timing sequences on up to
16 channels with a maximum resolution of one system clock cycle (eight cycles in
staggered mode). The CAPCOM2 unit is typically used to handle high-speed I/O tasks
such as pulse and waveform generation, pulse width modulation (PWM), digital to
analog (D/A) conversion, software timing, or time recording with respect to external
events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for
the capture/compare register array.
The input clock for the timers is programmable to a number of prescaled values of the
internal system clock. It may also be derived from an overflow/underflow of timer T6 in
module GPT2. This provides a wide range for the timer period and resolution while
allowing precise adjustments for application-specific requirements. An external count
input for CAPCOM2 timer T7 allows event scheduling for the capture/compare registers
with respect to external events.
The capture/compare register array contains 16 dual purpose capture/compare
registers. Each may be individually allocated to either CAPCOM2 timer T7 or T8 and
programmed for a capture or compare function.
Each register of the CAPCOM2 module has one port pin associated with it.A port pin is
associated with 12 registers of the CAPCOM2 module. This serves as an input pin to
trigger the capture function or as an output pin to indicate the occurrence of a compare
event.
Table 9
Compare Modes (CAPCOM2)
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
Several compare interrupts per timer period are possible
Mode 1
Pin toggles on each compare match;
Several compare events per timer period are possible
Mode 2
Interrupt-only compare mode;
Only one compare interrupt per timer period is generated
Mode 3
Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
Only one compare event per timer period is generated
Double Register
Mode
Two registers operate on one pin;
Pin toggles on each compare match;
Several compare events per timer period are possible
Single Event Mode
Generates single edges or pulses;
Can be used with any compare mode
Data Sheet
54
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin associated with this register. In
addition, a specific interrupt request for this capture/compare register is generated.
Either a positive, a negative, or both a positive and a negative external signal transition
at the pin can be selected as the triggering event.
The contents of all registers selected for one of the five compare modes are continuously
compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the compare mode selected.
Reload Reg.
T7REL
fCC
T7IN
T6OUF
T7
Input
Control
Timer T7
CC16IO
CC17IO
CC16IRQ
CC17IRQ
Mode
Control
(Capture
or
Compare)
Sixteen
16-bit
Capture/
Compare
Registers
CC31IO
fCC
T6OUF
T7IRQ
CC31IRQ
T8
Input
Control
Timer T8
T8IRQ
Reload Reg.
T8REL
MC_CAPCOM2_BLOCKDIAG
Figure 5
Data Sheet
CAPCOM2 Unit Block Diagram
55
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.9
Capture/Compare Units CCU6x
The XC226xM types feature several CCU6 units (CCU60, CCU61, CCU62, CCU63).
The CCU6 is a high-resolution capture and compare unit with application-specific
modes. It provides inputs to start the timers synchronously, an important feature in
devices with several CCU6 modules.
The module provides two independent timers (T12, T13), that can be used for PWM
generation, especially for AC motor control. Additionally, special control modes for block
commutation and multi-phase machines are supported.
Timer 12 Features
•
•
•
•
•
•
•
•
•
•
Three capture/compare channels, where each channel can be used either as a
capture or as a compare channel.
Supports generation of a three-phase PWM (six outputs, individual signals for highside and low-side switches)
16-bit resolution, maximum count frequency = peripheral clock
Dead-time control for each channel to avoid short circuits in the power stage
Concurrent update of the required T12/13 registers
Center-aligned and edge-aligned PWM can be generated
Single-shot mode supported
Many interrupt request sources
Hysteresis-like control mode
Automatic start on a HW event (T12HR, for synchronization purposes)
Timer 13 Features
•
•
•
•
•
•
One independent compare channel with one output
16-bit resolution, maximum count frequency = peripheral clock
Can be synchronized to T12
Interrupt generation at period match and compare match
Single-shot mode supported
Automatic start on a HW event (T13HR, for synchronization purposes)
Additional Features
•
•
•
•
•
•
•
Block commutation for brushless DC drives implemented
Position detection via Hall sensor pattern
Automatic rotational speed measurement for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC drives
Output levels can be selected and adapted to the power stage
Data Sheet
56
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
CCU6 Module Kernel
fSYS
com pare
Channel 0
Channel 3
com pare
1
3
2
2
2
trap i nput
T13
output select
st art
Trap
Control
Hal l i nput
1
Multichannel
Control
output select
Channel 2
compa re
1
compa re
Interrupts
Channel 1
Deadtime
Control
compa re
T12
capture
TxHR
1
3
1
CTRAP
CCPOS0
CCPOS1
CCPOS2
COUT60
CC60
COUT61
CC61
COUT62
CC62
COUT63
Input / Output Control
m c_ccu6_blockdiagram . vsd
Figure 6
Mod_Name Block Diagram
Timer T12 can work in capture and/or compare mode for its three channels. The modes
can also be combined. Timer T13 can work in compare mode only. The multi-channel
control unit generates output patterns that can be modulated by timer T12 and/or timer
T13. The modulation sources can be selected and combined for signal modulation.
Data Sheet
57
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.10
General Purpose Timer (GPT12E) Unit
The GPT12E unit is a very flexible multifunctional timer/counter structure which can be
used for many different timing tasks such as event timing and counting, pulse width and
duty cycle measurements, pulse generation, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers organized in two separate modules,
GPT1 and GPT2. Each timer in each module may either operate independently in a
number of different modes or be concatenated with another timer of the same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation: Timer, Gated Timer, Counter, and Incremental
Interface Mode. In Timer Mode, the input clock for a timer is derived from the system
clock and divided by a programmable prescaler. Counter Mode allows timer clocking in
reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes each timer has one associated port pin (TxIN) which serves as a gate or clock
input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.
The counting direction (up/down) for each timer can be programmed by software or
altered dynamically by an external signal on a port pin (TxEUD), e.g. to facilitate position
tracking.
In Incremental Interface Mode the GPT1 timers can be directly connected to the
incremental position sensor signals A and B through their respective inputs TxIN and
TxEUD. Direction and counting signals are internally derived from these two input
signals, so that the contents of the respective timer Tx corresponds to the sensor
position. The third position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer
overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to the basic operating modes, T2 and T4 may be configured as reload or
capture register for timer T3. A timer used as capture or reload register is stopped. The
contents of timer T3 is captured into T2 or T4 in response to a signal at the associated
input pin (TxIN). Timer T3 is reloaded with the contents of T2 or T4, triggered either by
an external signal or a selectable state transition of its toggle latch T3OTL. When both
T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL
with the low and high times of a PWM signal, this signal can be continuously generated
without software intervention.
Data Sheet
58
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
T3CON.BPS1
fGPT
n
2 :1
Basic Clock
Interrupt
Request
(T2IRQ)
Aux. Timer T2
T2IN
T2EUD
U/D
T2
Mode
Reload
Control
Capture
Interrupt
Request
(T3IRQ)
T3IN
T3
Mode
Control
T3EUD
Core Timer T3
U/D
T3OTL
T3OUT
Toggle
Latch
Capture
T4IN
T4EUD
T4
Mode
Control
Reload
Aux. Timer T4
U/D
Interrupt
Request
(T4IRQ)
MC_GPT_BLOCK1
Figure 7
Data Sheet
Block Diagram of GPT1
59
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
counting direction (up/down) for each timer can be programmed by software or altered
dynamically with an external signal on a port pin (TxEUD1)). Concatenation of the timers
is supported with the output toggle latch (T6OTL) of timer T6, which changes its state on
each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can also be used to clock the CAPCOM2
timers and to initiate a reload from the CAPREL register.
The CAPREL register can capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN); timer T5 may optionally be cleared
after the capture procedure. This allows the XC226xM to measure absolute time
differences or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) can also be generated upon transitions of
GPT1 timer T3 inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
1) Exception: T5EUD is not connected to a pin.
Data Sheet
60
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
T6CON.BPS2
fGPT
2n:1
Basic Clock
Interrupt
Request
(T5IRQ)
GPT2 Timer T5
T5IN
T5EUD
T5
Mode
Control
U/D
Clear
Capture
CAPIN
T3IN/
T3EUD
CAPREL
Mode
Control
GPT2 CAPREL
Interrupt
Request
(CRIRQ)
Reload
Clear
Interrupt
Request
(T6IRQ)
Toggle
FF
T6IN
T6
Mode
Control
GPT2 Timer T6
T6OTL
T6OUT
T6OUF
U/D
T6EUD
MC_GPT_BLOCK2
Figure 8
Data Sheet
Block Diagram of GPT2
61
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.11
Real Time Clock
The Real Time Clock (RTC) module of the XC226xM can be clocked with a clock signal
selected from internal sources or external sources (pins).
The RTC basically consists of a chain of divider blocks:
•
•
•
Selectable 32:1 and 8:1 dividers (on - off)
The reloadable 16-bit timer T14
The 32-bit RTC timer block (accessible via registers RTCH and RTCL) consisting of:
– a reloadable 10-bit timer
– a reloadable 6-bit timer
– a reloadable 6-bit timer
– a reloadable 10-bit timer
All timers count up. Each timer can generate an interrupt request. All requests are
combined to a common node request.
fRTC
:32
M UX
RUN
M UX
Interrupt Sub Node
:8
PRE
REFCLK
CNT
INT0
CNT
INT1
CNT
INT2
RTCINT
CNT
INT3
REL-Register
f CNT
T14REL
10 Bits
6 Bits
6 Bits
10 Bits
T14
10 Bits
6 Bits
6 Bits
10 Bits
T14-Register
CNT-Register
M CB05568B
Figure 9
RTC Block Diagram
Note: The registers associated with the RTC are only affected by a power reset.
Data Sheet
62
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
The RTC module can be used for different purposes:
•
•
•
•
System clock to determine the current time and date
Cyclic time-based interrupt, to provide a system time tick independent of CPU
frequency and other resources
48-bit timer for long-term measurements
Alarm interrupt at a defined time
Data Sheet
63
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.12
A/D Converters
For analog signal measurement, up to two 10-bit A/D converters (ADC0, ADC1) with
11 + 5 multiplexed input channels and a sample and hold circuit have been integrated
on-chip. 4 inputs can be converted by both A/D converters. Conversions use the
successive approximation method. The sample time (to charge the capacitors) and the
conversion time are programmable so that they can be adjusted to the external circuit.
The A/D converters can also operate in 8-bit conversion mode, further reducing the
conversion time.
Several independent conversion result registers, selectable interrupt requests, and
highly flexible conversion sequences provide a high degree of programmability to meet
the application requirements. Both modules can be synchronized to allow parallel
sampling of two input channels.
For applications that require more analog input channels, external analog multiplexers
can be controlled automatically. For applications that require fewer analog input
channels, the remaining channel inputs can be used as digital input port pins.
The A/D converters of the XC226xM support two types of request sources which can be
triggered by several internal and external events.
•
•
Parallel requests are activated at the same time and then executed in a predefined
sequence.
Queued requests are executed in a user-defined sequence.
In addition, the conversion of a specific channel can be inserted into a running sequence
without disturbing that sequence. All requests are arbitrated according to the priority
level assigned to them.
Data reduction features reduce the number of required CPU access operations allowing
the precise evaluation of analog inputs (high conversion rate) even at a low CPU speed.
Result data can be reduced by limit checking or accumulation of results.
The Peripheral Event Controller (PEC) can be used to control the A/D converters or to
automatically store conversion results to a table in memory for later evaluation, without
requiring the overhead of entering and exiting interrupt routines for each data transfer.
Each A/D converter contains eight result registers which can be concatenated to build a
result FIFO. Wait-for-read mode can be enabled for each result register to prevent the
loss of conversion data.
In order to decouple analog inputs from digital noise and to avoid input trigger noise,
those pins used for analog input can be disconnected from the digital input stages. This
can be selected for each pin separately with the Port x Digital Input Disable registers.
The Auto-Power-Down feature of the A/D converters minimizes the power consumption
when no conversion is in progress.
Broken wire detection for each channel and a multiplexer test mode provide information
to verify the proper operation of the analog signal sources (e.g. a sensor system).
Data Sheet
64
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.13
Universal Serial Interface Channel Modules (USIC)
The XC226xM features several USIC modules (USIC0, USIC1, USIC2, USIC3), each
providing two serial communication channels.
The Universal Serial Interface Channel (USIC) module is based on a generic data shift
and data storage structure which is identical for all supported serial communication
protocols. Each channel supports complete full-duplex operation with a basic data buffer
structure (one transmit buffer and two receive buffer stages). In addition, the data
handling software can use FIFOs.
The protocol part (generation of shift clock/data/control signals) is independent of the
general part and is handled by protocol-specific preprocessors (PPPs).
The USIC’s input/output lines are connected to pins by a pin routing unit. The inputs and
outputs of each USIC channel can be assigned to different interface pins, providing great
flexibility to the application software. All assignments can be made during runtime.
Bus
Buffer & Shift Structure Protocol Preprocessors
Pins
Control 0
DBU
0
PPP_B
DSU
0
PPP_C
PPP_D
Control 1
PPP_A
DBU
1
Pin Routing Shell
Bus Interface
PPP_A
PPP_B
DSU
1
PPP_C
PPP_D
fsys
Fractional
Dividers
Baud rate
Generators
USIC_basic.vsd
Figure 10
General Structure of a USIC Module
The regular structure of the USIC module brings the following advantages:
•
•
•
Higher flexibility through configuration with same look-and-feel for data management
Reduced complexity for low-level drivers serving different protocols
Wide range of protocols with improved performances (baud rate, buffer handling)
Data Sheet
65
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
Target Protocols
Each USIC channel can receive and transmit data frames with a selectable data word
width from 1 to 16 bits in each of the following protocols:
•
•
•
•
•
UART (asynchronous serial channel)
– module capability: maximum baud rate = fSYS / 4
– data frame length programmable from 1 to 63 bits
– MSB or LSB first
LIN Support (Local Interconnect Network)
– module capability: maximum baud rate = fSYS / 16
– checksum generation under software control
– baud rate detection possible by built-in capture event of baud rate generator
SSC/SPI/QSPI (synchronous serial channel with or without data buffer)
– module capability: maximum baud rate = fSYS / 2, limited by loop delay
– number of data bits programmable from 1 to 63, more with explicit stop condition
– MSB or LSB first
– optional control of slave select signals
IIC (Inter-IC Bus)
– supports baud rates of 100 kbit/s and 400 kbit/s
IIS (Inter-IC Sound Bus)
– module capability: maximum baud rate = fSYS / 2
Note: Depending on the selected functions (such as digital filters, input synchronization
stages, sample point adjustment, etc.), the maximum achievable baud rate can be
limited. Please note that there may be additional delays, such as internal or
external propagation delays and driver delays (e.g. for collision detection in UART
mode, for IIC, etc.).
Data Sheet
66
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.14
MultiCAN Module
The MultiCAN module contains independently operating CAN nodes with Full-CAN
functionality which are able to exchange Data and Remote Frames using a gateway
function. Transmission and reception of CAN frames is handled in accordance with CAN
specification V2.0 B (active). Each CAN node can receive and transmit standard frames
with 11-bit identifiers as well as extended frames with 29-bit identifiers.
All CAN nodes share a common set of message objects. Each message object can be
individually allocated to one of the CAN nodes. Besides serving as a storage container
for incoming and outgoing frames, message objects can be combined to build gateways
between the CAN nodes or to set up a FIFO buffer.
Note: The number of CAN nodes and message objects depends on the selected device
type.
The message objects are organized in double-chained linked lists, where each CAN
node has its own list of message objects. A CAN node stores frames only into message
objects that are allocated to its own message object list and it transmits only messages
belonging to this message object list. A powerful, command-driven list controller
performs all message object list operations.
MultiCAN Module Kernel
Clock
Control
CAN
Node 0
Interrupt
Control
Port
Control
...
Linked
List
Control
TXDCn
RXDCn
...
Message
Object
Buffer
...
Address
Decoder
CAN
Node n
fCAN
TXDC0
RXDC0
CAN Control
mc_multican_block.vsd
Figure 11
Data Sheet
Block Diagram of MultiCAN Module
67
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
MultiCAN Features
•
•
•
•
•
•
•
•
•
•
CAN functionality conforming to CAN specification V2.0 B active for each CAN node
(compliant to ISO 11898)
Independent CAN nodes
Set of independent message objects (shared by the CAN nodes)
Dedicated control registers for each CAN node
Data transfer rate up to 1 Mbit/s, individually programmable for each node
Flexible and powerful message transfer control and error handling capabilities
Full-CAN functionality for message objects:
– Can be assigned to one of the CAN nodes
– Configurable as transmit or receive objects, or as message buffer FIFO
– Handle 11-bit or 29-bit identifiers with programmable acceptance mask for filtering
– Remote Monitoring Mode, and frame counter for monitoring
Automatic Gateway Mode support
16 individually programmable interrupt nodes
Analyzer mode for CAN bus monitoring
3.15
System Timer
The System Timer consists of a programmable prescaler and two concatenated timers
(10 bits and 6 bits). Both timers can generate interrupt requests. The clock source can
be selected and the timers can also run during power reduction modes.
Therefore, the System Timer enables the software to maintain the current time for
scheduling functions or for the implementation of a clock.
Data Sheet
68
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.16
Watchdog Timer
The Watchdog Timer is one of the fail-safe mechanisms which have been implemented
to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after an application reset of the chip. It can be
disabled and enabled at any time by executing the instructions DISWDT and ENWDT
respectively. The software has to service the Watchdog Timer before it overflows. If this
is not the case because of a hardware or software failure, the Watchdog Timer
overflows, generating a prewarning interrupt and then a reset request.
The Watchdog Timer is a 16-bit timer clocked with the system clock divided by 16,384
or 256. The Watchdog Timer register is set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it
is serviced by the application software, the Watchdog Timer is reloaded and the
prescaler is cleared.
Time intervals between 3.2 μs and 13.4 s can be monitored (@ 80 MHz).
The default Watchdog Timer interval after power-up is 6.5 ms (@ 10 MHz).
3.17
Clock Generation
The Clock Generation Unit can generate the system clock signal fSYS for the XC226xM
from a number of external or internal clock sources:
•
•
•
•
External clock signals with pad voltage or core voltage levels
External crystal or resonator using the on-chip oscillator
On-chip clock source for operation without crystal/resonator
Wake-up clock (ultra-low-power) to further reduce power consumption
The programmable on-chip PLL with multiple prescalers generates a clock signal for
maximum system performance from standard crystals, a clock input signal, or from the
on-chip clock source. See also Section 4.6.2.
The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency
falls below a certain limit or stops completely. In this case, the system can be supplied
with an emergency clock to enable operation even after an external clock failure.
All available clock signals can be output on one of two selectable pins.
Data Sheet
69
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.18
Parallel Ports
The XC226xM provides up to 76 I/O lines which are organized into 7 input/output ports
and 2 input ports. All port lines are bit-addressable, and all input/output lines can be
individually (bit-wise) configured via port control registers. This configuration selects the
direction (input/output), push/pull or open-drain operation, activation of pull devices, and
edge characteristics (shape) and driver characteristics (output current) of the port
drivers. The I/O ports are true bidirectional ports which are switched to high impedance
state when configured as inputs. During the internal reset, all port pins are configured as
inputs without pull devices active.
All port lines have alternate input or output functions associated with them. These
alternate functions can be programmed to be assigned to various port pins to support the
best utilization for a given application. For this reason, certain functions appear several
times in Table 10.
All port lines that are not used for alternate functions may be used as general purpose
I/O lines.
Table 10
Summary of the XC226xM’s Ports
Port
Width
I/O
Connected Modules
P0
8
I/O
EBC (A7...A0), CCU6, USIC, CAN
P1
8
I/O
EBC (A15...A8), CCU6, USIC
P2
14
I/O
EBC (READY, BHE, A23...A16, AD15...AD13, D15...D13),
CAN, CC2, GPT12E, USIC, DAP/JTAG
P4
4
I/O
EBC (CS3...CS0), CC2, CAN, GPT12E, USIC
P5
11
I
Analog Inputs, CCU6, DAP/JTAG, GPT12E, CAN
P6
3
I/O
ADC, CAN, GPT12E
P7
5
I/O
CAN, GPT12E, SCU, DAP/JTAG, CCU6, ADC, USIC
P10
16
I/O
EBC(ALE, RD, WR, AD12...AD0, D12...D0), CCU6, USIC,
DAP/JTAG, CAN
P15
5
I
Analog Inputs, GPT12E
Data Sheet
70
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.19
Power Management
The XC226xM provides the means to control the power it consumes either at a given
time or averaged over a certain duration.
Three mechanisms can be used (and partly in parallel):
•
•
•
Supply Voltage Management permits the temporary reduction of the supply voltage
of major parts of the logic or even its complete disconnection. This drastically reduces
the power consumed because it eliminates leakage current, particularly at high
temperature.
Several power reduction modes provide the best balance of power reduction and
wake-up time.
Clock Generation Management controls the frequency of internal and external
clock signals. Clock signals for currently inactive parts of logic are disabled
automatically. The user can drastically reduce the consumed power by reducing the
XC226xM system clock frequency.
External circuits can be controlled using the programmable frequency output
EXTCLK.
Peripheral Management permits temporary disabling of peripheral modules. Each
peripheral can be disabled and enabled separately. The CPU can be switched off
while the peripherals can continue to operate.
Wake-up from power reduction modes can be triggered either externally with signals
generated by the external system, or internally by the on-chip wake-up timer. This
supports intermittent operation of the XC226xM by generating cyclic wake-up signals.
Full performance is available to quickly react to action requests while the intermittent
sleep phases greatly reduce the average system power consumption.
Note: When selecting the supply voltage and the clock source and generation method,
the required parameters must be carefully written to the respective bitfields, to
avoid unintended intermediate states. Recommended sequences are provided
which ensure the intended operation of power supply system and clock system.
Please refer to the Programmer’s Guide.
Data Sheet
71
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
3.20
Instruction Set Summary
Table 11 lists the instructions of the XC226xM.
The addressing modes that can be used with a specific instruction, the function of the
instructions, parameters for conditional execution of instructions, and the opcodes for
each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 11
Instruction Set Summary
Mnemonic
Description
Bytes
ADD(B)
Add word (byte) operands
2/4
ADDC(B)
Add word (byte) operands with Carry
2/4
SUB(B)
Subtract word (byte) operands
2/4
SUBC(B)
Subtract word (byte) operands with Carry
2/4
MUL(U)
(Un)Signed multiply direct GPR by direct GPR
(16- × 16-bit)
2
DIV(U)
(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B)
Complement direct word (byte) GPR
2
NEG(B)
Negate direct word (byte) GPR
2
AND(B)
Bitwise AND, (word/byte operands)
2/4
OR(B)
Bitwise OR, (word/byte operands)
2/4
XOR(B)
Bitwise exclusive OR, (word/byte operands)
2/4
BCLR/BSET
Clear/Set direct bit
2
BMOV(N)
Move (negated) direct bit to direct bit
4
BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit
4
BCMP
Compare direct bit to direct bit
4
BFLDH/BFLDL
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
4
CMP(B)
Compare word (byte) operands
2/4
CMPD1/2
Compare word data to GPR and decrement GPR by 1/2
2/4
CMPI1/2
Compare word data to GPR and increment GPR by 1/2
2/4
PRIOR
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
2
SHL/SHR
Shift left/right direct word GPR
2
Data Sheet
72
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
Table 11
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
ROL/ROR
Rotate left/right direct word GPR
2
ASHR
Arithmetic (sign bit) shift right direct word GPR
2
MOV(B)
Move word (byte) data
2/4
MOVBS/Z
Move byte operand to word op. with sign/zero extension
2/4
JMPA/I/R
Jump absolute/indirect/relative if condition is met
4
JMPS
Jump absolute to a code segment
4
JB(C)
Jump relative if direct bit is set (and clear bit)
4
JNB(S)
Jump relative if direct bit is not set (and set bit)
4
CALLA/I/R
Call absolute/indirect/relative subroutine if condition is met 4
CALLS
Call absolute subroutine in any code segment
4
PCALL
Push direct word register onto system stack and call
absolute subroutine
4
TRAP
Call interrupt service routine via immediate trap number
2
PUSH/POP
Push/pop direct word register onto/from system stack
2
SCXT
Push direct word register onto system stack and update
register with word operand
4
RET(P)
Return from intra-segment subroutine
(and pop direct word register from system stack)
2
RETS
Return from inter-segment subroutine
2
RETI
Return from interrupt service subroutine
2
SBRK
Software Break
2
SRST
Software Reset
4
IDLE
Enter Idle Mode
4
PWRDN
Unused instruction1)
4
SRVWDT
Service Watchdog Timer
4
DISWDT/ENWDT
Disable/Enable Watchdog Timer
4
EINIT
End-of-Initialization Register Lock
4
ATOMIC
Begin ATOMIC sequence
2
EXTR
Begin EXTended Register sequence
2
EXTP(R)
Begin EXTended Page (and Register) sequence
2/4
EXTS(R)
Begin EXTended Segment (and Register) sequence
2/4
Data Sheet
73
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Functional Description
Table 11
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
NOP
Null operation
2
CoMUL/CoMAC
Multiply (and accumulate)
4
CoADD/CoSUB
Add/Subtract
4
Co(A)SHR
(Arithmetic) Shift right
4
CoSHL
Shift left
4
CoLOAD/STORE
Load accumulator/Store MAC register
4
CoCMP
Compare
4
CoMAX/MIN
Maximum/Minimum
4
CoABS/CoRND
Absolute value/Round accumulator
4
CoMOV
Data move
4
CoNEG/NOP
Negate accumulator/Null operation
4
1) The Enter Power Down Mode instruction is not used in the XC226xM, due to the enhanced power control
scheme. PWRDN will be correctly decoded, but will trigger no action.
Data Sheet
74
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4
Electrical Parameters
The operating range for the XC226xM is defined by its electrical parameters. For proper
operation the specified limits must be respected during system design
4.1
General Parameters
These parameters are valid for all subsequent descriptions, unless otherwise noted.
Table 12
Absolute Maximum Rating Parameters
Parameter
Symbol
Min.
Typ.
Max.
Unit Note /
Test Condition
TST
Junction temperature
TJ
Voltage on VDDI pins with VDDIM,
VDDI1
respect to ground (VSS)
Voltage on VDDP pins with VDDPA,
respect to ground (VSS)
VDDPB
VIN
Voltage on any pin with
respect to ground (VSS)
-65
–
150
°C
–
-40
–
150
°C
under bias
-0.5
–
1.65
V
–
-0.5
–
6.0
V
–
-0.5
–
VDDP
V
Input current on any pin
during overload condition
–
-10
–
10
mA
1)
Absolute sum of all input
currents during overload
condition
–
–
–
|100|
mA
–
Output current on any pin
IOH, IOL
–
–
|30|
mA
–
Storage temperature
Values
VIN < VDDPmax
1)
+ 0.5
1) One of these limits must be kept.
Keeping VIN within the given limits avoids damage due to overload conditions.
Note: Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only. Functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for an extended time may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
75
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the XC226xM. All parameters specified in the following sections refer to these operating
conditions, unless otherwise noticed.
Note: Typical parameter values refer to room temperature and nominal supply voltage,
minimum/maximum
parameter
values
also
include
conditions
of
minimum/maximum temperature and minimum/maximum supply voltage.
Additional details are described where applicable.
Table 13
Operating Condition Parameters
Parameter
Symbol
Digital core supply voltage VDDI
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
1.4
–
1.6
V
Digital supply voltage for
IO pads and voltage
regulators,
upper voltage range
VDDPA,
VDDPB
4.5
5.0
5.5
V
1)
Digital supply voltage for
IO pads and voltage
regulators,
lower voltage range
VDDPA,
VDDPB
3.0
3.3
4.5
V
1)
Digital ground voltage
VSS
0
–
0
V
Reference
voltage
Overload current
IOV
-5
–
5
mA
Per IO pin2)3)
-2
–
5
mA
Per analog input
pin2)3)
KOVA
–
1.0 ×
10-6
1.0 ×
10-4
–
IOV > 0
Overload negative current KOVA
coupling factor for analog
inputs4)
–
2.5 ×
10-4
1.5 ×
10-3
–
IOV < 0
KOVD
–
1.0 ×
10-4
5.0 ×
10-3
–
Overload negative current KOVD
coupling factor for digital
I/O pins4)
–
1.0 ×
10-2
3.0 ×
10-2
–
Overload positive current
coupling factor for analog
inputs4)
Overload positive current
coupling factor for digital
I/O pins4)
Data Sheet
76
3)
3)
IOV > 0
3)
IOV < 0
3)
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 13
Operating Condition Parameters (cont’d)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
Absolute sum of overload
currents
Σ|IOV|
–
–
50
mA
3)
External Pin Load
Capacitance
CL
–
205)
–
pF
Pin drivers in
default mode6)
Voltage Regulator Buffer
Capacitance for DMP_M
CEVRM
1.0
–
4.7
μF
7)
Voltage Regulator Buffer
Capacitance for DMP_1
CEVR1
0.47
–
2.2
μF
One for each
supply pin7)
Operating frequency
fSYS
TA
–
–
80
MHz
8)
–
–
–
°C
Ambient temperature
1) Performance of pad drivers, A/D Converter, and Flash module depends on VDDP.
2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin (IOV < 0). The absolute sum of input
overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified
limits. Proper operation under overload conditions depends on the application.
Overload conditions must not occur on pin XTAL1 (powered by VDDIM).
3) Not subject to production test - verified by design/characterization.
4) An overload current (IOV) through a pin injects an error current (IINJ) into the adjacent pins. This error current
adds to that pin’s leakage current (IOZ). The value of the error current depends on the overload current and is
defined by the overload coupling factor KOV. The polarity of the injected error current is reversed from the
polarity of the overload current that produces it.
The total current through a pin is |ITOT| = |IOZ| + (|IOV| × KOV). The additional error current may distort the input
voltage on analog inputs.
5) This is the reference load. For bigger capacitive loads, use the derating factors from Section 4.6.4.
6) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (CL).
7) To ensure the stability of the voltage regulators the EVRs must be buffered with ceramic capacitors. Separate
buffer capacitors with the recomended values shall be connected as close as possible to each VDDI pin to keep
the resistance of the board tracks below 2 Ω. Connect all VDDI1 pins together.
The minimum capacitance value is required for proper operation under all conditions (e.g. temperature).
Higher values slightly increase the startup time.
8) The operating frequency range may be reduced for specific types of the XC226xM. This is indicated in the
device designation (…FxxL). 80-MHz devices are marked …F80L.
Parameter Interpretation
The parameters listed in the following include both the characteristics of the XC226xM
and its demands on the system. To aid in correctly interpreting the parameters when
evaluating them for a design, they are marked accordingly in the column “Symbol”:
Data Sheet
77
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
CC (Controller Characteristics):
The logic of the XC226xM provides signals with the specified characteristics.
SR (System Requirement):
The external system must provide signals with the specified characteristics to the
XC226xM.
Data Sheet
78
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.2
DC Parameters
These parameters are static or average values that may be exceeded during switching
transitions (e.g. output current).
The XC226xM can operate within a wide supply voltage range from 3.0 V to 5.5 V.
However, during operation this supply voltage must remain within 10 percent of the
selected nominal supply voltage. It cannot vary across the full operating voltage range.
Because of the supply voltage restriction and because electrical behavior depends on
the supply voltage, the parameters are specified separately for the upper and the lower
voltage range.
During operation, the supply voltages may only change with a maximum speed of
dV/dt < 1 V/ms.
Leakage current is strongly dependent on the operating temperature and the voltage
level at the respective pin. The maximum values in the following tables apply under worst
case conditions, i.e. maximum temperature and an input level equal to the supply
voltage.
The value for the leakage current in an application can be determined by using the
respective leakage derating formula (see tables) with values from that application.
The pads of the XC226xM are designed to operate in various driver modes. The DC
parameter specifications refer to the pad current limits specified in Section 4.6.4.
Data Sheet
79
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Pullup/Pulldown Device Behavior
Most pins of the XC226xM feature pullup or pulldown devices. For some special pins
these are fixed; for the port pins they can be selected by the application.
The specified current values indicate how to load the respective pin depending on the
intended signal level. Figure 12 shows the current paths.
The shaded resistors shown in the figure may be required to compensate system pull
currents that do not match the given limit values.
VDDP
Pullup
Pulldown
VSS
MC_XC2X_PULL
Figure 12
Data Sheet
Pullup/Pulldown Current Definition
80
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.2.1
DC Parameters for Upper Voltage Area
These parameters apply to the upper IO voltage range, 4.5 V ≤ VDDP ≤ 5.5 V.
Note: Operating Conditions apply.
Keeping signal levels within the limits specified in this table ensures operation
without overload conditions. For signal levels outside these specifications, also
refer to the specification of the overload current IOV.
Table 14
DC Characteristics for Upper Voltage Range
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
–
0.3 ×
V
–
–
VDDP
VDDP
V
–
HYS CC 0.11
–
× VDDP
–
V
VDDP in [V],
VOL CC –
VOL CC –
VOH CC VDDP
–
1.0
V
–
0.4
V
–
–
V
IOL ≤ IOLmax2)
IOL ≤ IOLnom2)3)
IOH ≥ IOHmax2)
VOH CC VDDP
–
–
V
IOH ≥ IOHnom2)3)
Input leakage current
(Port 5, Port 15)5)
IOZ1 CC –
±10
±200
nA
0 V < VIN < VDDP
Input leakage current
(all other)5)6)
IOZ2 CC –
±0.2
±5
μA
Input leakage current
(all other)5)6)
IOZ2 CC –
±0.2
±15
μA
Pull level keep current
IPLK
–
–
±30
μA
Pull level force current
IPLF
±250
–
–
μA
TJ ≤ 110°C,
0.45 V < VIN
< VDDP
TJ ≤ 150°C,
0.45 V < VIN
< VDDP
VPIN ≥ VIH (up)7)
VPIN ≤ VIL (dn)
VPIN ≤ VIL (up)7)
VPIN ≥ VIH (dn)
Pin capacitance8)
(digital inputs/outputs)
CIO CC
–
–
10
pF
Input low voltage
(all except XTAL1)
VIL SR
-0.3
Input high voltage
(all except XTAL1)
VIH SR
0.7 ×
1)
Input Hysteresis
Output low voltage
Output low voltage
4)
Output high voltage
VDDP
+ 0.3
Series
resistance = 0 Ω
- 1.0
Output high voltage4)
- 0.4
Data Sheet
81
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
1) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
2) The maximum deliverable output current of a port driver depends on the selected output driver mode, see
Section 4.6.4. The limit for pin groups must be respected.
3) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→VSS,
VOH→VDDP). However, only the levels for nominal output currents are verified.
4) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage is determined by the external circuit.
5) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to
the definition of the overload coupling factor KOV.
6) The given values are worst-case values. In production test, this leakage current is only tested at 125°C; other
values are ensured by correlation. For derating, please refer to the following descriptions:
Leakage derating depending on temperature (TJ = junction temperature [°C]):
IOZ = 0.05 × e(1.5 + 0.028×TJ) [μA]. For example, at a temperature of 95°C the resulting leakage current is 3.2 μA.
Leakage derating depending on voltage level (DV = VDDP - VPIN [V]):
IOZ = IOZtempmax - (1.6 × DV) [μA]
This voltage derating formula is an approximation which applies for maximum temperature.
Because pin P2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal
leakage.
7) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep
the default pin level: VPIN ≥ VIH for a pullup; VPIN ≤ VIL for a pulldown.
Force current: Drive the indicated minimum current through this pin to change the default pin level driven by
the enabled pull device: VPIN ≤ VIL for a pullup; VPIN ≥ VIH for a pulldown.
These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in
general purpose IO pins.
8) Not subject to production test - verified by design/characterization.
Because pin P2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal
capacitance.
Data Sheet
82
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.2.2
DC Parameters for Lower Voltage Area
These parameters apply to the lower IO voltage range, 3.0 V ≤ VDDP ≤ 4.5 V.
Note: Operating Conditions apply.
Keeping signal levels within the limits specified in this table ensures operation
without overload conditions. For signal levels outside these specifications, also
refer to the specification of the overload current IOV.
Table 15
DC Characteristics for Lower Voltage Range
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
–
0.3 ×
V
–
–
VDDP
VDDP
V
–
HYS CC 0.07
–
× VDDP
–
V
VDDP in [V],
VOL CC –
VOL CC –
VOH CC VDDP
–
1.0
V
–
0.4
V
–
–
V
IOL ≤ IOLmax2)
IOL ≤ IOLnom2)3)
IOH ≥ IOHmax2)
VOH CC VDDP
–
–
V
IOH ≥ IOHnom2)3)
Input leakage current
(Port 5, Port 15)5)
IOZ1 CC –
±10
±200
nA
0 V < VIN < VDDP
Input leakage current
(all other)5)6)
IOZ2 CC –
±0.2
±2.5
μA
Input leakage current
(all other)5)6)
IOZ2 CC –
±0.2
±8
μA
Pull level keep current
IPLK
–
–
±10
μA
Pull level force current
IPLF
±150
–
–
μA
TJ ≤ 110°C,
0.45 V < VIN
< VDDP
TJ ≤ 150°C,
0.45 V < VIN
< VDDP
VPIN ≥ VIH (up)7)
VPIN ≤ VIL (dn)
VPIN ≤ VIL (up)7)
VPIN ≥ VIH (dn)
Pin capacitance8)
(digital inputs/outputs)
CIO CC
–
–
10
pF
Input low voltage
(all except XTAL1)
VIL SR
-0.3
Input high voltage
(all except XTAL1)
VIH SR
0.7 ×
1)
Input Hysteresis
Output low voltage
Output low voltage
4)
Output high voltage
VDDP
+ 0.3
Series
resistance = 0 Ω
- 1.0
Output high voltage4)
- 0.4
Data Sheet
83
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
1) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
2) The maximum deliverable output current of a port driver depends on the selected output driver mode, see
Section 4.6.4. The limit for pin groups must be respected.
3) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→VSS,
VOH→VDDP). However, only the levels for nominal output currents are verified.
4) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage is determined by the external circuit.
5) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to
the definition of the overload coupling factor KOV.
The leakage current value is not tested in the lower voltage range but only in the upper voltage range. This
parameter is ensured by correlation.
6) The given values are worst-case values. In production test, this leakage current is only tested at 125°C; other
values are ensured by correlation. For derating, please refer to the following descriptions:
Leakage derating depending on temperature (TJ = junction temperature [°C]):
IOZ = 0.03 × e(1.35 + 0.028×TJ) [μA]. For example, at a temperature of 95°C the resulting leakage current is 1.65 μA.
Leakage derating depending on voltage level (DV = VDDP - VPIN [V]):
IOZ = IOZtempmax - (1.3 × DV) [μA]
This voltage derating formula is an approximation which applies for maximum temperature.
Because pin P2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal
leakage.
7) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep
the default pin level: VPIN ≥ VIH for a pullup; VPIN ≤ VIL for a pulldown.
Force current: Drive the indicated minimum current through this pin to change the default pin level driven by
the enabled pull device: VPIN ≤ VIL for a pullup; VPIN ≥ VIH for a pulldown.
These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in
general purpose IO pins.
8) Not subject to production test - verified by design/characterization.
Because pin P2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal
capacitance.
Data Sheet
84
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.2.3
Power Consumption
The power consumed by the XC226xM depends on several factors such as supply
voltage, operating frequency, active circuits, and operating temperature. The power
consumption specified here consists of two components:
•
•
The switching current IS depends on the device activity
The leakage current ILK depends on the device temperature
To determine the actual power consumption, always both components, switching current
IS (Table 16) and leakage current ILK (Table 17) must be added:
IDDP = IS + ILK.
Note: The power consumption values are not subject to production test. They are
verified by design/characterization.
To determine the total power consumption for dimensioning the external power
supply, also the pad driver currents must be considered.
The given power consumption parameters and their values refer to specific operating
conditions:
•
•
•
Active mode:
Regular operation, i.e. peripherals are active, code execution out of Flash.
Stopover mode:
Crystal oscillator and PLL stopped, Flash switched off, clock in domain DMP_1
stopped.
Standby mode:
Voltage domain DMP_1 switched off completely, power supply control switched off.
Note: The maximum values cover the complete specified operating range of all
manufactured devices.
The typical values refer to average devices under typical conditions, such as
nominal supply voltage, room temperature, application-oriented activity.
After a power reset, the decoupling capacitors for VDDI are charged with the
maximum possible current.
For additional information, please refer to Section 5.2, Thermal Considerations.
Note: Operating Conditions apply.
Data Sheet
85
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 16
Switching Power Consumption XC226xM
Parameter
SymValues
bol
Min. Typ.
Max.
Power supply current
ISACT
(active) with all peripherals
active and EVVRs on
Unit Note /
Test Condition
–
10 +
10 +
mA
0.6×fSYS 1.0×fSYS
Active mode1)2)3)
fSYS in [MHz]
Power supply current
in stopover mode,
EVVRs on
ISSO
–
0.7
2.0
mA
Stopover Mode3)
Power supply current
in standby mode
ISSB
–
100
250
μA
Standby mode4),
upper voltage area
Power supply current
in standby mode
ISSB
–
70
150
μA
Standby mode,
lower voltage area
1)The pad supply voltage pins (VDDPB) provide the input current for the on-chip EVVRs
and the current consumed by the pin output drivers. A small current is consumed
because the drivers’ input stages are switched.
In Fast Startup Mode (with the Flash modules deactivated), the typical current is reduced to 3 + 0.6×fSYS.
2) Please consider the additional conditions described in section “Active Mode Power Supply Current”.
3) The pad supply voltage has only a minor influence on this parameter.
4) These values are valid if the voltage validation circuits for VDDPB (SWD) and VDDIM (PVC_M) are off. Leaving
SWD and PVC_M active adds another 90 μA.
Active Mode Power Supply Current
The actual power supply current in active mode not only depends on the system
frequency but also on the configuration of the XC226xM’s subsystem.
Besides the power consumed by the device logic (Table 16) the power supply pins also
provide the current that flows through the pin output drivers.
A small current is consumed because the drivers’ input stages are switched.
The IO power domains can be supplied separately. Power domain A (VDDPA) supplies the
A/D converters and Port 6. Power domain B (VDDPB) supplies the on-chip EVVRs and all
other ports.
During operation domain A draws a maximum current of 1.5 mA for each active A/D
converter module from VDDPA.
In Fast Startup Mode (with the Flash modules deactivated), the typical current is reduced
to 3 + 0.6×fSYS mA.
Data Sheet
86
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
IS [mA]
100
ISACTmax
90
80
70
ISACTtyp
60
50
40
30
20
10
20
60
40
80
fSYS [MHz]
MC_XC2XM_IS
Figure 13
Supply Current in Active Mode as a Function of Frequency
Note: Operating Conditions apply.
Data Sheet
87
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 17
Leakage Power Consumption XC226xM
Parameter
Symbol
Min.
ILK1
Leakage supply current2)
(DMP_1 powered)
Formula3): 600,000 × e-α;
α = 5000 / (273 + B×TJ);
Typ.: B = 1.0, Max.: B = 1.3
2)
Leakage supply current
ILK0
(DMP_1 off)
Formula3): 500,000 × e-α;
α = 3000 / (273 + B×TJ);
Typ.: B = 1.0, Max.: B = 1.6
Values
Typ.
Max.
Unit Note /
Test Condition1)
–
0.03
0.05
mA
–
0.5
1.3
mA
–
2.1
6.2
mA
–
4.4
13.7
mA
–
20
35
μA
–
115
330
μA
–
270
880
μA
–
420
1,450
μA
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
1) All inputs (including pins configured as inputs) are set at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP and all outputs
(including pins configured as outputs) are disconnected.
2) The supply current caused by leakage depends mainly on the junction temperature (see Figure 14) and the
supply voltage. The temperature difference between the junction temperature TJ and the ambient temperature
TA must be taken into account. As this fraction of the supply current does not depend on device activity, it must
be added to other power consumption values.
3) This formula is valid for temperatures above 0°C. For temperatures below 0°C a value of below 10 μA can be
assumed.
Note: A fraction of the leakage current flows through domain DMP_A (pin VDDPA). This
current can be calculated as 7,000 × e-α, with α = 5000 / (273 + 1.3×TJ).
For TJ = 150°C, this results in a current of 160 μA.
Data Sheet
88
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
ILK [mA]
14
ILK1max
12
10
8
6
ILK1typ
4
2
-50
0
50
100
ILK0max
ILK0typ
TJ [°C]
150
MC_XC2X_ILK150
Figure 14
Leakage Supply Current as a Function of Temperature
Data Sheet
89
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.3
Analog/Digital Converter Parameters
These parameters describe the conditions for optimum ADC performance.
Note: Operating Conditions apply.
Table 18
A/D Converter Characteristics
Parameter
Symbol
Limit Values
Typ.
Max.
Unit Test
Condition
VAREF SR VAGND
–
VDDPA
V
1)
VAGND SR VSS
–
1.5
V
–
Analog input voltage
range
VAIN SR
VAGND
–
VAREF
V
2)
Analog clock frequency
fADCI
0.5
–
20
MHz Upper voltage
area3)
0.5
–
16.5
MHz Lower voltage
area3)
Min.
Analog reference supply
+ 1.0
Analog reference ground
+ 0.05
- 0.05
(13 + STC) × tADCI
+ 2 × tSYS
–
–
(11 + STC) × tADCI
+ 2 × tSYS
–
–
Wakeup time from analog tWAF CC
powerdown, fast mode
–
–
4
μs
–
Wakeup time from analog tWAS CC
powerdown, slow mode
–
–
15
μs
–
Broken wire detection
delay against VAGND
tBWG CC
–
–
50
5)
Result below
10% (66H)
Broken wire detection
delay against VAREF
tBWR CC
–
–
50
6)
Result above
80% (332H)
Total unadjusted error7)
TUE CC
–
±1
±2
LSB VAREF = 5.0 V1)
DNL error
EADNL CC –
±0.8
±1
LSB
INL error
EAINL CC –
±0.8
±1.2
LSB
Gain error
EAGAIN
CC
–
±0.4
±0.8
LSB
Offset error
EAOFF CC –
±0.5
±0.8
LSB
Conversion time for 10-bit tC10 CC
result4)
Conversion time for 8-bit
result4)
Data Sheet
tC8 CC
90
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 18
A/D Converter Characteristics (cont’d)
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit Test
Condition
Total capacitance
of an analog input
CAINT CC –
–
10
pF
8)9)
Switched capacitance
of an analog input
CAINS CC –
–
4
pF
8)9)
Resistance of
the analog input path
RAIN CC
–
–
2
kΩ
8)9)
Total capacitance
of the reference input
CAREFT
–
–
15
pF
8)9)
Switched capacitance
of the reference input
CAREFS
–
–
7
pF
8)9)
Resistance of
the reference input path
RAREF CC –
–
2
kΩ
8)9)
CC
CC
1) TUE is tested at VAREFx = VDDPA, VAGND = 0 V. It is verified by design for all other voltages within the defined
voltage range.
The specified TUE is valid only if the absolute sum of input overload currents on Port 5 or Port 15 pins (see
IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the measurement time.
2) VAIN may exceed VAGND or VAREFx up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
3) The limit values for fADCI must not be exceeded when selecting the peripheral frequency and the prescaler
setting.
4) This parameter includes the sample time (also the additional sample time specified by STC), the time to
determine the digital result and the time to load the result register with the conversion result.
Values for the basic clock tADCI depend on programming and are found in Table 19.
5) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 500 μs.
6) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 10 μs. This function is influenced by leakage current, in particular at high
temperature.
7) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of
individual errors.
All error specifications are based on measurement methods standardized by IEEE 1241.2000.
8) Not subject to production test - verified by design/characterization.
9) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation. At room temperature and nominal
supply voltage the following typical values can be used:
CAINTtyp = 12 pF, CAINStyp = 5 pF, RAINtyp = 1.0 kΩ, CAREFTtyp = 15 pF, CAREFStyp = 10 pF, RAREFtyp = 1.0 kΩ.
Data Sheet
91
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
RSource
V AIN
R AIN, On
C AINT - C AINS
C Ext
A/D Converter
CAINS
MCS05570
Figure 15
Data Sheet
Equivalent Circuitry for Analog Inputs
92
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Sample time and conversion time of the XC226xM’s A/D converters are programmable.
The timing above can be calculated using Table 19.
The limit values for fADCI must not be exceeded when selecting the prescaler value.
Table 19
A/D Converter Computation Table
GLOBCTR.5-0
(DIVA)
A/D Converter
Analog Clock fADCI
INPCRx.7-0
(STC)
000000B
fSYS
fSYS / 2
fSYS / 3
fSYS / (DIVA+1)
fSYS / 63
fSYS / 64
00H
000001B
000010B
:
111110B
111111B
01H
02H
:
FEH
FFH
Sample Time1)
tS
tADCI × 2
tADCI × 3
tADCI × 4
tADCI × (STC+2)
tADCI × 256
tADCI × 257
1) The selected sample time is doubled if broken wire detection is active (due to the presampling phase).
Converter Timing Example A:
Assumptions:
Analog clock
Sample time
fSYS
fADCI
tS
= 80 MHz (i.e. tSYS = 12.5 ns), DIVA = 03H, STC = 00H
= fSYS / 4 = 20 MHz, i.e. tADCI = 50 ns
= tADCI × 2 = 100 ns
Conversion 10-bit:
tC10
= 13 × tADCI + 2 × tSYS = 13 × 50 ns + 2 × 12.5 ns = 0.675 μs
Conversion 8-bit:
tC8
= 11 × tADCI + 2 × tSYS = 11 × 50 ns + 2 × 12.5 ns = 0.575 μs
Converter Timing Example B:
Assumptions:
Analog clock
Sample time
fSYS
fADCI
tS
= 40 MHz (i.e. tSYS = 25 ns), DIVA = 02H, STC = 03H
= fSYS / 3 = 13.3 MHz, i.e. tADCI = 75 ns
= tADCI × 5 = 375 ns
Conversion 10-bit:
tC10
= 16 × tADCI + 2 × tSYS = 16 × 75 ns + 2 × 25 ns = 1.25 μs
Conversion 8-bit:
tC8
Data Sheet
= 14 × tADCI + 2 × tSYS = 14 × 75 ns + 2 × 25 ns = 1.10 μs
93
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.4
System Parameters
The following parameters specify several aspects which are important when integrating
the XC226xM into an application system.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 20
Various System Parameters
Parameter
Supply watchdog (SWD)
supervision level
(see Table 21)
Symbol
VSWD
CC
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
VLV -
VLV
VLV +
V
VLV -
VLV
VLV +
V
0.15
0.10
1)
0.15
VLV = selected
voltage in upper
voltage area
0.15
VLV = selected
voltage in lower
voltage area
Core voltage (PVC)
supervision level
(see Table 22)
VPVC CC VLV -
VLV
VLV +
V
Wakeup clock source
frequency
fWU CC
400
500
600
kHz
FREQSEL=00B
210
270
330
kHz
FREQSEL=01B
140
180
220
kHz
FREQSEL=10B
110
140
170
kHz
FREQSEL=11B
4.8
5.0
5.2
MHz
–
1
%
Rel. to current
start frequency
Internal clock source
frequency
0.03
fINT CC
Short-term3) deviation of
dfINT CC -1
int. clock source frequency
0.07
2)
VLV = selected
voltage
Startup time from
stopover mode
tSSO CC 200
260
320
μs
User instruction
from PSRAM
Startup time from
standby mode
tSSB CC 2.5
2.8
3.5
ms
User instruction
from Flash
1) The limit VLV - 0.10 V is valid for the OK1 level. The limit for the OK2 level is VLV - 0.15 V.
2) This value includes a hysteresis of approximately 50 mV for rising voltage.
3) The short-term frequency deviation refers to a timeframe of 20 ms and is measured relative to the current
frequency at the beginning of the respective timeframe.
The short-term deviation with the duration of a LIN-frame allows error-free transmission.
Data Sheet
94
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 21
Coding of Bitfields LEVxV in Register SWDCON0
Code
Default Voltage Level
0000B
2.9 V
0001B
3.0 V
0010B
3.1 V
0011B
3.2 V
0100B
3.3 V
0101B
3.4 V
0110B
3.6 V
0111B
4.0 V
1000B
4.2 V
1001B
4.5 V
1010B
4.6 V
1011B
4.7 V
1100B
4.8 V
1101B
4.9 V
1110B
5.0 V
1111B
5.5 V
Notes1)
LEV1V: reset request
LEV2V: no request
1) The indicated default levels are selected automatically after a power reset.
Table 22
Coding of Bitfields LEVxV in Registers PVCyCONz
Notes1)
Code
Default Voltage Level
000B
0.95 V
001B
1.05 V
010B
1.15 V
011B
1.25 V
100B
1.35 V
LEV1V: reset request
101B
1.45 V
LEV2V: interrupt request
110B
1.55 V
111B
1.65 V
1) The indicated default levels are selected automatically after a power reset.
Data Sheet
95
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.5
Flash Memory Parameters
The XC226xM is delivered with all Flash sectors erased and with no protection installed.
The data retention time of the XC226xM’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 23
Flash Characteristics
Parameter
Symbol
Limit Values
Min.
Typ.
1)
Unit
Note / Test
Condition
3.5
ms
ms
Max.
Programming time per
128-byte page
tPR
–
3
Erase time per
sector/page
tER
–
71)
8
ms
ms
Data retention time
tRET
20
–
–
years
1,000 erase /
program
cycles
Flash erase endurance for NER
user sectors2)
15,000 –
–
cycles Data retention
time 5 years
Flash erase endurance for NSEC
security pages
10
–
–
cycles Data retention
time 20 years
32
–
–
cycles
3)
–
–
1
–
Unrestricted4)
execution
–
–
4
–
Restricted5)
execution
Drain disturb limit
Parallel Flash module
program/erase limit,
depending on the Flash
read activity
NDD
NPP
1) Programming and erase times depend on the internal Flash clock source. The control state machine needs a
few system clock cycles. This requirement is only relevant for extremely low system frequencies.
2) A maximum of 64 Flash sectors can be cycled 15,000 times. For all other sectors the limit is 1,000 cycles.
3) This parameter limits the number of subsequent programming operations within a physical sector. The drain
disturb limit is applicable if wordline erase is used repeatedly. For normal sector erase/program cycles this
limit will not be violated.
4) Flash module 3 can be erased/programmed while code is executed and/or data is read from any other Flash
modules.
5) All Flash modules can be erased/programmed while code is executed and/or data is read from only one Flash
module or from PSRAM.
The Flash module that delivers code/data can, of course, not be erased/programmed.
Data Sheet
96
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Access to the XC226xM Flash modules is controlled by the IMB. Built-in prefetch
mechanisms optimize the performance for sequential access.
Flash access waitstates only affect non-sequential access. Due to prefetch
mechanisms, the performance for sequential access (depending on the software
structure) is only partially influenced by waitstates.
Table 24
Flash Access Waitstates
Required Waitstates
System Frequency Range
4 WS (WSFLASH = 100B)
1 WS (WSFLASH = 001B)
fSYS ≤ fSYSmax
fSYS ≤ 17 MHz
fSYS ≤ 13 MHz
fSYS ≤ 8 MHz
0 WS (WSFLASH = 000B)
Forbidden! Must not be selected!
3 WS (WSFLASH = 011B)
2 WS (WSFLASH = 010B)
Note: The maximum achievable system frequency is limited by the properties of the
respective derivative.
Data Sheet
97
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.6
AC Parameters
These parameters describe the dynamic behavior of the XC226xM.
4.6.1
Testing Waveforms
These values are used for characterization and production testing (except pin XTAL1).
Output delay
Output delay
Hold time
Hold time
0.8 V DDP
0.7 V DDP
Input Signal
(driven by tester)
0.3 V DDP
0.2 V DDP
Output Signal
(measured)
Output timings refer to the rising edge of CLKOUT.
Input timings are calculated from the time, when the input signal reaches
V IH or V IL, respectively.
MCD05556C
Figure 16
Input Output Waveforms
VLoad + 0.1 V
Timing
Reference
Points
V Load - 0.1 V
V OH - 0.1 V
V OL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, but begins to float when a 100 mV
change from the loaded V OH /V OL level occurs (IOH / IOL = 20 mA).
MCA05565
Figure 17
Data Sheet
Floating Waveforms
98
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.6.2
Definition of Internal Timing
The internal operation of the XC226xM is controlled by the internal system clock fSYS.
Because the system clock signal fSYS can be generated from a number of internal and
external sources using different mechanisms, the duration of the system clock periods
(TCSs) and their variation (as well as the derived external timing) depend on the
mechanism used to generate fSYS. This must be considered when calculating the timing
for the XC226xM.
Phase Locked Loop Operation (1:N)
f IN
f SYS
TCS
Direct Clock Drive (1:1)
f IN
f SYS
TCS
Prescaler Operation (N:1)
f IN
f SYS
TCS
M C_XC2X_CLOCKGEN
Figure 18
Generation Mechanisms for the System Clock
Note: The example of PLL operation shown in Figure 18 uses a PLL factor of 1:4; the
example of prescaler operation uses a divider factor of 2:1.
The specification of the external timing (AC Characteristics) depends on the period of the
system clock (TCS).
Data Sheet
99
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11B), the system clock is
derived directly from the input clock signal CLKIN1:
fSYS = fIN.
The frequency of fSYS is the same as the frequency of fIN. In this case the high and low
times of fSYS are determined by the duty cycle of the input clock fIN.
Selecting Bypass Operation from the XTAL11) input and using a divider factor of 1 results
in a similar configuration.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY =
1B), the system clock is derived either from the crystal oscillator (input clock signal
XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1):
fSYS = fOSC / K1.
If a divider factor of 1 is selected, the frequency of fSYS equals the frequency of fOSC. In
this case the high and low times of fSYS are determined by the duty cycle of the input
clock fOSC (external or internal).
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
fSYS = fOSC / 1024.
Phase Locked Loop (PLL)
When PLL operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 0B),
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (fSYS = fIN × F).
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P × K2)).
The input clock can be derived either from an external source at XTAL1 or from the onchip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of fSYS so that it is
locked to fIN. The slight variation causes a jitter of fSYS which in turn affects the duration
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage VDDI1.
Data Sheet
100
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the
minimum TCS possible under the given circumstances.
The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is
constantly adjusting its output frequency to correspond to the input frequency (from
crystal or oscillator), the accumulated jitter is limited. This means that the relative
deviation for periods of more than one TCS is lower than for a single TCS (see formulas
and Figure 19).
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler K2 to generate the system clock signal fSYS. The number of VCO cycles
is K2 × T, where T is the number of consecutive fSYS cycles (TCS).
The maximum accumulated jitter (long-term jitter) DTmax is defined by:
DTmax [ns] = ±(220 / (K2 × fSYS) + 4.3)
This maximum value is applicable, if either the number of clock cycles T > (fSYS / 1.2) or
the prescaler value K2 > 17.
In all other cases for a timeframe of T × TCS the accumulated jitter DT is determined by:
DT [ns] = DTmax × [(1 - 0.058 × K2) × (T - 1) / (0.83 × fSYS - 1) + 0.058 × K2]
fSYS in [MHz] in all formulas.
Example, for a period of 3 TCSs @ 33 MHz and K2 = 4:
Dmax = ±(220 / (4 × 33) + 4.3) = 5.97 ns (Not applicable directly in this case!)
D3 = 5.97 × [(1 - 0.058 × 4) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 4]
= 5.97 × [0.768 × 2 / 26.39 + 0.232]
= 1.7 ns
Example, for a period of 3 TCSs @ 33 MHz and K2 = 2:
Dmax = ±(220 / (2 × 33) + 4.3) = 7.63 ns (Not applicable directly in this case!)
D3 = 7.63 × [(1 - 0.058 × 2) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 2]
= 7.63 × [0.884 × 2 / 26.39 + 0.116]
= 1.4 ns
Data Sheet
101
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Acc. jitter DT
ns
±9
fSYS = 33 MHz fSYS = 66 MHz
fVCO = 66 MHz
±8
±7
f VCO = 132 MHz
±6
±5
±4
±3
±2
±1
0
Cycles T
1
20
40
60
80
100
MC_XC 2X_JITTER
Figure 19
Approximated Accumulated PLL Jitter
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF (see Table 13).
The maximum peak-to-peak noise on the pad supply voltage (measured between
VDDPB pin 100/144 and VSS pin 1) is limited to a peak-to-peak voltage of VPP =
50 mV. This can be achieved by appropriate blocking of the supply voltage as
close as possible to the supply pins and using PCB supply and ground planes.
Different frequency bands can be selected for the VCO so that the operation of the PLL
can be adjusted to a wide range of input and output frequencies:
Table 25
VCO Bands for PLL Operation1)
PLLCON0.VCOSEL VCO Frequency Range
Base Frequency Range
00
50 … 110 MHz
10 … 40 MHz
01
100 … 160 MHz
20 … 80 MHz
1X
Reserved
1) Not subject to production test - verified by design/characterization.
Data Sheet
102
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Wakeup Clock
When wakeup operation is selected (SYSCON0.CLKSEL = 00B), the system clock is
derived from the low-frequency wakeup clock source:
fSYS = fWU.
In this mode, a basic functionality can be maintained without requiring an external clock
source and while minimizing the power consumption.
Selecting and Changing the Operating Frequency
When selecting a clock source and the clock generation method, the required
parameters must be carefully written to the respective bitfields, to avoid unintended
intermediate states.
Many applications change the frequency of the system clock (fSYS) during operation in
order to optimize system performance and power consumption. Changing the operating
frequency also changes the switching currents, which influences the power supply.
To ensure proper operation of the on-chip EVRs while they generate the core voltage,
the operating frequency shall only be changed in certain steps. This prevents overshoots
and undershoots of the supply voltage.
To avoid the indicated problems, recommended sequences are provided which ensure
the intended operation of the clock system interacting with the power system.
Please refer to the Programmer’s Guide.
Data Sheet
103
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.6.3
External Clock Input Parameters
These parameters specify the external clock generation for the XC226xM. The clock can
be generated in two ways:
•
•
By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2.
By supplying an external clock signal. This clock signal can be supplied either to
pin XTAL1 (core voltage domain) or to pin CLKIN1 (IO voltage domain).
If connected to CLKIN1, the input signal must reach the defined input levels VIL and VIH.
If connected to XTAL1, a minimum amplitude VAX1 (peak-to-peak voltage) is sufficient for
the operation of the on-chip oscillator.
Note: The given clock timing parameters (t1 … t4) are only valid for an external clock
input signal.
Note: Operating Conditions apply.
Table 26
External Clock Input Characteristics
Parameter
Symbol
Limit Values
Typ.
Max.
Unit Note / Test
Condition
–
1.7
V
1)
–
–
V
Peak-to-peak
voltage2)
–
±20
μA
0 V < VIN < VDDI
–
40
MHz Clock signal
4
–
16
MHz Crystal or
Resonator
6
–
–
ns
6
–
–
ns
–
8
8
ns
–
8
8
ns
Min.
Input voltage range limits
for signal on XTAL1
Input voltage (amplitude)
on XTAL1
XTAL1 input current
Oscillator frequency
High time
Low time
Rise time
Fall time
VIX1 SR -1.7 +
VDDI
VAX1 SR 0.3 ×
VDDI
IIL CC
–
fOSC CC 4
t1 SR
t2 SR
t3 SR
t4 SR
1) Overload conditions must not occur on pin XTAL1.
2) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the
operation and the resulting voltage peaks must remain within the limits defined by VIX1.
Data Sheet
104
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
t3
t1
VOFF
VAX1
t2
t4
tOSC = 1/fOSC
MC_EXTCLOCK
Figure 20
External Clock Drive XTAL1
Note: For crystal/resonator operation, it is strongly recommended to measure the
oscillation allowance (negative resistance) in the final target system (layout) to
determine the optimum parameters for oscillator operation.
Please refer to the limits specified by the crystal/resonator supplier.
Data Sheet
105
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.6.4
Pad Properties
The output pad drivers of the XC226xM can operate in several user-selectable modes.
Strong driver mode allows controlling external components requiring higher currents
such as power bridges or LEDs. Reducing the driving power of an output pad reduces
electromagnetic emissions (EME). In strong driver mode, selecting a slower edge
reduces EME.
The dynamic behavior, i.e. the rise time and fall time, depends on the applied external
capacitance that must be charged and discharged. Timing values are given for a
capacitance of 20 pF, unless otherwise noted.
In general, the performance of a pad driver depends on the available supply voltage
VDDP. Therefore, Table 27 and Table 28 list the pad parameters for the upper voltage
range and the lower voltage range, respectively.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 27
Standard Pad Parameters (Upper Voltage Range)
Parameter
Maximum output current
Nominal output current
Symbol
IOLmax,
-IOHmax
IOLnom,
-IOHnom
Rise/Fall time (10%-90%) tR/tF
Valid for external
capacitances in the range
of 20 pF ≤ CL ≤ 100 pF
(CL in [pF])
Data Sheet
Limit Values
Min.
Typ.
Max.
Unit Note / Test
Condition
–
–
10
mA
Strong Driver
–
–
4.0
mA
Medium Driver
–
–
0.5
mA
Weak Driver
–
–
2.5
mA
Strong Driver
–
–
1.0
mA
Medium Driver
–
–
0.1
mA
Weak Driver
–
–
4.2 +
ns
0.14*CL
Strong Driver,
Fast Edge
–
–
11.6 +
ns
0.22*CL
Strong Driver,
Medium Edge
–
–
20.6 +
ns
0.22*CL
Strong Driver,
Slow Edge
–
–
23 +
0.6*CL
ns
Medium Driver
–
–
212 +
1.9*CL
ns
Weak Driver
106
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 28
Standard Pad Parameters (Lower Voltage Range)
Parameter
Symbol
Maximum output current1) IOLmax,
-IOHmax
Nominal output current
IOLnom,
-IOHnom
Rise/Fall time (10%-90%) tR/tF
Valid for external
capacitances in the range
of 20 pF ≤ CL ≤ 100 pF
(CL in [pF])
Limit Values
Min.
Typ.
Max.
Unit Note / Test
Condition
–
–
10
mA
Strong Driver
–
–
2.5
mA
Medium Driver
–
–
0.5
mA
Weak Driver
–
–
2.5
mA
Strong Driver
–
–
1.0
mA
Medium Driver
–
–
0.1
mA
Weak Driver
–
–
6.2 +
ns
0.24*CL
Strong Driver,
Fast Edge
–
–
24 +
0.3*CL
ns
Strong Driver,
Medium Edge
–
–
34 +
0.3*CL
ns
Strong Driver,
Slow Edge
–
–
37 +
ns
0.65*CL
Medium Driver
–
–
500 +
2.5*CL
Weak Driver
ns
1) An output current above |IOXnom| may be drawn from up to three pins at the same time. For any group of 16
neighboring output pins, the total output current in each direction (ΣIOL and Σ-IOH) must remain below 50 mA.
Data Sheet
107
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.6.5
External Bus Timing
The following parameters specify the behavior of the XC226xM bus interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 29
CLKOUT Reference Signal
Parameter
Symbol
Limits
Min.
t5
t6
t7
t8
t9
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
Unit Note / Test
Condition
Max.
40/25/12.51)
CC
ns
CC 3
–
ns
CC 3
–
ns
CC –
3
ns
CC –
3
ns
1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fSYS = 25/40/80 MHz).
For longer periods the relative deviation decreases (see PLL deviation formula).
t9
t5
t6
t7
t8
CLKOUT
MC_X_EBCCLKOUT
Figure 21
CLKOUT Signal Timing
Note: The term CLKOUT refers to the reference clock output signal which is generated
by selecting fSYS as the source signal for the clock output signal EXTCLK on pin
P2.8 and by enabling the high-speed clock driver on this pin.
Data Sheet
108
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Variable Memory Cycles
External bus cycles of the XC226xM are executed in five consecutive cycle phases (AB,
C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module
using the READY handshake input.
This table provides a summary of the phases and the ranges for their length.
Table 30
Programmable Bus Cycle Phases (see timing diagrams)
Bus Cycle Phase
Parameter
Valid Values Unit
Address setup phase, the standard duration of this tpAB
phase (1 … 2 TCS) can be extended by 0 … 3 TCS
if the address window is changed
1 … 2 (5)
TCS
Command delay phase
tpC
0…3
TCS
Write Data setup/MUX Tristate phase
tpD
0…1
TCS
Access phase
tpE
1 … 32
TCS
Address/Write Data hold phase
tpF
0…3
TCS
Note: The bandwidth of a parameter (from minimum to maximum value) covers the
whole operating range (temperature, voltage) as well as process variations. Within
a given device, however, this bandwidth is smaller than the specified range. This
is also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Note: Operating Conditions apply.
Data Sheet
109
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 31
External Bus Cycle Timing for Upper Voltage Range
Parameter
Symbol
Limits
Min.
Typ.
Unit Note
Max.
Output valid delay for:
RD, WR(L/H)
t10 CC
–
13
ns
Output valid delay for:
BHE, ALE
t11 CC
–
14
ns
Address output valid delay for:
A23 … A16, A15 … A0
t12 CC
–
14
ns
Address output valid delay for:
AD15 … AD0
t13 CC
–
15
ns
Output valid delay for:
CS
t14 CC
–
13
ns
Data output valid delay for:
AD15 … AD0 (write data, MUX)
t15 CC
–
15
ns
Data output valid delay for:
D15 … D0 (write data, DEMUX)
t16 CC
–
15
ns
Output hold time for:
RD, WR(L/H)
t20 CC
-2
8
ns
Output hold time for:
BHE, ALE
t21 CC
-2
10
ns
Address output hold time for:
AD15 … AD0
t23 CC
-3
8
ns
Output hold time for:
CS
t24 CC
-3
11
ns
Data output hold time for:
D15 … D0, AD15 … AD0
t25 CC
-3
8
ns
Input setup time for:
READY, D15 … D0, AD15 … AD0
(read data)
t30 SR
25
–
ns
Input hold time for:
READY, D15 … D0, AD15 … AD0
(read data)1)
t31 SR
0
–
ns
1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge
of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can
change after the rising edge of RD.
Data Sheet
110
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 32
External Bus Cycle Timing for Lower Voltage Range
Parameter
Symbol
Limits
Min.
Typ.
Unit Note
Max.
Output valid delay for:
RD, WR(L/H)
t10 CC
–
20
ns
Output valid delay for:
BHE, ALE
t11 CC
–
21
ns
Address output valid delay for:
A23 … A16, A15 … A0
t12 CC
–
22
ns
Address output valid delay for:
AD15 … AD0
t13 CC
–
22
ns
Output valid delay for:
CS
t14 CC
–
13
ns
Data output valid delay for:
AD15 … AD0 (write data, MUX)
t15 CC
–
22
ns
Data output valid delay for:
D15 … D0 (write data, DEMUX)
t16 CC
–
22
ns
Output hold time for:
RD, WR(L/H)
t20 CC
-2
10
ns
Output hold time for:
BHE, ALE
t21 CC
-2
10
ns
Address output hold time for:
AD15 … AD0
t23 CC
-3
10
ns
Output hold time for:
CS
t24 CC
-3
11
ns
Data output hold time for:
D15 … D0, AD15 … AD0
t25 CC
-3
10
ns
Input setup time for:
READY, D15 … D0, AD15 … AD0
(read data)
t30 SR
29
–
ns
Input hold time for:
READY, D15 … D0, AD15 … AD0
(read data)1)
t31 SR
0
–
ns
1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge
of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can
change after the rising edge of RD.
Data Sheet
111
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
tpAB
tpC
tpD
tpE
tpF
CLKOUT
t21
t11
ALE
t11/ t12/t14
A23-A16,
BHE, CSx
t24
High Address
t20
t10
RD
WR(L/H)
t31
t13
AD15-AD0
(read)
AD15-AD0
(write)
t23
Low Address
t30
Data In
t13
t15
Low Address
t25
Data Out
MC_X_EBCMUX
Figure 22
Data Sheet
Multiplexed Bus Cycle
112
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
tpAB
tpC
tpD
tpE
tpF
CLKOUT
t21
t11
ALE
t11/ t12/t14
A23-A0,
BHE, CSx
t24
Address
t20
t10
RD
WR(L/H)
t31
t30
D15-D0
(read)
Data In
t16
D15-D0
(write)
t25
Data Out
MC_X_EBCDEMUX
Figure 23
Data Sheet
Demultiplexed Bus Cycle
113
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Bus Cycle Control with the READY Input
The duration of an external bus cycle can be controlled by the external circuit using the
READY input signal. The polarity of this input signal can be selected.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
An asynchronous READY signal puts no timing constraints on the input signal but incurs
a minimum of one waitstate due to the additional synchronization stage. The minimum
duration of an asynchronous READY signal for safe synchronization is one CLKOUT
period plus the input setup time.
An active READY signal can be deactivated in response to the trailing (rising) edge of
the corresponding command (RD or WR).
If the next bus cycle is controlled by READY, an active READY signal must be disabled
before the first valid sample point in the next bus cycle. This sample point depends on
the programmed phases of the next cycle.
Data Sheet
114
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
tpD
tpE
tpRDY
tpF
CLKOUT
t10
t20
RD, WR
t31
t30
D15-D0
(read)
Data In
t25
D15-D0
(write)
Data Out
t31
t30
READY
Synchronous
Not Rdy
t31
t30
READY
t31
t30
READY
Asynchron.
t31
t30
Not Rdy
READY
MC_X_EBCREADY
Figure 24
READY Timing
Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”)
a READY-controlled waitstate is inserted (tpRDY),
sampling the READY input active at the indicated sampling point (“Ready”)
terminates the currently running bus cycle.
Note the different sampling points for synchronous and asynchronous READY.
This example uses one mandatory waitstate (see tpE) before the READY input
value is used.
Data Sheet
115
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.6.6
Synchronous Serial Interface Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 33
SSC Master/Slave Mode Timing for Upper Voltage Range
Parameter
Symbol
Values
Unit Note /
Test Co
ndition
Min.
Typ.
Max.
t1 CC
tSYS
–
1)
ns
Slave select output SELO inactive t2 CC
after last SCLKOUT receive edge
tSYS
–
3)
ns
Master Mode Timing
Slave select output SELO active
to first SCLKOUT transmit edge
2)
-8
-6
t3 CC
t4 SR
-6
–
9
ns
31
–
–
ns
t5 SR
-4
–
–
ns
Select input DX2 setup to first
clock input DX1 transmit edge
t10 SR
7
–
–
ns
4)
Select input DX2 hold after last
clock input DX1 receive edge
t11 SR
7
–
–
ns
4)
Data input DX0 setup time to
clock input DX1 receive edge
t12 SR
7
–
–
ns
4)
Data input DX0 hold time from
clock input DX1 receive edge
t13 SR
5
–
–
ns
4)
Data output DOUT valid time
t14 CC
7
–
33
ns
4)
Transmit data output valid time
Receive data input setup time to
SCLKOUT receive edge
Data input DX0 hold time from
SCLKOUT receive edge
Slave Mode Timing
1) The maximum value further depends on the settings for the slave select output leading delay.
2) tSYS = 1/fSYS (= 12.5 ns @ 80 MHz)
3) The maximum value depends on the settings for the slave select output trailing delay and for the shift clock
output delay.
4) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
116
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 34
SSC Master/Slave Mode Timing for Lower Voltage Range
Parameter
Symbol
Values
Unit Note /
Test Co
ndition
Min.
Typ.
Max.
t1 CC
tSYS
–
1)
ns
2)
Slave select output SELO inactive t2 CC
after last SCLKOUT receive edge
tSYS
–
3)
ns
2)
Master Mode Timing
Slave select output SELO active
to first SCLKOUT transmit edge
- 10
-9
t3 CC
t4 SR
-7
–
11
ns
40
–
–
ns
t5 SR
-5
–
–
ns
Select input DX2 setup to first
clock input DX1 transmit edge
t10 SR
7
–
–
ns
4)
Select input DX2 hold after last
clock input DX1 receive edge
t11 SR
7
–
–
ns
4)
Data input DX0 setup time to
clock input DX1 receive edge
t12 SR
7
–
–
ns
4)
Data input DX0 hold time from
clock input DX1 receive edge
t13 SR
5
–
–
ns
4)
Data output DOUT valid time
t14 CC
8
–
41
ns
4)
Transmit data output valid time
Receive data input setup time to
SCLKOUT receive edge
Data input DX0 hold time from
SCLKOUT receive edge
Slave Mode Timing
1) The maximum value further depends on the settings for the slave select output leading delay.
2) tSYS = 1/fSYS (= 12.5 ns @ 80 MHz)
3) The maximum value depends on the settings for the slave select output trailing delay and for the shift clock
output delay.
4) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
117
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Master Mode Timing
t1
Select Output
SELOx
t2
Inactive
Inactive
Active
Clock Output
SCLKOUT
Receive
Edge
First Transmit
Edge
Last Receive
Edge
Transmit
Edge
t3
t3
Data Output
DOUT
t4
Data Input
DX0
t4
t5
Data
valid
t5
Data
valid
Slave Mode Timing
t10
Select Input
DX2
Clock Input
DX1
t11
Inactive
Inactive
Active
Receive
Edge
First Transmit
Edge
t12
Data Input
DX0
t12
t13
Data
valid
t 14
Last Receive
Edge
Transmit
Edge
t 13
Data
valid
t14
Data Output
DOUT
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched
.
Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.
USIC_SSC_TMGX.VSD
Figure 25
USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration where the slave select signal
is low-active and the serial clock signal is not shifted and not inverted.
Data Sheet
118
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.6.7
Debug Interface Timing
The debugger can communicate with the XC226xM either via the 2-pin DAP interface or
via the standard JTAG interface.
Debug via JTAG
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 35
JTAG Interface Timing Parameters for Upper Voltage Range
Parameter
Min.
Typ.
Max.
Unit Note /
Test Condition
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
50
–
–
ns
16
–
–
ns
16
–
–
ns
–
–
8
ns
–
–
8
ns
6
–
–
ns
TDI/TMS hold
after TCK rising edge
t7 SR
6
–
–
ns
TDO valid
after TCK falling edge2)
t8 CC
–
25
29
ns
TDO high imped. to valid
from TCK falling edge2)3)
t9 CC
–
25
29
ns
TDO valid to high imped.
from TCK falling edge2)
t10 CC
–
25
29
ns
TDO hold after
TCK falling edge2)
t18 CC
5
–
–
ns
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
Symbol
Values
1)
1) Under typical conditions, the JTAG interface can operate at transfer rates up to 20 MHz.
2) The falling edge on TCK is used to generate the TDO timing.
3) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
119
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 36
JTAG Interface Timing Parameters for Lower Voltage Range
Parameter
Symbol
Min.
Typ.
Max.
Unit Note /
Test Condition
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
50
–
–
ns
16
–
–
ns
16
–
–
ns
–
–
8
ns
–
–
8
ns
6
–
–
ns
TDI/TMS hold
after TCK rising edge
t7 SR
6
–
–
ns
TDO valid
after TCK falling edge1)
t8 CC
–
32
36
ns
TDO high imped. to valid
from TCK falling edge2)3)
t9 CC
–
32
36
ns
TDO valid to high imped.
from TCK falling edge1)
t10 CC
–
32
36
ns
TDO hold after
TCK falling edge1)
t18 CC
5
–
–
ns
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
Values
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
3) The setup time for TDO is given implicitly by the TCK cycle time.
t1
0.9 VDDP
0.5 VDDP
t2
t5
t3
t4
0.1 VDDP
MC_JTAG_TCK
Figure 26
Data Sheet
Test Clock Timing (TCK)
120
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
TCK
t6
t7
t6
t7
TMS
TDI
t9
t8
t10
TDO
t18
Figure 27
Data Sheet
MC_JTAG
JTAG Timing
121
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 37
DAP Interface Timing Parameters for Upper Voltage Range
Parameter
Min.
Typ.
Max.
Unit Note /
Test Condition
t11 SR
t12 SR
t13 SR
t14 SR
t15 SR
t16 SR
25
–
–
ns
–
8
–
–
ns
–
8
–
–
ns
–
–
–
4
ns
–
–
–
4
ns
–
6
–
–
ns
–
DAP1 hold
after DAP0 rising edge
t17 SR
6
–
–
ns
–
DAP1 valid per DAP0
clock period1)
t19 CC
17
20
–
ns
–
DAP0 clock period
DAP0 high time
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup
to DAP0 rising edge
Symbol
Values
1) The Host has to find a suitable sampling point by analyzing the sync telegram response.
Data Sheet
122
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 38
DAP Interface Timing Parameters for Lower Voltage Range
Parameter
Symbol
Min.
Typ.
Max.
Unit Note /
Test Condition
t11 SR
t12 SR
t13 SR
t14 SR
t15 SR
t16 SR
25
–
–
ns
–
8
–
–
ns
–
8
–
–
ns
–
–
–
4
ns
–
–
–
4
ns
–
6
–
–
ns
–
DAP1 hold
after DAP0 rising edge
t17 SR
6
–
–
ns
–
DAP1 valid per DAP0
clock period1)
t19 CC
12
17
–
ns
–
DAP0 clock period
DAP0 high time
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup
to DAP0 rising edge
Values
1) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t 11
0.9 VDDP
0.5 VDDP
t12
t15
t13
t 14
0.1 VDDP
MC_DAP0
Figure 28
Data Sheet
Test Clock Timing (DAP0)
123
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Electrical Parameters
DAP0
t1 6
t17
DAP1
MC_ DAP1_RX
Figure 29
Data Transfer Timing Host to Device (DAP1)
t1 1
DAP1
t1 9
MC_ DAP1_TX
Figure 30
Data Transfer Timing Device to Host (DAP1)
Note: The transmission timing is determined by the receiving debugger by evaluating the
sync-request synchronization pattern telegram.
Data Sheet
124
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Package and Reliability
5
Package and Reliability
In addition to the electrical parameters, the following specifications ensure proper
integration of the XC226xM into the target system.
5.1
Packaging
These parameters specify the packaging rather than the silicon.
Table 39
Package Parameters (PG-LQFP-100-8)
Parameter
Symbol
Limit Values
Min.
Unit Notes
Max.
Exposed Pad Dimension
Ex × Ey –
6.2 × 6.2
mm
–
Power Dissipation
PDISS
RΘJA
–
1.0
W
–
–
47
K/W No thermal via1)
29
K/W 4-layer, no pad2)
23
K/W 4-layer, pad3)
Thermal resistance
Junction-Ambient
1) Device mounted on a 2-layer JEDEC board (according to JESD 51-3) or a 4-layer board without thermal vias;
exposed pad not soldered.
2) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad not
soldered.
3) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad soldered
to the board.
Note: To improve the EMC behavior, it is recommended to connect the exposed pad to
the board ground, independent of the thermal requirements.
Board layout examples are given in an application note.
Package Compatibility Considerations
The XC226xM is a member of the XC2000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar series and subfamilies.
Each package is optimized for the chip it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the Exposed Pad (if present) may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
Data Sheet
125
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Package and Reliability
H
0.5
7˚ MAX.
+0.05
0.15 -0.06
1.6 MAX.
1.4 ±0.05
0.1 ±0.05
Package Outlines
0.6 ±0.15
0.08 C 100x
C
12
0.22 ±0.05
0.08 M A-B D C 100x
16
14
1)
0.2 A-B D 100x
Bottom View
0.2 A-B D H 4x
Ex
Ey
16
B
14
A
1)
D
100
100
1
1
Index Marking
Exposed Diepad
1) Does not include plastic or metal protrusion of 0.25 max. per side
PG-LQFP-100-3, -4, -8-PO V11
Figure 31
PG-LQFP-100-8 (Plastic Green Thin Quad Flat Package)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
Data Sheet
126
V2.0, 2009-03
XC2268M/67M, XC2265M/64M/63M
XC2000 Family Derivatives / Base Line
Package and Reliability
5.2
Thermal Considerations
When operating the XC226xM in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting thermal
damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 150 °C.
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
•
•
•
•
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
Data Sheet
127
V2.0, 2009-03
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
B158-H9270-G3-X-7600