EXAR XR19L200

XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
MAY 2007
REV. 1.0.1
GENERAL DESCRIPTION
APPLICATIONS
The XR19L200 (L200) is a highly integrated device that
combines a single channel Universal Asynchronous
Receiver and Transmitter (UART) and an RS-232
transceiver. The L200 is designed to operate with a single
3.3V or 5V power supply. The L200 is fully compliant with
EIA/TIA-232-F Standards from a +3.0V to +5.5V power
supply. The device operates at 250 Kbps data rate with
worst case 3K ohms load. Both RS-232 driver outputs and
receiver inputs can operate in harsh electrical environments
of +/-15V without damage and can survive multiple +/-15kV
ESD on the RS-232 lines, while maintaining RS-232 output
levels.
The L200 operates in three different modes: Awake, Partial
Sleep, and Full Sleep. Each mode can be invoked via
hardware or software. In the Awake mode, all functions are
active. In the Partial Sleep mode, the internal crystal
oscillator or charge pump is turned off. In Full Sleep mode,
the internal crystal oscillator and the charge pump is shut
down. All the RS-232 receivers remain active in any of
these four modes.
• Battery-Powered Equipment
• Handheld and Mobile Devices
• Handheld Terminals
• Industrial Peripheral Interfaces
• Point-of-Sale (POS) Systems
FEATURES
• Meets true EIA/TIA-232-F Standards from a 3.0 V to 5.5V
operation
• Up to 250 Kbps data transmission rate
• 45us sleep mode exit (charge pump to full power)
• ESD protection for RS-232 I/O pins at
■
■
■
+/-15kV - Human Body Model
+/-15kV - IEC 1000-4-2, Air-Gap Discharge
+/- 8kV - IEC 1000-4-2, Contact Discharge
• Software compatible with industry standard 16550 UART
• Intel/Motorola bus select
• Quarter-modem interface (TXD, RXD)
• Sleep modes to conserve battery power
• Wake-up interrupt upon exiting low power modes
C1-
C1+
C2-
C2+
ACP
GND
VCC
(3.0 to 5.5V)
XTAL2
XTAL1
FIGURE 1. BLOCK DIAGRAM
IOR#
IOW# (R/W#)
CS#
INT (IRQ#)
RESET (RESET#)
I/M#
*5 V
Tolerant
Inputs
Crystal
Osc/Buffer
UART Registers
A2:A0
D7:D0
Intel or Motorola Bus Interface
VREF+
BRG
16 Byte
TX FIFO
16 Byte
RX FIFO
Charge Pump
VREFTX
TXD
RX
5K
RXD
Modem
I/Os
UART
RS-232 Transceiver
XR19L200
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
32 31 30 29 28 27 26 25
XR19L200
Intel Bus Mode
32-pin QFN
24
23
22
21
20
19
18
17
C1+
RESET
GND
INT
A0
A1
A2
VREF-
GND
RXD
I/M#
D5
GND
D6
D7
CS#
TXD
VCC
VREF+
C1 -
D2
D1
D0
24
23
22
Motorola Bus Mode 21
20
32-pin QFN
19
18
17
XR19L200
C 1+
RESET#
GND
IRQ#
A0
A1
A2
VREF -
9 10 11 12 13 14 15 16
XTAL1
IOR#
C2+
C2-
IOW#
ACP
GND
XTAL1
XTAL2
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
C2-
1
2
3
4
5
6
7
8
GND
NC
C2+
RXD
I/M#
D5
GND
D6
D7
CS#
TXD
32 31 30 29 28 27 26 25
XTAL2
R/W#
ACP
VCC
D3
D4
C1 -
VCC
VREF+
D1
D0
D3
D2
D4
FIGURE 2. PIN OUT OF THE DEVICE
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
DEVICE STATUS
XR19L200IL32
32-QFN
-40°C to +85°C
Active
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XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
PIN DESCRIPTIONS
Pin Descriptions
NAME
32-QFN
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE (CMOS/TTL Voltage Levels)
A2
A1
A0
18
19
20
I
D7
D6
D5
D4
D3
D2
D1
D0
6
5
3
32
31
30
29
28
I/O
IOR#
(NC)
14
I
When I/M# pin is HIGH, the Intel bus interface is selected and this input becomes read
strobe (active LOW). The falling edge instigates an internal read cycle and retrieves the
data byte from an internal register pointed by the address lines [A2:A0], puts the data byte
on the data bus to allow the host processor to read it on the rising edge.
When I/M# pin is LOW, the Motorola bus interface is selected and this input is not used.
IOW#
(R/W#)
11
I
When I/M# pin is HIGH, it selects Intel bus interface and this input becomes write strobe
(active LOW). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines.
When I/M# pin is LOW, the Motorola bus interface is selected and this input becomes read
(HIGH) and write (LOW) signal.
CS#
7
I
This input is chip select (active LOW) to enable the device.
INT
(IRQ#)
21
Address bus lines [2:0]. These 3 address lines select one of the internal registers in the
UART during a data bus transaction.
Data bus lines [7:0] (bidirectional).
O When I/M# pin is HIGH, it selects Intel bus interface and this output become the active
(OD) HIGH device interrupt output. This output is enabled through the software setting of MCR[3]:
set to the active mode when MCR[3] is set to a logic 1, and set to the three state mode when
MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output becomes the active
LOW, open-drain interrupt output. An external pull-up resistor is required for proper operation. MCR[3] must be set to a logic 0 for proper operation of the interrupt.
MODEM OR SERIAL I/O INTERFACE (EIA-232/RS-232 Voltage Levels)
TXD
8
O
UART Transmit Data. The TX signal will be LOW (< -5V) during reset or idle (no data).
RXD
1
I
UART Receive Data. The RX data input must idle LOW (< -3V).
ANCILLARY SIGNALS (CMOS/TTL Voltage Levels)
XTAL1
9
I
Crystal or external clock input. This input is not 5V tolerant.
XTAL2
10
O
Crystal or buffered clock output. This output may be use to drive a clock buffer which can
drive other device(s).
ACP
12
I
Autosleep for Charge Pump (active HIGH). When this pin is HIGH, the charge pump is shut
off if the L200 is already in partial sleep mode, i.e. the crystal oscillator is stopped.
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XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
Pin Descriptions
NAME
32-QFN
PIN#
TYPE
I/M#
2
I
Intel or Motorola Bus Select.
When I/M# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of
interface.
When I/M# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus
type of interface.
RESET
(RESET#)
23
I
When I/M# pin is HIGH for Intel bus interface, this input becomes RESET (active high).
When I/M# pin is LOW for Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of
the UART. The UART transmitter output will be held HIGH, the receiver input will be ignored
and outputs are reset during reset period (see Table 11).
C2+
C2-
15
16
-
Charge pump capacitors. As shown in Figure 1, a 0.1 uF capacitor should be placed
between these 2 pins.
C1+
C1-
24
25
-
Charge pump capacitors. As shown in Figure 1, a 0.1 uF capacitor should be placed
between these 2 pins.
VREF+
26
Pwr +5.0V generated by the charge pump.
VREF-
17
Pwr -5.0V generated by the charge pump.
VCC
27
Pwr 3.0V to 5.5V power supply. All CMOS/TTL input pins, except XTAL1, are 5V tolerant.
GND
13
Pwr Power supply common, ground.
GND
-
NC
-
DESCRIPTION
Pwr The center pad on the backside of the 32-QFN package is metallic and is not electrically
connected to anything inside the device. It must be soldered on to the PCB and may be
optionally connected to GND on the PCB. The thermal pad size on the PCB should be the
approximate size of this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
-
No Connect. Note that in Motorola mode, the IOR# pin also becomes an NC pin.
NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. For CMOS/TTL Voltage levels, ’LOW’
indicates a voltage in the range 0V to VIL and ’HIGH" indicates a voltage in the range VIH to VCC. For RS-232
input voltage levels, ’LOW’ is any voltage < -3V and ’HIGH’ is any voltage > 3V. For RS-232 output voltage levels,
’LOW’ is any voltage < -5V and ’HIGH’ is any voltage > 5V.
4
XR19L200
REV. 1.0.1
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
1.0 PRODUCT DESCRIPTION
The XR19L200 interface converter consists of a full-functional UART with 16 bytes of transmit and receive
FIFO, a charge pump, two RS-232 drivers, two RS-232 receivers, and a sleep mode circuitry. It operates from
a single +3V to 5.5V supply at 250Kbps data rate, while meeting all EIA RS-232F specifications. Its feature set
is fully compatible to the XR16L580 device. Unlike the XR16L580, the modem signals are not CMOS/TTL
level, but conform to EIA/TIA 232 or RS-232 voltage levels. The configuration registers set is 16550 UART
compatible for control, status and data transfer. Also, the L200 has 16-bytes of transmit and receive FIFOs,
automatic Xon/Xoff and special character software flow control, transmit and receive FIFO trigger levels, and a
programmable baud rate generator with a prescaler of divide by 1 or 4. Additionally, the L200 includes the ACP
pin which the user can shut down the charge pump for the RS-232 drivers when the L200 is already in sleep
mode. The L200 is fabricated using an advanced CMOS process.
Enhanced Features
The L200 UART provides a solution that supports 16 bytes of transmit and receive FIFO memory. The L200 is
designed to work with low supply voltage and high performance data communication systems that require fast
data processing time. Increased performance is realized in the L200 by the transmit and receive FIFOs, FIFO
trigger level controls and automatic flow control mechanism. This allows the external processor to handle more
networking tasks within a given time. This increases the service interval giving the external CPU additional time
for other applications and reducing the overall UART interrupt servicing time.
Intel or Motorola Data Bus Interface
The L200 provides a host interface that supports Intel or Motorola microprocessor (CPU) data bus interface.
The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#,
IOW# and CS# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#
and CS# signals for data bus transactions. See pin description section for details on all the control signals. The
Intel and Motorola bus interface selection is made through the pin, I/M#.
Data Rate
The L200 is capable of operation up to 250Kbps data rate using the 16X internal sampling clock rate. The
UART section can operate at much higher speeds, but the speed of the RS-232 transceiver is limited to
250Kbps beyond which the L200 cannot comply with the EIA/TIA-232 electrical characteristics. The device can
operate either with a crystal on pins XTAL1 and XTAL2, or external clock source on XTAL1 pin.
Internal Enhanced Register Sets
The L200 UART has a set of enhanced registers providing control and monitoring functions. Interrupt enable/
disable and status, FIFO enable/disable, selectable TX and RX FIFO trigger levels, automatic hardware/
software flow control enable/disable, programmable baud rates, modem interface controls and status, and
sleep mode are all standard features. Following a power on reset or an external reset (and operating in 16 or
Intel Mode), the registers defaults to the reset condition and is compatible with the XR16L580.
RS-232 Interface
The L200 includes RS-232 drivers/receivers for the TXD and RXD signals (If more modem input and output
signals are needed, see the XR19L220 and XR19L210). This feature eliminates the need for an external RS232 transceiver. The charge pump provides output voltages of +5V and -5V for its drivers over the 3.0V to 5.5V
VCC supply voltage. The serial output TX swings between -5V (inactive) and 5V (active) RS-232 voltage
levels. The serial input RX is an RS-232 receiver and can take any voltage swing from -15V to +15V. The
receiver is always active, even in Partial or Full Sleep modes. The RS-232 drivers guarantee a data rate of
250Kbps even when fully loaded with 3Kohm in parallel with 1000pF load. Also, the slew rate of the driver
output is internally limited to a maximum of 30V/us in order to meet the EIA-232F standard.
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XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L200 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus
interconnection for Intel and Motorola mode is shown in Figure 3.
FIGURE 3. XR19L200 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A0
A1
VCC
VCC
16/68#
TX
RX
RS-232
Interface
A2
IOR#
IOR#
IOW#
IOW#
UART_CS#
CS#
UART_INT
INT
UART_RESET
RESET
GND
ACP
ACP
Intel Data Bus Interconnections
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A0
A1
A2
VCC
VCC
TX
RX
VCC
4.7K
VCC
RS-232
Interface
IOR#
IOW#
R/W#
CS#
UART_CS#
UART_IRQ#
INT
UART_RESET#
RESET
ACP
ACP
Motorola Data Bus Interconnections
6
16/68#
GND
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
2.2
5-Volt Tolerant Inputs
The CMOS/TTL level inputs of the L200 can accept up to 5V inputs when operating at 3.3V. Note that the
XTAL1 pin is not 5V tolerant when an external clock supply is used.
2.3
Device Hardware Reset
The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to
their default state (see Table 11). An active pulse of longer than 40 ns duration will be required to activate the
reset function in the device.
2.4
Device Identification and Revision
The XR19L200 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x01 to
indicate functional compatibility with XR16L580 and reading the content of DLL will provide the revision of the
part; for example, a reading of 0x01 means revision A.
2.5
Internal Registers
The L200 has a set of enhanced registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to those already available in the standard 16C550. These registers
function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control
register (FCR), receive line status and control registers, (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and an user accessible Scratchpad
register (SPR).
Beyond the general 16C550 features and capabilities, the L200 offers enhanced feature registers just like the
XR16L580, namely, EFR, Xon1, Xoff 1, Xon1 and Xoff2 that provide automatic Xon/Xoff software flow control.
All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL REGISTERS” on
page 15.
2.6
DMA Mode
The DMA Mode (a legacy term) refers to data block transfer operation. The DMA mode affects the state of the
RXRDY# and TXRDY# output pins available in the original 16C550. These pins are not available in the
XR19L200. The DMA Enable bit (FCR bit-3) does not have any function in this device and can be a ’0’ or a ’1’.
2.7
INT (IRQ#) Output
The interrupt output changes according to the operating mode and enhanced features setup. Table 1 and
Table 2 below summarize the operating behavior for the transmitter and receiver in the Intel and Motorola
modes. Also see Figures 16 through 19.
TABLE 1: INT (IRQ#) PIN OPERATION FOR TRANSMITTER
FCR BIT-0 = 0 (FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin
(I/M# = 1)
0 = one byte in THR
1 = THR empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO empty
IRQ# Pin
(I/M# = 0)
1 = one byte in THR
0 = THR empty
1 = FIFO above trigger level
0 = FIFO below trigger level or FIFO empty
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XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
TABLE 2: INT (IRQ#) PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
2.8
FCR BIT-0 = 1
(FIFO ENABLED)
INT Pin
(I/M# = 1)
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
IRQ# Pin
(I/M# = 0)
1 = no data
0 = 1 byte
1 = FIFO below trigger level
0 = FIFO above trigger level
Crystal or External Clock Input
The L200 includes an on-chip oscillator (XTAL1 and XTAL2) to generate a clock when a crystal is connected
between the XTAL1 and XTAL2 pins of the device. Alternatively, an external clock can be supplied through the
XTAL1 pin. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock input and XTAL2 pin is the bufferred output which can be used as a clock signal for
other devices in the system. Please note that the input XTAL1 is not 5V tolerant and therefore, the maximum
voltage at the pin should be VCC when an external clock is supplied. For programming details, see
“Programmable Baud Rate Generator.”
FIGURE 4. TYPICAL CRYSTAL CONNECTIONS
XTAL1
XTAL2
R2
500K - 1M
Y1
C1
22-47pF
R1
0-120
(Optional)
1.8432 MHz
to
24 MHz
C2
22-47pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. When VCC = 5V, the on-chip oscillator
can operate with a crystal whose frequency is not greater than 24 MHz. On the other hand, the L200 can
accept an external clock of up to 50MHz at XTAL1 pin also. Although the L200 can accept an exteran clock of
up to 50MHz, the maximum data rate supported by the RS-232 drivers is 250Kbps. For further reading on the
oscillator circuit please see the Application Note DAN108 on the EXAR web site at http://www.exar.com.
2.9
Programmable Baud Rate Generator
The L200 UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit (bit-7) in the MCR register. This bit selects the prescaler to divide the input crystal or external clock
by a factor of 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by
a programmable divisor (via DLL and DLM registers) between 1 and (216 -1) to obtain a 16X sampling rate
clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver
for data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon
power up.
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XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
FIGURE 5. BAUD RATE GENERATOR AND PRESCALER
DLL and DLM
Registers
Prescaler
Divide by 1
MCR Bit-7=0
(default)
Crystal
Osc/
Buffer
XTAL1
XTAL2
16X
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
Prescaler
Divide by 4
MCR Bit-7=1
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate. Table 3 shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X sampling rate clock rate. When using a non-standard data rate crystal or external clock, the
divisor value can be calculated for DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate OUTPUT Data Rate
DIVISOR FOR 16x DIVISOR FOR 16x
MCR Bit-7=1
MCR Bit-7=0
Clock (Decimal) Clock (HEX)
(DEFAULT)
DLM
PROGRAM
VALUE (HEX)
DLL
PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
2.10
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
2.10.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
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XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
2.10.2
REV. 1.0.1
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE
Transmit
Holding
Register
(THR)
Data
Byte
16X Clock
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
S
B
Transmit Shift Register (TSR)
L
S
B
TXNOFIFO1
2.10.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The Transmitter Empty Flag (LSR bit-6) is set when both the TSR and the FIFO become empty.
FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Data Byte
Transmit
FIFO
THR Interrupt (ISR bit-1):
- When the TX FIFO falls below the
programmed Trigger Level, and
- When the TX FIFO becomes empty.
FIFO is Enabled by FCR bit-0=1
Flow Control Characters
(Xoff1,2 and Xon1,2 Reg.)
Auto Software Flow Control
16X Clock
2.11
Transmit Data Shift Register
(TSR)
RECEIVER
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. On the rising edge of RXD
(or falling edge of RX) of a start or a false start bit, an internal receiver counter starts counting at the 16X clock
rate. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled
and if it is still LOW it is validated as a start bit. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Each of the data, parity and stop bits is sampled at the middle of the bit to
prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading
the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately
updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt
10
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the
host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as
defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is
enabled by IER bit-0.
2.11.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
Data Bit
Validation
Receive Data Characters
RHR Interrupt (ISR bit-2)
RXFIFO1
2.12
Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 10), the L200 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the L200 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the L200 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the L200 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 10) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters
are selected, the L200 compares two consecutive receive characters with two software flow control 8-bit
values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow
control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or
FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the L200 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The L200 sends the
Xoff character(s) two-character-times (= time taken to send two characters at the programmed baud rate) after
the receive FIFO crosses the programmed trigger level. To clear this condition, the L200 will transmit the
programmed Xon character(s) as soon as receive FIFO is less than one trigger level below the programmed
trigger level (see Table 8). The table below describes this.
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SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
TABLE 4: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
RX TRIGGER LEVEL
INT PIN ACTIVATION
XOFF CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
XON CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
1
1
1*
0
4
4
4*
1
8
8
8*
4
14
14
14*
8
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters);
for example, after 2.083ms has elapsed for 9600 baud and 8-bit word length, no parity and 1 stop bit setting.
2.13
Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The L200 compares each incoming receive character with the programmed Xoff-2 data. If a match exists, the
received data will be transferred to the RX FIFO and ISR bit-4 will be set to indicate detection of special
character. Although the Internal Register Table shows Xon, Xoff Registers with eight bits of character
information, the actual number of bits is dependent on the programmed word length. Line Control Register
(LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length
selected by LCR bits 0-1 also determines the number of bits that will be used for the special character
comparison. Bit-0 in the Xon, Xoff Registers corresponds with the LSB bit for the receive character.
2.14
Sleep Modes with Wake-Up Interrupt
There are two levels of power management integrated in the L200. The device is low power with low
operational and standby supply currents. In the Partial Sleep mode, the internal oscillator of the UART or
charge pump of the RS-232 transceiver is turned off to reduce the power consumption. In the Full Sleep mode,
both the oscillator and the charge pump are turned off.
2.14.1
Partial Sleep Mode
There are two different partial sleep modes. In the first mode, the UART is in sleep mode and the RS-232
transceiver is active. In the other mode, the UART is active but the charge pump of the RS-232 transceiver is
turned off.
2.14.1.1
UART in sleep mode, RS-232 transceiver active
If the ACP pin is LOW, then the charge pump for the RS-232 transceiver will always be active. But the UART
portion in the L200 can still enter sleep mode if all of these conditions are satisfied:
■
■
■
■
no interrupts pending (ISR bit-0 = 1)
the 16-bit divisor programmed in DLM and DLL registers is a non-zero value
sleep mode is enabled (IER bit-4 = 1)
RXD input pin is idling LOW
The L200 stops its crystal oscillator to conserve power in this mode. The user can check the XTAL2 pin for no
clock output as an indication that the device has entered the partial sleep mode.
The UART portion in the L200 resumes normal operation or active mode by any of the following:
■
■
a receive data start bit transition on the RXD input (LOW to HIGH)
a data byte is loaded to the transmitter, THR or FIFO
The UART portion in the L200 will return to the sleep mode automatically after all interrupting conditions have
been serviced and cleared. In any case, the sleep mode will not be entered while an interrupt is pending. The
UART portion of the L200 will stay in the sleep mode of operation until it is disabled by setting IER bit-4 to a
logic 0.
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SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
2.14.1.2
UART active, charge pump of RS-232 transceiver shut down
If the ACP pin is HIGH and the UART portion of the L200 is not in sleep mode, then the charge pump will
automatically shut down to conserve power if the following conditions are true:
■
■
no activity on the TXD output signals
RXD input signal has been idling LOW for approximately 30 seconds
When these conditions are satisfied, the L200 shuts down the charge pump and tri-states the RS-232 drivers
to conserve power. In this mode, the RS-232 receivers are fully active and the internal registers of the L200
can be accessed. The time for the charge pump to resume normal operation after exiting the sleep mode is
typically 45µs. It will wake up by any of the following:
■
■
a receive data start bit transition on the RXD input (LOW to HIGH)
a data byte is loaded to the transmitter, THR or FIFO
Because the receivers are fully active when the charge pump is turned off, any data received will be transferred
to/from the UART without any issues.
2.14.2
Full Sleep Mode
In full sleep mode, the L210 shuts down the charge pump and the internal oscillator. The L210 enters the full
sleep mode if the following conditions are satisfied:
■
■
the UART portion of the L210 is already in sleep mode (no output on XTAL2)
the ACP (Autosleep for Charge Pump) pin is HIGH
When these conditions are satisfied, both the UART and the charge pump will be in the sleep mode. In this
mode, the RS-232 receivers are fully active and the internal registers of the L200 can be accessed. The L200
exits the full sleep mode if either the ACP pin becomes LOW or the internal oscillator starts up. The time for the
charge pump to resume normal operation after exiting the full sleep mode is typically 45µs.
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XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
2.15
REV. 1.0.1
Internal Loopback
The L200 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally
including automatic hardware and software flow control. Figure 9 below shows how the internal UART signals
are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift
register input allowing the system to receive the same data that it was sending. The TX and RTS# pins are held
HIGH while RX and CTS# inputs are ignored. Caution: the RX input pin must be held at inactive during
loopback test else upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 9. INTERNAL LOOP BACK
VCC
TX
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
RX
RTS#
Modem / General Purpose Control Logic
Internal Data Bus Lines and Control Signals
MCR bit-4=1
CTS#
DTR#
DSR#
OP1#
RI#
OP2#
CD#
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SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
3.0 UART INTERNAL REGISTERS
The L200 has a set of configuration registers selected by address lines A0, A1 and A2 with CS# asserted. The
complete register set is shown on Table 5 and Table 6.
TABLE 5: UART INTERNAL REGISTERS
ADDRESSES
A2 A1 A0
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0
0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0
0 0
DLL - Divisor Latch Low Byte
Read/Write
LCR[7] = 1
0
0 1
DLM - Divisor Latch High Byte
Read/Write
0
0 0
DREV - Device Revision Code
Read-only
0
0 1
DVID - Device Identification Code
Read-only
0
0 1
IER - Interrupt Enable Register
Read/Write
LCR[7] = 0
0
1 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
LCR ≠ 0xBF
0
1 1
LCR - Line Control Register
Read/Write
1
0 0
MCR - Modem Control Register
Read/Write
1
0 1
LSR - Line Status Register
Read-only
1
1 0
MSR - Modem Status Register
Read-only
1
1 1
SPR - Scratchpad Register
Read/Write
LCR ≠ 0xBF
Read/Write
LCR = 0xBF
DLL = 0x00, DLM = 0x00
and LCR[7] = 1
LCR ≠ 0xBF
ENHANCED REGISTERS
0
1 0
EFR - Enhanced Function Register
1
0 0
Xon-1 - Xon Character 1
Write
1
0 1
Xon-2 - Xon Character 2
Write
1
1 0
Xoff-1 - Xoff Character 1
Write
1
1 1
Xoff-2 - Xoff Character 2
Write
15
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SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
.
TABLE 6: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
16C550 Compatible Registers
000
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
000
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
001
IER
RD/WR
0/
0/
0/
0/
Xoff Int.
Enable
Sleep
Mode
Enable
0/
0/
010
ISR
RD
FIFOs
FIFOs
Enabled Enabled
INT
Source
Bit-4
Modem RX Line
TX
RX
Stat. Int.
Stat.
Empty
Data
Enable
Int.
Int
Int.
Enable Enable Enable
INT
Source
Bit-3
LCR[7]=0
INT
INT
INT
Source Source Source
Bit-2
Bit-1
Bit-0
LCR ≠ 0xBF
010
FCR
WR
RX FIFO RX FIFO
Trigger Trigger
0/
0/
TX FIFO TX FIFO
Trigger Trigger
DMA
Mode
Enable
TX
FIFO
Reset
Parity
Enable
Stop
Bits
RX
FIFO
Reset
FIFOs
Enable
011
LCR
RD/WR
Divisor
Enable
Set TX
Break
Set Parity
Even
Parity
100
MCR
RD/WR
0/
0
0/
XonAny
Internal
Loopback
Enable
THR
Empty
RX
Break
RX Framing Error
RX
Parity
Error
RX
Overrun
Error
RX
LCR ≠ 0xBF
Data
Ready
DSR
Input
CTS
Input
Delta CD
Delta
RI
Delta
DSR
Delta
CTS
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR ≠ 0xBF
LCR[7]=1
BRG
Prescaler
101
LSR
RD
RX FIFO
Global
Error
110
MSR
RD
CD Input RI Input
111
SPR
RD/WR
Bit-7
THR &
TSR
Empty
Bit-6
Word
Word
Length Length
Bit-1
Bit-0
INT Out- (OP1#) RTS
DTR#
put
Output Output
Enable
Control Control
(OP2#)
Baud Rate Generator Divisor
000
DLL
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
001
DLM
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
000
DREV
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
001
DVID
RD
0
0
0
0
0
0
0
1
16
LCR[7]=1
DLL=0x00
DLM=0x00
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
TABLE 6: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
MCR[7:5],
MCR[2]
Software
Flow
Cntl
Bit-3
Software
Flow
Cntl
Bit-2
Software
Flow
Cntl
Bit-1
Software
Flow
Cntl
Bit-0
COMMENT
Enhanced Registers
010
EFR
RD/WR
0
0
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
100
XON1
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
101
XON2
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
110
XOFF1
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
111
XOFF2
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR=0XBF
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
Receive Holding Register (RHR) - Read- Only
SEE ”RECEIVER” ON PAGE 10.
4.2
Transmit Holding Register (THR) - Write-Only
SEE ”TRANSMITTER” ON PAGE 9.
4.3
Baud Rate Generator Divisors (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’. SEE
”PROGRAMMABLE BAUD RATE GENERATOR” ON PAGE 8. for more details.
4.4
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.4.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
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XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
4.4.2
REV. 1.0.1
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR bit-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR19L200 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the nonFIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of
the FIFO.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
• Logic 0 = Disable Sleep Mode (default).
• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[7:6]: Reserved
For proper functionality, these bits should remain at a ’0’.
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SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
4.5
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 7, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.5.1
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX trigger level or TX FIFO empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
• Receive Xoff/Special character is by detection of a Xoff or Special character.
• Wake-up Interrupt is when the device wakes up from sleep mode. See Sleep Mode section for more details.
4.5.2
Interrupt Clearing:
• LSR interrupt is cleared by reading the LSR register (but FIFO error bit does not clear until the character(s)
that generated the interrupt(s) is (are) read from the FIFO).
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading the RHR register.
• TXRDY interrupt is cleared by reading the ISR register or writing to the THR register.
• MSR interrupt is cleared by reading the MSR register.
• Xoff interrupt is cleared by reading the ISR or when Xon character(s) is received.
• Special character interrupt is cleared by reading the ISR or after the next character is received.
• Wake-up interrupt is cleared by reading the ISR register.
]
TABLE 7: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
0
0
1
1
0
LSR (Receiver Line Status Register)
2
0
0
1
1
0
0
RXRDY (Receive Data Time-out)
3
0
0
0
1
0
0
RXRDY (Received Data Ready)
4
0
0
0
0
1
0
TXRDY (Transmit Ready)
5
0
0
0
0
0
0
MSR (Modem Status Register)
6
0
1
0
0
0
0
RXRDY (Received Xoff or Special character)
-
0
0
0
0
0
1
None (default) or Wake-up Interrupt
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition) or wake-up interrupt. The wake-up interrupt is issued when
the L200 has been awakened from sleep mode.
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SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 7).
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. If it is a special
character interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is
received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has been deasserted.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.6
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO (default).
• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No receive FIFO reset (default)
• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select (Legacy)
This bit has no function and should be left at ’0’.
FCR[5:4]: Transmit FIFO Trigger Select
(’00’ = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 8 below shows the selections. EFR bit-4 must
be set to ‘1’ before these bits can be accessed.
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SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
FCR[7:6]: Receive FIFO Trigger Select
(’00’ = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 8 shows the selections.
TABLE 8: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
0
0
1
1
4.7
FCR
BIT-6
FCR
BIT-5
BIT-4
FCR
0
0
1
1
0
1
0
1
0
1
0
1
RECEIVE
TRANSMIT
TRIGGER LEVEL TRIGGER LEVEL
1 (default)
4
8
14
1 (default)
4
8
14
COMPATIBILITY
16L580 and 16C580 compatible.
16L580, 16C550, 16C580, 16C554,
16C2550 and 16C2552 compatible
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
BIT-2
WORD
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 9 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
21
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SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
• LCR BIT-5 = logic 0, parity is not forced (default).
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 9: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
X
0
No parity
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
Force parity to mark,
“1”
1
1
1
Forced parity to
space, “0”
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced LOW).
This condition remains, until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition (default).
• Logic 1 = Forces the transmitter output (TX) LOW for alerting the remote receiver of a line break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
• Logic 0 = Data registers are selected (default).
• Logic 1 = Divisor latch registers are selected.
4.8
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# output is not available as an output on this device. But for 16C550 compatibility, it can still be used
in internal loopback mode.
• Logic 0 = Force DTR output HIGH (default).
• Logic 1 = Force DTR output LOW.
22
XR19L200
REV. 1.0.1
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
MCR[1]: RTS# Output
The RTS# output is not available as an output on this device. But for 16C550 compatibility, it can still be used
in internal loopback mode.
• Logic 0 = Force RTS output HIGH (default).
• Logic 1 = Force RTS output LOW.
MCR[2]: OP1# (legacy term)
The OP1# output is not available on the XR19L200, however, it is available in internal loopback. In the Internal
Loopback Mode, this bit controls the state of the modem input RI bit in the MSR register as shown in Figure 9.
• Logic 0 = OP1# is HIGH (default).
• Logic 1 = OP1# is LOW.
In the Internal Loopback Mode, this bit controls the state of the modem input RI bit in the MSR register as
shown in Figure 9.
MCR[3]: INT Output Enable or OP2# (legacy term)
This bit enables and disables the operation of interrupt output, INT in the Intel mode. If INT output is not used,
OP2# can be used as a general purpose output in the Intel mode. In the Motorola mode, this bit must be set to
logic 0.
• Logic 0 = INT output disabled (three state mode) in Intel mode (default).
• Logic 1 = INT output enabled (active mode) in Intel mode.
In the Internal Loopback Mode, this bit functions like the OP2# in the 16C550 and is used to set the state of the
modem input CD bit in the MSR register.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 9.
MCR[5]: Xon-Any Enable
• Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the L200 is programmed to use the Xon/Xoff flow control.
MCR[6]: Reserved
For proper functionality, this bit should be set to a logic 0.
MCR[7]: BRG Clock Prescaler Select
• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates get reduced 4 times.
4.9
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
23
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
LSR[1]: Receiver Overrun Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Flag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Flag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Flag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
4.10
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. In the normal mode of operation,
none of the modem inputs (CTS, DSR, RI and CD) will change. However, all of the modem inputs can be
controlled in internal loopback mode. Lower four bits of this register are used to indicate the changed
information. These bits are set to a logic 1 whenever a signal from the modem changes state.
MSR[0]: Delta CTS Input Flag
• Logic 0 = No change on CTS input (default).
• Logic 1 = The CTS input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
24
XR19L200
REV. 1.0.1
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
MSR[1]: Delta DSR Input Flag
• Logic 0 = No change on DSR input (default).
• Logic 1 = The DSR input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI Input Flag
• Logic 0 = No change on RI input (default).
• Logic 1 = The RI input has changed from LOW to HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD Input Flag
• Logic 0 = No change on CD input (default).
• Logic 1 = Indicates that the CD input has changed state since the last time it was monitored. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS
(EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS signal. A HIGH on the CTS pin will stop UART transmitter as soon as the current character has
finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of
the CTS input. However in the loopback mode, this bit is equivalent to the RTS bit in the MCR register. The
CTS input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the complement of the DSR input. In the loopback mode, this bit is equivalent to the DTR bit
in the MCR register. The DSR input may be used as a general purpose input when the modem interface is not
used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD input may be used as a general purpose input when the modem interface is not used.
4.11
Scratchpad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.12
Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
• Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.13
Device Identification Register (DVID) - Read Only
This register contains the device ID (0x01 for XR19L200). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.14
Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
25
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
4.15
REV. 1.0.1
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 10). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
TABLE 10: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
0
0
0
0
No TX and RX flow control (default and reset)
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1, Xoff1
0
1
X
X
Transmit Xon2, Xoff2
1
1
X
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1, Xoff1
X
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 2, 5, 6 and 7
to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.
This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it
is recommended to leave it enabled, logic 1.
• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 2, 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 2, 5-7 are set to a logic 0 to be compatible with ST16C550 mode (default).
• Logic 1 = Enables the above-mentioned register bits to be modified by the user.
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REV. 1.0.1
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
EFR[5]: Special Character Detect Enable
• Logic 0 = Special Character Detect Disabled (default).
• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
EFR[7:6]: Reserved
For proper functionality, these bits should remain at a ’0’.
4.16
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Write Only
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, refer to “Section 2.12, Auto Xon/Xoff (Software) Flow Control” on page 11.
27
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B
REGISTERS
DLM and DLL
RESET STATE
Bits 15-0 = 0x0001. Resets upon power up only and not when only
the Reset Pin is asserted.
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 7-0 = 0x00
SPR
Bits 7-0 = 0xFF
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
I/O SIGNALS
RESET STATE
TX
RS-232 LOW or +5V
INT
Three-State Condition
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
7 Volts
Voltage at Any Pin
GND-0.3 V to 7 V
Operating Temperature
-40o to +85oC
Storage Temperature
-65o to +150oC
Package Dissipation
500 mW
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (32-QFN)
theta-ja = 33oC/W, theta-jc = 22oC/W
28
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA= - 40 TO + 85 (INDUSTRIAL GRADE), VCC= 3.0 - 5.5V
PARAMETER
SYMBOL
3.3V LIMITS
MIN MAX
5.0V LIMITS
MIN MAX
UNITS
CONDITIONS
DC CHARACTERISTICS
ICC
Supply Current, Normal Mode
30
35
mA
VCC=3.0V to 5.5V, TA=+25C, no load
ISLP
Supply Current, Partial Sleep Mode
(UART sleep, Transceiver active)
28
32
mA
VCC=3.0V to 5.5V, TA=+25C, no load
ISLP
Supply Current, Partial Sleep Mode
(UART active, Transceiver sleep)
2
3
mA
VCC=3.0V to 5.5V, TA=+25C, no load
ISLP
Supply Current, Full Sleep Mode
(UART sleep, Transceiver sleep)
20
40
uA
VCC=3.0V to 5.5V, TA=+25C, no load,
all inputs are idle
OSCILLATOR INPUT (X1)
VILCK
Clock Input Low Level
-0.3
0.6
-0.5
0.6
V
VIHCK
Clock Input High Level
2.4
VCC
3.0
VCC
V
LOGIC INPUTS/OUTPUTS (D[0:7], A[0:2], IOR#, IOW#/RW#, CS#, INT/IRQ#, RST#/RST, I/M#, ACP)
VIL
Input Low Voltage
-0.3
0.8
-0.5
0.8
V
VIH
Input High Voltage
2.0
5.5
2.2
5.5
V
VOL
Output Low Voltage
0.4
V
0.4
VOH
IOL = 6 mA
IOL = 4 mA
Output High Voltage
2.4
V
2.0
IOL = -6 mA
IOL = -1 mA
IIL
Input Low Leakage Current
±10
±10
uA
Inputs with no pull-up resistor
IHL
Input High Leakage Current
±10
±10
uA
Inputs with no pull-down resistor
±15
±15
V
RS-232 INPUT (RXD)
Input Voltage Range
VIHR
Input Threshold Low
0.6
0.8
VILR
Input Threshold High
2.0
VHYS
Input Hysteresis
0.5
RTR
Input Transmition Resistance
V
TA=+25C
2.4
V
TA=+25C
0.5
V
3
7
3
7
K ohm
Output Voltage Range
±5.0
±6.5
±5.0
±6.5
V
ROR
Output Resistance
300
IOS
Output Short-Circuit Current
TA=+25C
RS-232 OUTPUT (TXD)
300
ohm
3K ohm load on all transmitter outputs
Vcc=0V, transmitter output=+/-2V
±60
±60
mA
Maximum Data Rate
250
250
Kbps
RL=3Kohm, CL=1000pF
Transmitter Slew Rate
30
30
V/us
CL = 50pF to 2500pF, RL=3-7Kohm
RS-232 AC TIMING (TXD)
29
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
AC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc=3.0 - 5.5V, 50 pF
load where applicable
SYMBOL
LIMITS
3.3
PARAMETER
MIN
-
LIMITS
5.0
MAX
MIN
UNIT
MAX
Crystal Frequency
20
24
MHz
OSC
External Clock Frequency
33
50
MHz
CLK
External Clock Low/High Time
15
10
ns
TAS
Address Setup Time (16 Mode)
5
10
ns
TAH
Address Hold Time (16 Mode)
0
0
ns
TCS
Chip Select Width (16 Mode)
50
30
ns
TRD
IOR# Strobe Width (16 Mode)
50
30
ns
TDY
Read Cycle Delay (16 Mode)
50
30
ns
TRDV
Data Access Time (16 Mode)
TDD
Data Disable Time (16 Mode)
0
TWR
IOW# Strobe Width (16 Mode)
50
30
ns
TDY
Write Cycle Delay (16 Mode)
50
30
ns
TDS
Data Setup Time (16 Mode)
15
12
ns
TDH
Data Hold Time (16 Mode)
3
5
ns
TADS
Address Setup (68 Mode)
5
10
ns
TADH
Address Hold (68 Mode)
0
0
ns
TRWS
R/W# Setup to CS# (68 Mode)
10
10
ns
TRDA
Read Data Access (68 mode)
50
25
ns
TRDH
Read Data Disable Time (68 mode)
TWDS
Write Data Setup (68 mode)
15
12
ns
TWDH
Write Data Hold (68 Mode)
3
5
ns
TRWH
CS# De-asserted to R/W# De-asserted (68 Mode)
10
10
ns
TCSL
CS# Width (68 Mode)
50
30
ns
TCSD
CS# Cycle Delay (68 Mode)
50
30
ns
TWDO
Delay From IOW# To Output
75
50
ns
TMOD
Delay To Set Interrupt From MODEM Input
75
50
ns
TRSI
Delay To Reset Interrupt From IOR#
75
50
ns
TSSI
Delay From Stop To Set Interrupt
1
1
Bclk
50
20
0
20
30
25
ns
20
ns
20
ns
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
AC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc=3.0 - 5.5V, 50 pF
load where applicable
SYMBOL
LIMITS
3.3
PARAMETER
MIN
TRRI
LIMITS
5.0
MAX
MIN
UNIT
MAX
Delay From IOR# To Reset Interrupt
75
50
ns
TSI
Delay From Stop To Interrupt
75
50
ns
TINT
Delay From Initial INT Reset To Transmit Start
24
Bclk
TWRI
Delay From IOW# To Reset Interrupt
50
ns
TRST
Reset Pulse Width
40
N
Baud Rate Divisor
1
Bclk
8
24
8
75
Baud Clock
40
216-1
1
16X of data rate
FIGURE 10. CLOCK TIMING
CLK
CLK
EXTERNAL
CLOCK
OSC
31
ns
216-1
Hz
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
FIGURE 11. MODEM INPUT/OUTPUT TIMING
IOW#
T WDO
RTS#
DTR#
Change of state
Change of state
CD#
CTS#
DSR#
Change of state
Change of state
T MOD
T MOD
Activ
e
INT
Activ
e
Activ
e
T RSI
Activ
e
IOR#
Activ
e
Activ
e
T MOD
Change of state
RI#
32
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SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
FIGURE 12. 16 MODE (INTEL) DATA BUS READ TIMING
A0A2
Valid
Address
Valid
Address
TAS
TAS
TAH
TCS
TAH
TCS
CS#
TDY
TRD
TRD
IOR#
TDD
TRDV
TDD
TRDV
Valid
Data
D0-D7
Valid
Data
RDTm
FIGURE 13. 16 MODE (INTEL) DATA BUS WRITE TIMING
A0A2
Valid
Address
Valid
Address
TAS
TAS
TAH
TCS
TAH
TCS
CS#
TDY
TWR
TWR
IOW#
TDS
D0-D7
TDH
Valid
Data
TDS
TDH
Valid
Data
16Write
33
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
FIGURE 14. 68 MODE (MOTOROLA) DATA BUS READ TIMING
A0-A2
Valid Address
TADS
TCSL
Valid Address
TADH
CS#
TCSD
TRWS
TRWH
R/W#
TRDH
TRDA
D0-D7
Valid Data
Valid Data
68Read
FIGURE 15. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING
A0-A2
Valid Address
TADS
TCSL
Valid Address
TADH
CS#
TCSD
TRWS
TRWH
R/W#
TWDS
D0-D7
T WDH
Valid Data
Valid Data
68Write
34
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
FIGURE 16. RECEIVE READY INTERRUPT TIMING [NON-FIFO MODE]
RX
Start
Bit
Stop
Bit
D0:D7
INT
D0:D7
D0:D7
TSSR
TSSR
TSSR
1 Byte
in RHR
1 Byte
in RHR
1 Byte
in RHR
TRR
TRR
TRR
IOR#
(Reading data
out of RHR)
RXNFM
FIGURE 17. TRANSMIT READY INTERRUPT TIMING [NON-FIFO MODE]
TX
(Unloading)
IER[1]
enabled
Start
Bit
Stop
Bit
D0:D7
ISR is read
D0:D7
D0:D7
ISR is read
ISR is read
INT*
TWRI
TWRI
TSRT
TWRI
TSRT
TSRT
IOW#
(Loading data
into THR)
TXNonFIFO
*INT is cleared when the ISR is read or when data is loaded into the THR.
35
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
FIGURE 18. RECEIVE READY INTERRUPT TIMING [FIFO MODE]
Start
Bit
RX
S D0:D7
S D0:D7 T
D0:D7
Stop
Bit
S D0:D7 T
S D0:D7 T S D0:D7 T
S D0:D7 T
RX FIFO drops
below RX
Trigger Level
TSSI
INT
TSSR
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
TRRI
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
FIGURE 19. TRANSMIT READY INTERRUPT TIMING [FIFO MODE]
TX FIFO
Empty
TX
Start
Bit
Stop
Bit
S D0:D7 T
IER[1]
enabled
Last Data Byte
Transmitted
T S D0:D7 T S D0:D7 T
S D0:D7 T S D0:D7 T
TSI
ISR is read
S D0:D7 T
ISR is read
INT*
TX FIFO fills up
to trigger level
TWRI
TX FIFO drops
below trigger level
IOW#
(Loading data
into FIFO)
TX INT
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
36
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)
N o te: th e actu al cen ter p ad
is m etallic an d th e size (D 2)
is d evice-d ep en d en t w ith a
typ ical to leran ce o f 0.3m m
Note: The control dimension is in millimeter.
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.031
0.039
0.80
1.00
A1
0.000
0.002
0.00
0.05
A3
0.006
0.010
0.15
0.25
D
0.193
0.201
4.90
5.10
D2
0.138
0.150
3.50
3.80
b
0.007
0.012
0.18
0.30
e
0.0197 BSC
0.50 BSC
L
0.012
0.020
0.35
0.45
k
0.008
-
0.20
-
37
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
REVISION HISTORY
DATE
REVISION
DESCRIPTION
January 2006
P1.0.0
Preliminary Datasheet
March 2006
P1.0.1
Clarified Partial Sleep Mode and Full Sleep Mode descriptions. Ordering part
number changed to XR19L200IL32
April 2006
P1.0.2
Removed "Wireless Portable Devices" from list of applications since the
XR19L200 does not have infrared mode.
October 2006
1.0.0
Final Datasheet. Updated DC Electrical Characteristics.
May 2007
1.0.1
Modified "GND Center Pad" to pin description. Updated 32-pin QFN package
dimensions drawing to show minimum "k" parameter.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2007 EXAR Corporation
Datasheet May 2007.
Send your UART technical inquiry with technical details to hotline: [email protected].
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
38
XR19L200
REV. 1.0.1
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................ 1
APPLICATIONS .............................................................................................................................................. 1
FEATURES .................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1
FIGURE 2. PIN OUT OF THE DEVICE.................................................................................................................................................. 2
ORDERING INFORMATION ............................................................................................................................... 2
PIN DESCRIPTIONS ....................................................................................................... 3
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 5
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 6
2.1 CPU INTERFACE ................................................................................................................................................ 6
FIGURE 3. XR19L200 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS ............................................................................. 6
2.2 5-VOLT TOLERANT INPUTS ..............................................................................................................................
2.3 DEVICE HARDWARE RESET.............................................................................................................................
2.4 DEVICE IDENTIFICATION AND REVISION .......................................................................................................
2.5 INTERNAL REGISTERS......................................................................................................................................
2.6 DMA MODE .........................................................................................................................................................
2.7 INT (IRQ#) OUTPUT ............................................................................................................................................
7
7
7
7
7
7
TABLE 1: INT (IRQ#) PIN OPERATION FOR TRANSMITTER ................................................................................................................. 7
TABLE 2: INT (IRQ#) PIN OPERATION FOR RECEIVER ...................................................................................................................... 8
2.8 CRYSTAL OR EXTERNAL CLOCK INPUT ........................................................................................................ 8
FIGURE 4. TYPICAL CRYSTAL CONNECTIONS ..................................................................................................................................... 8
2.9 PROGRAMMABLE BAUD RATE GENERATOR............................................................................................... 8
FIGURE 5. BAUD RATE GENERATOR AND PRESCALER ....................................................................................................................... 9
TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ........................................................................ 9
2.10 TRANSMITTER.................................................................................................................................................. 9
2.10.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 9
2.10.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 10
FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 10
2.10.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 10
FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 10
2.11 RECEIVER ....................................................................................................................................................... 10
2.11.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 11
FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................... 11
2.12 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL..................................................................................... 11
TABLE 4: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 12
2.13 SPECIAL CHARACTER DETECT.................................................................................................................. 12
2.14 SLEEP MODES WITH WAKE-UP INTERRUPT............................................................................................. 12
2.14.1 PARTIAL SLEEP MODE.............................................................................................................................................
2.14.1.1 UART IN SLEEP MODE, RS-232 TRANSCEIVER ACTIVE.........................................................................................
2.14.1.2 UART ACTIVE, CHARGE PUMP OF RS-232 TRANSCEIVER SHUT DOWN ..................................................................
2.14.2 FULL SLEEP MODE ...................................................................................................................................................
12
12
13
13
2.15 INTERNAL LOOPBACK................................................................................................................................. 14
FIGURE 9. INTERNAL LOOP BACK ................................................................................................................................................... 14
3.0 UART INTERNAL REGISTERS............................................................................................................. 15
TABLE 5: UART INTERNAL REGISTERS .................................................................................................................................... 15
TABLE 6: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 .......................................... 16
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 17
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ..................................................................................
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ...............................................................................
4.3 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE ......................................................
4.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................
17
17
17
17
4.4.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 17
4.4.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 18
4.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 19
4.5.1 INTERRUPT GENERATION: ........................................................................................................................................ 19
4.5.2 INTERRUPT CLEARING: ............................................................................................................................................. 19
TABLE 7: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 19
4.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 20
TABLE 8: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION .............................................................................................. 21
I
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
4.7 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 21
TABLE 9: PARITY SELECTION .......................................................................................................................................................... 22
4.8 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE..
4.9 LINE STATUS REGISTER (LSR) - READ ONLY..............................................................................................
4.10 MODEM STATUS REGISTER (MSR) - READ ONLY .....................................................................................
4.11 SCRATCHPAD REGISTER (SPR) - READ/WRITE ........................................................................................
4.12 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE.................................................
4.13 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY.......................................................................
4.14 DEVICE REVISION REGISTER (DREV) - READ ONLY .................................................................................
4.15 ENHANCED FEATURE REGISTER (EFR) ....................................................................................................
22
23
24
25
25
25
25
26
TABLE 10: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 26
4.16 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - WRITE ONLY ................... 27
TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 28
ABSOLUTE MAXIMUM RATINGS.................................................................................. 28
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 28
ELECTRICAL CHARACTERISTICS ................................................................................................................... 29
AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 30
FIGURE 10. CLOCK TIMING .............................................................................................................................................................
FIGURE 11. MODEM INPUT/OUTPUT TIMING ....................................................................................................................................
FIGURE 12. 16 MODE (INTEL) DATA BUS READ TIMING ...................................................................................................................
FIGURE 13. 16 MODE (INTEL) DATA BUS WRITE TIMING..................................................................................................................
FIGURE 14. 68 MODE (MOTOROLA) DATA BUS READ TIMING ..........................................................................................................
FIGURE 15. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING .........................................................................................................
FIGURE 16. RECEIVE READY INTERRUPT TIMING [NON-FIFO MODE] ...............................................................................................
FIGURE 17. TRANSMIT READY INTERRUPT TIMING [NON-FIFO MODE] .............................................................................................
FIGURE 18. RECEIVE READY INTERRUPT TIMING [FIFO MODE] .......................................................................................................
FIGURE 19. TRANSMIT READY INTERRUPT TIMING [FIFO MODE] .....................................................................................................
31
32
33
33
34
34
35
35
36
36
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm) .............................................. 37
REVISION HISTORY...................................................................................................................................... 38
I
TABLE OF CONTENTS......................................................................................................
II