EXAR XRK32308CD-1

XRK32308
PRELIMINARY
3.3V ZERO DELAY BUFFER
FEBRUARY 2007
REV. P1.0.3
GENERAL DESCRIPTION
The XRK32308–1H is the high-drive version of the –
1. Rise and fall times on this device are faster.
FUNCTIONAL DESCRIPTION
The XRK32308–2 allows the user to obtain 1X, and
2X or X/2 depending on which Bank sources the FB
signal.
XRK32308 is a 3.3V Zero Delay Buffer designed to
distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance
applications.
The XRK32308–3 allows the user to obtain 4X and
2X frequencies or 1X and 2X.
The part has an on-chip PLL which locks to an input
clock presented on the REF pin. The PLL feedback is
required to be driven into the FB pin, and can be
obtained from one of the outputs. The input-to-output
skew is guaranteed to be less than 350 ps, and
output-to-output skew is guaranteed to be less than
200 ps.
The XRK32308–4 enables the user to obtain 2X
clocks on all outputs.
The XRK32308–5H is a high-drive version with REF/
2 on both banks.
FEATURES
• Zero input-output propagation delay, adjustable by
XRK32308 has two banks of four outputs each.
These can be controlled by the Select inputs as
shown in Table 2, “Select Input Decoding,” on page 2.
If all output clocks are not required, Bank B can be
three-stated. The select inputs also allow the input
clock to be directly applied to the output for chip and
system testing purposes.
capacitive load on FB input
• Multiple configurations, see “Available XRK32308
Configurations” table
• Multiple low-skew outputs
• Two banks of four outputs, three-stateable by two
select inputs
Multiple XRK32308 devices can accept the same
input clock and distribute it in a system. In this case,
the skew between the outputs of two devices is
guaranteed to be less than 700 ps.
• 10-MHz to 120-MHz operating range
• 75ps typical cycle-to-cycle jitter (15pF, 66MHz)
• Space-saving 16-pin 150-mil SOIC package, 16-pin
TSSOP or 16-pin QFN
XRK32308 devices are available in five different
configurations, as shown in Table 3, “Available
XRK32308 Configurations,” on page 3.
• 3.3V operation
• Industrial and commercial temperature available
The XRK32308–1 is the base part, where the output
frequencies equal the reference if there is no counter
in the feedback path.
FIGURE 1. BLOCK DIAGRAM AND PIN CONFIGURATION OF THE XRK32308
/2
PLL
REF
MUX
/2
Extra Divider (-3, -4)
Extra Divider (-5H)
S2
S1
QA0 REF
FB
REF
1
16
FB
QA0
QA0
2
15
QA3
14
13
1
12
QA2
VDD
VDD
2
11
VDD
12
GND
GND
3
10
GND
QB0
4
9
QB3
QA1
3
14
QA2
QA2
VDD
4
13
QA3
GND
5
QB0
6
11
QB3
QB0
QB1
7
10
QB2
QB1
S2
8
9
/2
Extra Divider (-2, -3)
15
QA3
QA1
QA1
Select Input
Decoding
16
FB
S1
5
6
7
8
QB1
S2
S1
QB2
QB2
QB3
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
TABLE 1: PIN D ESCRIPTION
PIN
SIGNAL
DESCRIPTION
SOIC/TSSOP
QFN
1
15
REF[1]
Input reference frequency
2
16
QA0[2]
Clock output, Bank A
3
1
QA1[2]
Clock output, Bank A
4
2
VDD
3.3V supply
5
3
GND
Ground
6
4
QB0[2]
Clock output, Bank B
7
5
QB1[2]
Clock output, Bank B
8
6
S2[3]
Select input, bit 2
9
7
S1[3]
Select input, bit 1
10
8
QB2[2]
Clock output, Bank B
11
9
QB3[2]
Clock output, Bank B
12
10
GND
Ground
13
11
VDD
3.3V supply
14
12
QA2[2]
Clock output, Bank A
15
13
QA3[2]
Clock output, Bank A
16
14
FB
PLL feedback input
TABLE 2: SELECT INPUT D ECODING
S2
S1
QA0-QA3
QB0-QB3
OUTPUT SOURCE
0
0
Three-State
Three-State
PLL
0
1
Driven
Three-State
PLL
1
0
Driven[4]
Driven[4]
Reference
1
1
Driven
Driven
PLL
NOTES:
1.
Weak pull-down.
2.
Weak pull-down on all outputs.
3.
Weak pull-ups on these inputs.
4.
Outputs inverted on XRK32308–2 and XRK32308–3 in bypass mode, S2 = 1 and S1 = 0.
2
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
TABLE 3: AVAILABLE XRK32308 CONFIGURATIONS
DEVICE
FEEDBACK FROM
BANK A FREQUENCY
BANK B FREQUENCY
XRK32308-1
Bank A or Bank B
Reference
Reference
XRK32308-1H
Bank A or Bank B
Reference
Reference
XRK32308-2
Bank A
Reference
Reference/2
XRK32308-2
Bank B
2 X Reference
Reference
XRK32308-3
Bank A
2 X Reference
Reference or Reference[5]
XRK32308-3
Bank B
4 X Reference
2 X Reference
XRK32308-4
Bank A or Bank B
2 X Reference
2 X Reference
XRK32308-5H
Bank A or Bank B
Reference/2
Reference/2
NOTES:
5.
Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the XRK32308–2.
ZERO DELAY AND SKEW CONTROL
FIGURE 2. REF INPUT TO QAX/QB X DELAY VS DIFFERENCE IN LOADING BETWEEN FB AND QAX/QBX PINS
1500
REF Input to QAx/QBx Delay (ps)
1000
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
Output Load Difference: FB Load - QAx/QBx Load (pF)
Note: Target only, actual characterization curve may be slightly different.
To close the feedback loop of the XRK32308, the FB pin can be driven from any of the eight available output
pins. The output driving the FB pin will be driving a total load of 7 pF plus any additional load that it drives. The
relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is
shown in the graph above.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be
equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading
differences between the feedback output and remaining outputs.
For zero output-output skew, be sure to load outputs equally.
3
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
TABLE 4: ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground Potential
-0.5V to +7.0V
DC Input Voltage (Except Ref)
-0.5V to V DD +0.5V
DC Input Voltage REF
-0.5 to 7V
Storage Temperature
-65°C to +150°C
Junction Temperature
150°C
Static Discharge Voltage (per MIL-STD-883, Method 3015)
>2000V
TABLE 5: OPERATING CONDITIONS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES
PARAMETER
MIN
MAX
UNIT
3.0
3.6
V
Operating Temperature (Ambient Temperature)
0
70
°C
Load Capacitance, below 100MHz
-
30
pF
Load Capacitance, from 100MHz to 120MHz
-
15
pF
CIN
Input Capacitance[6]
-
7
pF
tPU
Power-up time for all VDDs to reach minimum
specified voltage (power ramps must be monotonic)
0.05
50
ms
VDD
TA
DESCRIPTION
Supply Voltage
CL
NOTES:
6.
Applies to both Ref Clock and FB.
TABLE 6: ELECTRICAL CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE D EVICES
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
M AX
UNIT
VIL
Input Low Voltage
-
0.8
V
VIH
Input High Voltage
2.0
-
V
IIL
Input Low Current
VIN=0V
-
50.0
µA
IIH
Input High Current
VIN=VDD
-
100.0
µA
VOL
Output Low Voltage[7]
IOL= 8mA (-1, -2, -3, -4)
-
0.4
V
2.4
-
V
IOL= 12mA (-1H, -5H)
VOH
Output High Voltage[7]
IOH= -8mA (-1, -2, -3, -4)
IOH= -12mA (-1H, -5H)
4
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
TABLE 6: ELECTRICAL CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES
PARAMETER
IDD
DESCRIPTION
Supply Current
TEST CONDITIONS
MIN
M AX
UNIT
Unloaded outputs, 100-MHz REF,
Select inputs at VDD or GND
-
45.0
mA
-
70
(-1H, -5H)
mA
Unloaded outputs, 66-MHz REF
(-1, -2, -3, -4)
-
32.0
mA
Unloaded outputs, 33-MHz REF
(-1, -2, -3, -4)
-
18.0
mA
NOTES:
7.
Parameter is guaranteed by design and characterization. Not 100% tested in production.
TABLE 7: SWITCHING CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES[8]
PARAMETER
t1
DC
NAME
Output Frequency
Cycle[7]
Duty
= t2 ÷ t1
(-1, -2, -3, -4, -1H, -5H)
Time[7]
Rise
(-1, -2, -3, -4)
t3
Rise Time[7]
(-1H, -5H)
Time[7]
Fall
(-1, -2, -3, -4)
t4
Fall Time[7]
(-1H, -5H)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
30-pF load, All devices
10
-
100
MHz
20-pF load, -1H, -5H devices[9]
10
-
120
MHz
15-pF load, -1, -2, -3, -4 devices
10
-
120
MHz
Measured at 1.4V, FOUT=66.66MHz
30-pF load
40.0
50.0
60.0
%
Measured at 1.4V, FOUT<50.0MHz
15-pF load
45.0
50.0
55.0
%
Measured between 0.8V and 2.0V,
30-pF load
-
-
2.20
ns
Measured between 0.8V and 2.0V,
15-pF load
-
-
1.50
ns
Measured between 0.8V and 2.0V,
30-pF load
-
-
1.50
ns
Measured between 0.8V and 2.0V,
30-pF load
-
-
2.20
ns
Measured between 0.8V and 2.0V,
15-pF load
-
-
1.50
ns
Measured between 0.8V and 2.0V,
30-pF load
-
-
1.25
ns
5
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
TABLE 7: SWITCHING CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES[8]
PARAMETER
t5
t6
NAME
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output to Output Skew on All outputs equally loaded
same Bank
(-1, -2, -3, -4)[7]
-
-
200
ps
Output to Output Skew
(-1H, -5H)[7]
All outputs equally loaded
-
-
200
ps
Output Bank A to Output
Bank B Skew
(-1, -4, -5H)
All outputs equally loaded
-
-
200
ps
Output Bank A to Output
Bank B Skew
(-2, -3)
All outputs equally loaded
-
-
400
ps
-
0
+250
ps
700
ps
Delay, REF Rising Edge to Measured at VDD/2
FB Rising Edge[7]
t7
Device to Device Skew[7]
Measured at VDD/2 on the FB pins of
devices
-
0
t8
Output Slew Rate[7]
Measured between 0.8V and 2.0V on
-1H, -5H device using Test Circuit #2
1
-
Measured at 66.67MHz, loaded outputs,
15-pF load
-
75
200
ps
Measured at 66.67MHz, loaded outputs,
30-pF load
-
-
200
ps
Measured at 120MHz, loaded outputs,
15-pF load
-
-
100
ps
Measured at 66.67MHz, loaded outputs,
30-pF load
-
-
400
ps
Measured at 66.67MHz, loaded outputs,
15-pF load
-
-
400
ps
Stable power suppy, valid clock
presented on REF and FB pins
-
-
1.0
ms
Cycle to Cycle Jitter[7]
(-1, -1H, -4, -5H)
tJ
Cycle to Cycle
(-2, -3)
tLOCK
Jitter[7]
PLL Lock Time[7]
NOTES:
8.
All parameters are specified with loaded outputs.
9.
XRK32308 has maximum input frequency of 120MHz and maximum output of 66.67MHz.
6
V/ns
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
TABLE 8: OPERATING C ONDITIONS FOR XRK32308 INDUSTRIAL TEMPERATURE DEVICES
PARAMETER
MIN
MAX
UNIT
Supply Voltage
3.0
3.6
V
Operating Temperature (Ambient Temperature)
-40
85
°C
Load Capacitance, below 100MHz
-
30
pF
Load Capacitance, from 100MHz to 120MHz
-
15
pF
CIN
Input Capacitance[6]
-
7
pF
tPU
Power-up time for all VDDs to reach minimum
specified voltage (power ramps must be monotonic)
0.05
50
ms
VDD
TA
DESCRIPTION
CL
TABLE 9: ELECTRICAL CHARACTERISTICS FOR XRK32308 INDUSTRIAL TEMPERATURE DEVICES
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
M AX
UNIT
VIL
Input Low Voltage
-
0.8
V
VIH
Input High Voltage
2.0
-
V
IIL
Input Low Current
VIN=0V
-
50.0
µA
IIH
Input High Current
VIN=VDD
-
100.0
µA
VOL
Output Low Voltage[7]
IOL= 8mA (-1, -2, -3, -4)
-
0.4
V
2.4
-
V
Unloaded outputs, 100 MHz REF,
Select inputs at VDD or GND
-
45.0
mA
-
70
(-1H, -5H)
mA
Unloaded outputs, 66-MHz REF
(-1, -2, -3, -4)
-
35.0
mA
Unloaded outputs, 33-MHz REF
(-1, -2, -3, -4)
-
20.0
mA
IOL= 12mA (-1H, -5H)
VOH
Output High Voltage[7]
IOH= -8mA (-1, -2, -3, -4)
IOH= -12mA (-1H, -5H)
IDD
Supply Current
7
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
TABLE 10: SWITCHING CHARACTERISTICS FOR XRK32308 INDUSTRIAL TEMPERATURE DEVICES[8]
PARAMETER
t1
NAME
MIN
TYP
MAX
UNIT
30-pF load, All devices
10
-
100
MHz
20-pF load, -1H, -5H devices[9]
10
-
120
MHz
15-pF load, 01, 02, 03, 04 devices
10
-
120
MHz
Measured at 1.4V, FOUT=66.66MHz
30-pF load
40.0
50.0
60.0
%
Measured at 1.4V, FOUT<50.0MHz
15-pF load
45.0
50.0
55.0
%
Measured between 0.8V and 2.0V,
30-pF load
-
-
2.5
ns
Measured between 0.8V and 2.0V,
15-pF load
-
-
1.50
ns
Measured between 0.8V and 2.0V,
30-pF load
-
-
1.50
ns
Measured between 0.8V and 2.0V,
30-pF load
-
-
2.50
ns
Measured between 0.8V and 2.0V,
15-pF load
-
-
1.50
ns
Measured between 0.8V and 2.0V,
30-pF load
-
-
1.25
ns
-
-
200
ps
All outputs equally loaded
-
-
200
ps
Output Bank A to Output
Bank B Skew
(-1, -4, -5H)
All outputs equally loaded
-
-
200
ps
Output Bank A to Output
Bank B Skew
(-2, -3)
All outputs equally loaded
-
-
400
ps
-
0
+250
ps
700
ps
Output Frequency
[7]
DC
Duty Cycle = t2 ÷ t1
(-1, -2, -3, -4, -1H, -5H)
Rise Time[7]
(-1, -2, -3, -4)
t3
Rise Time[7]
(-1H, -5H)
Fall Time[7]
(-1, -2, -3, -4)
t4
Fall Time[7]
(-1H, -5H)
TEST CONDITIONS
Output to Output Skew on All outputs equally loaded
same Bank
(-1, -2, -3, -4)[7]
Output to Output Skew
(-1H, -5H)
t5
t6
Delay, REF Rising Edge to Measured at VDD/2
FB Rising Edge[7]
t7
Device to Device Skew[7]
Measured at VDD/2 on the FB pins of
devices
-
0
t8
Output Slew Rate[7]
Measured between 0.8V and 2.0V on
-1H, -5H device using Test Circuit #2
1
-
8
V/ns
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
TABLE 10: SWITCHING CHARACTERISTICS FOR XRK32308 INDUSTRIAL TEMPERATURE DEVICES[8]
PARAMETER
NAME
TEST CONDITIONS
Cycle to Cycle Jitter[7]
(-1, -1H, -4, -5H)
tJ
[7]
Cycle to Cycle Jitter
(-2, -3)
tLOCK
PLL Lock Time[7]
MIN
TYP
MAX
UNIT
Measured at 66.67MHz, loaded outputs,
15-pF load
-
75
200
ps
Measured at 66.67MHz, loaded outputs,
30-pF load
-
-
200
ps
Measured at 120MHz, loaded outputs,
15-pF load
-
-
100
ps
Measured at 66.67MHz, loaded outputs,
30-pF load
-
-
400
ps
Measured at 66.67MHz, loaded outputs,
15 pF load
-
-
400
ps
Stable power suppy, valid clocks
presented on REF and FB pins
-
-
1.0
ms
FIGURE 3. SWITCHING WAVEFORMS
All Outputs Rise/Fall Time
Duty Cycle Timing
t1
t2
1.4V
OUTPUT
1.4V
1.4V
2.0V
0.8V
t3
Output-Output Skew
OUTPUT
Input-Output Skew
1.4V
INPUT
1.4V
OUTPUT
VDD/2
VDD/2
FB
t6
t5
Device-Device Skew
FB, Device 1
VDD/2
VDD/2
FB, Device 2
2.0V
0.8V
t4
t7
9
3.3V
0V
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
FIGURE 4. TEST CIRCUIT
Test Circuit #1
Test Circuit #2
VDD
0.1µF
VDD
Outputs
QAx/QBx
0.1µF
CLOAD
VDD
1KΩ
QAx/QBx
1KΩ
10pF
Outputs
VDD
0.1µF
0.1µF
GND
GND
Test Circuit for all parameters except t 8.
GND
GND
Test Circuit for t 8. Output slew rate on -1H, -5 device.
10
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
TABLE 11: ORDERING INFORMATION
PART O RDERING NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRK32308CD-1
16 Pin SOIC
0° to +70°
XRK32308CDTR-1
16 Pin SOIC
0° to +70°
XRK32308ID-1
16 Pin SOIC
-40° to +85°
XRK32308IDTR-1
16 Pin SOIC
-40° to +85°
XRK32308CL-1
16 Pin QFN
0° to +70°
XRK32398IL-1
16 Pin QFN
-40° to +85°
XRK32308CD-1H
16 Pin SOIC
0° to +70°
XRK32308CDTR-1H
16 Pin SOIC
0° to +70°
XRK32308ID-1H
16 Pin SOIC
-40° to +85°
XRK32308IDTR-1H
16 Pin SOIC
-40° to +85°
XRK32308CG-1H
16 Pin TSSOP
0° to +70°
XRK32308CGTR-1H
16 Pin TSSOP
0° to +70°
XRK32308IG-1H
16 Pin TSSOP
-40° to +85°
XRK32308IGTR-1H
16 Pin TSSOP
-40° to +85°
XRK32308CL-1H
16 Pin QFN
0° to +70°
XRK32308IL-1H
16 Pin QFN
-40° to +85°
XRK32308CD-2
16 Pin SOIC
0° to +70°
XRK32308CDTR-2
16 Pin SOIC
0° to +70°
XRK32308ID-2
16 Pin SOIC
-40° to +85°
XRK32308IDTR-2
16 Pin SOIC
-40° to +85°
XRK32308CL-2
16 Pin QFN
0° to +70°
XRK32308IL-2
16 Pin QFN
-40° to +85°
XRK32308CD-3
16 Pin SOIC
0° to +70°
XRK32308CDTR-3
16 Pin SOIC
0° to +70°
XRK32308ID-3
16 Pin SOIC
-40° to +85°
XRK32308IDTR-3
16 Pin SOIC
-40° to +85°
XRK32308CL-3
16 Pin QFN
0° to +70°
XRK32308IL-3
16 Pin QFN
-40° to +85°
XRK32308CD-4
16 Pin SOIC
0° to +70°
XRK32308CDTR-4
16 Pin SOIC
0° to +70°
XRK32308ID-4
16 Pin SOIC
-40° to +85°
XRK32308IDTR-4
16 Pin SOIC
-40° to +85°
11
XRK32308
PRELIMINARY
3.3V ZERO DELAY BUFFER
REV. P1.0.3
TABLE 11: ORDERING INFORMATION
PART O RDERING NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRK32308CL-4
16 Pin QFN
0° to +70°
XRK32308IL-4
16 Pin QFN
-40° to +85°
XRK32308CD-5H
16 Pin SOIC
0° to +70°
XRK32308CDTR-5H
16 Pin SOIC
0° to +70°
XRK32308CL-5H
16 Pin QFN
0° to +70°
XRK32308IL-5H
16 Pin QFN
-40° to +85°
12
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
PACKAGE DRAWINGS AND DIMENSIONS
16 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
rev. 1.00
D
16
9
E
1
H
8
C
A
Seating
Plane
α
e
B
A1
L
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.053
0.069
1.35
1.75
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.19
0.25
D
0.386
0.394
9.80
10.00
E
0.150
0.157
3.80
4.00
e
0.050 BSC
1.27 BSC
H
0.228
0.244
5.80
6.20
L
0.016
0.050
0.40
1.27
α
0°
8°
0°
8°
13
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
16 LEAD TSSOP THIN SHRINK SMALL OUTLINE
(4.4mm TSSOP)
Rev. 1.0
SYMBOL
A
A1
A2
B
C
D
E
E1
e
L
α
INCHES
MIN
MAX
0.031
0.043
0.002
0.006
0.031
0.037
0.007
0.012
0.004
0.008
0.193
0.201
0.248
0.260
0.169
0.177
0.0256 BSC
0.018
0.030
0°
8°
14
MILLIMETERS
MIN
MAX
0.80
1.10
0.05
0.15
0.80
0.95
0.19
0.30
0.09
0.20
4.90
5.10
6.30
6.60
4.30
4.50
0.65 BSC
0.45
0.75
0°
8°
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
16 LEAD QUAD FLAT NO LEAD
(4 mm x 4 mm x 0.9mm, 0.65 pitch QFN)
Rev. 1.02
Note: the actual center pad
is metallic and the size (D2)
is device-dependent w/ a
typical tolerance of 0.3mm
Note: The control dimension is in millimeter.
MIN
MAX
MILLIMETERS
MIN
MAX
A
0.031
0.039
0.80
1.00
A1
0.000
0.002
0.00
0.05
A3
0.000
0.008
0.00
0.20
D
0.154
0.161
3.90
4.10
D2
0.087
0.102
2.20
2.60
b
0.010
0.014
0.25
0.35
SYMBOL
e
L
INCHES
0.0256 BSC
0.018
0.65 BSC
0.026
15
0.45
0.65
PRELIMINARY
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
REVISIONS
REV. #
DATE
DESCRIPTION OF CHANGES
P1.0.0
04/05/06
Initial release.
P1.0.1
04/21/06
Ordering information edit: Added "H" to last two product numbers.
P1.0.2
05/12/06
Operating range changed to 10MHz to 120MHz - edit all references of this.
P1.0.3
02/01/07
Add QFN package.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2007 EXAR Corporation
Datasheet February 2007.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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