ZILOG Z8623012PSC

Z86230
ADVANCED VIOLENCE BLOCKING
AND NTSC LINE 21 XDS
PRELIMINARY PRODUCT SPECIFICATION
PS000400-TVC0499
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©1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC.
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2
Z86230—PRELIMINARY
PS000400-TVC0499
TABLE OF CONTENTS
1. ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1. BLOCK DIAGRAM AND OPERATIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . 9
2. PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3. Z86230 FEATURE SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1. VBI DATA PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2. SERIAL COMMUNICATIONS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3. SETUP AND OPERATIONAL CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. SERIAL COMMUNICATIONS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1. I2C BUS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5. COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1. SERIAL PORT COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2. READ AND WRITE COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3. WRITING TO THE Z86230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6. CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1. REGISTERS SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2. XDS DATA RECOVERY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3. Z86230 COMMANDS AND REGISTERS SUMMARY . . . . . . . . . . . . . . . . . . 38
6.4. PROGRAM BLOCKING MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7. DEMONSTRATION PROGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1. COMMUNICATING WITH THE Z86230 . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2. I2C OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.3. IICO PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.4. GENERAL COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.5. SCRIPTI PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.6. SCRIPT FILES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.1. ABSOLUTE MAXIMUM RATINGS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2. STANDARD TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.3. DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.4. AC AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.5. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9. APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1. REFERENCE DESIGNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10. PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1. PART NUMBER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12. PRECHARACTERIZATION PRODUCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CUSTOMER FEEDBACK FORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Z86230 PRODUCT SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
CUSTOMER INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PRODUCT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
RETURN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PROBLEM DESCRIPTION OR SUGGESTION . . . . . . . . . . . . . . . . . . . . . . . 56
PS000400-TVC0499
Z86230—PRELIMINARY
3
4
Z86230—PRELIMINARY
PS000400-TVC0499
LIST OF FIGURES
FIGURE 1.
VOLTAGE/CIRCUIT REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
FIGURE 2.
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FIGURE 3.
18-PIN DIP AND SOIC DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FIGURE 4.
I2C BUS WRITE (COMMAND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FIGURE 5.
I2C BUS READ (COMMAND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FIGURE 6.
I2C SERIAL TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
FIGURE 7.
STANDARD TEST LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
FIGURE 8.
Z86230 REFERENCE CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FIGURE 9.
PCB DESIGN OF Z86230 REFERENCE CIRCUIT . . . . . . . . . . . . . . . . . . 52
FIGURE 10. 18-LEAD DIP PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
FIGURE 11. 18-LEAD SOIC PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PS000400-TVC0499
Z86230—PRELIMINARY
5
6
Z86230—PRELIMINARY
PS000400-TVC0499
LIST OF TABLES
PS000400-TVC0499
TABLE 1.
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TABLE 2.
Z86230 SERIAL CONTROL SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TABLE 3.
USER PROGRAMMABLE FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TABLE 4.
Z86230 I2C SLAVE ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TABLE 5.
Z86230 I2C READ BANK SELECT (RBS) COMMAND . . . . . . . . . . . . 20
TABLE 6.
I2C SERIAL TIMING MIN/MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TABLE 7.
BASIC SERIAL COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TABLE 8.
RDS1–READ ONE BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TABLE 9.
RSD2–READ TWO BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TABLE 10.
WRXX–WRITE REGISTER XX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TABLE 11.
SERIAL STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TABLE 12.
CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TABLE 13.
XDS DATA ACTIVITY REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TABLE 14.
XDS FILTER REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TABLE 15.
XDS SECONDARY FILTER SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . 27
TABLE 16.
INTERRUPT REQUEST REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TABLE 17.
INTERRUPT MASK REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TABLE 18.
CONTENT ADVISORY RATINGS SELECT REGISTER 1 . . . . . . . . . . . . . . 28
TABLE 19.
CONTENT ADVISORY RATINGS SELECT REGISTER 2 . . . . . . . . . . . . . . 29
TABLE 20.
CONTENT ADVISORY RATINGS SELECT REGISTER 3 . . . . . . . . . . . . . . 30
TABLE 21.
CONTENT ADVISORY RATINGS SELECT REGISTER 4 . . . . . . . . . . . . . . 31
TABLE 22.
CONTENT ADVISORY REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TABLE 23.
CONTENT ADVISORY REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TABLE 24.
BLOCKING CONTROL REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TABLE 25.
CONTENT ADVISORY RATINGS SELECT REGISTER 5 . . . . . . . . . . . . . . 32
TABLE 26.
CONTENT ADVISORY RATINGS SELECT REGISTER 6 . . . . . . . . . . . . . . 34
TABLE 27.
BLOCKING CONTROL REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TABLE 28.
XDS DATA EXTRACTION EXAMPLE FILTER SETTINGS . . . . . . . . . . . . . 36
TABLE 29.
Z86230 SUMMARY OF CONTROL COMMANDS . . . . . . . . . . . . . . . . . . 38
TABLE 30.
SUMMARY OF Z86230 INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . 39
TABLE 31.
MPAA MATRIX (USE CONTENT ADVISORY RATING REGISTER . . . . . . 40
TABLE 32.
TV PARENTAL GUIDELINES MATRIX . . . . . . . . . . . . . . . . . . . . . . . . . 40
TABLE 33.
CANADIAN ENGLISH MATRIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TABLE 34.
CANADIAN FRENCH MATRIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TABLE 35.
CONFIGURATION REGISTER SCRIPT FILES . . . . . . . . . . . . . . . . . . . . . . 44
TABLE 36.
DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
TABLE 37.
COMPOSITE VIDEO INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
TABLE 38.
NON-STANDARD VIDEO SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Z86230—PRELIMINARY
7
8
TABLE 39.
HIN/XIN SIGNAL INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
TABLE 40.
LINE 21 INPUT PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TABLE 41.
RECOMMENDED COMPONENT VALUES—REFERENCE CIRCUIT . . . . . . . 51
Z86230—PRELIMINARY
PS000400-TVC0499
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
1.
ARCHITECTURAL OVERVIEW
ARCHITECTURAL OVERVIEW
The Z86230 is a stand-alone integrated circuit, capable of processing Extended
Data Services (XDS) in Field 2 of the Vertical Blanking Interval (VBI) of a video
frame. This device conforms to the transmission format defined in the Television
Decoder Circuits Act of 1990, in accordance with the Electronics Industry Association specification EIA-608A and EIA-744A.
The XDS data is processed to provide either a Program Blocking signal (PB) or a
recovered XDS data packet. The PB matches the contents of the recovered Content Advisory packet to the user selections input on the decoder. On-chip XDS filters in the Z86230 are fully-programmable, enabling recovery of only those XDS
data packets selected for use in TVs, VCRs, and Set-Top boxes.
In addition, the Z86230 is ideally suited to monitor Picture-In-Picture (PiP) window video for violence blocking and other XDS data services.
Highlights of the Z86230 include:
1. A stand-alone Line 21 Decoder for Extended Data Services (XDS).
2. Extractable XDS data from the input video.
3. Full output of a selectable V-Chip Program Blocking signal (PB).
4. Selectable XDS filter parameters from a list of preprogrammed values.
5. Minimal communications and control overhead that provides simple
implementation of Violence Blocking and Auto Clock Set Features.
6. Full output of the recovered XDS data through the I2C serial communication
port.
7. Two different slave addresses that are selectable in the I2C serial
communication port.
8. Selectable NTSC or PAL operation.
1.1 BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
The Z86230 is designed to process XDS data of the television VBI. The device
requires both a Composite Video and a horizontal timing signal ( HIN/XIN input).
Several passive components are required for proper operation. Commands are
input to enable the decoder to process and control the V-Chip response to the XDS
Content Advisory packet. The Z86230 can also be configured to operate with PAL
video signals. In PAL mode, the device decodes information encoded into VBI
Line 22. The encoded data must conform to the waveform and command structure
defined for NTSC Line 21 operation.
Figure 1 illustrates the Functional Block Diagram of the Z86230.
PS000400-TVC0499
Z86230—PRELIMINARY
9
ARCHITECTURAL OVERVIEW
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
Data Line
RREF
V/I Ref
Sliced
Data Slicer Data
Data CLK
Recovery
Lock
VIDEO
AW FEW
PG
H Lock
Buffer
POR Ckt
STG MSYNC
Dual Clamp
CSYNC
NC
NC
SYNC Slicer
Slice Level
Addr Bus
Command
Processor
SCLK
SDA
PB
INTRO
NRST
I2C SEL
Serial
Control Port
Test Reg
Address
Decoder
Data Bus
VW
RAM
Status Reg
MSYNC
CG Lines COMP SYNC
CG Logic
O/S
PH1
OSC
DCLK
PH2
HIN/XIN
H SEL
XOUT
FR & MUX
COMP
DCLK
DIV
Control
I Dr & MUX
V Lock
CCLK
CW
MSGR
FLD
LS
SLS
SFLD
C CIR
Line & Field
Control
Line & Fld Dec
CLK DIV
LPF
VDD
10
VSS
VSS(A)
Z86230—PRELIMINARY
PS000400-TVC0499
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
ARCHITECTURAL OVERVIEW
1.1.1 Input Signals
The Composite Video input should be a signal which is nominally 1.0 Volt p-p,
with sync tips negative and band limited to 600 kHz. The Z86230 operates with an
input level variation of ±3 dB.
The HIN/XIN input signal is required to bring the voltage-controlled oscillator
(VCO) close to the required operating frequency.
1.1.2 Video Input Signal Processing
The Composite Video input is AC-coupled to the device where the sync tip is
internally clamped to a fixed reference voltage.
The Data Slicer extracts a clean CMOS-level data signal by slicing the signal at its
midpoint. The slice level is established on an adaptive basis during Line 21.
The Sync Slicer processes the clamped Composite Video signal to extract Composite Sync. This signal is used to lock the internal logic to the incoming video.
The slice level is stored on the sync slice capacitor, CSYNC.
The Data Clock Recovery circuit operates in conjunction with the Horizontal (H)
Lock circuit. These circuits produce a data clock (DCLK) and, when Line 21 code
appears, DCLK phase lock is achieved during the clock run-in burst (used to
reclock the sliced data). When phase lock is established, DCLK is maintained until
a change in the video signal occurs.
1.1.3 Voltage-Controlled Oscillator (VCO) and One-Shot
All internal timing and synchronizing signals are derived from the on-board 12MHz VCO. Its output is the DCLK signal used to drive the Horizontal and Vertical
counter chains.
The One-Shot circuit produces a horizontal timing signal derived from the incoming video.
The VCO exhibits stable gain characteristics and good power supply rejection.
1.1.4 Timing and Counting Circuits
The DCLK is divided to generate the horizontal timing signals H and 2H.The H
signal is further divided in the line counter (LINE CNTR) and field counter (FLD
CNTR) to produce the various decodes used to establish vertical lock and to time
the control functions required for proper operation.
1.1.5 Command Processor
The Command Processor controls the manipulation of the data for storage. During
the recovery time, the command processor, in conjunction with the data recovery
circuits, recovers the XDS data.
PS000400-TVC0499
Z86230—PRELIMINARY
11
ARCHITECTURAL OVERVIEW
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
1.1.6 Decoder Control Circuit
The Decoder Control circuit block is the users communications port. This circuit
converts the information from the control port into the internal control signals
required to establish the operating mode of the decoder.
The Z86230 responds to its slave address for both the READ and WRITE conditions. If the READ bit is Low (indicating a WRITE sequence), then the Z86230
responds with an Acknowledge. The master should then send an address byte followed by a data byte. If the READ bit is High (indicating a READ sequence), then
the Z86230 responds with an Acknowledge followed sequentially by a status byte
and a data byte. READ data is only available through indirect addressing. WRITE
addressing exhibits both indirect and direct modes. The busy bit in the status byte
indicates if the WRITE operation is completed or if READ data is available.
1.1.7 Voltage/Current Reference
The Voltage/Current reference circuit uses an externally connected resistor to
establish the reference levels that are used throughout the Z86230. For a minimal
investment, the use of an external resistor can also provide improved internal precision.
FIGURE 2. VOLTAGE/CIRCUIT REFERENCE
Pin 10
RREF
10 kΩ ±2%
GND
12
Z86230—PRELIMINARY
PS000400-TVC0499
PIN DESCRIPTIONS
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
2.
PIN DESCRIPTIONS
There are 2 different packages, 18-pin DIP and 18-pin SOIC, available in the
Z86230.
FIGURE 3. 18-PIN DIP AND SOIC DEVICES
I2C SEL
H SEL
XOUT
NRST
HIN/XIN
VSS
VIDEO
CSYNC
LPF
1
2
3
4
5
6
7
8
9
Z86230
DIP/SOIC
18
17
16
15
14
13
12
11
10
NC
INTRO
NC
SCLK
SDA
PB
VDD
VSS(A)
RREF
TABLE 1. PIN DESCRIPTIONS
Symbol
Pin #
Function
Direction
Description
1
I2C
Input
H SEL
2
HIN/XIN Select
Input
XOUT
3
XTAL Output
Output
Selects I2C Address. Low(0) sets the slave
address to 28h for WRITE and 29h for
READ. HIGH(1) sets the slave address to 2Ah
for WRITE and 2Bh for READ.
Selects the source of the horizontal frequency
signal. Tying pin 2 HIGH(1) selects XIN mode.
Tying pin 2 Low(0) selects HIN mode.
When operating in XIN mode this pin is the
output pin for the XTAL circuit. In HIN mode,
the XOUT pin is a no connect (NC).
NRST
4
RESET
Input
I2C
SEL
PS000400-TVC0499
Address Select
Capable of being tied to an RESET signal if a
Power-On Reset action is required. RESET
must be held Low(0) for at least 100ns;
otherwise, the pin must be tied HIGH(1).
Z86230—PRELIMINARY
13
PIN DESCRIPTIONS
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
TABLE 1. PIN DESCRIPTIONS
Symbol
Pin #
HIN/XIN 5
Function
Direction
Horizontal In/XTAL In Input
Description
When XTAL mode is selected, the horizontal
frequency signal may be generated on the chip
using the external 32.768-kHz crystal circuit, as
shown below. This circuit must be connected
between pin 5 and 3.
Z86230
Pin 5
C1
10pF
Y1
32.768KHz
Pin 3
R2
470K
R1
22M
C2
20pF
Crystal Type: 32.768 kHz, CL=12.5pF
Series Resistance < 35 kOhms
(18 kOhms typ)
Epson, C-001R 32.768 kHz or
Fox, NC26, NC28 or equivalent
VSS
6
Power Supply
(digital) GND
N/A
VIDEO
7
Composite Video
Input
CSYNC
8
Composite Sync
Output
14
When HIN mode is selected, a horizontal
frequency signal must be supplied to the pin.
This signal must be within +3% Fh; however,
the frequency signal can exhibit any polarity
and duty cycle. Alternatively, an external
horizontal frequency signal may be used in
XIN mode operation. In this case, the signal
must exhibit a frequency of 32.768 KHz.
This pin is the lowest potential power pin for
the digital circuit that is typically tied to
system ground.
Composite NTSC video input, 1.0V p-p (nom),
band limited to 600 kHz. The circuit operates
with signal variation between 0.7–1.4V p-p.
The polarity is sync tips negative. This signal
pin should be AC-coupled through a 0.1 µF
capacitor and driven by a source impedance
of 470 ohms or less.
Sync slice level. A 0.1 µmF capacitor must be
tied between this pin and analog ground
VSS(A). This capacitor stores the sync slice
level voltage.
Z86230—PRELIMINARY
PS000400-TVC0499
PIN DESCRIPTIONS
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
TABLE 1. PIN DESCRIPTIONS
Symbol
Pin #
Function
Direction
Description
LPF
9
Loop Filter
Output
Loop Filter. A series RC low-pass filter must be
tied between this pin and analog ground
VSS(A). There must also be second capacitor
from the pin to VSS(A).
C6
C7
R5
9
C5 8
RREF
10
Resistor Reference
Input
VSS(A)
11
Power Supply
(Anlalog) GND
N/A
VDD
12
Power Supply +5V
N/A
PB
13
Program Blocking
Output
SDA
14
Serial Data
SCLK
15
Serial Clock
NC
INTRO
16
17
No Connect
Interrupt Output
NC
18
No Connect
PS000400-TVC0499
LPF
CSYNC
Reference setting resistor. This resistor must
be 10 kOhms, ±2%.
This pin is the lowest potential power pin for
the analog circuit that is typically tied to
system ground.
The voltage on this pin is nominally 5.0 Volts,
and may range between 4.75 to 5.25 Volts with
respect to the VSS pins.
This pin is HIGH(1) when the received Content
Advisory packet matches the viewers
selection as entered into the Content Advisory
Rating Select registers.
In/Output This pin is the bidirectional data line for
sending and receiving serial data.
Input
This pin acts as an input pin for the serial clock
signal from the I2C master. The clock rate is
expected to be within I2C limits.
N/A
No Connect
Output
This pin provides an interrupt signal to the
master control device in accordance with the
settings in the Interrupt Mask Register.
N/A
No Connect
Z86230—PRELIMINARY
15
Z86230 FEATURE SET
3.
VBI DATA PROCESSING
Z86230 FEATURE SET
The primary features of the Z86230 are briefly described below. More complete
descriptions can be found in later sections of this document.
3.1 VBI DATA PROCESSING
The Z86230 extracts the XDS data in Line 21 of the incoming video. Processing
includes:
1. Extracting XDS data from the input video.
2. Outputting the V-Chip Program Blocking signal (PB).
3. Outputting the XDS data through the serial port (raw or filtered).
4. Selecting the XDS filter parameters from a list of preprogrammed values.
5. Selecting either NTSC or PAL operation.
3.2 SERIAL COMMUNICATIONS INTERFACE
Communications and control of the Z86230 is possible through the I 2C serial control interface, composed of:
1. A 2-wire I2C interface.
2. Two available slave addresses.
TABLE 2. Z86230 SERIAL CONTROL SIGNALS
I2C SEL
SCLK
SDA
1st I2C Address (28h(W)/29h(R))
1
I
0
15
I
CLK
14
I/O
Data
2nd I2C Address(2Ah(W)/2Bh(R))
1
CLK
Data
Signal
Pin #
I/O
16
Z86230—PRELIMINARY
PS000400-TVC0499
SETUP AND OPERATIONAL CONTROL
Z86230 FEATURE SET
3.3 SETUP AND OPERATIONAL CONTROL
The Z86230 is fully programmable through its flexible I2C serial communication
port. The following tables provide a partial list of User-Programmable Features
and Default Conditions upon RESET.
TABLE 3. USER PROGRAMMABLE FEATURES
PS000400-TVC0499
Feature
Parameters
RESET Condition
Video Standard
VCO Lock
H Lock
XDS Data Output
Contents Advisory Rating
Select
Program Blocking
Blocking No Rating
Programs
Program Unblock Hold Off
NTSC/PAL
Video/External HIN
Video/External HIN
Raw/Filtered
ON/OFF
NTSC
Video
Video
OFF
OFF
ON/OFF
ON/OFF
ON
OFF
Up to 254 Vertical Frames
0
Z86230—PRELIMINARY
17
I2C BUS OPERATION
SERIAL COMMUNICATIONS INTERFACE
4.
SERIAL COMMUNICATIONS INTERFACE
Commands and data are sent to and from the Z86230 through its I 2C serial communications interface. This port is the path for setting the configuration and operational modes of the device. The interface is also used as the port for outputting
the recovered XDS data.
4.1 I2C BUS OPERATION
The Z86230 supports a bidirectional 2-wire bus and data transmission protocol.
The bus is controlled by the master device, which generates the serial clock
(SCLK), controls the bus access, and generates the START and STOP conditions.
The serial data (SDA) pin is the bidirectional data line. The Z86230 is a slave
device with two possible slave addresses. When the I2C SEL pin is Low, the slave
address is 28h for WRITE and 29h for READ. When the I2C SEL pin is High,
the slave address is 2Ah for WRITE and 2Bh for READ.
The Z86230 can receive or transmit data under control of the master device. Communication is initiated when the master device sends the START condition followed by the Z86230 Slave Address READ byte or Slave Address WRITE byte.
The Z86230 responds with an Acknowledge.
The I2C RD/WR bit is the Least Significant Bit (LSB) of the I2C addresses listed
below in Table 4.
TABLE 4. Z86230 I2C SLAVE ADDRESSES
READ
WRITE
1st I2C Address
29h
28h
2nd I2C Address
2Bh
2Ah
NOTE: Low(0) on pin 1 selects the 1st I2C Address; HIGH(1) on pin 1 selects the
2nd I2C Address.
4.1.1 The I2C Bus Protocol
The Bus Protocol requires that:
1. Data transfer can only be started when the bus is not busy.
2. During data transfer, data transitions must not occur while the clock is High.
4.1.2 Bus Conditions
Bus Conditions are defined as:
Not Busy. Data and Clock lines are both High.
START. A High-to-Low transition of the SDA line while the SCLK line is High.
STOP. A Low-to-High transition of the SDA line while the SCLK line is High.
18
Z86230—PRELIMINARY
PS000400-TVC0499
I2C BUS OPERATION
SERIAL COMMUNICATIONS INTERFACE
Acknowledge. When addressed, the receiving device must output an Acknowl-
edge after the reception of each byte. The master device must generate the clock
for the Acknowledge bit. Acknowledge is SDA = Low. Not Acknowledge (NACK)
is SDA = High.
Data. The data (SDA) is output by the transmitting device on the falling edge of
SCLK, MSB first. The receiving device interprets the data, MSB first, on the rising
edge of SCLK.
Communication with the Z86230 is initiated when the master device sends the
Z86230 slave address following a START condition. The Z86230 has a preset,
single, seven-bit slave address. The Z86230 responds with an Acknowledge. The
eighth bit of the slave address is driven High for READ operations and Low for
WRITE operations.
4.1.3 Writing to the I2C Bus
Commands and data are written to the Z86230 using the I2C bus interface. The
device is enabled when an I2C START condition, followed by its Slave Address
WRITE byte, is received. A WRITE operation is ended and the bus is disabled upon
the receipt of an I2C STOP condition. Any number of command bytes, up to 32,
may be sent after the device is WRITE-enabled. Each of these commands is either
1 or 2 bytes in length. The device executes the commands in order of receipt.
Overflowing the 32 byte buffer causes improper operation. The RDY bit of the
Serial Status Register (SSR) may be read to determine if there is room in the command buffer for at least 2 bytes of command data. The Status register data is output immediately following the receipt of the Slave Address READ.
The first byte of a 2-byte command is always written first. The master’s sequence
for writing a 2-byte command, followed by a 1-byte command is displayed in the
following example:
Start
Slave_Address_Write/Slave ACK
CMD1_Write/Slave ACK
DATA1_Write/Slave ACK
CMD2_Write/Slave ACK
Stop
PS000400-TVC0499
Z86230—PRELIMINARY
19
I2C BUS OPERATION
SERIAL COMMUNICATIONS INTERFACE
FIGURE 4. I2C BUS WRITE (COMMAND)
I2C One-Byte WRITE (Command)
START
SLAVE ADDR
(WRITE=28h for the
WRITE CMD
1st I2C
STOP
Address and 2Ah for the 2nd I2C Address)
I2C Two-Byte WRITE (Command & Data)
START
SLAVE ADDR
WRITE CMD
WRITE DATA
STOP
(WRITE=28h for the 1st I2C Address and 2Ah for the 2nd I2C Address)
NOTE: The Status Register RDY bit must be read and checked prior to the START
condition of either WRITE sequence above. Refer to the One Byte READ (Status Only)
in Figure 5 for more information on reading the Status Register.
4.1.4 Reading Data Using the I2C Bus
The Z86230 I2C bus supports READ sequences up to 34 bytes in length. All READ
sequences output the Serial Status Register (SSR) as the first output byte. The data
to be read is selected by sending the READ BANK SELECT (RBS) command. Four
READ bank modes are available in the Z86230:
TABLE 5. Z86230 I2C READ BANK SELECT (RBS) COMMAND
RBS
Command
Bank 0
Bank 1
Bank 2
Bank 3
Descriptions
A general-purpose bank used to read the Z86230-defined internal registers. The
register to be read from Bank 0 is set up manually using the READ SELECT
commands, RDS1 and RDS2. These commands load the selected data byte (or pair
of bytes) into the first location(s) of Bank 0, and set the DAV bit to indicate the
availability of data.
A special purpose bank provided to facilitate the reading of commonly accessed
data. This bank contains the Program Blocking registers and permits direct,
multibyte reading of internal registers 08h through 11h. These registers are
described in the internal register section. When it is selected, the sequence of bytes
read is SSR, followed by internal registers 08h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh,
10h, and 11h.
A special purpose bank provided to facilitate the reading of commonly accessed
data. This bank contains the XDS Program Name data from the most recently
received current class type 3 packet.
A special purpose bank provided to facilitate the reading of commonly accessed
data. This bank contains the XDS Network Name and Call Letter data. The first 26
bytes has the XDS Network Name from the most recently received XDS channel
class type 1 packet. Bytes 26 through 31 has the XDS Call Letters data from the
most recently received XDS channel class type 2 packet
NOTE: Banks 2 and 3 are 33 bytes in length. Byte 32 of these banks contains an 8 bit checksum. The checksum
is calculated such that the addition of the 32 data bytes and the checksum modulo 256 equals zero. The
checksum should always be evaluated after reading this data to ensure that the XDS data is not being updated
during the READ operation. The result is a meaningless combination of two unrelated XDS data packets. If a
bad checksum is encountered, the READ operation should be repeated.
20
Z86230—PRELIMINARY
PS000400-TVC0499
I2C BUS OPERATION
SERIAL COMMUNICATIONS INTERFACE
All READ sequences output the SSR first. If the Serial Status register DAV bit is
set, a 2- or multiple-byte READ sequence can be initiated, beginning with a
START condition. If the DAV bit is not set, the I2C master device should not
attempt to read any data bytes or the required data can be lost from the Z86230
output registers. The I2C master device should end the READ sequence by failing
to acknowledge the received byte. This sequence is repeated until the DAV bit
becomes true.
NOTE: In all I2C READ operations (1-, 2- and 3-byte reads are illustrated in Figure 5), the
most recent byte read from the Z86230 should be acknowledged by the master with a Not
Acknowledge (NACK). The DAV bit of the Serial Status Register (SSR) is cleared by the
master clocking out the eighth bit of the first data byte read. The DAV bit is never cleared
by just reading the SSR (One Byte READ) alone. All data is output MSB first.
The master’s sequence for reading two data bytes (total of 3 bytes including SSB)
from the Z86230 is:
Start
Slave_Address_Read/Slave_ACK
SS_Byte/Master ACK
First_Byte/Master ACK
Second_Byte/Master_NACK
Stop
FIGURE 5. I2C BUS READ (COMMAND)
I2C One-Byte READ (Status Only)
START
SLAVE ADDR
(READ=29h for the
NACK
SERIAL STATUS
STOP
1st 2
I C Address and 2Bh for the 2nd I2C Address)
I2C Two-Byte READ (Status & Data1)
START
SLAVE ADDR
SERIAL STATUS
NACK
READ DATA1
STOP
(READ=29h for the 1st I2C Address and 2Bh for the 2nd I2C Address)
I2C Three-Byte READ (Status, Data1, & Data2)
START
SLAVE ADDR
SERIAL STATUS
READ DATA1
NACK
READ DATA2
STOP
(READ=29h for the 1st I2C Address and 2Bh for the 2nd I2C Address)
NOTE: In all I2C READ operations, the most recent byte read from the Z86230 must be
acknowledged by the master with a NACK (Not ACKnowledge).
4.1.5 Clock and Data Transitions
The SCLK and SDA bus lines are normally pulled High with a resistor. Data on the
SDA bus may only change during SCLK Low time periods. Data changes during
SCLK High periods indicate a START or STOP condition as defined in Table 6.
4.1.6 START Condition
A High-to-Low transition of SDA with SCLK High is a START condition which
must precede any other command.
PS000400-TVC0499
Z86230—PRELIMINARY
21
I2C BUS OPERATION
SERIAL COMMUNICATIONS INTERFACE
4.1.7 STOP Condition
A Low-to-High transition of SDA with SCLK High is a STOP condition which terminates all communications.
4.1.8 Acknowledge
All address and data words are serially transmitted to and from the Z86230 in
eight bit words. A ninth bit time is used for the Acknowledge. The acknowledging
device pulls the SDA bus Low during the ninth bit. A Not Acknowledge (NACK)
is returned by SDA = High during the ninth clock time.
FIGURE 6. I2C SERIAL TIMING
tHigh
tF
tLow
tR
SCLK
tSU.DAT
tSU.STA
tSU.STO
tHD.STA
tHD.DAT
SDA (IN)
tAA
tBUF
tDH
SDA (OUT)
TABLE 6. I2C SERIAL TIMING MIN/MAX
22
Symbol
Parameter
fSCLK
Clock Frequency
tLOW
Clock Pulse Width Low
tHigh
Max
Units
100
kHz
4.7
–
ms
Clock Pulse Width High
4.0
–
ms
tR
SDA and SCL Rise Time
–
1.0
ms
tF
SDA and SCL Fall Time
–
300
ns
tAA
Clock Low to Data Out Valid
0.1
3.5
ms
tBUF
Bus Free Time
4.7
–
ms
tHD.STA
Start Hold Time
4.0
–
ms
tSU.STA
Start Set-up Time
4.7
–
ms
tHD.DAT
Data In Hold Time
0
–
ms
tSU.DAT
Data In Set-up Time
250
–
ns
tSU.STO
Stop Set-up Time
4.7
–
ms
tDH
Data Out Hold Time
100
–
ns
tI
Input Filter Time Constant
100
ns
Z86230—PRELIMINARY
Min
PS000400-TVC0499
COMMANDS
SERIAL PORT COMMANDS
5.
COMMANDS
5.1 SERIAL PORT COMMANDS
The commands must be contained within the Start–Slave Address–etc. sequence.
NOTE: In the following Command descriptions, the letter h following a command code
designates hexadecimal notation.
5.1.1 RESET = FBh
RESET is a 1-byte command. The RESET command establishes all of the speci-
fied default settings in the device, but it does not reset the serial port itself. The
RESET command must be followed by a no operation (NOP) command, because
RESET stays active until deactivated by the NOP. This sequence can be entered
without the RDY bit being set.
5.1.2 NOP = 00h
NOP is a 1-byte command. The NOP command does not affect the status of the
RDY bit in the Serial Status Register (SSR) and can be executed independent of
the RDY status.
TABLE 7. BASIC SERIAL COMMANDS
Serial Command
Command Code
RESET
NOP
FBh
00h
5.2 READ AND WRITE COMMANDS
All register diagrams indicated in this section incorporate the following conventions, unless otherwise noted:
•
•
R = Read, W = Write, X = Indeterminate, and res = Reserved
All register bits marked as res must be set to Low(0)
5.2.1 READ Bank Select (RBS = FDh)
RDS1 is a 2-byte command to select the read data bank. The lower 2 bits of the
second data byte select one of four banks of up to 33 bytes. A subsequent I2C
READ deciphers data from the specified bank.
5.2.2 READ SELECTs (RDS1 = 40h–51H)
RDS1 is a 1-byte command used to initiate a 1-byte READ sequence. This activity
is performed by moving the contents of the register identified by the address field
(AD00:04) of the command to the first location of READ bank 0. Addresses 00h–
11h are valid in the RDS1 command field AD00:04.
PS000400-TVC0499
Z86230—PRELIMINARY
23
COMMANDS
WRITING TO THE Z86230
TABLE 8. RDS1–READ ONE BYTE (RDS1 = 40h–51h)
Bit
R/W
CM7
0
W
CM6
1
W
CM5
0
W
CM4
AD04
W
CM3
AD03
W
CM2
AD02
W
CM1
AD01
W
CM0
AD00
W
5.2.3 RDS2 = 60h–70h
RDS2 is a 1-byte command which is used to initiate a 2-byte READ sequence by
moving the contents of the two consecutive registers, starting with the one identified by the address portion of the command (AD00:AD04), to the first 2 locations
of read bank 0. Only Addresses 00h–10h are valid in the RDS2 command field
AD00:04.
NOTE: For XDS data recovery, when the XDS Filter Register (see Control Registers) is
enabled for the required packets, the Z86230 automatically establishes the 2-byte recovery
mode and moves the recovered data bytes to the first 2 locations of bank 0.
TABLE 9. RSD2–READ TWO BYTES (RDS2 = 60h–70h)
Bit
R/W
CM7
0
W
CM6
1
W
CM5
1
W
CM4
AD04
W
CM3
AD03
W
CM2
AD02
W
CM1
AD01
W
CM0
AD00
W
CM2
AD2
W
CM1
AD1
W
CM0
AD0
W
5.3 WRITING TO THE Z86230
5.3.1 WRxx = C0h–D1h
TABLE 10. WRXX–WRITE REGISTER XX (WRX = C0h–D1h)
Bit
R/W
CM7
1
W
CM6
1
W
CM5
0
W
CM4
AD04
W
CM3
AD3
W
The WRITE commands require 2 bytes to execute. The first byte is the write command and includes the Z86230 register address (AD00:04) being written. The second byte is the data to be written.
24
Z86230—PRELIMINARY
PS000400-TVC0499
CONTROL REGISTERS
REGISTERS SUMMARY
6.
CONTROL REGISTERS
Information controlling the setup and operation of the Z86230 are maintained in
several registers. The user may read or alter the contents of these registers as
required.
All register diagrams indicated in this section incorporate the following conventions, unless otherwise noted:
•
•
R = Read, W = Write, X = Indeterminate, and res = Reserved
All register bits marked as res must be set to Low(0)
6.1 REGISTERS SUMMARY
6.1.1 Serial Status Register
TABLE 11. SERIAL STATUS REGISTER (ADDRESS NOT REQUIRED)
Bit
7
RDY
R
R/W
6
DAV
R
5
res
R
4
WOVR
R
3
INTR
R
2
ROVR
R
1
FLD
R
0
LOCK
R
D0–LOCK. Active High, indicating that the internal sync circuits are locked. May
be used as an indication of the presence of a video signal.
D1–FLD. Signals the current video field. Low = Field 2, High = Field 1.
D2–ROVR. Active High, indicating that the data available in the output buffer is
not read out and new data is written over it.
D3–INTR. Active High, indicating that an interrupt other than DAV is pending.
Reserved.
D4–WOVR. Active High, indicating a serial input data overrun.
D5-Res. Reserved.
D6-DAV. Active High, indicating that data is available to be read out.
D7–RDY. Active High, indicating that the port input buffer is empty. Only the
NOP, RESET and READ instructions may be sent if RDY is Low.
6.1.2 Configuration Register
TABLE 12. CONFIGURATION REGISTER (ADDRESS = 00h)
Bit
R/W
PS000400-TVC0499
7
res
R
6
res
R
5
res
R
Z86230—PRELIMINARY
4
res
R
3
res
R
2
res
R/W
1
res
R
0
TVS
R/W
25
CONTROL REGISTERS
REGISTERS SUMMARY
D0–TVS. Selects the television standard. High selects PAL and Low selects NTSC.
The default is NTSC. When PAL is selected, the display defaults to 15 TV scan
lines per display row.
D1-Res. Reserved
D2-D7-Res. Reserved.
6.1.3 XDS Data Activity Register
TABLE 13. XDS DATA ACTIVITY REGISTER (ADDRESS = 04h)
Bit
7
res
R
R/W
6
res
R
5
res
R
4
res
R
3
res
R
2
res
R
1
XDS
R
0
res
R
D0-Res. Reserved.
D1–XDS. Indicates XDS data is being processed. This bit becomes inactive if no
XDS data is received within the previous 16 seconds: High = Active, Low = Inactive. The RESET state is Low.
D2-D7-Res. Reserved.
6.1.4 XDS Filter Register
TABLE 14. XDS FILTER REGISTER (ADDRESS = 05h)
Bit
R/W
7
s2
6
s1
5
s0
4
PUBL
R/W
R/W
R/W
R/W
3
2
1
0
MISC CHAN FUTR CURR
R/W
R/W
R/W
R/W
D0–CURR. Selects Current Class packets for output through the Serial Control
port when XDS recovery is enabled.
D1–FUTR. Selects Future Class packets for output through the Serial Control port
when XDS recovery is enabled.
D2–CHAN. Selects Channel Information Class packets for output through the
Serial Control port when XDS recovery is enabled.
D3–MISC. Selects Miscellaneous Class packets for output through the Serial Con-
trol port when XDS recovery is enabled.
D4–PUBL. Selects Public Service Class packets for output through the Serial Con-
trol port when XDS recovery is enabled.
D5-D7–s0–s2. Selects a set of secondary parameters, tabulated below, to be used in
filtering the XDS data when XDS recovery is enabled.
26
Z86230—PRELIMINARY
PS000400-TVC0499
CONTROL REGISTERS
REGISTERS SUMMARY
TABLE 15. XDS SECONDARY FILTER SETTINGS
Secondary Filter
Filter Value (s0:s2)
All
Time Information
In Band Only
Content Advisory
VCR Information
Reserved
Reserved
Reserved
0h
1h
2h
3h
4h
5h
6h
7h
Notes:
1. Setting this register to 00h turns XDS data recovery off. Setting bits D0
through D4 enables XDS data recovery for the Classes selected as qualified by
the Secondary Filter (bits D5–D7). If Bits D0–D4 are all set to 1, all Classes of
XDS data are output (even Reserved and Undefined).
2. The Time Information Only selection includes the Time of Day (TOD) and Local
Time Zone (LTZ) packets.
3. VCR Information selects TOD, LTZ, Net ID, Local Call Letters, Impulse Capture,
Tape Delay, Composite 2, and Out-of-Band Channel Number packets for recovery.
6.1.5 Interrupt Request Register
TABLE 16. INTERRUPT REQUEST REGISTER (ADDRESS = 06h)
Bit
7
res
R/W
R/W
6
5
res dXDS
R/W R/W
4
res
R/W
3
dLOK
R/W
2
EOF
R
1
DLE
R
0
res
—
D0-Res. Reserved.
D1-DLE. Active High, indicating that the data line has ended. This bit sets two
lines after the data line, and clears about 20 lines before the end of the field.
D2–EOF. Active High, indicating that the video signal is currently at the end of a
field. This bit sets during line 262 in Field 1 and line 524 in Field 2. This bit clears
about 2 lines before the end of the field.
D3–dLOK. Active High, indicating that the state of the LOCK signal has changed.
The SSR must be read to determine the current state.
D4-Res. Reserved.
D5–dXDS. Active High, indicating that a change in XDS activity has occurred.
The Line 21 Activity Register must be read to determine if XDS data is active.
D6-D7-Res. Reserved.
NOTE: Except as noted for the case of D1 and D2 above, the master device must write a 1
to the appropriate bit in the Interrupt Request Register to clear the Interrupt. Writing a 1 to
PS000400-TVC0499
Z86230—PRELIMINARY
27
CONTROL REGISTERS
REGISTERS SUMMARY
any valid bit position the Interrupt Request Register is equivalent to CLEARing an interrupt request on that bit.
6.1.6 Interrupt Mask Register
TABLE 17. INTERRUPT MASK REGISTER (ADDRESS = 07h)
Bit
R/W
7
res
R/W
6
res
R/W
5
dXDS
R/W
4
res
R/W
3
dLOK
R/W
2
EOF
R/W
1
DLE
R/W
0
DAV
R/W
This register identifies which activities in the Interrupt Request Register is used to
cause an interrupt. Setting the bit to 1 enables the interrupt when the corresponding event becomes active. Setting all bits of this register to zero disables interrupts.
6.1.7 Content Advisory Ratings Select Register 1
This register holds the MPAA Content Advisory selections made by the viewer.
TABLE 18. CONTENT ADVISORY RATINGS SELECT REGISTER 1 (ADDRESS = 08h)
Bit
R/W
7
res
R
6
Not
Rated
R/W
5
X
4
NC-17
3
R
2
PG-13
1
PG
0
G
R/W
R/W
R/W
R/W
R/W
R/W
D0–G. The Z86230 outputs High on pin 13 when the incoming video program is
G-rated according to the MPAA Ratings standards, and this bit is set to High.
D1–PG. The Z86230 outputs High on pin 13 when the incoming video program is
PG-rated according to the MPAA Ratings standards, and this bit is set to High.
D2-PG-13. The Z86230 outputs High on pin 13 when the incoming video program
is PG-13-rated in MPAA Ratings standards, and this bit is set to High.
D3-R. The Z86230 outputs High on pin 13 when the incoming video program is R-
rated according to the MPAA Ratings standards, and this bit is set to High.
D4-NC-17. The Z86230 outputs High on pin 13 when the incoming video program
is NC-17-rated according to the MPAA Ratings standards, and this bit is set to
High.
D5-X. The Z86230 outputs High on pin 13 when the incoming video program is
X-rated according to EIA-744A and EIA-608A specifications. MPAA no longer
recognizes the X rating.
D6-Not Rated. The Z86230 outputs High on pin 13 when the incoming video pro-
gram is Not Rated according to the MPAA Ratings standards, and this bit is set to
High.
28
Z86230—PRELIMINARY
PS000400-TVC0499
CONTROL REGISTERS
REGISTERS SUMMARY
D7-Res. Reserved. This bit must be kept Low(0).
NOTE: The Z86230 outputs Low when a bit in this register is set to Low, and the incoming
video program possesses the corresponding MPAA Rating. The device outputs High onto
pin 13 only when a bit is set to High; it recovers the corresponding MPAA Rating in the
incoming video program.
6.1.8 Content Advisory Ratings Select Register 2
This register holds the TV Parental Guidelines (Base Content) Content Advisory
selections made by the viewer.
TABLE 19. CONTENT ADVISORY RATINGS SELECT REGISTER 2 (ADDRESS = 09h)
Bit
R/W
7
res
R
6
5
4
NONE TV-MA TV-14
R
R/W
R/W
3
TV-PG
R/W
2
TV-G
R/W
1
TV-Y7
R/W
0
TV-Y
R/W
D0-TV-Y. The Z86230 outputs High on pin 13 when the incoming video program
is TV-Y-rated according to the TV Parental Guidelines Ratings standards, and this
bit is set to High.
D1-TV-Y7. The Z86230 outputs High on pin 13 when the incoming video program
is TV-Y7-rated according to the TV Parental Guidelines Ratings standards, and
this bit is set to High.
D2-TV-G. The Z86230 outputs High on pin 13 when the incoming video program
is TV-G-rated according to the TV Parental Guidelines Ratings standards, and this
bit is set to High.
D3-TV-PG. The Z86230 outputs High on pin 13 when the incoming video program is TV-PG-rated according to the TV Parental Guidelines Ratings standards,
and this bit is set to High.
D4-TV-14. The Z86230 outputs High on pin 13 when the incoming video program
is TV-14-rated according to the TV Parental Guidelines Ratings standards, and
this bit is set to High.
D5-TV-MA. The Z86230 outputs High on pin 13 when the incoming video program is TV-MA-rated according to the TV Parental Guidelines Ratings standards,
and this bit is set to High.
D6-TV-MA. The Z86230 outputs High on pin 13 when the incoming video pro-
gram is TV-NONE-rated according to the TV Parental Guidelines Ratings standards, and this bit is set to High.
D7-Res. Reserved. This bit must be kept Low(0).
NOTE: The Z86230 outputs Low when a bit in this register is set to Low, and the incoming
video program possesses the corresponding TV Parental Guidelines Rating. The device
outputs High onto pin 13 only when a bit is set to High; it recovers the corresponding TV
PS000400-TVC0499
Z86230—PRELIMINARY
29
CONTROL REGISTERS
REGISTERS SUMMARY
Parental Guidelines Ratings in the incoming video program. This control register is for the
base rating of TV Parental Guidelines.
6.1.9 Content Advisory Ratings Select Register 3
This register holds the TV Parental Guidelines (V and S Contents) Content Advisory selections made by the viewer.
TABLE 20. CONTENT ADVISORY RATINGS SELECT REGISTER 3 (ADDRESS = 0Ah)
Bit
R/W
7
TVMA-V
R/W
6
5
4
TV-14- TV-PG- TV-Y7V
V
FV
R/W
R/W
R/W
3
res
R/W
2
TVMA-S
R/W
1
0
TV-14- TV-PGS
S
R/W
R/W
D0-TV-PG-S. The Z86230 outputs High on pin 13 when the incoming video pro-
gram is TV-PG-S-rated according to the TV Parental Guidelines Ratings standards, and this bit is set to High.
D1-TV-14-S. The Z86230 outputs High on pin 13 when the incoming video program is TV-14-S-rated according to the TV Parental Guidelines Ratings standards,
and this bit is set to High.
D2-TV-MA-S. The Z86230 outputs High on pin 13 when the incoming video pro-
gram is TV-MA-S-rated according to the TV Parental Guidelines Ratings standards, and this bit is set to High.
D3-Res. Reserved. This bit must be kept Low(0).
D4-TV-Y7-FV. The Z86230 outputs High on pin 13 when incoming video program
is TV-Y7-FV-rated in TV Parental Guidelines Ratings standards, and this bit is set
to High.
D5-TV-PG-V. The Z86230 outputs High on pin 13 when the incoming video pro-
gram is TV-PG-V-rated according to the TV Parental Guidelines Ratings standards, and this bit is set to High.
D6-TV-14-V. The Z86230 outputs High on pin 13 when the incoming video pro-
gram is TV-14-V-rated according to the TV Parental Guidelines Ratings standards, and this bit is set to High.
D7-TV-MA-V. The Z86230 outputs High on pin 13 when the incoming video pro-
gram is TV-MA-V-rated according to the TV Parental Guidelines Ratings standards, and this bit is set to High.
NOTE: The Z86230 outputs Low when a bit in this register is set to Low and the incoming
video program possesses the corresponding TV Parental Guidelines Rating. The device
outputs High onto pin 13 only when a bit is set to High; it recovers the corresponding TV
Parental Guidelines Rating in the incoming video program. This control register is for the
S- and V-rated programs in TV Parental Guidelines Rating.
30
Z86230—PRELIMINARY
PS000400-TVC0499
CONTROL REGISTERS
REGISTERS SUMMARY
6.1.10 Content Advisory Ratings Select Register 4
This register holds the TV Parental Guidelines (L and D Content) Content Advisory selections made by the viewer.
TABLE 21. CONTENT ADVISORY RATINGS SELECT REGISTER 4 (ADDRESS = 0Bh)
Bit
R/W
7
res
6
5
4
TV-MA- TV-14- TV-PGL
L
L
R/W
R/W
R/W
R
3
res
2
res
R
R
1
0
TV-14- TV-PGD
D
R/W
R/W
D0-TV-PG-D. The Z86230 outputs High on pin 13 when the incoming video pro-
gram is TV-PG-D-rated according to the TV Parental Guidelines Ratings standards, and this bit is set to High.
D1-TV-14-D. The Z86230 outputs High on pin 13 when the incoming video program is TV-14-D-rated according to the TV Parental Guidelines Ratings standards, and this bit is set to High.
D2-D3. Reserved. These bits must kept Low(0).
D4-TV-PG-L. The Z86230 outputs High on pin 13 when the incoming video program is TV-PG-L-rated according to the TV Parental Guidelines Ratings standards, and this bit is set to High.
D5-TV-14-L. The Z86230 outputs High on pin 13 when the incoming video pro-
gram is TV-14-L-rated according to the TV Parental Guidelines Ratings standards, and this bit is set to High.
D6-TV-MA-L. The Z86230 outputs High on pin 13 when the incoming video pro-
gram is TV-MA-L-rated according to the TV Parental Guidelines Ratings standards, and this bit is set to High.
D7-Res. Reserved. This bit must be kept Low(0).
NOTE: The Z86230 outputs Low when a bit in this register is set to Low and the incoming
video program possesses the corresponding TV Parental Guidelines Rating. The device
outputs High onto pin 13 only when a bit is set to High and it recovers the corresponding
TV Parental Guidelines Rating in the incoming video program. This control register is for
the D- and L-rated programs in TV Parental Guidelines Rating.
6.1.11 Content Advisory Register 1
TABLE 22. CONTENT ADVISORY REGISTER 1 (ADDRESS = 0Ch)
Bit
R/W
PS000400-TVC0499
7
B
R
6
1
R
5
D
R
Z86230—PRELIMINARY
4
a1
R
3
a0
R
2
r2
R
1
r1
R
0
r0
R
31
CONTROL REGISTERS
REGISTERS SUMMARY
D0-D6. These bits hold the corresponding information recovered from the first
byte of the received Content Advisory Ratings packet.
D7-B. This bit indicates the blocking status. When this bit is High, it indicates that
the data from the received Content Advisory packet matches the user selection
contained in one of the Content Advisory Ratings registers, and the PB pin is in
the blocking status.
6.1.12 Content Advisory Register 2
TABLE 23. CONTENT ADVISORY REGISTER 2 (ADDRESS = 0Dh)
Bit
R/W
7
P
R
6
1
R
5
(F)V
R
4
S
R
3
L
R
2
g2
R
1
g1
R
0
g0
R
D0-D6. These bits hold the corresponding information recovered from the second
byte of the received Content Advisory Ratings packet.
D7-P. This bit indicates the validity of the data in the recovered Content Advisory
packet. When this bit is High, it indicates that the data from the received Content
Advisory packet is valid. This bit clears if no Content Advisory packet is received
after 5 seconds.
6.1.13 Blocking Control Register 1
TABLE 24. BLOCKING CONTROL REGISTER 1 (ADDRESS = 0Eh)
Bit
R/W
7
BLEN
R/W
6
5
4
R/W
R/W
R/W
3
BTE
R/W
2
1
0
R/W
R/W
R/W
D0-D6-BTE. These bits set the Block Timer which controls the duration of the hold
of the blocking signal on a change of channel. The default value of 0 has a hold
time of 2 seconds. The time is extended in 2 frames with each binary step.
D7-BLEN. These bits enable the blocking capability. BLEN=0 enables blocking;
BLEN=1 disables blocking.
6.1.14 Content Advisory Ratings Select 5
This register holds the Canadian English Language Content Advisory selections
made by the viewer.
TABLE 25. CONTENT ADVISORY RATINGS SELECT REGISTER 5 (ADDRESS = 0Fh)
Bit
R/W
32
7
res
R
6
18+
R/W
5
14+
R/W
4
PG
R/W
Z86230—PRELIMINARY
3
G
R/W
2
C8+
R/W
1
C
R/W
0
E
R/W
PS000400-TVC0499
REGISTERS SUMMARY
CONTROL REGISTERS
D0-E. The Z86230 outputs High on pin 13 when the incoming video program is E-
rated according to the Canadian English Language Ratings standards, and this bit
is set to High.
D1-C. The Z86230 outputs High on pin 13 when the incoming video program is
C-rated according to the Canadian English Language Ratings standards, and this
bit is set to High.
D2-C8+. The Z86230 outputs High on pin 13 when the incoming video program is
C8+-rated according to the Canadian English Language Ratings standards, and
this bit is set to High.
D3-G. The Z86230 outputs High on pin 13 when the incoming video program is
G-rated according to the Canadian English Language Ratings standards, and this
bit is set to High.
D4-PG. The Z86230 outputs High on pin 13 when the incoming video program is
PG-rated according to the Canadian English Language Ratings standards, and
this bit is set to High.
D5-14+. The Z86230 outputs High on pin 13 when the incoming video program is
14+-rated according to the Canadian English Language Ratings standards, and
this bit is set to High.
D6-18+. The Z86230 outputs High on pin 13 when the incoming video program is
18+-rated according to the Canadian English Language Ratings standards, and
this bit is set to High.
D7-Res. Reserved. This bit must be kept Low(0).
NOTE: The Z86230 outputs Low when a bit in this register is set to Low and the incoming
video program possesses the corresponding Canadian French Language Rating. The
device outputs High onto pin 13 only when a bit is set to High and it recovers the corresponding Canadian English Language Rating in the incoming video program.
6.1.15 Content Advisory Ratings Select Register 6
This register holds the Canadian French Language Content Advisory selections
made by the viewer.
PS000400-TVC0499
Z86230—PRELIMINARY
33
CONTROL REGISTERS
REGISTERS SUMMARY
TABLE 26. CONTENT ADVISORY RATINGS SELECT REGISTER 6 (ADDRESS = 10h)
Bit
R/W
7
res
R
6
res
R
5
4
3
2
18ans+ 16ans+ 13ans+ 8ans+
R/W
R/W
R/W
R/W
1
G
R/W
0
E
R/W
D0-E. The Z86230 outputs High on pin 13 when the incoming video program is E-
rated according to the Canadian French Language Ratings standards, and this bit
is set to High.
D1-G. The Z86230 outputs High on pin 13 when the incoming video program is
G-rated according to the Canadian French Language Ratings standards, and this
bit is set to High.
D2-8ans+. The Z86230 outputs High on pin 13 when incoming video program is
8ans+-rated in Canadian French Language Ratings standards, and this bit is set to
High.
D3-13ans+. The Z86230 outputs High on pin 13 when incoming video program is
13ans+-rated in Canadian French Language Ratings standards, and this bit is set
to High.
D4-16ans+. The Z86230 outputs High on pin 13 when incoming video program is
16ans+-rated in Canadian French Language Ratings standards, and this bit is set
to High.
D5-18ans+. The Z86230 outputs High on pin 13 when the incoming video pro-
gram is 18ans+-rated according to the Canadian French Language Ratings and
this bit is set to High.
D6-D7-Res. Reserved. These bits must be kept Low(0).
NOTE: The Z86230 outputs Low when a bit in this register is set to Low and the incoming
video program possesses the corresponding Canadian French Language Rating. The
device outputs High onto pin 13 only when a bit is set to High and it recovers the corresponding Canadian French Language Rating in the incoming video program.
6.1.16 Blocking Control Register 2
TABLE 27. BLOCKING CONTROL REGISTER 2 (ADDRESS = 11AH)
Bit
R/W
7
res
R
6
res
R
5
res
R
4
res
R
3
res
R
2
res
R
1
res
R
0
BNR
R/W
D0-BNR. The Z86230 outputs High on pin 13 when the incoming video program
has No Rating and this bit is set to Low. Setting this bit to High disables blocking
on No Rating.
34
Z86230—PRELIMINARY
PS000400-TVC0499
XDS DATA RECOVERY
CONTROL REGISTERS
D1-D7-Res. Reserved. These bits must be kept Low(0).
6.2 XDS DATA RECOVERY
The Z86230 is able to recover Extended Data Services (XDS) information from
the input video signal. This data, formatted according to EIA-608A, can contain a
wide variety of information about current and future programs, the channel currently tuned, other channels, and miscellaneous data, including time of day.
XDS data packets are tagged according to a Class/Type system defined by EIA608A. The Z86230 can be programmed to filter the XDS data stream to extract
only the classes of interest to the application. An additional level of filtering is
provided that permits selection of certain groups of packets that are of use in specific applications. XDS filtering reduces the traffic on the serial bus, reduces the
load of the TV/VCR control processor, and simplifies external XDS decoding.
XDS data recovery is enabled by selecting one or more classes in the XDS Filter
Register. Optionally, a secondary filter code can be specified which further limits
the packets to be recovered. When XDS recovery is enabled, filtered data pairs are
loaded into the first two data locations of Bank 0 immediately upon receipt. The
DAV bit of the Serial Status Register (SSR) then goes High, indicating the availability of two output bytes.
When the XDS Filter Register is set to 00h (the default state), XDS recovery is
disabled.
CAUTION: When XDS data recovery is enabled, the external controller should never perform any other read operation, except SSR reads, in the beginning of Field 2. Commands
other than READ SELECTs do not interfere with XDS data recovery regardless of their
position in the video frame.
Some examples of Z86230 WRITE commands that could be used to set the XDS
Filter Register are indicated in Table 28. The XDS Filter Register bit assignments
are defined in Table 30.
PS000400-TVC0499
Z86230—PRELIMINARY
35
CONTROL REGISTERS
XDS DATA RECOVERY
TABLE 28. XDS DATA EXTRACTION EXAMPLE FILTER SETTINGS
{WRITE Command,
Filter Code}
XDS Filter Output
{C5,41}
{C5,61}
{C5,1F}
{C5,01}
{C5,28}
{C5,9F}
All In Band; Current Class packets recovered.
Program Rating; Current Class packets recovered. This
filter may be used for Program Blocking Data Packet
Recovery.
All XDS packets recovered.
All Current Class packets recovered.
Time information recovered. This filter extracts the
Time of Day (TOD) and Local Time Zone (LTZ) packets
from the Miscellaneous Class data.
This filter may be used to implement Auto ClockSetting in TVs, and VCRs.
VCR Information recovered. This filter selects TOD, LTZ,
Net ID, Local Call Letters, Impulse Capture, Tape Delay,
Composite 2, and Out-of-Band Channel Number
packets for recovery.
6.2.1 Filtered XDS Data Format
Filtered XDS data is output from the Z86230 in the order it is received on Line 21.
In other words, think of the Z86230 XDS filter function as creating a new, smaller
stream of XDS data packets. This new data stream looks exactly as though the
Class and Type specified in the XDS Filter Register (05h) are the only data
encoded on Line 21 of Field 2. The filtered data output from the Z86230 is in full
compliance with EIA-608 specifications for XDS data streams (headers and control codes intact). Refer to the NOTE paragraph on the next page for a special
exception to this rule.
XDS data and header information (including START, CONTINUE, and END commands) are passed through the filter for the XDS Class and Type specified in the
XDS Filter Register. All other Line 21 data is filtered out. This data does not output or generate a data available flag (DAV) in the Serial Status Register (SSR).
To properly read filtered XDS data from the Z86230, the master device must first
write the XDS Filter Register (05h) with its required XDS Class and Type information. For example, in the Z86230, in order to extract ONLY the Line 21 Program Rating information, the master must write the value 61h to the XDS Filter
Register. The master should then poll the state of the DAV bit in the SSR until
DAV = 1.
As soon as DAV = 1, the master may initiate a 3-byte READ in RBS Read Bank 0
mode (XDS data bytes always arrive in pairs, so it is safe to read the first 2 bytes
of read bank 0 when DAV = 1 in the SSB). A 3-byte READ always yields two data
bytes, which in this case are the first 2 bytes of the Current Class, Program Rating
Type XDS data stream encountered on Line21, Field 2. The master device must
then interpret those 2 bytes according to EIA-608 specifications for Current Class,
Program Rating Type data. Refer to EIA-608 for the appropriate data formats.
36
Z86230—PRELIMINARY
PS000400-TVC0499
XDS DATA RECOVERY
CONTROL REGISTERS
The XDS filters on the Z86230 greatly reduce the amount of Field 2 data passed
on to the master device for further processing and interpretation; however, the
master device must still interpret the filtered data stream in accordance with EIA608A. In other words, only the selected XDS data Class and Type packets are chosen. The filtered data stream contains all of the XDS command and data packets.
Though the Z86230 filtered data stream is in full compliance with the EIA-608
specification, the master device must still interpret the necessary packets to ensure
full compliance with EIA-608A.
NOTE: The Z86230 XDS filter for Program Rating information functions differently than
all other Z86230 predefined XDS filters. This change has been made to minimize the
amount of data passed through the Program Rating XDS filter, thereby minimizing the
interpretation and communications load on the master device. When the XDS Filter Register is set to 61h (Class=01h (Current), Type=05h (Program Rating) the only data from
Line 21 Field 2 that passes through the filter is:
1. Program Rating Packet: [xxh,xxh]. The Current Class Program Rating
data byte pair as defined in EIA-608. The program’s rating is encoded per
EIA-608 in the xxh byte pair.
2. The END Packet [0Fh,CHKSUM]. A 2-byte packet that includes a CHKSUM
computed per EIA-608A. The checksum calculation includes the START
packet [01h,05h] even though this value was not passed through the filter.
PS000400-TVC0499
Z86230—PRELIMINARY
37
CONTROL REGISTERS
Z86230 COMMANDS AND REGISTERS SUMMARY
6.3 Z86230 COMMANDS AND REGISTERS SUMMARY
TABLE 29. Z86230 SUMMARY OF CONTROL COMMANDS
38
Name
Code
Function
RESET
FBh
NOP
00h
RDS1
40h–51h
RDS2
60h–70h
WRxx
C0h–D1h, XXh
RBS
FDh, 0Xh
RESET is 1-byte command sequence serial
communication. The RESET command
establishes all of the specified default settings
in the device; however, it does not reset the
serial port itself. This sequence can be entered
without RDY being set.
NOP is a 1-byte command for use in serial
communication. The NOP command does not
affect the status of the RDY bit in the Serial
Status Register (SSR) and can be executed
independent of the RDY status.
RDS1 is a 1-byte command used to initiate a 1byte READ sequence by moving the contents of
the register identified by the address field
(AD00:04) of the command to the output
register. Addresses 00h–11h are valid in the
RDS1 command field AD00:04.
RDS2 is a 1-byte command which is used to
initiate a 2-byte READ sequence. This activity is
accomplished by moving the contents of the
two consecutive registers, starting with the one
identified by the address portion of the
command (AD00:AD04), to the output registers.
Only Addresses 00h–10h are valid in the RDS2
command field AD00:04.
The WRITE commands require 2 bytes to
execute. The first byte is the WRITE command
includes the Z86230 register address (AD00:04)
being written. The second byte (XXh) is the data
to be written.
RBS is 2-byte command to select the READ data
bank. The 2 LSBs of the second byte (0Xh)
select one of four banks of up to 33 bytes.
Subsequent I2C READs interpret data from this
bank.
Z86230—PRELIMINARY
PS000400-TVC0499
CONTROL REGISTERS
PROGRAM BLOCKING MAP
TABLE 30. SUMMARY OF Z86230 INTERNAL REGISTERS
Register Name
Addr
D7
D6
D5
D4
D3
D2
D1
D0
Serial Status
Register (SSR)
Configuration
XDS Data Activity
XDS Filter
None
RDY
DAV
res
WOVR
INTR
ROVR
FLD
LOCK
00h
04h
05h
res
res
s2
res
res
s1
res
res
s0
res
res
PUBL
res
res
MISC
res
res
CHAN
res
XDS
FUTR
TVS
res
CURR
Interrupt Request
Register
Interrupt Mask
Register
Content Advisory
Rating Select 1
Content Advisory
Rating Select 2
Content Advisory
Rating Select 3
Content Advisory
Rating Select 4
Content Advisory1
Content Advisory 2
Blocking Control 1
Content Advisory
Rating Select 5
Content Advisory
Rating Select 6
Blocking Control 2
06h
res
res
dXDS
res
dLOK
EOF
DLE
res
07h
res
res
dXDS
res
dLOK
EOF
DLE
DAV
08h
res
NC-17
R
PG-13
PG
G
09h
res
Not
X
Rated
NONE TV-MA
TV-14
TV-PG
TV-G
TV-Y7
TV-Y
TV-MA TV-14 TV-PG
V
V
V
res
TV-MA TV-14
L
L
B
1
D
P
1
(F)V
BLEN
res
18+
14+
TV-Y7
FV
TV-PG
L
a1
S
res
TV-MA
S
res
r2
g2
TV-14
S
TV-14
D
r1
g1
TV-PG
S
TV-PG
D
r0
g0
C8+
C
E
8ans+
G
E
res
res
BNR
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
res
res
11h
res
res
PG
res
a0
L
BTE
G
18ans+ 16ans+ 13ans+
res
res
res
NOTE: All register bits marked as res must be set to Low(0).
6.4 PROGRAM BLOCKING MAP
The following matrices demonstrate the program-blocking response of the
Z86230. The first column lists the possible entries into the Content Advisory Rating registers. The first row lists the ratings that might be recovered from the
received Content Advisory packet. Blocking action is indicated by the black
boxes.
Each matrix shows the response to the possible user selections entered into the
Content Advisory Rating registers when programs having specific Content Advisory packets are received. For example, as shown in the TV Parental Guidelines
Rating matrix, entering the viewer selection from TV-PG D in register 09B causes
blocking whenever the received Content Advisory packet is TV-PG D, TV-PG VD,
TV-PG SD, TV-PG LD, TV-PG VSD, TV-PG VLD, TV-PG SLD or TV-PG VSLD.
PS000400-TVC0499
Z86230—PRELIMINARY
39
CONTROL REGISTERS
PROGRAM BLOCKING MAP
Table 31. MPAA Matrix (Use Content Advisory Rating Register 08h)
G
PG
PG-13
R
NC-17
X
NR
G
PG
PG-13
R
NC-17
X
NR
TABLE 32. TV PARENTAL GUIDELINES MATRIX (USE CONTENT ADVISORY RATING REGISTER 09h, 0Ah, 0Bh)
Y Y7 G
PG
14
MA
– – F – – V S L DV V V S S L V V V S V – V S L DV V V SS L V V V S
V
S L DL D DS S L L S
SL DLDD SS L L
L DDDL
L DDD
D
V – V SL VVSV
S
SL LS
L
L
D
Y
Y7
Y7-FV
G
PG
PG-V
PG-S
PG-L
PG-D
14
14-V
14-S
14-L
14-D
MA
MA-V
MA-S
MA-L
NOTE: “–” denotes a base rating.
40
Z86230—PRELIMINARY
PS000400-TVC0499
CONTROL REGISTERS
PROGRAM BLOCKING MAP
TABLE 33. CANADIAN ENGLISH MATRIX (USE CONTENT ADVISORY RATING REGISTER 0Fh)
E
C
C8+
G
PG
14+
18+
E
C
C8+
G
PG
14+
18+
TABLE 34. CANADIAN FRENCH MATRIX (USE CONTENT ADVISORY RATING REGISTER 10h)
E
G
8ans+
13ans+
16ans+
18ans+
E
G
8ans+
13ans+
16ans+
18ans+
PS000400-TVC0499
Z86230—PRELIMINARY
41
DEMONSTRATION PROGRAMS
7.
COMMUNICATING WITH THE Z86230
DEMONSTRATION PROGRAMS
7.1 COMMUNICATING WITH THE Z86230
Communications with the Z86230 is accomplished using its serial communications interface (it is assumed that the user is familiar with the serial protocol
requirements).
NOTE: In the following descriptions, <ENTER> means “press the Enter key”.
7.2 I2C OPERATION
The Z86230 is configurable as an I2C slave device. The PC communicates with
the Z86230 through its parallel port. Though these programs are not intended as
examples of how to program the application they do provide a means of illustrating the serial control process and capability of the Z86230.
The three programs available are titled IICO, SCRIPTI and XDSCAP. These programs compile and run satisfactorily with the Z86230 in a test board. Compiled
versions are available on disk. Contact your local ZiLOG sales office for further
information on these programs.
7.3 IICO PROGRAM
This program sends 1 byte to the Z86230 without checking the status of the RDY
bit. The program returns the contents of the Serial Status Register (SSR) after the
command is entered. When the program is active the screen displays:
IIC Command Byte >
The user may enter any valid 1-byte command such as FBh (RESET) or 00h
(NOP) and then hit the ENTER key. The screen then displays the byte entered and
the SSR contents as follows:
IIC Byte = 00
IIC Status = 83h
This example shows that the NOP command was entered. The SSR contents, 83h,
indicate that the RDY, FLD, and LOCK bits are High, which implies that the serial
port is ready for further input, that the input video signal was in Field 1 at the time
the status was read, and that the part is operating in video lock mode.
The IICO program is exited by entering a Control+C (^C) character.
For example, entering the following two 1-byte commands displays the following:
Reset the part
42
FB, 00
Z86230—PRELIMINARY
PS000400-TVC0499
DEMONSTRATION PROGRAMS
GENERAL COMMANDS
7.4 GENERAL COMMANDS
Serial Command
Command Code
RESET
NOP
SSB
FBh, FCh, 00h
00h
FFh,...FFh,FEh
7.5 SCRIPTI PROGRAM
This program is designed to send any number of 1 or 2-byte commands to the
Z86230. The list of commands to be executed are contained in Script files that
have the extension .SER. For example, a file called FILFA.SER contains the 1-byte
command:
{C5, 02} * Set xds filter to all future class
The program is invoked by typing: SI File_name <ENTER>
NOTE: File_name without the .SER extension.
The screen displays:
EEG CCD2 Serial Interface Script Player Version x.xx
Slave Address is 28h
Script File Done
The responding slave address is reported to the screen. When all of the commands
in the file are successfully sent to the Z86230, the PC returns to the system
prompt.
The program checks the RDY status before sending each byte. If, during the entry of
a command, the RDY bit is not found to be a 1 after an extended wait, the program
reports the contents of the SSR and then continues checking for RDY.
7.6 SCRIPT FILES
Script files can be generated to perform all of the setup and control functions
required to use the part in an application. The script files shown in the following
pages are examples used to set up the Z86230 for different operating conditions.
Some of the files contain only a single command while others include several
commands. The user should refer to Z86230 Commands and Registers Summary
for details. Although the following examples are organized according to a particular register, some of the files contain information for several registers.
PS000400-TVC0499
Z86230—PRELIMINARY
43
DEMONSTRATION PROGRAMS
SCRIPT FILES
7.6.1 Configuration Register Script Files
TABLE 35. CONFIGURATION REGISTER SCRIPT FILES
File Name
Command
Function
FIGVH
{C7,00}
{83,12}
{C0,00}
{C0,01}
Set INT Mask register clear
Bit set ext V pulse for pos
Set config back to default state
Set config register to TVS=1. Changes VBI line to
L22 PAL.
FIGN
FIGPAL
7.6.2 XDSCAP Program
This program performs the task of XDS data recovery. XDS recovery must first be
enabled through the appropriate XDS Filter command. Script file examples for
setting the XDS Filter are shown below.
The program is invoked by typing: SI File_name <ENTER>
When the program is invoked, the PC screen displays:
EEG CCD2 XDS Data Recovery Test Program Version x.xx
Slave Address is 28h
The responding slave address is reported to the screen.
When communication is acknowledged, the program displays all XDS data recovered from those packets that were enabled through the XDS Filter command:
{01,03}Current Program{00}{0F,7F}....etc
The ASCII characters are displayed as ASCII characters, while the nonprinting characters are displayed by their Hex values within curly braces. Byte pairs, such as
Class, Type, are shown as pairs within the curly braces, separated by a comma, for
example: {01,03}.
If no data is received within approximately 45 seconds, the program times out,
reports Data Not Available, and exits.
NOTE: The XDSCAP program can also be exited by entering a Control+C (^C) character.
44
Z86230—PRELIMINARY
PS000400-TVC0499
DEMONSTRATION PROGRAMS
SCRIPT FILES
7.6.3 XDS Filter Register Script Files
PS000400-TVC0499
File Name
Command
Function
FILA
FIL0
FILCA
FILC
FILFA
FILCH
FILM
FILTIME
FILVCR
{C5,1F}
{C5,00}
{C5,01}
{C5,41}
{C5,02}
{C5,04}
{C5,08}
{C5,28}
{C5,9E}
Set XDS filter to all
Set XDS filter to none; turns off XDS recovery
Set XDS filter to all current class
Set XDS filter to current, in band class
Set XDS filter to all future class
Set XDS filter to channel class
Set XDS filter for misc. info
Set XDS filter time only
Set XDS filter vcr info
Z86230—PRELIMINARY
45
ELECTRICAL CHARACTERISTICS
8.
ABSOLUTE MAXIMUM RATINGS1
ELECTRICAL CHARACTERISTICS
8.1 ABSOLUTE MAXIMUM RATINGS1
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage
–0.5 to 6.0
V
VIN
DC Input Voltage
–0.5 to VDD +0.5
V
VOUT
DC Output Voltage
–0.5 to VDD +0.5
V
IIN
CAUTION: DC Input Current per Pin
+10
mA
IOUT
DC Output Current per Pin
+20
mA
IDD
DC Supply Current
+30
mA
PD
Power Dissipation per Device
300
mW
TSTG
Storage Temperature
–65 to +150
ºC
TL
Lead Temperature, 1 mm from Case for 10
seconds
260
ºC
Notes:
1. Voltages referenced to VSS (A).
Maximum ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits specified in the DC and AC Characteristics tables
or Pin Description section.
8.2 STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All
voltages are referenced to Ground. Positive current flows into the referenced pin
(Figure 7).
FIGURE 7. STANDARD TEST LOAD
+5V
2.1 kΩ
From Output
Under Test
150 pF
46
250 µµA
Z86230—PRELIMINARY
PS000400-TVC0499
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
8.3 DC CHARACTERISTICS
TABLE 36. DC CHARACTERISTICS—TA = 0ºC to +70ºC; VDD = +4.75V to +5.25V
Symbol
Parameter
VIL
Conditions
Min.
Max.
Unit
Input Voltage Low
0
0.2 VDD
V
VIH
Input Voltage High
0.7 VDD
VDD
V
VOL
Output Voltage Low
IOL = 1.00 mA
–
0.4
V
VOH
Output Voltage High
IOH = 0.75 mA
VDD –0.4V
–2
V
IIL
Input Leakage
0V, VDD
–3.0
3.0
mA
IDD
Supply Current
30
mA
Kf
ILP
VCO Gain
Loop Filter Current
TBD
TBD
MHz/V
mA
–
–
8.4 AC AND TIMING CHARACTERISTICS
8.4.1 Composite Video Input
TABLE 37. COMPOSITE VIDEO INPUT
Parameter
Conditions
Amplitude
Polarity
Bandwidth
Signal Type
Max Input R
DC Offset
1.0V p-p ±3 dB
Sync tips negative
600 kHz
Interlaced
470 ohms
Signal must be AC-coupled with a minimum series
capacitance of 0.1 µF
8.5 ELECTRICAL CHARACTERISTICS
8.5.1 Non-Standard Video Signals
Non-standard video signals must have the following characteristics:
TABLE 38. NON-STANDARD VIDEO SIGNALS
PS000400-TVC0499
Parameter
Conditions
Sync Amplitude
Vertical Pulse
Width
Vertical Pulse Tilt
200 mV minimum
3H ±0.5H
20 mV maximum
Z86230—PRELIMINARY
47
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
TABLE 38. NON-STANDARD VIDEO SIGNALS
Parameter
Conditions
H Timing
Phase Step (Head Switch) ±10 µs maximum
Fh Deviation (long term) ±0.5% maximum
Fh p-p Deviation (short term) ±0.3% maximum
The internal sync circuits lock to all 525- or 625-line
signals that exhibit a vertical sync pulse that meets the
following conditions:
Vertical Sync
Signal
1. It is at least 3H ±0.5H wide.
2. It starts at the proper 2H boundary for its field.
3. If equalizing pulse serrations are present, they
must be less than 0.125H in width.
Minimum Signal- The Z86230 functions down to a 25 dB signal-to-noise
to-Noise
ratio (CCIR-weighted) with one error per row or better
at that level.
Ratio to Composite Input
Video
8.5.2 HIN/XIN Signal Input
Table 39. HIN/XIN Signal Input
Mode
1. HIN
Input
2. XIN
Input
Parameter
Conditions
(Video Lock Mode)
Amplitude
CMOS level signal where Low ≤ 0.2 VCC
(HIN Lock Mode)
Polarity
Frequency
Amplitude
Any
15,734.263 Hz @ 3%
CMOS level signal where Low ≤ 0.2 VCC
Polarity
Frequency
Any
Same as Display Horizontal Flyback (HFB)
pulse
32.768 KHz
±20ppm @ TA = 25C, CL = 12.5pF
(XTAL)
(Clock)
Frequency
Frequency
tolerance
Amplitude
Frequency
48
CMOS level signal where Low ≤ 0.2 VCC
32.768 kHz ±2%
Z86230—PRELIMINARY
PS000400-TVC0499
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
8.5.3 Line 21 Input Parameters (at 1.0V p-p)
Line 21 must be in its proper position to the leading edge of the Vertical Sync signal.
TABLE 40. LINE 21 INPUT PARAMETERS
Parameter
Conditions
Code Amplitude
Code Zero Level
Start of Code
50 IRE*
5 IRE, +15 IRE relative to Back Porch
10.5 ±0.5 µs (measure from the midpoint of the leading
edge of the composite video Hsync pulse to the
midpoint of the rising edge of the first clock run-in
cycle.)
3.972 ms, –0.00 µs, +0.30 µs (measure from the
midpoint of the falling edge of the most recent clock
run-in cycle to the midpoint of the rising edge of the
start bit.)
Start of the Data
NOTE: *A relative unit of measure developed by the Institute of Radio Engineers (IRE).
One IRE equals 1/140th of the composite video signal's peak-to-peak voltage. IRE is
the former name of what is now known as the Institute of Electrical and Electronics
Engineers (IEEE).
PS000400-TVC0499
Z86230—PRELIMINARY
49
APPLICATION INFORMATION
9.
REFERENCE DESIGNS
APPLICATION INFORMATION
The recommended schematic, component placement, and PCB layout for a single-sided DIP design are provided in the following figures. I2C communication
and XTAL mode are chosen in the reference circuit design. EMI and noise in the
video frequency range is kept to an absolute minimum by running the ground
plane underneath the entire Z86230 package length. This design is recommended
for both SOIC and DIP package styles.
9.1 REFERENCE DESIGNS
FIGURE 8. Z86230 REFERENCE CIRCUIT
.
13
I2C Bus
XOUT 5
PB
14
SDA
15
SCLK
4
NRST
1
I2C SEL
17 INTRO
R3
C2
Y1 R2
XIN 3
H SEL 2
VDD 12
C1
+5V
+5V
L1
CA1
CB1
C6
C7
9
R5
C5 8
C3
7
R4
C4
LPF
CSYNC
VIDEO
RREF 10
VSS 6
VSS(A) 11
R1
Z86230
50
Z86230—PRELIMINARY
PS000400-TVC0499
APPLICATION INFORMATION
REFERENCE DESIGNS
TABLE 41. RECOMMENDED COMPONENT VALUES FOR Z86230 REFERENCE CIRCUIT
PS000400-TVC0499
Component
Value
Units
R1
R2
R3
R4
R5
C1
C2
C3
C4
C5
C6
C7
CA1
CB1
L1
Y1
U1
10
22
470
470
6.8
10
20
0.1
560
0.1
6800
0.068
0.1
0.1
bead
32.768
Z86230
KΩ
MΩ
KΩ
Ω
KΩ
pF
pF
µF
pF
µF
pF
µF
µF
µF
N/A
kHz
N/A
Z86230—PRELIMINARY
51
APPLICATION INFORMATION
REFERENCE DESIGNS
FIGURE 9. PCB DESIGN OF Z86230 REFERENCE CIRCUIT
INTRO
SCLK
SDA
NRST
I2C SEL
VDD(+5V)
VIDEO
VSS
C2
C1
Y1
R3
R2
L1
52
Z86230—PRELIMINARY
CB1
R1
U1
CA1
C5
C7
R5
C6
R4
C3
C4
PS000400-TVC0499
REFERENCE DESIGNS
PACKAGING
10. PACKAGING
FIGURE 10. 18-LEAD DIP PACKAGE DIAGRAM
FIGURE 11. 18-LEAD SOIC PACKAGE DIAGRAM
PS000400-TVC0499
Z86230—PRELIMINARY
53
ORDERING INFORMATION
PART NUMBER DESCRIPTION
11. ORDERING INFORMATION
Z86230 (12 MHz)
Standard Temperature
18-Pin DIP
Z8623012PSC
18-Pin SOIC
Z8623012SSC
For fast results, contact your local ZiLOG sale offices for assistance in ordering
the part(s) required.
11.1 PART NUMBER DESCRIPTION
The ZiLOG part numbers consist of a number of components.
EXAMPLE: Part number Z86230 12 P S C is a Z86230, 12-MHz DIP, 0ºC to +70ºC, Plastic
Standard Flow, and consists of the codes indicated in the following table.
Z
86230
12
P
S
C
54
ZiLOG prefix
Product Number
Speed (in MHz)
Package
Temperature
Environmental Flow
Z86230—PRELIMINARY
PS000400-TVC0499
PART NUMBER DESCRIPTION
PRECHARACTERIZATION PRODUCT
12. PRECHARACTERIZATION PRODUCT
The product represented by this document is newly introduced and ZiLOG has not
completed the full characterization of the product. The document states what
ZiLOG knows about this product at this time, but additional features or non-conformance with some aspects of the document may be found, either by ZiLOG or
its customers in the course of further application and characterization work. In
addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up
yield issues.
ZiLOG, Inc.
910 East Hamilton Avenue, Suite 110
Campbell, CA 95008
Telephone (408) 558-8500
FAX 408 558-8300
Internet: http://www.zilog.com
PS000400-TVC0499
Z86230—PRELIMINARY
55
CUSTOMER FEEDBACK FORM
PART NUMBER DESCRIPTION
CUSTOMER FEEDBACK FORM
Z86230 PRODUCT SPECIFICATION
If you experience any problems while operating this product, or if you note any
inaccuracies while reading this Product Specification, please copy and complete
this form, then mail or fax it to ZiLOG (see Return Information, below). We also
welcome your suggestions!
CUSTOMER INFORMATION
Name
Company
Address
City/State/Zip
Country
Phone
Fax
E-Mail
PRODUCT INFORMATION
Serial # or Board Fab #/Rev. #
Software Version
Document Number
Host Computer Description/Type
RETURN INFORMATION
ZiLOG
System Test/Customer Support
910 E. Hamilton Avenue, Suite 110, MS 4–3
Campbell, CA 95008
Fax: (408) 558-8536
Email: [email protected]
PROBLEM DESCRIPTION OR SUGGESTION
Provide a complete description of the problem or your suggestion. If you are
reporting a specific problem, include all steps leading up to the occurrence of the
problem. Attach additional pages as necessary.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
56
Z86230—PRELIMINARY
PS000400-TVC0499
INDEX
NUMERICS
Commands . . . . . . . . . . . . . . . . . . . . . . . . . 23
Communicating with the Z86230 . . . . . . . . 42
Comp Sync . . . . . . . . . . . . . . . . . . . . . . . . . 10
Composite Video . . . . . . . . . . . . . . . 9, 14, 49
input . . . . . . . . . . . . . . . . . . . . . . . 9, 10, 47
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Configuration Register . . . . . . . . . . . . . . . . 25
Script Files . . . . . . . . . . . . . . . . . . . . . . . 44
Content Advisory
packet . . . . . . . . . . . . . . . . . . . 9, 15, 32, 39
Rating registers . . . . . . . . . . . . . . . . . . . . 39
Rating Select Register . . . . . . 15, 28-31, 33
Registers . . . . . . . . . . . . . . . . . . . . . . 31-32
CONTINUE . . . . . . . . . . . . . . . . . . . . . . . . . 36
Control+C (^C) . . . . . . . . . . . . . . . . . . . 42, 44
Counting Circuits . . . . . . . . . . . . . . . . . . . . 10
C-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CSYNC . . . . . . . . . . . . . . . . . . . . . . . . . 10, 14
CURR . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 39
Current Class . . . . . . . . . . . . . . . . . . . . . . . . 36
packets . . . . . . . . . . . . . . . . . . . . . . . 26, 36
Program Rating data . . . . . . . . . . . . . . . . 37
Customer Feedback Form . . . . . . . . . . . . . . 56
Customer Information . . . . . . . . . . . . . . . . . 56
14+-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
18+-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
18-Lead DIP Package . . . . . . . . . . . . . . . . . 53
18-Lead SOIC Package . . . . . . . . . . . . . . . . 53
2-wire bus . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3-byte READ . . . . . . . . . . . . . . . . . . . . . . . . 36
A
Absolute Maximum Ratings . . . . . . . . . . . . 46
AC and Timing Characteristics . . . . . . . . . . 47
Acknowledge . . . . . . . . . . . . . . . 11, 18-19, 22
Application Information . . . . . . . . . . . . . . . 50
Architectural Overview . . . . . . . . . . . . . . . . . 9
ASCII characters . . . . . . . . . . . . . . . . . . . . . 44
Auto Clock Set . . . . . . . . . . . . . . . . . . . . . . . 9
B
base rating . . . . . . . . . . . . . . . . . . . . . . . 30, 40
Basic Serial Commands . . . . . . . . . . . . . . . 23
Block Diagram and Operational Overview . . 9
Block Timer . . . . . . . . . . . . . . . . . . . . . . . . 32
blocking 32, 39
Blocking Control Registers . . . . . . . . . . 32, 34
Blocking No Rating Programs . . . . . . . . . . 17
Bus Conditions . . . . . . . . . . . . . . . . . . . . . . 18
Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . 18
busy bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Byte pairs . . . . . . . . . . . . . . . . . . . . . . . . . . 44
C
C8+-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Call Letter . . . . . . . . . . . . . . . . . . . . 20, 27, 36
Canadian English Language
Content Advisory . . . . . . . . . . . . . . . . . . . 32
Canadian French Language
Content Advisory . . . . . . . . . . . . . . . . . . . 33
CHAN . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 39
Channel Information Class packets . . . . . . . 26
CHKSUM . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
class type 2 packet . . . . . . . . . . . . . . . . . . . . 20
class type 3 packet . . . . . . . . . . . . . . . . . . . . 20
Class/Type system . . . . . . . . . . . . . . . . . . . . 35
Clock and Data Transitions . . . . . . . . . . . . . 21
Command Processor . . . . . . . . . . . . . . . . . . 10
PS000400-TVC0499
D
D- and L-rated programs . . . . . . . . . . . . . . . 31
data available flag . . . . . . . . . . . . . . . . . . . . 36
data clock . . . . . . . . . . . . . . . . . . . . . . . . . . 10
recovery circuits . . . . . . . . . . . . . . . . . . . 10
Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Available Flag (DAV) . . . . . . . . . . 25, 39
DAV bit . . . . . . . . . . . . . . . . . . . .20-21, 35-36
DC Characteristics . . . . . . . . . . . . . . . . . . . 47
DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
phase lock . . . . . . . . . . . . . . . . . . . . . . . . 10
Decoder Control circuit block . . . . . . . . . . . 10
Demonstration Programs . . . . . . . . . . . . . . 42
DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13, 54
DIP package . . . . . . . . . . . . . . . . . . . . . . . . 50
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
DLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-28
dLOK . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-28
dXDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Z86230ÑPRELIMINARY
57
I2C master . . . . . . . . . . . . . . . . . . . . . . . 15, 21
I2C Operation . . . . . . . . . . . . . . . . . . . . . . . 42
I2C SEL . . . . . . . . . . . . . . . . . . . . . . 13, 16, 18
I2C serial
communication port . . . . . . . . . . . . . . 9, 17
control interface . . . . . . . . . . . . . . . . . . . 16
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I2C slave device . . . . . . . . . . . . . . . . . . . . . 42
I2C START condition . . . . . . . . . . . . . . . . . 19
I2C STOP condition . . . . . . . . . . . . . . . . . . 19
IICO Program . . . . . . . . . . . . . . . . . . . . . . . 42
Impulse Capture . . . . . . . . . . . . . . . . . . 27, 36
indirect addressing . . . . . . . . . . . . . . . . . . . 11
Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . 9
Internal Registers . . . . . . . . . . . . . . . . . 20, 39
Interrupt
Mask Register . . . . . . . . . . . . . . . . . . 15, 28
Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Request Register . . . . . . . . . . . . . . . . . . . 27
INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 39
INTRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
E
EIA–608 . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
EIA–608A . . . . . . . . . . . . . . . . . . . . . 9, 35, 37
EIA-744A . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics . . . . . . . . . . . . 46-47
Electronics Industry Association . . . . . . . . . . 9
EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
END . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
END packet . . . . . . . . . . . . . . . . . . . . . . . . . 37
EOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-28
E-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Extended Data Services . . . . . . . . . . . . . . 9, 35
F
Field 1 . . . . . . . . . . . . . . . . . . . . . . . 25, 27, 42
Field 2 . . . . . . . . . . . . . . . 9, 25, 27, 35, 36-37
field counter (FLD CNTR) . . . . . . . . . . . . . . 10
FLD . . . . . . . . . . . . . . . . . . . . . . . . . 25, 39, 42
fully programmable . . . . . . . . . . . . . . . . . 9, 17
FUTR . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 39
Future Class packets . . . . . . . . . . . . . . . . . . 26
L
G
Least Significant Bit (LSB) . . . . . . . . . . . . . 18
Line 21 . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 16
Activity Register . . . . . . . . . . . . . . . . . . . 27
field 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Input Parameters . . . . . . . . . . . . . . . . . . . 49
Program Rating information . . . . . . . . . . 36
line counter (LINE CNTR) . . . . . . . . . . . . . . 10
Local Time Zone . . . . . . . . . . . . . . . . . . 27, 36
LOCK . . . . . . . . . . . . . . . . . . . . . 25, 27, 39, 42
Loop Filter (LPF) . . . . . . . . . . . . . . . . . . 15, 47
LTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 36
General Commands . . . . . . . . . . . . . . . . . . . 43
G-rated . . . . . . . . . . . . . . . . . . . . . . . 28, 33-34
H
H Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
H SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
H signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hex values . . . . . . . . . . . . . . . . . . . . . . . . . . 44
HIN
Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Lock Mode . . . . . . . . . . . . . . . . . . . . . . . 48
mode . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
HIN/XIN . . . . . . . . . . . . . . . . . . . . . . . 9, 13-14
input signal . . . . . . . . . . . . . . . . . . . . . . . 10
Signal Input . . . . . . . . . . . . . . . . . . . . . . . 48
Horizontal (H) Lock circuit . . . . . . . . . . . . . 10
horizontal frequency signal . . . . . . . . . . . . . 14
horizontal timing signal . . . . . . . . . . . . . . 9-10
M
master device . . . . . . . . . . . 18-19, 21, 27, 36
MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 39
Miscellaneous Class
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
packets . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MPAA
Content Advisory . . . . . . . . . . . . . . . . . . 28
Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Ratings standards . . . . . . . . . . . . . . . . . . 28
I
I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
interface . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operation . . . . . . . . . . . . . . . . . . . . . . . . 18
I2C communication . . . . . . . . . . . . . . . . . . . 50
58
N
No Connect (NC) . . . . . . . . . . . . . . . . . . . . . 15
Z86230ÑPRELIMINARY
PS000400-TVC0499
READ . . . . . . . . . . . . . . . . . . 11, 13, 18-19, 25
and WRITE Commands . . . . . . . . . . . . . . 23
NC-17-rated . . . . . . . . . . . . . . . . . . . . . . . . . 28
Net ID . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 36
no operation (NOP) . . . . . . . . . . . . . . . . . . . 23
Non-Standard Video Signals . . . . . . . . . . . . 47
NOP command . . . . . . . . . . . . . . . . . . . 23, 42
Not Acknowledge (NACK) . . . . . . . 19, 21-22
Not Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Not Rated . . . . . . . . . . . . . . . . . . . . . . . 28, 39
NRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
NTSC . . . . . . . . . . . . . . . . . . . 9, 14, 16-17, 26
NTSC Line 21 . . . . . . . . . . . . . . . . . . 9, 16, 26
Bank 0 mode . . . . . . . . . . . . . . . . . . . . . . 36
Bank Select . . . . . . . . . . . . . . . . . . . . 20, 23
SELECT . . . . . . . . . . . . . . . . . . . . 20, 23, 35
sequence . . . . . . . . . . 11, 20-21, 23-24, 38
Reading Data Using the I2C Bus . . . . . . . . 20
Reference Designs . . . . . . . . . . . . . . . . . . . 50
Registers Summary . . . . . . . . . . . . . . . . . . . 25
RESET . . . . . . . . . . . 13, 17, 23, 25, 38, 42-43
RESET state . . . . . . . . . . . . . . . . . . . . . . . . . 26
Resistor Reference . . . . . . . . . . . . . . . . . . . 15
Return Information . . . . . . . . . . . . . . . . . . . 56
ROVR . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 39
R-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
RREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
O
Ordering Information . . . . . . . . . . . . . . . . . 54
Out-of-Band Channel Number packets . 27, 36
P
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PAL . . . . . . . . . . . . . . . . . . . . 9, 16-17, 26, 44
Part Number Description . . . . . . . . . . . . . . . 54
PB . . . . . . . . . . . . . . . . . . . . . . . . 9, 15-16, 32
PG-13-rated . . . . . . . . . . . . . . . . . . . . . . . . . 28
PG-rated . . . . . . . . . . . . . . . . . . . . . . . . 28, 33
Picture-In-Picture (PiP) . . . . . . . . . . . . . . . . . 9
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . 13
Power Supply . . . . . . . . . . . . . . . . . . . . . . . 15
Precharacterization . . . . . . . . . . . . . . . . . . . 55
Problem Description . . . . . . . . . . . . . . . . . . 56
Product Information . . . . . . . . . . . . . . . . . . 56
Program Blocking . . . . . . . . . . . . . . . . . 15-17
Data Packet Recovery . . . . . . . . . . . . . . . 36
Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
registers . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Program Rating information . . . . . . . . . 36-37
Program Rating XDS filter . . . . . . . . . . . . . 37
Program Unblock Hold Off . . . . . . . . . . . . . 17
program-blocking response . . . . . . . . . . . . . 39
PUBL . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 39
Public Service Class . . . . . . . . . . . . . . . . . . 26
R
RBS . . . . . . . . . . . . . . . . . . . . . .20, 23, 36, 38
RDS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 20, 38
RDS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 20, 38
RDY . . . . . . . . . . . . . . . . . .20, 23, 25, 38, 39
bit . . . . . . . . . . . . . . . . . . 19, 23, 38, 42-43
status . . . . . . . . . . . . . . . . . . . . . . 23, 38, 43
PS000400-TVC0499
S
S- and V-rated programs . . . . . . . . . . . . . . . 30
SCLK . . . . . . . . . . . . . . . 15-16, 18-19, 21-22
Script Files . . . . . . . . . . . . . . . . . . . . . . 43-45
SCRIPTI . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SDA . . . . . . . . . . . . . . . . . . . . . . 15, 19, 21-22
SDA line . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
serial clock . . . . . . . . . . . . . . . . . . . . . . 15, 18
Serial Communications Interface . . . . . 18, 42
Serial Control
port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
process . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Serial Data . . . . . . . . . . . . . . . . . . . . . . . . . . 15
serial port . . . . . . . . . . . . . . . . . 16, 23, 38, 42
Serial Status Register
(SSR) . . . . 19, 21, 23, 25, 27, 35, 38, 42-43
DAV bit . . . . . . . . . . . . . . . . . . . . . . . . . 21
single-sided DIP design . . . . . . . . . . . . . . . 50
slave address . . . . . . . . . .9, 11, 13, 16, 18, 44
READ . . . . . . . . . . . . . . . . . . . . . . . . 18-19
WRITE . . . . . . . . . . . . . . . . . . . . . . . . 18-19
slave device . . . . . . . . . . . . . . . . . . . . . . . . . 18
slice level . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . 13, 54
SOIC package . . . . . . . . . . . . . . . . . . . . . . . 50
SSB . . . . . . . . . . . . . . . . . . . . . . . . . 21, 36, 43
Standard Test Conditions . . . . . . . . . . . . . . 46
START . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
condition . . . . . . . . . . . . . . . . . . . 18-19, 21
packet . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Z86230ÑPRELIMINARY
59
Video
Input Signal Processing . . . . . . . . . . . . . 10
Lock Mode . . . . . . . . . . . . . . . . . . . . 42, 48
Standard . . . . . . . . . . . . . . . . . . . . . . . . . 17
violence blocking . . . . . . . . . . . . . . . . . . . . . 9
Voltage/Current Reference . . . . . . . . . . . . . 11
Voltage-Controlled Oscillator (VCO) . . . . . 10
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VSS(A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Status register
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RDY bit . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STOP condition . . . . . . . . . . . . . . . . 18, 21-22
Sync slice level . . . . . . . . . . . . . . . . . . . . . . 14
Sync Slicer . . . . . . . . . . . . . . . . . . . . . . . . . 10
T
Tape Delay . . . . . . . . . . . . . . . . . . . . . . 27, 36
Television Decoder Circuits Act of 1990 . . . 9
television VBI . . . . . . . . . . . . . . . . . . . . . . . . 9
The I2C Bus Protocol . . . . . . . . . . . . . . . . . 18
Time of Day (TOD) . . . . . . . . . . . . . . . . 27, 36
Timing and Counting Circuits . . . . . . . . . . . 10
Timing Characteristics . . . . . . . . . . . . . . . . 47
TV Parental Guidelines . . . . . . . . . . . . . . . . 29
Rating matrix . . . . . . . . . . . . . . . . . . . . . 39
Ratings standards . . . . . . . . . . . . . . . 29-30
TV-14-L-rated . . . . . . . . . . . . . . . . . . . . . . . 31
TV-14-rated . . . . . . . . . . . . . . . . . . . . . . . . . 29
TV-14-S-rated . . . . . . . . . . . . . . . . . . . . . . . 30
TV-14-V-rated . . . . . . . . . . . . . . . . . . . . . . . 30
TV-G-rated . . . . . . . . . . . . . . . . . . . . . . . . . 29
TV-MA-L-rated . . . . . . . . . . . . . . . . . . . . . . 31
TV-MA-rated . . . . . . . . . . . . . . . . . . . . . . . 29
TV-MA-S-rated . . . . . . . . . . . . . . . . . . . . . . 30
TV-MA-V-rated . . . . . . . . . . . . . . . . . . . . . 30
TV-NONE-rated . . . . . . . . . . . . . . . . . . . . . 29
TV-PG-D-rated . . . . . . . . . . . . . . . . . . . . . . 31
TV-PG-L-rated . . . . . . . . . . . . . . . . . . . . . . 31
TV-PG-rated . . . . . . . . . . . . . . . . . . . . . . . . 29
TV-PG-S-rated . . . . . . . . . . . . . . . . . . . . . . 30
TV-PG-V-rated . . . . . . . . . . . . . . . . . . . . . . 30
TVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TV-Y7-FV-rated . . . . . . . . . . . . . . . . . . . . . 30
TV-Y7-rated . . . . . . . . . . . . . . . . . . . . . . . . 29
TV-Y-rated . . . . . . . . . . . . . . . . . . . . . . . . . 29
V
VBI Data Processing . . . . . . . . . . . . . . . . . . 16
VBI line . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
V-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VCO Gain . . . . . . . . . . . . . . . . . . . . . . . . . . 47
VCO Lock . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Vertical Blanking Interval (VBI) . . . . . . . . . . 9
VIDEO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
60
W
WOVR . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 39
WRITE . . . . . . . . 11, 13, 18-20, 23-24, 35, 38
addressing . . . . . . . . . . . . . . . . . . . . . . . . 11
sequence . . . . . . . . . . . . . . . . . . . . . . 11, 20
Writing to the I2C Bus . . . . . . . . . . . . . . . . 19
Writing to the Z86230 . . . . . . . . . . . . . . . . . 24
WRxx . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 38
X
XDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 35
activity . . . . . . . . . . . . . . . . . . . . . . . . . . 27
class and type . . . . . . . . . . . . . . . . . . . . . 36
Content Advisory packet . . . . . . . . . . . . . 9
data . . . . . . . . . . . . . . . 9-10, 16, 26-27, 36
Data Activity . . . . . . . . . . . . . . . . . . . . . 39
Data Activity Register . . . . . . . . . . . . . . 26
Data Output . . . . . . . . . . . . . . . . . . . . . . 17
data packets . . . . . . . . . . . . . . . . . . . . 9, 36
data recovery . . . . . . . . . . . .24, 27, 35, 44
data stream . . . . . . . . . . . . . . . . . . . . . . . 36
decoding . . . . . . . . . . . . . . . . . . . . . . . . . 35
Filter . . . . . . . . . . . . . . . . . . . . 9, 36-37, 39
Filter command . . . . . . . . . . . . . . . . . . . . 44
Filter Register . . . . . . . . . . . . . . . 24, 35-37
Filter Register Script Files . . . . . . . . . . . 45
filtering . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Network Name and Call Letter data . . . . 20
packets . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Program Name data . . . . . . . . . . . . . . . . 20
recovery . . . . . . . . . . . . . . . . . . . . . . . . . 26
XDSCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
XDSCAP Program . . . . . . . . . . . . . . . . . . . 44
XIN Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
XOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
X-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Z86230ÑPRELIMINARY
PS000400-TVC0499
XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 48
circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
mode . . . . . . . . . . . . . . . . . . . . . . . . . 14, 50
Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PS000400-TVC0499
Z
Z86230 Feature Set . . . . . . . . . . . . . . . . . . . 16
Z86230 output registers . . . . . . . . . . . . . . . 21
Z86230 Reference Circuit . . . . . . . . . . . 50-52
Z86230 register address . . . . . . . . . . . . 24, 38
Z86230 WRITE commands . . . . . . . . . . . . 35
Z86230ÑPRELIMINARY
61