ZILOG Z86C17

Z86217/C17
CP95KEY1000
P R E L I M I N A R Y
PRELIMINARY
CUSTOMER PROCUREMENT SPECIFICATION
Z86217/C17
CMOS Z8® 8-BIT MICROCONTROLLERS
(POINTING DEVICE/TRACKBALL)
FEATURES
■
Permanent Watch-Dog Timer (WDT)
■
Oscillator Filter
■
Two Programmable 8-Bit Counter/Timers
* General-Purpose
■
Low-EMI Operation
■
18-Pin DIP and SOIC Packages
■
Scalable Trip-Point Buffer
■
3.0- to 5.5-Volt Operating Range
■
On-Board Pull-Up Resistors
■
0°C to 70°C Operating Temperature Range
■
High Drive Ports Can Sink 20 mA Per Pin, with Three
Pins Maximum
Part
Number
ROM
(Kbytes)
RAM*
(Bytes)
I/O
Lines
Speed
(MHz)
Z86217
Z86C17
2
2
124
124
14
14
4
4
GENERAL DESCRIPTION
The Z86217/C17 are members of Zilog's Z8® family of
microcontrollers designed to reduce external system components and offer easy software/hardware development
tools for pointing device and trackball applications.
The devices feature on-board pull-up resistors, and a
scalable trip-point buffer to accommodate opto-transistor
outputs. The high drive ports are capable of up to 20 mA
(at VOL = 0.8-volt) current sinking per pin, with three pins
maximum, providing extra sinking current capability.
The Z86217/C17's permanently enabled Watch-Dog Timer
(WDT) operates upon power-up of the MCU, and provides
added operational reliability for pointing device and
trackball environments.
An oscillator filter assists in separating out high-frequency
noise from the oscillator input pin.
CP95KEY1000 8/95
Two on-chip counter/timers with a large number of
selectable modes, offload the system of administering
real-time tasks such as counting/timing and I/O data
communications.
Notes:
Refer to the DC electrical characteristics for detailed specification of the
sinking current.
On the Z86C17, P24-P27 has a 20K pull-up, and P32 has a 47K pulldown. The Z86217 does not have these functions.
All Signals with a preceding front slash, "/", are active Low, e.g.; B//W
(WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
1
Z86217/C17
CP95KEY1000
P R E L I M I N A R Y
BLOCK DIAGRAM
Input
VDD
XTAL
VSS
Machine
Timing & Inst.
Control
Port 3
ALU
Counter/
Timers (2)
Prg. Memory
2048 x 8-Bit
FLAG
Register
Pointer
Interrupt
Control
Program
Counter
Register File
144 x 8-Bit
Port 2
Port 0
I/O
(Bit Programmable)
I/O
Functional Block Diagram
PIN DESCRIPTIONS
P24
1
18
P23
P24
1
18
P23
P25
2
17
P22
P25
2
17
P22
P26
3
16
P21
P26
3
16
P21
P27
4
15
P20
P27
4
15
P20
VDD
5
14
VSS
VDD
5
14
VSS
XTAL2
6
13
P02
XTAL2
6
13
P02
7
12
P01
XTAL1
7
12
XTAL1
P01
11
P00
8
11
P00
P31
8
P31
P32
9
10
P33
P32
9
10
P33
18-Pin DIP Configuration
2
18-Pin SOIC Configuration
Z86217/C17
CP95KEY1000
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Sym
Parameter
Min
Max
Units
VDD
TSTG
TA
Supply Voltage (*)
Storage Temp
Oper Ambient Temp
–0.3
–65°
†
+7
+150°
†
V
C
C
Notes:
* Voltages on all pins with respect to GND
† See Ordering Information
Stress greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Test Load).
From Output
Under Test
I
150 pF
Test Load Diagram
CAPACITANCE
TA = GND = 0V, f = 1.0 MHz, unmeasured pins to GND
Parameter
Max
Input capacitance
Output capacitance
I/O capacitance
10 pF
20 pF
25 pF
Vdd SPECIFICATION
Vdd = 3.0V to 5.5V
3
Z86217/C17
CP95KEY1000
P R E L I M I N A R Y
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
Max Input Voltage
VCH
VCL
VIH
Clock Input High
Voltage
Clock Input Low
Voltage
VOH
Input High Voltage
Schmitt-Triggered
Input High Voltage
CMOS Input
Input Low Voltage
Schmitt-Triggered
Input Low Voltage
CMOS Input
Output High Voltge
VOL1
Output Low Voltage
VOL2
Output Low Voltage
VIH
VIL
VIL
VDD
TA = 0°C to +70°C
Min
Max
VTP
IIL
IOL
VCC Low Voltage
Protection Voltage
Trip Point
Voltage
Input Leakage
Output Leakage
2.0
V
V
V
0.7 VDD
12
12
VDD + 0.3
5.5V
0.7 VDD
VDD + 0.3
3.0
V
3.0V
VSS – 0.3
0.2 VDD
0.8
V
5.5V
VSS – 0.3
0.2 VDD
1.5
V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
0.7 VDD
0.7 VDD
0.7 VDD
0.7 VDD
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
VDD – 0.4
VDD – 0.4
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
0.2 VDD
0.2 VDD
0.2 VDD
0.2 VDD
0.4
0.4
1.5
1.6
2.6
1.4
2.6
1.4
2.6
1.3
2.4
2.8
5.5
0.13
0.07
0.8
V
V
V
V
V
V
V
V
V
V
V
V
V
0.8
0.3
V
2.7
2.3
V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
0.4 VDD
–1.0
–1.0
–1.0
–1.0
Note:
For 2.75V operating, the device operates down to VLV. The minimum
operational VDD is determined on the value of the voltage VLV at the
ambient temperature. The VLV increases as the temperature decreases.
4
Units
3.0V
5.5V
3.0V
5.5V
VLV
Typical
@ 25°C
1.0
1.0
1.0
1.0
Conditions
VIN = 250 µA
VIN = 250 µA
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
IOH = –2.0 mA
IOH = –2.0 mA
IOL = +4.0 mA
IOL = +4.0 mA
IOL = 20.0 mA,
3 Pin Max
IOL = 20.0 mA,
3 Pin Max
@ 2 MHz Max
V
0.4
0.4
µA
µA
µA
µA
VIN = OV, VCC
VIN = OV, VCC
VIN = OV, VCC
VIN = OV, VCC
Z86217/C17
CP95KEY1000
P R E L I M I N A R Y
Units
Conditions
1.5
0.41
mA
5.5V
3.0
1.44
mA
3.0V
2.0
0.93
mA
5.5V
4.0
2.60
mA
3.0V
3.0
1.64
mA
5.5V
6.0
4.28
mA
All Output and I/OPins
Floating @ 1 MHz
All Output and I/O Pins
Floating @ 1 MHz
All Output and I/O Pins
Floating @ 2 MHz
All Output and I/O Pins
Floating @ 2 MHz
All Output and I/O Pins
Floating @ 4 MHz
All Output and I/O Pins
Floating @ 4 MHz
3.0V
0.6
0.15
mA
5.5V
1.3
0.70
mA
3.0V
0.8
0.20
mA
5.5V
1.5
0.80
mA
3.0V
1.0
0.3
mA
5.5V
2.0
1.0
mA
3.0V
200
120
µA
5.5V
200
120
µA
Port P00-P03
Port P31, P33
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
–35
–100
–100
–400
–35
–100
–13
–57
–58
–270
–13
–56
µA
µA
µA
µA
µA
µA
Pull-Down Current
Port P32* (47K)
3.0V
5.5V
80
250
40
160
µA
µA
Parameter
VDD
IDD
Supply Current
3.0V
IDD1
IDD2
IPU
Standby Current
Standby Current
Pull-Up Current
Port P20-P23 (100K)
Port P24-P27* (20K)
IPD
TA = 0°C to +70°C
Min
Max
Typical
@ 25°C
Sym
HALT Mode VIN = 0V,
VCC @ 1 MHz
HALT Mode VIN = 0V,
VCC @ 1 MHz
HALT Mode VIN = 0V,
VCC @ 2 MHz
HALT Mode VIN = 0V,
VCC @ 2 MHz
HALT Mode VIN = 0V,
VCC @ 4 MHz
HALT Mode VIN = 0V,
VCC @ 4 MHz
STOP Mode VIN = 0V,
VCC WDT is Running
STOP Mode VIN = 0V,
VCC WDT is Running
Note:
*Available on the Z86C17 only.
5
Z86217/C17
CP95KEY1000
P R E L I M I N A R Y
AC ELECTRICAL CHARACTERISTICS
No Symbol
Parameter
VDD
TA = 0°C to +70°C
1 MHz
4 MHz
Min
Max
Min
Max
1
TpC
Input Clock Period
3.0V
5.5V
1,000
1,000
2
TrC,TfC
Clock Input Rise
and Fall Times
3.0V
5.5V
3
TwC
Input Clock Width
4
TwTinL
5
Units
Notes
100,000
100,000
ns
ns
[1]
[1]
25
25
25
25
ns
ns
[1]
3.0V
5.5V
475
475
100
100
ns
ns
[1]
[1]
Timer Input Low Width
3.0V
5.5V
100
70
100
70
ns
ns
[1]
[1]
TwTinH
Timer Input High Width
3.0V
5.5V
2.5TpC
2.5TpC
2.5TpC
2.5TpC
[1]
[1]
6
TpTin
Timer Input Period
3.0V
5.5V
4TpC
4TpC
4TpC
4TpC
[1]
[1]
7
TrTin,
TtTin
Timer Input Rise
and Fall Timer
3.0V
5.5V
8
TwIL
Int. Request Input
Low Time
3.0V
5.5V
100
70
100
70
9
TwIH
Int. Request Input
High Time
3.0V
5.5V
2.5TpC
2.5TpC
2.5TpC
2.5TpC
10 Twdt
Watch-Dog Timer
Time Out Timer
3.0V
5.5V
25
10
25
10
ms
ms
[1]
[1]
11 TPOR
Power-On Reset
Time
3.0V
5.5V
6
2
6
2
ms
ms
[1]
[1]
Notes:
[1] Timing Reference uses 0.9 VDD for a logic 1 and 0.1 VDD for a logic 0.
[2] Interrupt request through Port 3 (P33-P31)
6
100,000
100,000
250
250
100
100
100
100
ns
ns
[1]
[1]
ns
ns
[1,2]
[1,2]
[1]
[1,2]
Z86217/C17
CP95KEY1000
P R E L I M I N A R Y
TIMING DIAGRAM
3
1
Clock
2
7
2
3
7
T
IN
4
5
6
IRQ
N
8
9
Electrical Timing Diagram
Low Margin:
Customer is advised that this product does not meet
Zilog’s internal guardbanded test policies for the specification requested and is supplied on an exception basis.
Customer is cautioned that delivery may be uncertain and
that, in addition to all other limitations on Zilog liability
Pre-Characterization Product:
The product represented by this CPS is newly introduced
and Zilog has not completed the full characterization of the
product. The CPS states what Zilog knows about this
product at this time, but additional features or non-con-
© 1995 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
stated on the front and back of the acknowledgement,
Zilog makes no claim as to quality and reliability under the
CPS. The product remains subject to standard warranty for
replacement due to defects in materials and workmanship.
formance with some aspects of the CPS may be found,
either by Zilog or its customers in the course of further
application and characterization work. In addition, Zilog
cautions that delivery may be uncertain at times, due to
start-up yield issues.
Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
7