Z86C21 MCU WITH 8K ROM P RODUCT S PECIFICA TION Z86C21 8K ROM Z8® CMOS MICROCONTROLLER FEATURES ■ 8-Bit CMOS MCU with 8 Kbytes of ROM ■ Full-Duplex UART ■ 256 Byte Register File - 236 Bytes of General-Purpose RAM - 16 Bytes Control/Status Registers - 4 Bytes for Ports ■ All Digital Inputs are TTL Levels ■ Auto Latches ■ RAM and ROM Protect ■ Two Programmable 8-Bit Counter/Timers each with 6-Bit Programmable Prescaler. ■ Six Vectored, Priority Interrupts from Eight Different Sources ■ Clock Speeds: 12 and 16 MHz ■ On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, or External Clock Drive. ■ 40-Pin DIP, 44-Pin PLCC or 44-Pin QFP Package ■ 4.5V to 5.5V Operating Range ■ Low Power Consumption: 220 mW (max) @ 16 MHz ■ Fast instruction pointer: 1.0 µs @ 12 MHz ■ Two Standby Modes: STOP and HALT ■ 32 Input/Output Lines GENERAL DESCRIPTION The Z86C21 microcontroller is a member of the Z8 singlechip microcontroller family with 8 Kbytes of ROM and 236 bytes of RAM. The device is packaged in a 40-pin DIP, 44-pin PLCC, or a 44-pin QFP with a ROMless pin option available on the 44-pin versions only. With the ROM/ ROMless feature selectively, the Z86C21 offers both external memory and preprogrammed ROM, making it wellsuited for high-volume applications or where code flexibility is required. Zilog’s CMOS microcontroller offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The Z86C21 architecture is characterized by Zilog’s 8-bit microcontroller core. The device offers a flexible I/O scheme, an efficient register and address space structure, multiplexed capabilities between address/data, I/O, and a number of ancillary features that are useful in many industrial and advanced scientific applications. For applications demanding powerful I/O capabilities, the Z86C21 provides 32 pins dedicated to input and output. These lines are grouped into four ports. Each port consists of eight lines, and is configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory. There are three basic address spaces available to support this configuration: Program Memory, Data Memory, and 236 general-purpose registers. 1 Z86C21 MCU WITH 8K ROM GENERAL DESCRIPTION (Continued) To unburden the program from coping with the real-time tasks, such as counting/timing and serial data communication, the Z86C21 offers two on-chip counter/timers with a large number of user selectable modes, and an on-board UART. Vcc Output Input Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS XTAL /AS /DS R//W /RESET GND Machine Timing and Instruction Control Port 3 UART ALU Counter/ Timers (2) FLAGS Prg. Memory 8192 x 8-Bit Register Pointer Interrupt Control Program Counter Register File 256 x 8-Bit Port 2 Port 0 4 I/O (Bit Programmable) Port 1 4 Address or I/O (Nibble Programmable) 8 Address/Data or I/O (Byte Programmable) Figure 1. Z86C21 Functional Block Diagram \2 Z86C21 MCU WITH 8K ROM PIN DESCRIPTION VCC 1 40 P36 XTAL2 2 39 P31 XTAL1 3 38 P27 P37 4 37 P26 P30 5 36 P25 /RESET 6 35 P24 R//W 7 34 P23 /DS 8 33 P22 /AS 9 32 P21 P35 Z86C21 10 DIP 31 P20 GND 11 30 P33 P32 12 29 P34 P00 13 28 P17 P01 14 27 P16 P02 15 26 P15 P03 16 25 P14 P04 17 24 P13 P05 18 23 P12 P06 19 22 P11 P07 20 21 P10 Figure 2. 40-Pin DIP Pin Assignments Table 1. 40-Pin DIP Pin Identification Pin # Symbol Function Direction Pin # Symbol Function 1 2 3 4 5 V CC XTAL2 XTAL1 P37 P30 6 7 8 9 10 /RESET R//W /DS /AS P35 Direction Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Input Output Input Output Input 11 12 13-20 21-28 29 GND P32 P00-P07 P10-P17 P34 Ground Port 3, Pin 2 Port 0, Pins 0,1,2,3,4,5,6,7 Port 1, Pins 0,1,2,3,4,5,6,7 Port 3, Pin 4 Input Input In/Output In/Output Output Reset Read/Write Data Strobe Address Strobe Port 3, Pin 5 Input Output Output Output Output 30 31-38 39 40 P33 P20-P27 P31 P36 Port 3, Pin 3 Port 2, Pins 0,1,2,3,4,5,6,7 Port 3, Pin 1 Port 3, Pin 6 Input In/Output Input Output 3 Z86C21 MCU WITH 8K ROM P25 P26 P27 2 P31 3 P36 4 VCC XTAL2 5 P37 P30 6 XTAL1 N/C PIN DESCRIPTION (Continued) 1 44 43 42 41 40 /RESET 7 39 N/C R//W 8 38 P24 /DS 9 37 P23 /AS 10 36 P22 P35 11 35 P21 34 P20 Z86C21 PLCC GND 12 P32 13 33 P33 P00 14 32 P34 P01 15 31 P17 P02 16 30 P16 R//RL 17 29 P15 N/C P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 18 19 20 21 22 23 24 25 26 27 28 Figure 3. 44-Pin PLCC Pin Assignments Table 2. 44-Pin PLCC Pin Identification Pin # Symbol Function 1 2 3 4 VCC XTAL2 XTAL1 P37 5 6 7 8 9 10 11 12 13 \4 Direction Pin # Symbol Function Direction Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Input Output Input Output 14-16 17 18-22 23-27 P00-P02 R//RL P03-P07 P10-P14 Port 0, Pins 0,1,2 ROM/ROMless control Port 0, Pins 3,4,5,6,7 Port 1, Pins 0,1,2,3,4 In/Output Input In/Output In/Output P30 N/C /RESET R//W Port 3, Pin 0 Not Connected Reset Read/Write Input Input Input Output 28 29-31 32 33 N/C P15-P17 P34 P33 Not Connected Port 1, Pins 5,6,7 Port 3, Pin 4 Port 3, Pin 3 Input In/Output Output Input /DS /AS P35 GND P32 Data Strobe Address Strobe Port 3, Pin 5 Ground Port 3, Pin 2 Output Output Output Input Input 34-38 39 40-42 43 44 P20-P24 N/C P25-P27 P31 P36 Port 2, Pins 0,1,2,3,4 Not Connected Port 2, Pins 5,6,7 Port 3, Pin 1 Port 3, Pin 6 In/Output Input In/Output Input Output Z86C21 MCU P25 P26 P27 P31 P36 GND VCC XTAL2 XTAL1 P37 P30 WITH 8K ROM 33 32 31 30 29 28 27 26 25 24 23 /RESET 34 22 GND R//W 35 21 P24 /DS 36 20 P23 /AS 37 19 P22 P35 38 18 P21 GND 39 17 P20 P32 40 16 P33 P00 41 15 P34 P01 42 14 P17 P02 43 13 P16 R//RL 44 12 P15 P06 P07 GND 7 8 9 10 11 P14 6 P13 5 P12 4 P11 3 P10 2 P05 P03 1 P04 Z86C21 QFP Figure 4. 44-Pin QFP Pin Assignments Table 3. 44-Pin QFP Pin Identification Pin # Symbol Function 1-5 6 7-14 15 P03-P07 GND P10-P17 P34 Port 0, Pins 3,4,5,6,7 Ground Port 1, Pins 0 through 7 Port 3, Pin 4 16 17-21 22 23-25 P33 P20-P24 GND P25-P27 26 27 28 29 30 P31 P36 GND VCC XTAL2 Direction Pin # Symbol Function Direction In/Output Input In/Output Output 31 32 33 34 XTAL1 P37 P30 /RESET Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Reset Input Output Input Input Port 3, Pin 3 Port 2, Pins 0,1,2,3,4 Ground Port 2, Pins 5,6,7 Input In/Output Input In/Output 35 36 37 38 R//W /DS /AS P35 Read/Write Data Strobe Address Strobe Port 3, Pin 5 Output Output Output Output Port 3, Pin 1 Port 3, Pin 6 Ground Power Supply Crystal, Oscillator Clock Input Output Input Input Output 39 40 41-43 44 GND P32 P00-P02 R//RL Ground Port 3, Pin 2 Port 0, Pins 0,1,2 ROM/ROMless control Input Input In/Output Input 5 Z86C21 MCU WITH 8K ROM PIN FUNCTIONS /ROMless (input, active Low). This pin, when connected to GND, disables the internal ROM and forces the device to function as a Z86C91 ROMless Z8. For more details on the ROMless version, refer to the Z86C91 product specification. (Note: When left unconnected or pulled high to VCC, the part functions as a normal Z86C21 ROM version). This pin is only available on the 44-pin versions of the Z86C21. /DS (output, active Low). Data Strobe is activated once for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of /DS. For WRITE operations, the falling edge of /DS indicates that output data is valid. /AS (output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle. Address output is through Port 1 for all external programs. Memory address transfers are valid at the trailing edge of /AS. Under program control, /AS is placed in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/ Write. XTAL1, XTAL2 Crystal 1, Crystal 2 (time-based input and output, respectively). These pins connect a parallel-resonant crystal, ceramic resonator, LC, or any external singlephase clock to the on-chip oscillator and buffer. R//W (output, write Low). The Read/Write signal is Low when the MCU is writing to the external program or data memory. /RESET (input, active Low). To avoid asynchronous and noisy reset problems, the Z86C21 is equipped with a reset filter of four external clocks (4TpC). If the external /RESET signal is less than 4TpC in duration, no reset occurs. \6 On the fifth clock after the /RESET is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external /RESET, whichever is longer. During the reset cycle, /DS is held active Low while /AS cycles at a rate of TpC2. When /RESET is deactivated, program execution begins at location 000C (HEX). Power-up reset time must be held Low for 50 ms, or until VCC is stable, whichever is longer. Port 0 (P07-P00). Port 0 is an 8-bit, nibble programmable, bidirectional, TTL compatible port. These eight I/O lines can be configured under software control as a nibble I/O port, or as an address port for interfacing external memory. When used as an I/O port, Port 0 may be placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control /DAV0 and RDY0 (Data Available and Ready). Handshake signal assignment is dictated by the I/O direction of the upper nibble P07-P04. The lower nibble must have the same direction as the upper nibble to be under handshake control. For external memory references, Port 0 can provide address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 is programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 Mode register. In ROMless mode, after a hardware reset, Port 0 lines are defined as address lines A15-A8, and extended timing is set to accommodate slow memory access. The initialization routine includes reconfiguration to eliminate this extended timing mode (Figure 5). Z86C21 MCU WITH 8K ROM 4 Port 0 (I/O) Z86C21 MCU 4 Handshake Controls /DAV0 and RDY0 (P32 and P35) OEN PAD Out TTL Level Shifter In Auto Latch R ≈ 500 KΩ Figure 5. Port 0 Configuration 7 Z86C21 MCU WITH 8K ROM PIN FUNCTIONS (Continued) Port 1 (P17-P10). Port 1 is an 8-bit, byte programmable, bidirectional, TTL compatible port. It has multiplexed Address (A7-A0) and Data (D7-D0) ports. For Z86C21, these eight I/O lines can be programmed as Input or Output lines or can be configured under software control as an address/data port for interfacing external memory. When used as an I/O port, Port 1 can be placed under handshake control. In this configuration, Port 3 line P33 and P34 are used as the handshake controls RDY1 and /DAV1. for the multiplexed Address/Data mode. If more than 256 external locations are required, Port 0 must output the additional lines. Port 1 can be placed in a high-impedance state along with Port 0, /AS, /DS and R//W, allowing the MCU to share common resource in multiprocessor and DMA applications. Data transfers are controlled by assigning P33 as a Bus Acknowledge input, and P34 as a Bus request output (Figure 6). Memory locations greater than 8192 are referenced through Port 1. To interface external memory, Port 1 is programmed 8 Port 1 (AD7-AD0) Z86C21 MCU Handshake Controls /DAV1 and RDY1 (P33 and P34) OEN PAD Out TTL Level Shifter In Auto Latch R ≈ 500 KΩ Figure 6. Port 1 Configuration \8 Z86C21 MCU WITH 8K ROM Port 2 (P27-P20). Port 2 is an 8-bit, bit programmable, bidirectional, CMOS compatible port. Each of these eight I/O lines can be independently programmed as an input or output or globally as an open-drain output. Port 2 is always available for I/O operation. When used as an I/O port, Port 2 may be placed under handshake control. In this configuration, Port 3 lines P31 and P36 are used as the handshake control lines /DAV2 and RDY2. The handshake signal assignment for Port 3 lines P31 and P36 is dictated by the direction (input or output) assigned to P27 (Figure 7). Port 2 (I/O) Z86C21 MCU Handshake Controls /DAV2 and RDY2 (P31 and P36) Open-Drain OEN PAD Out TTL Level Shifter In Auto Latch R ≈ 500 KΩ Figure 7. Port 2 Configuration 9 Z86C21 MCU WITH 8K ROM PIN FUNCTIONS (Continued) Port 3 (P37-P30). Port 3 is an 8-bit, CMOS compatible fourfixed-input and four-fixed-output port. These eight I/O lines have four-fixed input (P33-P30) and four fixed output (P37-P34) ports. Port 3, when used as serial I/O, is programmed as serial in and serial out, respectively (Figure 8 and Table 4) Port 3 pins have Auto Latches only. Port 3 is configured under software control to provide the following control functions: handshake for Ports 0 and 2 (/DAV and RDY); four external interrupt request signals (IRQ3-IRQ0); timer input and output signals (TIN and TOUT), and Data Memory Select (/DM). UART Operation. Port 3 lines P30 and P37, are be programmed as serial I/O lines for full-duplex serial asynchro- nous receiver/transmitter operation. The bit rate is controlled by the Counter/Timer0. The Z86C21 automatically adds a start bit and two stop bits to transmitted data (Figure 9). Odd parity is also available as an option. Eight data bits are always transmitted, regardless of parity selection. If parity is enabled, the eighth bit is the odd parity bit. An interrupt request (IRQ4) is generated on all transmitted characters. Received data must have a start bit, eight data bits and at least one stop bit. If parity is on, bit 7 of the received data is replaced by a parity error flag. Received characters generate the IRQ3 interrupt request. Z86C21 MCU Port 3 (I/O or Control) PAD Out Port 3 Output Configuration PAD In Auto Latch R ≈ 500 KΩ Port 3 Input Configuration Figure 8. Port 3 Configuration \10 Z86C21 MCU WITH 8K ROM Table 4. Port 3 Pin Assignments Pin I/O CTC1 Int. P0 HS P30 P31 P32 P33 IN IN IN IN TIN IRQ3 IRQ2 IRQ0 IRQ1 P34 P35 P36 OUT OUT OUT P37 T0 T1 OUT P1 HS P2 HS UART Ext Serial In D/R D/R D/R R/D DM R/D TOUT R/D Serial Out IRQ4 IRQ5 Notes: HS = Handshake Signals; D = Data Available; R = Ready Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs that are not externally driven. This reduces excessive supply current flow in the input buffer when it is not been driven by any source. ■ The pre-drivers slew rate reduced to 10 ns typical. ■ Low EMI output drivers have resistance of 200 Ohms typical. Low EMI Option. The Z86C21 is available in a Low EMI option. This option is mask-programmable, to be selected by the customer at the time when the ROM code is submitted. Use of this feature results in: ■ Oscillator divide-by-two circuitry is eliminated. ■ Internal SCLK/TCLK operation is limited to a maximum of 4 MHz (250 ns cycle time) Transmitted Data (No Parity) Received Data (No Parity) SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST SP D7 D6 D5 D4 D3 D2 D1 D0 ST Start Bit Start Bit Eight Data Bits Eight Data Bits Two Stop Bits One Stop Bit Transmitted Data (With Parity) SP SP P Received Data (With Parity) D6 D5 D4 D3 D2 D1 D0 ST SP P D6 D5 D4 D3 D2 D1 D0 ST Start Bit Start Bit Seven Data Bits Seven Data Bits Odd Parity Parity Error Flag Two Stop Bits One Stop Bit Figure 9. Serial Data Formats 11 Z86C21 MCU WITH 8K ROM FUNCTIONAL DESCRIPTION Address Space Program Memory. The Z86C21 can address up to 56K bytes of external program memory (Figure 10). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. For ROM mode, byte 13 to byte 8191 consists of on-chip ROM. At addresses 8192 and greater, the Z86C21 executes external program memory fetches. In the ROMless mode, the Z86C21 can address up to 64K bytes of external program memory. Program execution begins at external location 000C (HEX) after a reset. Data Memory (/DM). The ROM version can address up to 56K bytes of external data memory space beginning at location 8192. The ROMless version can address up to 64K bytes of external data memory. External data memory can be included with, or separated from, the external program memory space. /DM, an optional I/O function that can be programmed to appear on P34, is used to distinguish between data and program memory space (Figure 11). The state of the /DM signal is controlled by the type instruction being executed. An LDC opcode references PROGRAM (/DM inactive) memory, and an LDE instruction references DATA (/DM active Low) memory. 65535 External ROM and RAM 65535 8192 8191 On-Chip ROM Location of First Byte of Instruction Executed After RESET Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) 12 11 IRQ5 10 IRQ5 9 IRQ4 8 IRQ4 7 IRQ3 6 IRQ3 5 IRQ2 4 IRQ2 3 IRQ1 2 IRQ1 1 IRQ0 0 IRQ0 External Data Memory 8192 8191 Not Addressable 0 Figure 11. Data Memory Configuration Figure 10. Program Memory Configuration \12 Z86C21 MCU WITH 8K ROM Register File. The Register File consists of four I/O port registers, 236 general-purpose registers and 16 control and status registers (Figure 12). The instructions can access registers directly or indirectly through an 8-bit address field. The Z86C21 also allows short 4-bit register addressing using the Register Pointer (Figure 13). In the 4-bit mode, the Register File is divided into 16 working LOCATION register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working-register group. For the reset and power-up conditions of the Register File, see Figure 14. Note: Register Bank E0-EF can only be accessed through working registers and indirect addressing modes. IDENTIFIERS R255 Stack Pointer (Bits 7-0) SPL R254 Stack Pointer (Bits 15-8) SPH R253 Register Pointer r7 r6 RP Program Control Flags FLAGS R251 Interrupt Mask Register IMR R250 Interrupt Request Register IRQ R249 Interrupt Priority Register IPR R248 Ports 0-1 Mode P01M R247 Port 3 Mode P3M R246 Port 2 Mode P2M R245 T0 Prescaler PRE0 R244 Timer/Counter0 R243 T1 Prescaler R242 Timer/Counter1 R241 Timer Mode TMR 2F R240 Serial I/O SIO 20 1F PRE1 T1 R239 r3 r2 r1 r0 R253 (Register Pointer) The upper nibble of the register file address provided by the register pointer specifies the active working-register group. R252 T0 r5 r4 FF Register Group F R15 to R0 F0 • • • • • • • • • • • • • • 10 0F General-Purpose Registers Specified Working Register Group The lower nibble of the register file address provided by the instruction points to the specified register. Register Group 1 R15 to R0 Register Group 0 R15 to R4 I/O Ports R3 to R0 00 R4 R3 Port 3 P3 R2 Port 2 P2 R1 Port 1 P1 R0 Port 0 P0 Figure 13. Register Pointer Figure 12. Register File 13 Z86C21 MCU WITH 8K ROM FUNCTIONAL DESCRIPTION (Continued) REGISTER POINTER D7 D6 D5 D4 0 0 0 Z8 STANDARD CONTROL REGISTERS 0 RESET CONDITION Working Register Group Pointer D7 D6 D5 D4 D3 D2 D1 D0 REGISTER Z8 REGISTER FILE %FF %F0 † %7F SPL U U U U U U U % FE SPH U U U U U U U U % FD RP U U U U U U U U % FC FLAGS U U U U U U U U % FB IMR 0 U U U U U U U % FA IRQ 0 0 0 0 0 0 0 0 % F9 IPR U U U U U U U U % F8 P01M 0 1 0 0 1 1 0 1 % F7 P3M 0 0 0 0 0 0 0 0 % F6 P2M 1 1 1 1 1 1 1 1 % F5 PRE0 U U U U U U U 0 % F4 T0 U U U U U U U U % F3 PRE1 U U U U U U 0 0 % F2 T1 U U U U U U U U % F1 TMR 0 0 0 0 0 0 0 0 % F0 S10 U U U U U U U U REGISTER %0F %00 Notes: 1. General-purpose registers are not reset after Stop-Mode Recovery or after a Reset. 2. General-purpose registers are undefined after Power-up. U % FF RESET CONDITION % (0) 03 P3 1 1 1 1 U U U U % (0) 02 P2 U U U U U U U U % (0) 01 P1 U U U U U U U U % (0) 00 P0 U U U U U U U U U = Unknown † = For ROMless (Z86C91) reset condition = 10110110 Figure 14. RAM Register File Reset Condition RAM Protect. The upper portion of the RAM’s address spaces 80FH to EFH (excluding the control registers) can be protected from reading and writing. The RAM Protect bit option is mask-programmable and is selected by the customer when the ROM code is submitted. After the mask option is selected, the user activates from the internal ROM code to turn off/on the RAM Protect by loading a bit D6 in the IMR register to either a 0 or a 1, respectively. A 1 in D6 indicates RAM Protect enabled. ROM Protect. The first 8 Kbytes of program memory is mask programmable. A ROM protect feature prevents dumping of the ROM contents by inhibiting execution of LDC, LDCI, LDE, and LDEI instructions to Program Memory in all modes. \14 The ROM Protect option is mask-programmable, to be selected by the customer at the time when the ROM code is submitted. Note: With RAM/ROM protect on, the Z86C21 cannot access the memory space. Stack. The Z86C21 has a 16-bit Stack Pointer (R254R255) used for external stack that resides anywhere in the data memory for the ROMless mode, but only from 8192 to 65535 in the ROM mode. An 8-bit Stack Pointer (R255) is used for the internal stack that resides within the 236 general-purpose registers (R4-R239). The high byte of the Stack Pointer (SPH-Bit 8-15) is used as a general-purpose register when using internal stack only. Z86C21 MCU WITH 8K ROM Counter/Timers. There are two 8-bit programmable counter/timers (T0-T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 prescaler is driven by the internal clock only (Figure 15). The 6-bit prescalers divides the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When both the counter and prescaler reach the end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated. The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counter, but not the prescalers, can be read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and can be either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that is retriggerable or nonretriggerable, or as a gate input for the internal clock. Port 3, line P36, also serves as a timer output (TOUT) through which T0, T1 or the internal clock is output. The counter/ timers are cascaded by connecting the T0 output to the input of T1. Internal Data Bus Write OSC Write Read PRE0 Initial Value Register T0 Initial Value Register 6-Bit Down Counter 8-bit Down Counter T0 Current Value Register ÷2 ÷4 Internal Clock IRQ4 Serial I/O Clock ÷2 External Clock Tout P36 Clock Logic ÷4 Internal Clock Gated Clock Triggered Clock TIN P31 Write 6-Bit Down Counter 8-Bit Down Counter PRE1 Initial Value Register T1 Initial Value Register Write IRQ5 T1 Current Value Register Read Internal Data Bus Figure 15. Counter/Timers Block Diagram 15 Z86C21 MCU WITH 8K ROM FUNCTIONAL DESCRIPTION (Continued) Interrupts. The Z86C21 has six different interrupts from eight different sources. The interrupts are maskable and prioritized. The eight sources are divided as follow: four sources are claimed by Port 3, lines P33-P30; one in Serial Out, one in Serial In, and two in the counter/timers (Figure 16). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests. When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. (Refer to Table 4.) All Z86C21 interrupts are vectored through locations in the program memory. When an interrupt machine cycle is activated, an interrupt request is granted. Thus, this disables all of the subsequent interrupts, save the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request register is polled to determine which of the interrupt requests need service. Software initialed interrupts are supported by setting the appropriate bit in the Interrupt Request Register (IRQ). Internal interrupt requests are sampled on the falling edge of the last cycle of every instruction, and the interrupt request must be valid 5TpC before the falling edge of the last clock cycle of the currently executing instruction. For the ROMless mode, when the device samples a valid interrupt request, the next 48 (external) clock cycles are used to prioritize the interrupt, and push the two PC bytes and the FLAG register on the stack. The following nine cycles are used to fetch the interrupt vector from external memory. The first byte of the interrupt service routine is fetched beginning on the 58th TpC cycle following the internal sample point, which corresponds to the 63rd TpC cycle following the external interrupt sample point. IRQ0 - IRQ5 IRQ IMR 6 Global Interrupt Enable Interrupt Request IPR PRIORITY LOGIC Vector Select Figure 16. Interrupt Block Diagram \16 Z86C21 MCU WITH 8K ROM Clock. The Z86C21 on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 1 MHz to 16 MHz max, and series resistance (RS) is less than or equal to 100 Ohms. The crystal should be connected across XTAL1 and XTAL2 using the recom- mended capacitors (10 pF < CL < 300 pF) from each pin 11, ground instead of just system ground. This prevents noise injection into the clock input (Figure 17). Note: Actual capacitor value is specified by the crystal manufacturer. XTAL1 C1 C1 Pin 11 Pin 11 XTAL1 XTAL2 XTAL2 L XTAL2 C2 XTAL1 C2 Pin 11 Ceramic Resonator or Crystal Pin 11 External Clock LC Clock Figure 17. Oscillator Configuration HALT. Turns off the internal CPU clock but not the XTAL oscillation. The counter/timers and the external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 5 µA (typical) or less. The STOP mode is terminated by a reset which causes the processor to restart the application program at address 000C (HEX). In order to enter STOP (or HALT) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (opcode=0FFH) immediately before the appropriate sleep instruction. i.e., FF NOP 6F STOP FF NOP 7F HALT ; clear the pipeline ; enter STOP mode or ; clear the pipeline ; enter HALT mode 17 Z86C21 MCU WITH 8K ROM ABSOLUTE MAXIMUM RATINGS Symbol Description Min Max Units VCC TSTG TA –0.3 –65 +7.0 +150 † V °C °C Supply Voltage* Storage Temp Oper Ambient Temp Notes: * Voltages on all pins with respect to GND. † See Ordering Information Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 18). +5V 2.1 KΩ From Output Under Test 150 pF 9.1 kΩ Figure 18. Test Load Diagram \18 Z86C21 MCU WITH 8K ROM DC CHARACTERISTICS Sym Parameter TA = 0°C to +70°C Min Max 7 VCC +0.3 0.8 TA = –40°C to +105°C Min Max V V V IIN < 250 µA Driven by External Clock Generator Driven by External Clock Generator VCC +0.3 0.8 V V V IOH = –2.0 mA Max Input Voltage Clock Input High Voltage Clock Input Low Voltage 3.8 –0.3 VIH VIL VOH Input High Voltage Input Low Voltage Output High Voltage 2 –0.3 2.4 VOH VOL VRH Output High Voltage Output Low Voltage Reset Input High Voltage VCC –100 mV VRl IIL IOL Reset Input Low Voltage Input Leakage Output Leakage IIR ICC Reset Input Current Supply Current –80 30 35 –80 30 35 ICC1 Standby Current ICC2 IALL Standby Current Auto Latch Low Current 6.5 7 10 10 6.5 7 20 14 VCC +0.3 0.8 VCC –100 mV 3.8 0.4 VCC+0.3 –0.3 –2 –2 0.8 2 2 –10 2.0 –0.3 2.4 Conditions 7 VCC+0.3 0.8 VCH VCL 3.8 –0.3 Typical @ 25°C Units IOH = –100 µA IOL = +5.0 mA 3.8 0.4 VCC +0.3 V V V –0.3 –2 –2 0.8 2 2 V µA µA VIN = 0V, VCC VIN = 0V, VCC 20 24 µA mA mA VRL = 0V [1] @ 12 MHz [1] @ 16 MHz 4 4.5 1 5 mA mA µA µA [1] HALT mode VIN = OV, VCC@ 12 MHz [1] HALT mode VIN = OV, VCC@ 16 MHz [1] STOP mode V IN = OV, VCC –14 Note: [1] All inputs driven to either 0V or VCC, outputs floating. 19 Z86C21 MCU WITH 8K ROM AC CHARACTERISTICS External I/O or Memory Read or Write Timing Diagram R//W 13 12 Port 0, /DM 16 3 18 Port 1 A7 - A0 1 D7 - D0 IN 9 2 /AS 8 11 4 5 /DS (Read) 6 17 10 Port 1 A7 - A0 D7 - D0 OUT 14 15 7 /DS (Write) 17 Figure 19. External I/O or Memory Read/Write Timing \20 Z86C21 MCU WITH 8K ROM AC CHARACTERISTICS External I/O or Memory Read or Write Timing Table TA = 0°C to +70°C 12 MHz 16 MHz Min Max Min Max TA = –40°C to +105°C 12 MHz 16 MHz Min Max Min Max 35 45 No Symbol Parameter 1 2 3 4 TdA(AS) TdAS(A) TdAS(DR) TwAS Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req’d Valid /AS Low Width 35 45 55 40 55 40 5 6 7 8 TdAZ(DS) TwDSR TwDSW TdDSR(DR) Address Float to /DS Fall /DS (Read) Low Width /DS (Write) Low Width /DS Fall to Read Data Req’d Valid 0 185 110 0 135 80 0 185 110 0 135 80 9 10 11 12 ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay 0 65 45 30 0 50 35 20 0 65 45 33 13 14 15 16 TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) /DS Rise to R//W Not Valid Write Data Valid to /DS Fall (Write) Delay /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req’d Valid 50 35 55 35 25 35 50 35 55 17 18 TdAS(DS) TdDM(AS) /AS Rise to /DS Fall Delay /DM Valid to /AS Rise Delay 65 50 Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. Standard Test Load All timing references use 2.0V for a logic 1 and 0.8V for a logic 0. 25 35 250 180 130 ns ns ns ns [2,3] [2,3] [1,2,3] [2,3] ns ns ns ns [1,2,3] [1,2,3] [1,2,3] 0 50 35 25 ns ns ns ns [2,3] [2,3] [2,3] [2,3] 35 25 35 ns ns ns ns [2,3] [2,3] [2,3] [1,2,3] ns ns [2,3] [2,3] 25 35 180 130 230 45 30 Notes 250 75 310 Units 75 310 65 50 230 45 30 Clock Dependent Formulas Number Symbol Equation 1 2 3 4 TdA(AS) TdAS(A) TdAS(DR) TwAS 0.40TpC + 0.32 0.59TpC – 3.25 2.83TpC + 6.14 0.66TpC – 1.65 6 7 8 10 TwDSR TwDSW TdDSR(DR) TdDS(A) 2.33TpC – 10.56 1.27TpC + 1.67 1.97TpC – 42.5 0.8TpC 11 12 13 14 TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) 0.59TpC – 3.14 0.4TpC 0.8TpC – 15 0.4TpC 15 16 17 18 TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) 0.88TpC – 19 4TpC –20 0.91TpC –10.7 0.9TpC – 26.3 21 Z86C21 MCU WITH 8K ROM AC CHARACTERISTICS Additional Timing Diagram 3 1 Clock 2 2 3 7 7 TIN 4 5 6 IRQN 8 9 Figure 20. Additional Timing AC CHARACTERISTICS Additional Timing Table TA = 0°C to +70°C 12 MHz 16 MHz Min Max Min Max TA = –40°C to +105°C 12 MHz 16 MHz Min Max Min Max 83 No Sym Parameter 1 2 3 4 TpC TrC,TfC TwC TwTinL Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width 83 5 6 7 TwTinH TpTin TrTin,TfTin Timer Input High Width Timer Input Period Timer Input Rise & Fall Times 3TpC 8TpC 100 3TpC 8TpC 100 3TpC 8TpC 100 3TpC 8TpC 100 8A 8B 9 TwIL TwIL TwIH Interrupt Request Input Low Times Interrupt Request Input Low Times Interrupt Request Input High Times 70 3TpC 3TpC 70 3TpC 3TpC 70 3TpC 3TpC 50 3TpC 3TpC 1000 15 35 75 Notes: [1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0. [2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. [3] Interrupt references request through Port 3. [4] Interrupt request through Port 3 (P33-P31). [5] Interrupt request through Port 30. \22 62.5 1000 10 25 75 35 75 1000 15 62.5 1000 10 25 75 Units Notes ns ns ns ns [1] [1] [1] [2] ns [2] [2] [2] ns [2,4] [2,5] [2,3] Z86C21 MCU WITH 8K ROM AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid 1 Next Data In Valid 2 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Figure 21. Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Figure 22. Output Handshake Timing AC CHARACTERISTICS Handshake Timing Table No Sym Parameter 1 2 3 4 TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) Data In Setup Time Data In Hold Time Data Available Width DAV Fall to RDY Fall Delay 5 6 7 8 TdDAVId(RDY) TdRDYO(DAV) TdD0(DAV) TdDAV0(RDY) DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay 9 10 11 TdRDY0(DAV) TwRDY TdRDY0d(DAV) RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay TA = 0°C to +70°C 12 MHz 16 MHz Min Max Min Max TA = –40°C to +105°C 12 MHz 16 MHz Min Max Min Max 0 145 110 0 145 110 0 145 110 115 115 115 0 TpC 0 TpC 115 115 TpC 115 TpC 0 115 110 115 115 0 0 110 115 115 0 0 110 115 115 0 0 145 110 115 110 115 115 Data Direction IN IN IN IN IN IN OUT OUT OUT OUT OUT 23 Z86C21 MCU WITH 8K ROM Z8 CONTROL REGISTER DIAGRAMS R240 SIO R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Serial Data (D0 = LSB) Count Mode 0 T1 Single Pass 1 T1 Modulo N Clock Source 1 T1 Internal 0 T1 External Timing Input (TIN) Mode Figure 23. Serial I/O Register (F0H: Read/Write) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) R241 TMR D7 D6 D5 D4 D3 D2 D1 D0 0 1 No Function Load T0 0 1 Disable T0 Count Enable T0 Count 0 1 No Function Load T1 0 1 Disable T1 Count Enable T1 Count Figure 26. Prescaler 1 Register (F3H: Write Only) R244 T0 D7 D6 D5 D4 D3 D2 D1 D0 TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When Read) TOUT Modes 00 Not Used 01 T0 Out 10 T1 Out 11 Internal Clock Out Figure 24. Timer Mode Register (F1H: Read/Write) Figure 27. Counter/Timer 0 Register (F4H : Read/Write) R245 PRE0 D7 D6 D5 D4 D3 D2 D1 D0 Count Mode 0 T0 Single Pass 1 T0 Modulo N R242 T1 D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) T1 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T1 Current Value (When Read) Figure 25. Counter/Timer 1 Register (F2H: Read/Write) \24 Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) Figure 28. Prescaler 0 Register (F5H: Write Only) Z86C21 MCU WITH 8K ROM R248 P01M R246 P2M D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 P00 - P00 Mode 00 Output 01 Input 1X A11 - A8 P20 - P27 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input Stack Selection 0 External 1 Internal Figure 29. Port 2 Mode Register (F6H: Write Only) P17 - P10 Mode 00 Byte Output 01 Byte Input 10 AD7 - AD0 11 High-Impedance AD7 - DA0, /AS, /DS, /R//W, A11 - A8, A15 - A12, If Selected R247 P3M D7 D6 D5 D4 D3 D2 D1 D0 External Memory Timing 0 Normal 1 Extended 0 Port 2 Open Drain 1 Port 2 Push-pull Reserved (Must be 0) P07 - P04 Mode 00 Output 01 Input 1X A 15 - A12 0 P32 = Input P35 = Output 1 P32 = /DAV0/RDY0 P35 = RDY0//DAV0 00 P33 = Input P34 = Output 01 P33 = Input 10 P34 = /DM 11 P33 = /DAV1/RDY1 P34 = RDY1//DAV1 0 P31 = Input (TIN) P36 = Output (TOUT) 1 P31 = /DAV2/RDY2 P36 = RDY2//DAV2 0 1 P30 = Input P37 = Output P30 = Serial In P37 = Serial Out 0 Parity Off 1 Parity On Figure 30. Port 3 Mode Register (F7H: Write Only) Figure 31. Port 0 and 1 Mode Register (F8H: Write Only) R249 IPR D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Group Priority Reserved = 000 C > A > B = 001 A > B > C = 010 A > C > B = 011 B > C > A = 100 C > B > A = 101 B > A > C = 110 Reserved = 111 IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0) Figure 32. Interrupt Priority Register (F9H: Write Only) 25 Z86C21 MCU WITH 8K ROM Z8 CONTROL REGISTER DIAGRAMS (Continued) R253 RP R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 IRQ0 = P32 IRQ1 = P33 IRQ2 = P31 IRQ3 = P30 IRQ4 = T0 IRQ5 = T1 0 Reserved (Must be 0) Input (D0 = IRQ0) Input Input Input, Serial Input Serial Output r4 r5 Register Pointer r6 r7 Reserved (Must be 0) Figure 33. Interrupt Request Register (FAH : Read/Write) Figure 36. Register Pointer Register (FDH : Read/Write) R254 SPH R251 IMR D7 D7 D6 D5 D4 D3 D2 D1 D0 1 Enables IRQ5-IRQ0 (D0 = IRQ0) 1 Enables RAM Protect 1 Enables Interrupts D6 D5 D4 D3 D2 D1 D0 Stack Pointer Upper Byte (SP15 - SP8) Figure 37. Stack Pointer Register (FE H: Read/Write) Figure 34. Interrupt Mask Register (FBH : Read/Write) R255 SPL D7 D6 D5 D4 D3 D2 D1 D0 R252 FLAGS Stack Pointer Lower Byte (SP7 - SP0) D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Figure 35. Flag Register (FCH : Read/Write) \26 Figure 38. Stack Pointer Register (FFH: Read/Write) Z86C21 MCU WITH 8K ROM INSTRUCTION SET NOTATION Addressing Modes. The following notation is used to describe the addressing modes and instruction operations as shown in the instruction summary. Symbol Meaning IRR Indirect register pair or indirect workingregister pair address Indirect working-register pair only Indexed address Direct address Relative address Immediate Register or working-register address Working-register address only Indirect-register or indirect working-register address Indirect working-register address only Register pair or working register pair address Irr X DA RA IM R r IR Ir RR Flags. Control register (R252) contains the following six flags: Symbol Meaning C Z S V D H Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Affected flags are indicated by: 0 1 * x Clear to zero Set to one Set to clear according to operation Unaffected Undefined Symbols. The following symbols are used in describing the instruction set. Symbol Meaning dst src cc @ SP PC FLAGS RP IMR Destination location or contents Source location or contents Condition code Indirect address prefix Stack Pointer Program Counter Flag register (Control Register 252) Register Pointer (R253) Interrupt mask register (R251) 27 Z86C21 MCU WITH 8K ROM CONDITION CODES Value Mnemonic Meaning Flags Set 1000 0111 1111 0110 1110 C NC Z NZ Always True Carry No Carry Zero Not Zero C=1 C=0 Z=1 Z=0 1101 0101 0100 1100 0110 PL MI OV NOV EQ Plus Minus Overflow No Overflow Equal S=0 S=1 V=1 V=0 Z=1 1110 1001 0001 1010 0010 NE GE LT GT LE Not Equal Greater Than or Equal Less than Greater Than Less Than or Equal Z=0 (S XOR V) = 0 (S XOR V) = 1 [Z OR (S XOR V)] = 0 [Z OR (S XOR V)] = 1 1111 0111 1011 0011 0000 UGE ULT UGT ULE F Unsigned Greater Than or Equal Unsigned Less Than Unsigned Greater Than Unsigned Less Than or Equal Never True (Always False) C=0 C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1 \28 Z86C21 MCU WITH 8K ROM INSTRUCTION FORMATS OPC dst CCF, DI, EI, IRET, NOP, RCF, RET, SCF OPC One-Byte Instructions OPC MODE dst/src OR 1110 dst/src OPC CLR, CPL, DA, DEC, DECW, INC, INCW, POP, PUSH, RL, RLC, RR, RRC, SRA, SWAP OPC MODE src OR 1110 src dst OR 1110 dst OR 1110 dst src OR 1110 src dst OR 1110 dst ADC, ADD, AND, CP, LD, OR, SBC, SUB, TCM, TM, XOR JP, CALL (Indirect) dst OR 1110 dst OPC MODE dst OPC ADC, ADD, AND, CP, LD, OR, SBC, SUB, TCM, TM, XOR VALUE SRP VALUE MODE OPC MODE dst src MODE OPC dst/src src/dst dst/src OPC ADC, ADD, AND, CP, OR, SBC, SUB, TCM, TM, XOR LD, LDE, LDEI, LDC, LDCI OPC MODE OPC dst/src x LD LD ADDRESS src/dst LD OR 1110 src cc OPC JP DAU dst OPC LD DAL VALUE OPC dst/CC OPC DJNZ, JR DAL RA FFH 6FH CALL DAU STOP/HALT 7FH Two-Byte Instructions Three-Byte Instructions INSTRUCTION SUMMARY Note: Assignment of a value is indicated by the symbol “ ← ”. For example: dst ← dst + src indicates that the source data is added to the destination data and the result is stored in the destination location. The notation “addr (n)” is used to refer to bit (n) of a given operand location. For example: dst (7) refers to bit 7 of the destination operand. 29 Z86C21 MCU WITH 8K ROM INSTRUCTION SUMMARY (Continued) Instruction and Operation Address Mode Opcode Flags Affected dst src Byte (Hex) C Z S V D H ADC dst, src † dst←dst + src + C 1[ ] ✻ ✻ ✻ ✻ 0 ✻ ADD dst, src dst←dst + src † 0[ ] ✻ ✻ ✻ ✻ 0 ✻ AND dst, src dst←dst AND src † 5[ ] - ✻ ✻ 0 - - CALL dst SP←SP – 2 @SP←PC, PC←dst DA IRR D6 D4 - - - - - - EF ✻ - - - - - CCF C←NOT C CLR dst dst←0 R IR B0 B1 - - - - COM dst dst←NOT dst R IR 60 61 - ✻ ✻ 0 - - CP dst, src dst – src † A[ ] ✻ ✻ ✻ ✻ - DA dst dst←DA dst R IR 40 41 DEC dst dst←dst – 1 R IR 00 01 DECW dst dst←dst – 1 RR IR DI IMR(7)←0 DJNZr, dst r←r – 1 if r ≠ 0 PC←PC + dst Range: +127, –128 RA - - INC dst dst←dst + 1 INCW dst dst←dst + 1 Address Mode Opcode Flags Affected dst src Byte (Hex) C Z S V D H - ✻ ✻ ✻ - - R IR rE r=0–F 20 21 RR IR A0 A1 - ✻ ✻ ✻ - - BF ✻ ✻ ✻ ✻ ✻ ✻ cD c=0–F 30 - - - - - - cB c=0–F - - - - - - - - - - - - r IRET FLAGS←@SP; SP←SP + 1 PC←@SP; SP←SP + 2; IMR(7)←1 JP cc, dst if cc is true PC←dst DA IRR RA - JR cc, dst if cc is true, PC←PC + dst Range: +127, –128 ✻ ✻ ✻ X - - LD dst, src dst←src r r R Im R r - ✻ ✻ ✻ - - 80 81 - ✻ ✻ ✻ - - 8F - - - - - - r X r Ir R R R IR IR X r Ir r R IR IM IM R rC r8 r9 r=0–F C7 D7 E3 F3 E4 E5 E6 E7 F5 rA r=0–F - - - - - LDC dst, src r Irr C2 - - - - - - LDCI dst, src dst←src r←r +1; rr←rr + 1 Ir Irr C3 - - - - - - EI IMR(7)←1 9F - - - - - - HALT 7F - - - - - - \30 Instruction and Operation Z86C21 MCU WITH 8K ROM INSTRUCTION SUMMARY (Continued) Instruction and Operation Address Mode Opcode Flags Affected dst src Byte (Hex) C Z S V D H NOP - - Address Mode Opcode Flags Affected dst src Byte (Hex) C Z S V D H Instruction and Operation FF - - - - STOP 6F - - - - - - OR dst, src dst←dst OR src † 4[ ] - ✻ ✻ 0 - - SUB dst, src dst←dst←src † 2[ ] ✻ ✻ ✻ ✻ 1 ✻ POP dst dst←@SP; SP←SP + 1 R IR 50 51 - - - SWAP dst R IR F0 F1 X ✻ ✻ X - - TCM dst, src (NOT dst) AND src † 6[ ] - ✻ ✻ 0 - - TM dst, src dst AND src † 7[ ] - ✻ ✻ 0 - - XOR dst, src dst←dst XOR src † B[ ] - ✻ ✻ 0 - - 70 71 - RCF C←0 CF 0 - RET PC←@SP; SP←SP + 2 AF R IR RL dst 7 R IR 0 RLC dst C 7 0 RR dst C 7 0 RRC dst C 7 0 SBC dst, src dst←dst←src←C 90 91 SRA dst SRP src RP←src - - - - - - - - - - - - ✻ ✻ ✻ ✻ - 0 - - - R IR E0 E1 ✻ ✻ ✻ ✻ - - R IR C0 C1 ✻ ✻ ✻ ✻ - - † 3[ ] ✻ ✻ ✻ ✻ 1 ✻ DF 1 - - - D0 D1 ✻ ✻ ✻ 0 - - 31 - - - 3 - ✻ ✻ ✻ ✻ - - 4 - 10 11 R IR 7 - R IR SCF C←1 C - 7 PUSH src SP←SP – 1; @SP←src C - † These instructions have an identical set of addressing modes, which are encoded for brevity. The first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13. Address Mode dst src Lower Opcode Nibble r r [2] r Ir [3] R R [4] R IR [5] R IM [6] IR IM [7] 0 Im - - - - 31 Z86C21 MCU WITH 8K ROM OPCODE MAP Lower Nibble (Hex) 0 1 2 3 4 5 Upper Nibble (Hex) 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 6.5 DEC R1 6.5 RLC R1 6.5 INC R1 8.0 JP IRR1 8.5 DA R1 10.5 POP R1 6.5 COM R1 10/12.1 PUSH R2 10.5 DECW RR1 6.5 RL R1 10.5 INCW RR1 6.5 CLR R1 6.5 RRC R1 6.5 SRA R1 6.5 RR R1 8.5 SWAP R1 6.5 DEC IR1 6.5 RLC IR1 6.5 INC IR1 6.1 SRP IM 8.5 DA IR1 10.5 POP IR1 6.5 COM IR1 12/14.1 PUSH IR2 10.5 DECW IR1 6.5 RL IR1 10.5 INCW IR1 6.5 CLR IR1 6.5 RRC IR1 6.5 SRA IR1 6.5 RR IR1 8.5 SWAP IR1 6.5 ADD r1, r2 6.5 ADC r1, r2 6.5 SUB r1, r2 6.5 SBC r1, r2 6.5 OR r1, r2 6.5 AND r1, r2 6.5 TCM r1, r2 6.5 TM r1, r2 12.0 LDE r1, Irr2 12.0 LDE r2, Irr1 6.5 CP r1, r2 6.5 XOR r1, r2 12.0 LDC r1, Irr2 12.0 LDC r1, Irr2 6.5 ADD r1, Ir2 6.5 ADC r1, Ir2 6.5 SUB r1, Ir2 6.5 SBC r1, Ir2 6.5 OR r1, Ir2 6.5 AND r1, Ir2 6.5 TCM r1, Ir2 6.5 TM r1, Ir2 18.0 LDEI Ir1, Irr2 18.0 LDEI Ir2, Irr1 6.5 CP r1, Ir2 6.5 XOR r1, Ir2 18.0 LDCI Ir1, Irr2 18.0 LDCI Ir1, Irr2 6.5 LD r1, IR2 6.5 LD Ir1, r2 10.5 ADD R2, R1 10.5 ADC R2, R1 10.5 SUB R2, R1 10.5 SBC R2, R1 10.5 OR R2, R1 10.5 AND R2, R1 10.5 TCM R2, R1 10.5 TM R2, R1 10.5 ADD IR2, R1 10.5 ADC IR2, R1 10.5 SUB IR2, R1 10.5 SBC IR2, R1 10.5 OR IR2, R1 10.5 AND IR2, R1 10.5 TCM IR2, R1 10.5 TM IR2, R1 10.5 ADD R1, IM 10.5 ADC R1, IM 10.5 SUB R1, IM 10.5 SBC R1, IM 10.5 OR R1, IM 10.5 AND R1, IM 10.5 TCM R1, IM 10.5 TM R1, IM 8 6.5 10.5 LD ADD IR1, IM r1, R2 10.5 ADC IR1, IM 10.5 SUB IR1, IM 10.5 SBC IR1, IM 10.5 OR IR1, IM 10.5 AND IR1, IM 10.5 TCM IR1, IM 10.5 TM IR1, IM 9 A B C 12/10.5 12/10.0 6.5 6.5 LD JR DJNZ LD r2, R1 r1, RA cc, RA r1, IM D E 12.10.0 JP cc, DA 6.5 INC r1 6.0 STOP 7.0 HALT 6.1 DI 6.1 EI 14.0 RET 10.5 10.5 10.5 10.5 CP CP CP CP R2, R1 IR2, R1 R1, IM IR1, IM 10.5 10.5 10.5 10.5 XOR XOR XOR XOR R2, R1 IR2, R1 R1, IM IR1, IM 10.5 LD r1,x,R2 10.5 20.0 20.0 LD CALL CALL* r2,x,R1 DA IRR1 10.5 10.5 10.5 10.5 LD LD LD LD R2, R1 IR2, R1 R1, IM IR1, IM 10.5 LD R2, IR1 2 3 16.0 IRET 6.5 RCF 6.5 SCF 6.5 CCF 6.0 NOP 2 3 Bytes per Instruction Lower Opcode Nibble Execution Cycles Pipeline Cycles 4 Upper Opcode Nibble First Operand A 10.5 CP R1, R2 Mnemonic Second Operand Legend: R = 8-bit Address r = 4-bit Address R1 or r1 = Dst Address R2 or r2 = Src Address Sequence: Opcode, First Operand, Second Operand Note: Blank areas not defined. *2-byte instruction appears as a 3-byte instruction \32 F 1 Z86C21 MCU WITH 8K ROM PACKAGE INFORMATION 40-Pin PDIP Package Diagram 44-Pin PLCC Package Diagram 33 Z86C21 MCU WITH 8K ROM PACKAGE INFORMATION (Continued) 44-Pin QFP Package Diagram \34 Z86C21 MCU WITH 8K ROM ORDERING INFORMATION Z86C21 12 MHz 40-pin DIP Z86C2112PSC Z86C2112PEC 16 MHz 44-pin PLCC Z86C2112VSC Z86C2112VEC 44-pin QFP Z86C2112FSC Z86C2112FEC 40-pin DIP Z86C2116PSC 44-pin PLCC Z86C2116VSC 44-pin QFP Z86C2116FSC For fast results, contact your local Zilog Sales Office for assistance in ordering the part desired. CODES Preferred Package P = Plastic DIP V = Plastic Chip Carrier Longer Lead Time F = Plastic Quad Flat Pack Preferred Temperature S = 0°C to +70°C Longer Lead Time E = -40°C to +105°C Speeds 12 = 12 MHz 16 = 16 MHz Environmental C = Plastic Standard Example: Z 89C21 12 P S C is a Z89C21, 12 MHz, DIP, 0°C to +70°C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix © 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com 35