HYNIX GMS81C3004

GMS81C3004
Table of Contents
1. OVERVIEW............................................1
13. INTERRUPTS ....................................46
Description .........................................................1
Features .............................................................1
Development Tools ............................................1
Interrupt Sequence .......................................... 48
Multi Interrupt .................................................. 50
External Interrupt ............................................. 51
2. BLOCK DIAGRAM .................................2
14. KEY SCAN.........................................53
3. PIN ASSIGNMENT ................................3
15. LCD DRIVER .....................................55
4. PACKAGE DIAGRAM ............................4
Configuration of LCD driver ............................. 55
Control of LCD Driver Circuit ........................... 56
Bias Resistor ................................................... 57
LCD Display Memory ...................................... 59
LCD Port Selection .......................................... 60
Control Method of LCD Driver ......................... 60
LCD Waveform ................................................ 62
5. PIN FUNCTION......................................5
6. PORT STRUCTURES............................7
7. ELECTRICAL CHARACTERISTICS ....10
Absolute Maximum Ratings .............................10
Recommended Operating Conditions ..............10
DC Electrical Characteristics ...........................10
A/D Comparator Characteristics ......................12
AC Characteristics ...........................................12
Typical Characteristics .....................................14
8. MEMORY ORGANIZATION.................16
Registers ..........................................................16
Program Memory .............................................19
Data Memory ...................................................22
Addressing Mode .............................................25
9. I/O PORTS ...........................................29
Registers for Port .............................................29
I/O Ports Configuration ....................................30
10. CLOCK GENERATOR .......................33
Operation Mode ...............................................35
Operation Mode Switching ...............................36
11. TIMER ................................................38
Basic Interval Timer .........................................38
Timer/Event Counter 1 .....................................39
Watch Timer .....................................................43
12. COMPARATOR .................................44
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16. WATCHDOG TIMER .........................64
17. BUZZER DRIVER ..............................66
18. POWER DOWN OPERATION...........68
SLEEP Mode ................................................... 68
STOP Mode .................................................... 69
19. OSCILLATOR CIRCUIT.....................73
20. RESET ...............................................74
External Reset Input ........................................ 74
Watchdog Timer Reset ................................... 74
21. POWER FAIL PROCESSOR.............75
A. CONTROL REGISTER LIST .................. i
B. PAD COORDINATION .......................... ii
Pad Layout ......................................................... ii
Bonding Pad Coordination ................................ iii
C. INSTRUCTION..................................... iv
Terminology List ................................................iv
Instruction Map ...................................................v
Instruction Set ...................................................vi
D. MASK ORDER SHEET ....................... xii
GMS81C3004
GMS81C3004
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH LCD DRIVER
1. OVERVIEW
1.1 Description
The GMS81C3004 is an advanced CMOS 8-bit microcontroller with 4K bytes of ROM. The device is one of GMS800 family. The LG Semicon GMS81C3004 is a powerful microcontroller which provides a highly flexible and cost effective solution to many LCD applications such as controller with LCD and toys. The GMS81C3004 provides the following standard
features: 4K bytes of ROM, 256 bytes of RAM, 8-bit timer/counter, on-chip oscillator and clock circuitry. In addition, the
GMS81C3004 supports power saving modes to reduce power consumption.
Device name
ROM Size
RAM Size
Package
GMS81C3004
4K bytes
256 bytes
80QFP or DIE
1.2 Features
• 4K Bytes On-chip Program Memory
• Key Scan
• 256 Bytes of On-chip Data RAM
(Included 64 bytes stack memory)
• One 8-bit Timer/ Counter
• Dot Matrix LCD Driver
- Max. 320 dots (40 seg. x 8 com.)
- 40 bytes of Display RAM
• Instruction Cycle Time:
- 0.5us, 1.9us, 3.8us, 15.2us at 4.19MHz
- 61us, 244us, 488us, 1.95ms at 32.768KHz
• 51 Programmable I/O pins
(Included 32 LCD pins)
• 2.2V to 5.5V Wide Operating Range
• Dual Clock Operation (4.19MHz, 32kHz)
• One 8-bit Basic Interval Timer
• Watch Timer
• Watchdog timer
• Eight Interrupt sources
- External input: 3
- Keyscan input: 1
- Timer: 4
• Buzzer Driving port
- 500Hz ~ 130kHz
• 4-channel 5-bit On-chip Comparator
• Power Down Mode
- STOP mode
- SLEEP mode
1.3 Development Tools
The GMS81C3004 is supported by a full-featured macro
assembler, an in-circuit emulator CHOICE-DrTM.
In Circuit Emulators
CHOICE-Dr. (with EVA81C)
LCD Simulator
Under development
Assembler
LGS Macro Assembler
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GMS81C3004
2. BLOCK DIAGRAM
Segment Drive Output
SEG0 ~ SEG39
(R4, R5, R6, R7)
Common Drive Output
COM0 ~ COM7
LCD Power
Supply
VCL1
VCL2
VCL3
VCL4
VCL5
LCD CONTROLLER
PSW
RESET
TEST
Accumulator
ALU
Stack Pointer
R6
R5
Program
Memory
System controller
Timing generator
Data Table
8-bit Basic
Interval
Tim er
XIN
High freq.
Low freq.
Clock
Generator
Watchdog
Timer
Watch
Timer
8-bit
Timer/
Counter
PC
5-bit
C om parator
VDD
VSS
R4
PC
Data
Memory
LCD
Display
Memory
Interrupt Controller
System
Clock Controller
XOUT
SXIN
SXOUT
R7
R2
R0
R1
Buzzer
Driver
Power
Supply
R20~R22
2
R00
R01
R02
R03
R04
R05
R06
R07
/ INT0
/ INT1
/ INT2
/ EC1
/ LCDCK
R10/ KS0
R11 / KS1
R12 / KS2
R13 / BUZ / KS3
R14 / CMP0 / KS4
R15 / CMP1 / KS5
R16 / CMP2 / KS6
R17 / CMP3 / KS7
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GMS81C3004
R21
R22
RESET
TEST
VDD
XOUT
XIN
SXOUT
SXIN
SEG0 / R40
SEG1 / R41
SEG2 / R42
SEG3 / R43
SEG4 / R44
SEG5 / R45
SEG6 / R46
SEG7 / R47
SEG8 / R50
SEG9 / R51
SEG10 / R52
SEG11 / R53
SEG12 / R54
R20
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SEG13 / R55
3. PIN ASSIGNMENT
SEG14 / R56
65
40
R07
SEG15 / R57
66
39
R06 / LCDCK
SEG16 / R60
67
38
R05
SEG17 / R61
68
37
R04
SEG18 / R62
69
36
R03 / EC1
SEG19 / R63
70
35
R02 / INT2
SEG20 / R64
71
34
R01 / INT1
SEG21 / R65
72
33
R00 / INT0
SEG22 / R66
73
32
R17 / CMP3 / KS7
SEG23 / R67
74
31
R16 / CMP2 / KS6
SEG24 / R70
75
30
R15 / CMP1 / KS5
SEG25 / R71
76
29
R14 / CMP0 / KS4
SEG26 / R72
77
28
R13 / BUZ / KS3
SEG27 / R73
78
27
R12 / KS2
SEG28 / R74
79
26
R11 / KS1
SEG29 / R75
80
25
R10 / KS0
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SEG30 / R76
SEG31 / R77
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
VSS
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
VCL1
VCL2
VCL3
VCL4
VCL5
GMS81C3004
3
GMS81C3004
4. PACKAGE DIAGRAM
24.15
23.65
UNIT: mm
14.10
13.90
SEE DETAIL "A"
0.36
0.10
0-7°
3.10 max.
0.45
0.30
0.8 BSC
1.03
0.73
0.23
0.13
18.15
17.65
20.10
19.90
1.95
REF
DETAIL "A"
Figure 4-1 Package Diagram
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5. PIN FUNCTION
VDD: Supply voltage.
VSS: Circuit ground.
TEST: Used for shipping inspection of the IC. For normal
operation, it should be connected to VSS.
R20~R22: R2 is a 3-bit CMOS bidirectional I/O port. Each
pins 1 or 0 written to the their Port Direction Register can
be used as outputs or inputs.
XIN: Input to the inverting oscillator amplifier and input to
the internal main clock operating circuit.
R40~R47, R50~57, R60~R67, R70~R77:
R4, R5, R6, R7 are four 8-bit CMOS bidirectional I/O port.
Each pins 1 or 0 written to the their Port Direction Register
can be used as outputs or inputs.
XOUT: Output from the inverting oscillator amplifier.
Ports is multiplexed with SEG0~SEG31 respectively.
RESET: Reset the MCU.
SXIN: Input to the internal sub system clock operating circuit.
Port pin
Alternate function
SXOUT: Output from the inverting subsystem oscillator
amplifier.
SEG0~SEG7
R40~R47
SEG8~SEG15
R50~R57
R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
SEG16~SEG23
R60~R67
SEG24~SEG31
R70~R77
In addition, R0 serves the functions of the various following special features.
Port pin
R00
R01
R02
R03
R06
Alternate function
INT0 (External interrupt 0)
INT1 (External interrupt 1)
INT2 (External interrupt 2)
Event counter input
LCD clock output
R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
After the reset of the MCU, port is initialized as a segment
output port.
SEG0~SEG39: Segment signal output pins for the LCD
display. See "15. LCD DRIVER" on page 55 for details.
COM0~COM7: Common signal output pins for the LCD
display. See "15. LCD DRIVER" on page 55 for details.
VCL1~VCL5: Power supply pins for the LCD driver. Since
the LCD driving resistors are provided internally, no lines
should be connected to these pins. The voltage on each pin
is VDD> V CL1> VCL2> VCL3> VCL4> VCL5 > V SS. For details, Refer to Section "15.".
In addition, R1 serves the functions of the various following special features.
Port pin
Alternate function
R10
R11
R12
R13
KS0 (Key scan input 0)
KS1 (Key scan input 1)
KS2 (Key scan input 2)
BUZ / KS3 (Buzzer output or Key scan input
3)
CMP0 / KS4 (Comparator input or Key scan
input 4)
CMP1 / KS5 (Comparator input or Key scan
input 5)
CMP2 / KS6 (Comparator input or Key scan
input 6)
CMP3 / KS7 (Comparator input or Key scan
input 7)
R14
R15
R16
R17
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GMS81C3004
PIN NAME
Pin No.
In/Out
VDD
46
-
Supply voltage
VSS
11
-
Circuit ground
TEST
45
I
For test purposes. Should connect it to GND for normal operation.
RESET
44
I
Reset signal input
20~24
-
LCD power supply
XIN
48
I
Main oscillation input
XOUT
47
O
Main oscillation output
SXIN
50
I
Sub oscillation input
SXOUT
49
O
Sub oscillation output
R00 (INT0)
33
I/O (Input)
External interrupt 0 input
R01 (INT1)
34
I/O (Input)
External interrupt 1 input
R02 (INT2)
35
I/O (Input)
External interrupt 2 input
R03 (EC1)
36
I/O (Input)
R04
37
I/O
R05
38
I/O
R06 (LCDCK)
39
I/O (Output)
R07
40
I/O
R10 (KS0)
25
I/O (Input)
R11 (KS1)
26
I/O (Input)
R12 (KS2)
27
I/O (Input)
R13 (BUZ/KS3)
28
I/O (Output/Input)
R14~R17
(CMP0~CMP3/
KS4~KS7)
29~32
I/O
(Input/Input)
R20~R22
41,42,
43
I/O
SEG0~SEG7
(R40~R47)
51~58
Output (I/O)
8-bit general I/O ports
SEG8~SEG15
(R50~R57)
59~66
Output (I/O)
8-bit general I/O ports
SEG16~SEG23
(R60~R67)
67~74
Output (I/O)
8-bit general I/O ports
SEG24~SEG31
(R70~R77)
1,2,
75~80
Output (I/O)
8-bit general I/O ports
SEG32~SEG39
3~10
O
Segment signal output ports
COM0~COM7
12~19
O
Common signal output ports
VCL1~VCL5
Function
8-bit general I/O ports
External counter input
LCD clock output
-
Key scan input
8-bit general I/O ports
Buzzer output or key scan input
Comparator input 0~3 or key scan
input 4~7
3-bit general I/O ports
-
Segment signal output ports
Table 5-1 Port Function Description
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6. PORT STRUCTURES
R00~R03 / INT0~INT2, EC1
DB
R10~R12 / KS0~KS2
Pull up
Reg.
Pull up
Reg.
DB
Pull-up Tr.
Pull-up Tr.
VDD
VDD
DB
Data Reg.
DB
Dir. Reg.
Pin
Data Reg.
DB
Dir. Reg.
MUX
DB
MUX
RD
RD
INT
Pin
VSS
VSS
DB
DB
Noise
Canceler
Key Scan
EC1
Key Scan
Enable
R04, R05, R07, R20~R23
R13 / BUZ, KS3
DB
DB
Pull up
Reg.
Pull-up Tr.
VDD
Pull up
Reg.
DB
Data Reg.
Pull-up Tr.
Buzzer Enable
VDD
BUZZER
DB
Pin
Dir. Reg.
MU X
DB
D ata R eg.
VSS
DB
DB
MU X
Pin
Dir. Reg.
RD
VSS
MUX
DB
RD
R06/LCDCK
Key Scan
DB
Pull up
Reg.
Pull-up Tr.
Key Scan
Enable
LCR[2]
VDD
LCDCK
MU X
DB
DB
D ata R eg.
Pin
Dir. Reg.
VSS
MUX
DB
RD
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GMS81C3004
R14~R17 / CIN0~CIN3, KS4~KS7
Pull up
Reg.
DB
DB
SEG32 ~ SEG39
LCVDD
Pull-up Tr.
VDD
LCD
Data Reg.
DB
Data Reg.
LCD Control
DB
SEG n Pin
Pin
Dir. Reg.
LCD Control
VSS
n=32 to 39
LCVSS
MUX
DB
RD
COM0 ~ COM7
Comparator
Channel
Selection
LCVDD
Frame Counter
Key Scan
Key Scan
Enable
COMn Pin
n=0 to 7
LCD Control
LCVSS
SEG0~SEG31 / R4, R5, R6, R7
VDD
DB
Data Reg.
DB
Dir. Reg.
VCL1 ~ VCL5
Pin
LCDEN
LCR.4
VSS
DB
MU X
VCL1
RD
LCVDD
DB
VCL2
LCD
Data Reg.
LCD
Control
DB
VCL3
Port / SEG
Selection Reg.
VCL4
LCVSS
VCL5
LCDEN
LCR.5
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GMS81C3004
XIN, XOUT ( Crystal or Ceramic resonator Option)
RESET
VDD
VDD
Main frequency
clock
RESET
Noise
Canceler
XOUT
VDD
VSS
VDD
VSS
XIN
STOP
VSS
TEST
XIN, XOUT (RC Option)
VDD
TEST
VDD
Noise
Canceler
Main frequency
clock
XOUT
VSS
VDD
VSS
VDD
RC
Oscillator
XIN
STOP
VSS
SXIN, SXOUT
VDD
SXIN
VDD
VSS
VDD
Sub frequency
clock
VSS
Noise
Canceler
SXOUT
VSS
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GMS81C3004
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ........................................... -0.3 to +6.0 V
Maximum current (ΣIOL) ...................................... 80 mA
Storage Temperature ................................-40 to +125 °C
Maximum current (ΣIOH)...................................... 50 mA
Voltage on any pin with respect to Ground (VSS)
............................................................... -0.3 to VDD+0.3
Maximum current out of VSS pin ........................100 mA
Maximum current into VDD pin ............................80 mA
Maximum current sunk by (IOL per I/O Pin) ........20 mA
Maximum output current sourced by (IOH per I/O Pin)
.................................................................................8 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
Specifications
Parameter
Symbol
Condition
Unit
Min.
Max.
Supply Voltage
VDD
fXIN=4.19MHz
fSXIN=32.768kHz
2.2
5.5
V
Operating Frequency
fXIN
VDD=2.2~5.5V
1
4.5
MHz
Sub Operating Frequency
fSXIN
VDD=2.2~5.5V
32
35
kHz
Operating Temperature
TOPR
-20
85
°C
7.3 DC Electrical Characteristics
(TA=-20~85°C, V DD=2.2~5.5V),
Specifications
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
VIH1
All input pins except XIN and SXIN
0.8 VDD
-
VDD
V
VIH2
XIN and SXIN
VDD-0.5
-
VDD
V
VIL1
All input pins except XIN and SXIN
-
-
0.2 VDD
V
VIL2
XIN and SXIN
-
-
0.4
V
Output High Voltage
VOH
VDD=2.2 ~ 5.5V, IOH1=-500µA
R0,R1,R2,R4,R5,R6,R7
0.8 VDD
-
-
V
Output Low Voltage
VOL
VDD=2.2 ~ 5.5V, IOL1=500µA
R0,R1,R2,R4,R5,R6,R7
-
-
0.1 VDD
V
Input High
Leakage Current
IIH1
VIN=VDD , All input pins except XIN, SX IN
-
-
3
µA
IIH2
VIN=VDD, XIN, SXIN
-
-
20
µA
Input Low
Leakage Current
IIL1
VIN=VDD , All input pins except XIN, SX IN
-
-
-3
µA
IIL2
VIN=VDD, XIN, SXIN
-
-
-20
µA
Input High Voltage
Input Low Voltage
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Specifications
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
Output High
Leakage Current
IOHL
VO= VDD, All output pins
-
-
3
µA
Output Low
Leakage Current
IOLL
VO=0V , All output pins
-
-
-3
µA
Pull-up Resistor1
RPORT
VIN=0V, VDD=3V±10%, R0, R1, R2
50
100
200
RRESET
VIN=0V, VDD=3V±10%, RESET
30
60
120
50
70
90
kΩ
kΩ
LCD Voltage Dividing
Resistor
RLCD
VDD=2.7 ~ 5.5V
Voltage Drop
|VDD -COMn| , n=0~7
VDC
VDD=2.7 ~ 5.5V
-15µA per common pin
-
-
120
mV
Voltage Drop
|VDD -SEGn| , n=0~39
VDS
VDD=2.7 ~ 5.5V
-15µA per segment pin
-
-
120
mV
VCL1 Output Voltage
VCL1
0.75VDD
-0.2
0.75VDD
0.75VDD
+0.2
VCL2 Output Voltage
VCL2
0.5VDD0.2
0.5VDD
0.5VDD+
0.2
VCL3 Output Voltage
VCL3
0.5VDD0.2
0.5VDD
0.5VDD+
0.2
VCL4 Output Voltage
VCL4
0.25VDD
-0.2
0.25VDD
0.25VDD
+0.2
VCL5 Output Voltage
VCL5
-0.2
0
+0.2
Supply
Current1
VDD=2.7 ~ 5.5V
1/4 bias ( VCL2=VCL3)
V
IDD1
Main clock mode2
VDD=3V±10%
4.19M H z C rystal O scillator, C L1 =C L2 =30pF
-
1.4
3.0
mA
IDD2
Sleep mode3
V D D =3V±10%
4.19M H z C rystal O scillator, C L1 =C L2 =30pF
-
0.6
1.0
mA
IDD3
Sub clock mode4
V D D =3V±10%
SXIN=32kH z
-
10
30
µA
IDD4
Sleep mode
VDD=3V±10%
SXIN=32kH z
-
6
10
µA
IDD5
Stop mode5
VDD=5V±10%
SXIN=0V
-
1.3
10
µA
1.
2.
3.
4.
†
The Data for 5V operation, refer to "7.6. Typical Characteristics" on page 14.
This mode set System Clock Mode Register(SCMR) to xxxx0000 that is fXIN /2
This mode set SCMR to xxxx0000 (fXIN /2)
Main-frequency clock stops and the sub-frequency clock is operates.
Supply current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, comparator voltage divide resistor, LVD circuit and output port drive currents.
5. Main-frequency clock stops and sub-frequency clock in not used
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GMS81C3004
7.4 A/D Comparator Characteristics
(TA=-20~85°C, V DD=5.0V)
Specifications
Parameter
Symbol
Pins
Analog Input Voltage Range
VAIN
CMP0~CMP3
Accuracy
NFS
-
Unit
Min.
Typ.
Max.
VSS
-
VDD
V
-
-
±1
LSB
7.5 AC Characteristics
(TA=-20~+85°C, VDD=5V ±10% , VSS=0V)
Specifications
Parameter
Symbol
Pins
Unit
Min.
Typ.
Max.
fMAIN
XIN
1
-
4.5
MHz
fSUB
SXIN
32
-
35
kHz
tMCPW
XIN
80
-
500
nS
tSCPW
SXIN
5
-
15
µS
tMRCP,tMFCP
XIN
-
-
20
nS
tSRCP,tSFCP
SXIN
-
-
20
nS
Oscillation Stabilizing Time
tST
XIN, XOUT
-
-
20
mS
Interrupt Pulse Width
tIW
INT0, INT1, INT2
2
-
-
tSYS1
RESET Input Width
tRST
RESET
8
-
-
tSYS1
Event Counter Input Pulse
Width
tECW
EC1
2
-
-
tSYS1
tREC,tFEC
EC1
-
-
20
nS
Operating Frequency
External Clock Pulse Width
External Clock Transition Time
Event Counter Transition Time
1. tSYS is one of 2/fMAIN or 8/fMAIN or 16/fMAIN or 64/fMAIN in main clock operation mode,
tSYS is one of 2/fSUB or 8/fSUB or 16/fSUB or 64/fSUB in sub clock operation mode.
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tMCPW
1/fMAIN
tMCPW
VDD-0.5V
XIN
0.5V
tMRCP
tSYS
tMFCP
tSCPW
1/f SUB
tSCPW
VDD-0.5V
SXIN
0.5V
tSRCP
tIW
INT0, INT1
INT2
tSFCP
tIW
0.8VDD
0.2VDD
tRST
RESET
0.2VDD
tECW
tECW
0.8VDD
EC1
0.2VDD
tREC
tFEC
Figure 7-1 Timing Chart
MAR. 1999 Ver 1.01
13
GMS81C3004
7.6 Typical Characteristics
This graphs and tables provided in this section are for design guidance only and are not tested or guranteed.
The data presented in this section is a statistical summary
of data collected on units from different lots over a period
of time. “Typical” represents the mean of the distribution
while “max” or “min” represents (mean + 3σ) and (mean −
3σ) respectively where σ is standard deviation
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified
VDD range). This is for imformation only and divices
are guranteed to operate properly only within the
specified range.
IOH−VOH, VDD=5.5V
IOH−VOH, VDD=3.0V
IOH
(mA)
IOH
(mA) -25°C
-25°C
-8
25°C
-20
85°C
R0,R1,R2 pin
VDD=3.0V
85°C
25°C
-6
−Ta
R−
R
(kΩ)
100
-15
-4
-10
-2
-5
VDD=5.5V
50
0
0
0.5
1.0 1.5
2.0
VOH
(V)
2.5
0
2
IOL−VOL, VDD=3.0V
3
4
VOH
6 (V)
5
-20
-25°C
−Ta
R−
-25°C
25°C
16
40
80
Ta
(°C)
IOL−VOL, VDD=5.5V
IOL
(mA)
IOL
(mA)
0
40
R
(kΩ)
25°C
85°C
100
85°C
12
30
8
20
RESET pin
VDD=3.0V
50
VDD=5.5V
10
4
0
0.5
VIH1
(V)
1.0 1.5
2.0
2.5
0
1
VDD−VIH1
R0,R1,R2 pin
fXIN=4MHz
Ta=25°C
4
4
3
3
2
2
1
1
1
2
3
4
5
VDD
6 (V)
2
3
VDD−VIH2
VIH2
(V)
0
14
VOL
(V)
VOL
5 (V)
4
-20
0
40
80
Ta
(°C)
RESET pin
fSXIN=32kHz
Ta=25°C
0
2
3
4
5
VDD
6 (V)
MAR. 1999 Ver 1.01
GMS81C3004
VDD−VIL1
VIL1
(V)
VDD−VIL2
VIL2
(V)
f XIN=4MHz
Ta=25°C
4
4
3
3
2
2
1
1
0
1
2
3
4
5
VDD
6 (V)
fXIN−VDD
fXIN
(MHz)
Ta=25°C
fSXIN=32kHz
Ta=25°C
0
2
fXIN(25°C)
R = 20kΩ
5
VDD
6 (V)
Operating Area
REXT = 82kΩ
1.05
fXIN
(MHz) Ta= -20~85°C
(Main-clock mode)
4
VDD=3.0V
R = 30kΩ
3
4
fXIN−T
fXIN
4
3
1.00
3
R = 51kΩ
2
0.95
2
1
R = 100kΩ
0.90
1
VDD
6 (V)
0
2
3
4
5
0.85
-20
Normal Operation
IDD1−VDD
IDD
(mA)
0
25
T
75 (°C)
50
0
2
3
4
5
VDD
6 (V)
5
VDD
6 (V)
Normal Operation
IDD3−VDD
I DD
(µA)
Ta=25°C
4
Ta=25°C
20
fSXIN=32kHz
3
fXIN = 4MHz
15
2
10
2MHz
1
5
1MHz
0
2
3
4
5
VDD
6 (V)
0
2
Sleep Mode
ISLEEP(IDD2)−VDD
IDD
(µA)
IDD
(µA)
800
8
fXIN = 4MHz
400
2MHz
200
1MHz
0
2
3
4
MAR. 1999 Ver 1.01
4
5
VDD
6 (V)
Sleep Mode
ISLEEP(IDD4)−VDD
Ta=25°C
600
3
5
VDD
6 (V)
Stop Mode
ISTOP(IDD5)−VDD
IDD
(µA)
fSXIN=32kHz
Ta=25°C
4
6
3
4
2
2
1
0
2
3
4
5
VDD
6 (V)
fSXIN=32kHz
Ta=25°C
0
2
3
4
15
GMS81C3004
8. MEMORY ORGANIZATION
The GMS81C3004 has separate address spaces for Program memory, Data Memory and Display memory. Program memory can only be read, not written to. It can be up
to 4K bytes of Program memory. Data memory can be read
and written to up to 256 bytes including the stack area. Display memory has prepared 40 bytes for LCD.
8.1 Registers
This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
A
ACCUMULATOR
X
X REGISTER
Y
Y REGISTER
SP
PCH
STACK POINTER
PCL
PROGRAM COUNTER
PSW
PROGRAM STATUS
WORD
Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.
The stack can be located at any position within 1C0H to
1FFH of the internal data memory. The SP is not initialized
by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is
used.
Stack Address ( 1C0H ~ 1FFH )
15
8
7
1
Figure 8-1 Configuration of Registers
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc.
The Accumulator can be used as a 16-bit register with Y
Register as shown below.
0
SP
Hardware fixed
Caution:
The Stack Pointer must be initialized by software because its value is undefined after RESET.
Example: To initialize the SP
Y
LDX
TXSP
Y
#0FFH
; SP ← FFH
A
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
Program Counter: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH).
X, Y Registers: In the addressing mode which uses these
index registers, the register contents are added to the specified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators.
Program Status Word: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3 . It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.
Stack Pointer: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).
This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.
16
[Carry flag C]
MAR. 1999 Ver 1.01
GMS81C3004
[Zero flag Z]
or data transfer is "0" and is cleared by any other result.
This flag is set when the result of an arithmetic operation
MSB
PSW
N
LSB
V
G
B
H
I
Z
C
RESET VALUE : 00 H
CARRY FLAG RECEIVES
CARRY OUT
NEGATIVE FLAG
OVERFLOW FLAG
ZERO FLAG
SELECT DIRECT PAGE
when g=1, page is addressed by RPR
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
BRK FLAG
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
[Half carry flag H]
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector address.
[Direct page flag G]
MAR. 1999 Ver 1.01
This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00H to 0FFH when this flag is "0". If it is set to "1",
addressing area is assigned by RPR register (address
0F8H). It is set by SETG instruction and cleared by CLRG.
[Overflow flag V]
This flag is set to "1" when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80 H ). The CLRV instruction
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
17
GMS81C3004
At execution of
a CALL/TCALL/PCALL
At acceptance
of interrupt
01FC
01FC
01FD
01FD
PSW
01FE
PCL
01FF
PCH
01FE
PCL
01FF
PCH
Push
down
At execution
of RET instruction
01FC
01FC
01FD
Push
down
At execution
of RET instruction
01FE
PCL
01FF
PCH
Pop
up
01FD
PSW
01FE
PCL
01FF
PCH
SP before
execution
01FF
01FF
01FD
01FC
SP after
execution
01FD
01FC
01FF
01FF
At execution
of PUSH instruction
PUSH A (X,Y,PSW)
At execution
of POP instruction
POP A (X,Y,PSW)
01FC
01FC
01FD
01FD
01FE
01FF
Pop
up
01C0H
Stack
depth
01FE
A
Push
down
01FF
A
SP before
execution
01FF
01FE
SP after
execution
01FE
01FF
Pop
up
01FFH
Figure 8-4 Stack Operation
18
MAR. 1999 Ver 1.01
GMS81C3004
8.2 Program Memory
A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 4K bytes program memory
space only physically implemented. Accessing a location
above FFFFH will cause a wrap-around to 0000H.
Example: Usage of TCALL
Figure 8-5 , shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFEH and FFFFH as shown in Figure 8-6 .
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA
LRG0
RET
;
FUNC_B: LDA
LRG1
2
RET
;
;TABLE CALL ADD. AREA
;
ORG
0FFC0H
DW
FUNC_A
DW
FUNC_B
As shown in Figure 8-5 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program.
F000H
PROGRAM
MEMORY
FEFFH
FF00H
FFC0H
FFDFH
FFE0H
FFFFH
TCALL
AREA
PCALL
AREA
INTERRUPT
VECTOR AREA
Figure 8-5 Program Memory Map
LDA
#5
TCALL 0FH
:
:
Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0H for TCALL15, 0FFC2 H for
TCALL14, etc., as shown in Figure 8-7 .
1
;TC A LL A DD R E SS A RE A
The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte
interval: 0FFF8H and 0FFF9 H for External Interrupt 1,
0FFFAH and 0FFFBH for External Interrupt 0, etc.
Any area from 0FF00H to 0FFFFH, if it is not going to be
used, its service location is available as general purpose
Program Memory.
Address
0FFE0H
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length.
;1B Y TE INS T RU CT IO N
;IN S TE A D O F 2 B Y TE S
;N O R M A L CA LL
E2
Vector Area Memory
-
E4
-
E6
Key Scan Interrupt Vector Area
E8
Watch Timer Interrupt Vector Area
EA
-
EC
-
EE
-
F0
Watchdog Timer Interrupt Vector Area
F2
External Interrupt 2 Vector Area
F4
Timer/Counter 1 Interrupt Vector Area
F6
-
F8
External Interrupt 1 Vector Area
FA
External Interrupt 0 Vector Area
FC
Basic Interval Timer Interrupt Vector Area
FE
RESET Vector Area
NOTE:
"-" means reserved area.
Figure 8-6 Interrupt Vector Area
MAR. 1999 Ver 1.01
19
GMS81C3004
Address
Address
Program Memory
0FFC0H
C1
TCALL 15
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
PCALL Area Memory
0FF00H
PCALL Area
(192 Bytes)
0FFBFH
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
TCALL 8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
→ rel
PCALL→
→n
TCALL→
4F35
4A
PCALL 35H
TCALL 4
4A
4F
35
~
~
~
~
~
~
0D125H
~
~
NEXT
0FF00H
0FF35H
0FFFFH
01001010
➊
PC: 11111111 11010110
FH FH
DH 6 H
➌
NEXT
0FF00H
0FFD6H
25
0FFD7H
D1
Reverse
➋
0FFFFH
20
MAR. 1999 Ver 1.01
GMS81C3004
Example: The usage software example of Vector address and the initialize part.
ORG
0FFE0H
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
NOT_USED
NOT_USED
NOT_USED
KEY_INT
WT_INT
NOT_USED
NOT_USED
NOT_USED
WDT_INT
INT2
TMR1_INT
NOT_USED
INT1
INT0
BIT_INT
RESET
ORG
0F000H
; Key Scan
; Watch Timer
; Watch Dog Timer
; Int.2
; Timer-1
;
;
;
;
Int.1
Int.0
BIT
Reset
;********************************************
;
MAIN
PROGRAM
*
;*******************************************
;
RESET:
DI
;Disable All Interrupts
CLRG
LDX
#0
RAM_CLR: LDA
#0
;RAM Clear(!0000H->!00BFH)
STA
{X}+
CMPX
#0C0H
BNE
RAM_CLR
;
LDX
#0FFH
;Stack Pointer Initialize
TXSP
;
CALL
LCD_CLR
;Clear LCD display memory
;
LDM
R0, #0
;Normal Port 0
LDM
R0DD,#1000_0010B
;Normal Port Direction
LDM
PUR0,#1000_0010B
;Pull Up Selection Set
LDM
PMR0,#0000_0001B
;R0 port / int
:
:
LDM
PCOR,#1
;Enable Peripheral clock
:
:
MAR. 1999 Ver 1.01
21
GMS81C3004
8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four groups, a user RAM,
control registers, Stack, and LCD memory.
0000H
USER
MEMORY
PAGE0
00BFH
00C0H
00FFH
01C0H
01FFH
CONTROL
REGISTERS
USER MEMORY
OR STACK AREA
PAGE1
UNIMPLEMENTED
AREA
0C00H
0C4FH
LCD DISPLAY
MEMORY
PAGE12
Figure 8-8 Data Memory Map
User Memory
The GMS81C3004 has 256 × 8 bits for the user memory
(RAM).
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0H to 0FFH.
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
More detailed informations of each register are explained
in each peripheral section.
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
Example; To write at CKCTLR
LDM
22
Address
Symbol
R/W
RESET
Value
Addressing
mode
0C0H
0C1H
0C2H
0C4H
0C5H
0C6H
0C7H
0C8H
0C9H
0CAH
0CCH
0CDH
0CEH
0CFH
R0
R1
R2
R4
R5
R6
R7
R0DD
R1DD
R2DD
R4DD
R5DD
R6DD
R7DD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
00000000
00000000
-----000
00000000
00000000
00000000
00000000
byte, bit1
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte2
byte
byte
byte
byte
byte
byte
0D4H
0D5H
0D6H
0D8H
0D9H
0DAH
0DBH
0DCH
0DDH
0DEH
0DFH
PUR0
PUR1
PUR2
IESR
PMR0
IENL
IENH
IRQL
IRQH
SLMR
WDTR
W
W
W
W
W
R/W
R/W
R/W
R/W
W
W
00000000
00000000
-----000
--000000
----0000
--00---0
--00-000
--00---0
--00-000
-------0
00111111
byte
byte
byte
byte
byte
byte, bit
byte, bit
byte, bit
byte, bit
byte
byte
0E4H
0E5H
0E5H
0ECH
0EDH
TM1
T1
TDR1
CMR
CSR
R/W
R
W
W
W
---00000
00000000
Undefined
00-00000
0-----00
byte, bit
byte, bit
byte
byte
byte
0F0H
0F1H
0F3H
0F4H
0F5H
0F6H
0F7H
0F8H
0F9H
0F9H
0FAH
0FBH
0FEH
WTMR
LCR
LPMR
KSCR
KDTR
PMR1
BUR
RPR
BITR
CKCTLR
SCMR
PCOR
LVDR
W
R/W
R/W
R/W
R
R/W
W
R/W
R
W
R/W
W
R/W
----0000
0-00-000
00000000
00000000
00000000
-------0
11111111
----0000
Undefined
----0111
----0000
-------0
---10000
byte
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte
byte, bit
byte, bit
byte
byte, bit
byte
byte, bit
Table 8-1 Control Registers
1. "byte, bit" means that register can be addressed by not only bit
but byte manipulation instruction.
2. "byte" means that register can be addressed by only byte
manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for
clearing bit.
CKCTLR,#09H ;Divide ratio ÷8
MAR. 1999 Ver 1.01
GMS81C3004
Stack Area
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-4 on page 18.
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the program counter and flags.
LCD Display Memory
Bit 7
0C0H
R0
xxxx xxxx
0C1H
R1
xxxx xxxx
0C2H
R2
0C4H
R4
xxxx xxxx
0C5H
R5
xxxx xxxx
0C6H
R6
xxxx xxxx
0C7H
R7
xxxx xxxx
0C8H
R0DD
0000 0000
0C9H
R1DD
0000 0000
0CAH
R2DD
0CCH
R4DD
0000 0000
0CDH
R5DD
0000 0000
0CEH
R6DD
0000 0000
0CFH
R7DD
0000 0000
0D4H
PUR0
0000 0000
0D5H
PUR1
0000 0000
0D6H
PUR2
-
-
0D8H
IESR
-
-
0D9H
PMR0
-
-
-
-
0DAH
IENL
-
-
KSEN
WTEN
-
-
-
WDTEN
--00 ---0
0DBH
IENH
-
-
INT2EN
T1EN
-
INT1EN
INT0EN
BITEN
--00 -000
MAR. 1999 Ver 1.01
-
-
-
-
-
Bit 4
-
-
-
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
Reset value
Symbol
-
Bit 5
See "15.4 LCD Display Memory" on page 59.
Address
-
Bit 6
LCD display data area is handled in LCD section.
-
---- -xxx
-
---- -000
-
---- -000
--00 0000
---- 0000
23
GMS81C3004
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
Reset value
IRQL
-
-
KSIF
WTIF
-
-
-
WDTIF
--00 ---0
0DDH
IRQH
-
-
INT2IF
T1IF
-
INT1IF
INT0IF
BITIF
--00 -000
0DEH
SLMR
-
-
-
-
-
-
-
0DFH
WDTR
0E4H
TM1
0E5H 1
T1
0000 0000
0E5H 1
TDR1
Undefined
0ECH
CMR
0EDH
CSR
0F0H
WTMR
0F1H
LCR
0F3H
LPMR
0000 0000
0F4H
KSCR
0000 0000
0F5H
KDTR
0000 0000
0F6H
PMR1
0F7H
BUR
0F8H
RPR
0F9H 2
BITR
0F9H 2
CKCTLR
-
-
-
-
---- 0111
0FAH
SCMR
-
-
-
-
---- 0000
0FBH
PCOR
-
-
-
-
0FEH
LVDR
-
-
-
Address
Symbol
0DCH
---- ---0
0011 1111
-
-
-
---0 0000
-
-
00-0 0000
-
-
-
-
-
-
-
-
-
-
-
0--- --00
---- 0000
-
-
-
-
0-00 -000
-
-
R13/BUZ
---- ---0
1111 1111
-
-
-
-
---- 0000
Undefined
-
-
-
---- ---0
---1 0000
1. The register T1 and TMR1 are located at same address. Address 0E5H is read as T1, and written to TMR1.
2. The register BITR and CKCTLR are located at same address. Address 0F9H is read as BITR, and written to CKCTLR.
SFR bit and byte addressable
SFR not bit addressable
- : this bit location is reserved
24
MAR. 1999 Ver 1.01
GMS81C3004
8.4 Addressing Mode
The GMS81C3004 uses six addressing modes;
(3) Direct Page Addressing → dp
• Register addressing
In this mode, a address is specified within direct page.
• Immediate addressing
Example; G=0
• Direct page addressing
C535
LDA
;A ←RAM[35H]
35H
• Absolute addressing
• Indexed addressing
35H
• Register-indirect addressing
data
➋
~
~
(1) Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
~
~
0E550H
C5
0E551H
35
➊
data → A
(2) Immediate Addressing → #imm
In this mode, second byte (operand) is accessed as a data
immediately.
(4) Absolute Addressing → !abs
Example:
0435
ADC
#35H
MEMORY
04
A+35H+C → A
35
Absolute addressing sets corresponding memory data to
Data , i.e. second byte(Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY
Example;
0735F0
ADC
;A ←ROM[0F035H]
!0F035H
When G-flag is 1, then RAM address is difined by 16-bit
address which is composed of 8-bit RAM paging register
(RPR) and 8-bit immediate data.
Example: G=1, RPR=0CH
E45535
LDM
0F035H
data
~
~
0F100H
➊
data ← 55H
data
0C35H
➋
35H,#55H
~
~
~
~
0F100H
E4
0F101H
55
0F102H
35
MAR. 1999 Ver 1.01
~
~
➊
A+data+C → A
07
0F101H
35
0F102H
F0
address: 0F035
➋
25
GMS81C3004
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
Example; Addressing accesses the address 0135H regardless of G-flag and RPR.
983501
INC
;A ←ROM[135H]
!0135H
→ {X}+
X indexed direct page, auto increment→
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
LDA, STA
Example; G=0, X=35H
DB
135H
data
~
~
LDA
{X}+
➌
~
~
➋
35H
data+1 → data
0F100H
98
➊
0F101H
35
address: 0135
0F102H
01
➋
data
~
~
~
~
data → A
➊
36H → X
DB
(5) Indexed Addressing
X indexed direct page (no offset) → {X}
X indexed direct page (8 bit offset) → dp+X
In this mode, a address is specified by the X register.
This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15H, G=1, RPR=01H
D4
LDA
{X}
;ACC←RAM[X].
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
Example; G=0, X=0F5H
C645
115H
data
~
~
0E550H
LDA
45H+X
➋
~
~
data → A
➊
3AH
data
➌
D4
~
~
26
➋
~
~
0E550H
C6
0E551H
45
data → A
➊
45H+0F5H=13AH
MAR. 1999 Ver 1.01
GMS81C3004
Y indexed direct page (8 bit offset) → dp+Y
3F35
JMP
[35H]
This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in
Direct page.
This is same with above (2). Use Y register instead of X.
35H
0A
36H
E3
Y indexed absolute → !abs+Y
~
~
Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify memory in whole area.
Example; Y=55H
D500FA
LDA
~
~
D5
00
0F102H
FA
~
~
~
~
➊
3F
35
!0FA00H+Y
0F101H
➋ jump to address 0E30AH
NEXT
0FA00H
0F100H
0FA55H
0E30AH
~
~
➊
0FA00H+55H=0FA55H
~
~
➋
data
➌
data → A
X indexed indirect → [dp+X]
Processes memory data as Data, assigned by 16-bit pair
m em ory w hich is deter mined by pair data
[dp+X+1][dp+X] Operand plus X-register data in Direct
page.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0, X=10H
1625
ADC
[25H+X]
(6) Indirect Addressing
Direct page indirect → [dp]
Assigns data address to use for accomplishing command
which sets memory data(or pair memory) by Operand.
Also index can be used with Index register X,Y.
JMP, CALL
35H
05
36H
E0
0E005H
~
~ ➋
~
~
0E005H
~
~
Example; G=0
0FA00H
~
~
16
25
MAR. 1999 Ver 1.01
➊ 25 + X(10) = 35H
data
➌ A + data + C → A
27
GMS81C3004
Y indexed indirect → [dp]+Y
Absolute indirect → [!abs]
Processes momory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y-register data.
The program jumps to address specified by 16-bit absolute
address.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0, Y=10H
1725
ADC
JMP
Example; G=0
1F25E0
JMP
[!0C025H]
[25H]+Y
PROGRAM MEMORY
25H
05
0E025H
25
26H
E0
0E026H
E7
~
~
0E015H
~
~
0FA00H
~
~
➊
0E725 H
~
~
0FA00H
17
➌
➋
jump to
address 0E30AH
NEXT
~
~
~
~
25
28
0E005 H + Y(10) = 0E015H
➊
data
~
~
➋
~
~
1F
25
A + data + C → A
E0
MAR. 1999 Ver 1.01
GMS81C3004
9. I/O PORTS
The GMS81C3004 has seven ports (R0, R1, R2, R4, R5,
R6, and R7), and LCD segment port (SEG0~SEG39), and
LCD common port (COM0~COM7).
These ports pins may be multiplexed with an alternate
function for the peripheral features on the device. In general, in a initial reset state, R0,R1,R2 ports are used as a
general purpose input port and R4, R5, R6 and R7 ports are
used as LCD segment drive output port.
9.1 Registers for Port
Port Data Registers
The Port Data Registers in I/O buffer in each seven ports
(R0,R1,R2,R4,R5,R6,R7) are represented as a Type D flipflop, which will clock in a value from the internal bus in response to a "write to data register" signal from the CPU.
The Q output of the flip-flop is placed on the internal bus
in response to a "read data register" signal from the CPU.
The level of the port pin itself is placed on the internal bus
in response to "read data register" signal from the CPU.
Some instructions that read a port activating the "read register" signal, and others activating the "read pin" signal
Port Direction Registers
All pins have data direction registers which can define
these ports as output or input. A "1" in the port direction
register configure the corresponding port pin as output.
Conversely, write "0" to the corresponding bit to specify it
as input pin. For example, to use the even numbered bit of
R0 as output ports and the odd numbered bits as input
ports, write "55H" to address 0C8H (R0 port direction register) during initial setting as shown in Figure 9-1 .
Pull-up Control Registers
The R0, R1, and R2 ports have internal pull-up resistors.
Figure 9-2 shows a functional diagram of a typical pull-up
port. It is connected or disconnected by Pull-up Control
register (PURn). The value of that resistor is typically
100kΩ. Refer to DC characteristics for more details.
When a port is used as key input, input logic is firmly either low or high, therefore external pull-down or pull-up
resisters are required practically. The GMS81C3004 has
internal pull-up, it can be logic high by pull-up that can be
able to configure either connect or disconnect individually
by pull-up control registers PURn.
When ports are configured as inputs and pull-up resistor is
selected by software, they are pulled to high. If port is configured as an output, pull-up is disabled automatically regardless of setting of PURn.
VDD
VDD
PULL-UP RESISTOR
All the port direction registers in the GMS81C3004 have 0
written to them by reset function. On the other hand, its initial status is input.
PORT PIN
GND
WRITE "55H" TO PORT R0 DIRECTION REGISTER
0C0H
R0 DATA
0C1H
R1 DATA
~
~
0C8H
0C9H
0 1 0 1 0 1 0 1
7 6 5 4 3 2 1 0
Pull-up control bit
0: Disconnect
1: Connect
BIT
Figure 9-2 Pull-up Port Structure
~
~
R0 DIRECTION
I O I O
R1 DIRECTION
7 6 5 4 3 2 1 0
I O I O PORT
I : INPUT PORT
O : OUTPUT PORT
Figure 9-1 Example of port I/O assignment
MAR. 1999 Ver 1.01
29
GMS81C3004
9.2 I/O Ports Configuration
R0 Ports
R0 is an 8-bit CMOS bidirectional I/O port (address
0C0H). Each I/O pin can independently used as an input or
an output through the R0DD register (address 0C8H).
R0 has internal pull-ups that is independently connected or
disconnected by PUR0. The control registers for R0 are
shown below.
R1 has internal pull-ups that is independently connected or
disconnected by register PUR1. If the key scan function is
used, these pin can input the key switch signal without external pull-up registers. For more details refer to "14.. KEY
SCAN" on page 53.
The control registers for R1 are shown below.
ADDRESS : 0C1H
RESET VALUE : Undefined
R1 Data Register
ADDRESS : 0C0H
RESET VALUE : Undefined
R0 Data Register
R0
R07 R06 R05 R04 R03 R02 R01 R00
ADDRESS : 0C8H
RESET VALUE : 00H
R0 Direction Register
R1
R17 R16 R15 R14 R13 R12 R11 R10
ADDRESS : 0C9H
RESET VALUE : 00H
R1 Direction Register
R1DD
Port Direction
0: Input
1: Output
R0DD
Port Direction
0: Input
1: Output
R0 Pull-up Selection Register
ADDRESS :0D4H
RESET VALUE : 00H
R1 Pull-up Selection Register
PUR1
Pull-up select
0: Without pull-up
1: With pull-up
PUR0
Pull-up select
0: Without pull-up
1: With pull-up
In addition, Port R0 is multiplexed with various special
features. The control register PMR0 (address 0D9H) controls the selection of alternate function. After reset, this
value is "0", port may be used as normal I/O port.
To use alternate function such as External Interrupt rather
than normal I/O, write "1" in the corresponding bit of
PMR0.
Port R1 is multiplexed with various special features.The
control registers controls the selection of alternate function. After reset, this value is "0", port may be used as normal I/O port. The way to select alternate function such as
comparator input or buzzer will be shown in each peripheral section.
In addition, R1 port is used as key scan function which operate with normal input port.
Port Pin
Port Pin
Alternate Function
R00
R01
R02
R03
R06
INT0 (External Interrupt 0)
INT1 (External Interrupt 1)
INT2 (External Interrupt 2)
EC1 (External count input to Timer/Counter 1)
LCDCK (LCD clock output)
R1 Ports
R1 is an 8-bit CMOS bidirectional I/O port (address
0C1H). Each I/O pin can independently used as an input or
an output through the R1DD register (address 0C9H).
30
ADDRESS : 0D5 H
RESET VALUE : 00 H
R10
R11
R12
R13
R14
R15
R16
R17
Alternate Function
KS0
KS1
KS2
KS3/BUZ (Buzzer frequency output)
KS4/CMP0 (Comparator input 0)
KS5/CMP1 (Comparator input 1)
KS6/CMP2 (Comparator input 2)
KS7/CMP3 (Comparator input 3)
Input or output is configured automatically by each function register (CSR, PMR1, KSCR) regardless of R1DD.
MAR. 1999 Ver 1.01
GMS81C3004
R2 Port
R2 is an 3-bit CMOS bidirectional I/O port (address
0C2H). Each I/O pin can independently used as an input or
an output through the R2DD register (address 0CAH).
R2 has internal pull-ups that is independently connected or
disconnected by PUR2 (address 0D6H). The control registers for R2 are shown as below.
-
-
-
-
-
R2 Direction Register
R2DD
-
Example: To use as I/O ports
:
:
LDM
:
:
:
LPMR,#xxxx_xx11B
ADDRESS: 0C2H
RESET VALUE: Undefined
R2 Data Register
R2
On the initial reset, R4 is configured as LCD segment output ports regardless of Direction Register R4DD. The LCD
Port Mode Register (LPMR) should be properly set to be
used as normal I/O.
-
-
-
R22 R21 R20
x: Don’t care
ADDRESS : 0CAH
RESET VALUE : 00H
R5 Port / SEG8 ~ SEG15
-
Port Direction
0: Input
1: Output
R5 is an 8-bit CMOS bidirectional I/O port (address
0C5H). Each I/O pin can independently used as an input or
an output through the R5DD register (address 0CDH).
R5 is shared with LCD segment ports.
ADDRESS : 0D6 H
RESET VALUE : 00 H
R2 Pull-up Selection Register
PUR2
-
-
-
-
-
ADDRESS: 0C5H
RESET VALUE : Undefined
R5 Data Register
Pull-up select
0: Without pull-up
1: With pull-up
R5
R57 R56 R55 R54 R53 R52 R51 R50
R5 Direction Register
R5DD
R4 Port / SEG0 ~ SEG7
Port Direction
0: Input
1: Output
R4 is an 8-bit CMOS bidirectional I/O port (address
0C4H). Each I/O pin can independently used as an input or
an output through the R4DD register (address 0CCH).
R4 has difference that it doesn’t have internal pull-ups and
is shared with LCD segment ports.
R4 Data Register
R4
ADDRESS :0CDH
RESET VALUE : 00H
ADDRESS : 0C4H
RESET VALUE : Undefined
On the initial reset, R5 is configured as LCD segment output port regardless of Direction Register R5DD. The LCD
Port Mode Register (LPMR) should be set properly to be
used as normal I/O. Refer to example below.
Example: To use as an I/O port
R17 R16 R15 R14 R13 R12 R11 R10
R4 Direction Register
ADDRESS : 0CCH
RESET VALUE : 00H
R4DD
Port Direction
0: Input
1: Output
MAR. 1999 Ver 1.01
:
:
LDM
:
:
:
LPMR,#xxxx_11xxB
x: Don’t care
31
GMS81C3004
R6 Port / SEG16 ~ SEG23
R7 Port / SEG24 ~ SEG31
R6 is an 8-bit CMOS bidirectional I/O port (address
0C6H). Each I/O pin can independently used as an input or
an output through the R6DD register (address 0CEH).
R7 is an 8-bit CMOS bidirectional I/O port (address
0C7H). Each I/O pin can independently used as an input or
an output through the R7DD register (address 0CFH).
R6 is shared with LCD segment ports.
R7 is shared with LCD segment ports.
ADDRESS : 0C6H
RESET VALUE : Undefined
R6 Data Register
R6
R67 R66 R65 R64 R63 R62 R61 R60
R6 Direction Register
ADDRESS : 0CEH
RESET VALUE : 00H
R6DD
ADDRESS : 0C7H
RESET VALUE : Undefined
R7 Data Register
R7
R77 R76 R75 R74 R73 R72 R71 R70
R7 Direction Register
ADDRESS : 0CFH
RESET VALUE : 00H
R7DD
Port Direction
0: Input
1: Output
Port Direction
0: Input
1: Output
After reset, R6 is initialized as LCD segment output ports
regardless of Direction Register R6DD. The LCD Port
Mode Register (LPMR) should be set properly to use as
normal I/O. Refer to example below.
After reset, R7 is initialized as LCD segment output ports
regardless of Direction Register R7DD. The LCD Port
Mode Register (LPMR) should be set properly to use as
normal I/O. Refer to example below.
Example: To use as an I/O port
Example: To use as an I/O port
LDM
x: Don’t care
LPMR,#xx11_xxxxB
LDM
LPMR,#11xx_xxxxB
x: Don’t care
SEG0~SEG39
Segment signal output pins for the LCD display.
COM0~COM7
Common signal output pins for the LCD display.
32
MAR. 1999 Ver 1.01
GMS81C3004
10. CLOCK GENERATOR
As shown in Figure 10-1 , the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It contains two oscillators: a main-frequency clock oscillator and
a sub-frequency clock oscillator. Power consumption can
be reduced by switching them to the low power operation
frequency clock can be easily obtained by attaching a resonator between the XIN and X OUT pin and the SX IN and
SXOUT pin, respectively. The system clock can also be obtained from the external oscillator.
The registers are shown in Figure 10-2 .
The clock generator produces the system clocks forming
clock pulse, which are supplied to the CPU and the peripheral hardware. The internal system clock can be selected
by bit2, and bit3 of the system clock mode register, SCMR.
To the peripheral block, the clock among the not-divided
original clocks, divided by 2, 4,..., up to 1024 can be provided. Peripheral clock is enabled or disabled by bit 0 of
the peripheral clock enable register (ENPCK).
Instruction cycle time
CPU clock
fMAIN = 4.19MHz
fSUB = 32.768kHz
÷2
0.48 us
61 us
÷8
1.90 us
244 us
÷ 16
3.80 us
488 us
÷ 64
15.30 us
1953 us
select clock
SX IN PIN
1X
fEX
0X
XIN PIN
÷2
PRESCALER
MPX
÷8
÷16
Internal system clock
MPX
÷64
PRESCALER
2
2
ENPCK
[0FAH]
[0FBH]
SCMR
System clock
mode register
PCOR
Peripheral clock
enable register
÷1
÷2 ÷4
÷8 ÷16
÷32
÷64
÷256
÷1024
÷128
÷512
Peripheral clock
Figure 10-1 Block Diagram of Clock Generator
Example; PCOR setting and Basic Interval Timer
Note: On the initial reset, all peripherals are stopped because peripheral clock is not supplied to each function
block. Therefore, Peripheral Clock Enable Register, PCOR
must be written to “1” in software initial part. Then, timer and
other functions may be operated by provided clock.
MAR. 1999 Ver 1.01
PCOR
CKCTLR
IENL
IENH
BITEN
EQU
EQU
EQU
EQU
EQU
0FBH
0F9H
0DAH
0DBH
0,IENH
LDM
LDM
SET1
EI
PCOR,#1
CKCTLR,#0CH
BITEN
33
GMS81C3004
MSB
R/W
SCMR
-
-
-
R/W
R/W
LSB
R/W
-
ADDRESS: 0FAH
INITIAL VALUE: ---- 0000
System clock control
00: main clock on
01: main clock on
10: sub clock on (main clock on)
11: sub clock on (main clock off)
System clock source select
00: fM÷2 or f S÷2
01: fM÷8 or fS÷8
10: fM÷16 or fS÷16
11: fM÷64 or fS÷64
MSB
PCOR
-
LSB
W
-
-
-
-
-
-
ENPCK
fM: fMAIN
fS: fSUB
ADDRESS: 0FBH
INITIAL VALUE: ---- ---0
Peripheral clock control
0: Off (All function block are disabled except CPU)
1: On
Figure 10-2 SCMR, PCOR: System Clock Control Registers
34
MAR. 1999 Ver 1.01
GMS81C3004
10.1 Operation Mode
Sub-clock operating mode
The system clock controller starts or stops the main-frequency clock oscillator and switches between the sub frequency clock. The operating mode is generally divided
into the main-clock mode and the sub-clock mode, which
are controlled by System clock mode register (SCMR).
Figure 10-3 shows the operating mode transition diagram.
This mode is low-frequency operating mode
In this mode, the high-frequency clock oscillation is stops
to operate the CPU and the peripheral hardware on the
low-frequency clock, thereby reducing power consumption
System clock control is performed by the system clock
mode register, SCMR. During reset, this register is initialized to "0" so that the main-clock operating mode is selected.
SLEEP mode
In this mode, the CPU clock stops while peripherals and
the oscillation source continue to operate normally.
Main-clock operating mode
STOP mode
This mode is fast-frequency operating mode.
The CPU and the peripheral hardwares are operated on the
high-frequency clock. At reset release, this mode is invoked.
Main - Oscillating
Sub - Oscillating
In this mode, the system operations are all stopped, holding
the internal states valid immediately before the stop at the
low power consumption level.
Main - According to SCMR
Sub - Oscillating
Instruction
n
te 1
no
no
fe r
to
RESET
All Interrupts
ctio
to
Release (Main clock)
n
c ti o
tru
ns
NOTE2:
tru
fe r
te 2
Re
RESET
Key Scan Interrupt
Watch Timer Interrupt
Timer interrupt (EC1)
External Interrupt
In s
Re
ST
OP
I
NOTE1:
Sub-clock
Mode
RESET
Operation
t
se
Re
Main: Stopped
Sub: Oscillating
Instruction
Reset
Main-clock
Mode
Re
Main: Oscillating
Sub: Oscillating
se
t
SLEEP
Mode
STOP
Mode
Main: According to SCMR
Sub: Oscillating
Figure 10-3 Operating Mode
MAR. 1999 Ver 1.01
35
GMS81C3004
10.2 Operation Mode Switching
In the Main-clock operation mode, only the high-frequency clock oscillator is used.
In the Sub-clock operation mode, the high-frequency clock
oscillation stops, enabling the low power voltage operation
or the low power consumption operation. Instruction execution does not stop when the operation speed switching is
performed. However, some peripheral hardware capabilities may be affected. For details, refer to the description of
the relevant operation.
The following describes the switching between the Mainclock and the Sub-clock operations. During reset, the system clock mode register is initialized at the Main-clock
mode. It must be set to the Sub-clock operation for the lowpower consumption mode.
Switching from main clock operation to subclock operation
First, write "10B" into lower 2 bits of SCMR to switch the
main system clock to the sub-frequency clock.
Next, write "11B" to turn off main frequency oscillation.
Example:
:
:
:
MOV
MOV
:
:
SCMR,#2
SCMR,#3
;Switch to sub mode
;Turn off main clock
First, write "10B" into lower 2 bits of the SCMR to turn on
the main-frequency oscillation, when the stabilization
(warm-up) has been taken by the software delay routine.
Sub clock operation mode can also be released by setting
the RESET pin to low, which immediately performs the reset operation. After reset, the GMS81C3004 is placed in
main frequency operation mode.
Example:
36
;20ms software delay
DLY:
LDY
#0
DLP0:
LDA
#0
DLP1:
NOP
INC
A
BCC
DLP1
INC
Y
CMPY #20
BCC
DLP0
RET
Shifting from the Normal operation to the SLEEP
mode
By setting bit 0 of SMR, the CPU clock stops and the
SLEEP mode is invoked. The CPU stops while other peripherals are operate normally.
The way of release from this mode is RESET and all available interrupts.
For more detail, See "18.1 SLEEP Mode" on page 68
Returning from Sub clock operation to main
clock operation
:
:
:
MOV
CALL
MOV
:
:
:
SCMR,#2
DLY
SCMR,#0
Shifting from the Normal operation to the STOP
mode
By executing STOP instruction, the main-frequency clock
oscillation stops and the STOP mode is invoked. But subfrequency clock oscillation is operated continuously.
After the STOP operation is released by reset, the operation mode is changed to Main-clock mode.
The methods of release are RESET, Key scan interrupt,
Watch Timer interrupt, Timer/Event counter1 (EC1 pin),
and External Interrupt.
For more details, see "18.2. STOP Mode" on page 69.
Note: In the STOP and SLOW operating modes, the power
consumed by the oscillator and the internal hardware is reduced. However, the power for the pin interface (depending
on external circuitry and program) is not directly associated
with the low-power consumption operation. This must be
considered in system design as well as interface circuit design.
;Turn on main-clock
;Wait until stable
;Move to main mode
MAR. 1999 Ver 1.01
GMS81C3004
~
~
Sub freq. clock
(SX IN pin)
~
~
~
~
Main freq. clock
(XIN pin)
~
~
Operation clock
~
~
Main-clock operation
Sub-clock operation
Changed to the Sub-clock
SCMR ← XXXX XX10B
Turn off main clock
SCMR ← XXXX XX11B
(a) Main clock mode → Sub clock mode
~
~
~
~
Main freq. clock
(XIN pin)
Stabilizing Time > 20ms
~
~
Sub freq. clock
(SX IN pin)
Operation clock
~
~
Sub-clock operation
Changed to the Transition
SCMR ← XXXX XX10B
Main-clock operation
Changed to the Main-clock
SCMR ← XXXX XX00B
or 01B
(b) Sub clock → Main clock
Figure 10-4 System Clock Switching Timing
MAR. 1999 Ver 1.01
37
GMS81C3004
11. TIMER
11.1 Basic Interval Timer
The GMS81C3004 has one 8-bit Basic Interval Timer that
is free-run and can not stop. Block diagram is shown in
Figure 11-1 .
rupt to be generated. The Basic Interval Timer is controlled
by the clock control register (CKCTLR) shown in Figure
11-2 .
The Basic Interval Timer generates the time base for key
scanning, watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (BITIF). As the count
overflow from FFH to 00H, this overflow causes the inter-
Source clock can be selected by lower 3 bits of CKCTLR.
fM÷23 or fS÷23
fM÷24 or fS÷24
f M÷2 5 or fS÷25
f M÷2 6 or fS÷26
f M÷2 7 or fS÷27
fM÷28 or fS÷28
MUX
BITR and CKCTLR are located at same address, and address 0F9H is read as a BITR, and written to CKCTLR..
8-bit up-counter
source
clock
overflow
BITIF
BITR
[0F9 H]
f M÷2 9 or fS÷29
fM÷210 or fS÷210
Basic Interval Timer Interrupt
Watchdog timer clock (WDTCK)
clear
Select Input clock 3
BITCK
BTCL
CKCTLR
[0F9H]
Basic Interval Timer
clock control register
Internal bus line
Figure 11-1 Block Diagram of Basic Interval Timer
Source clock
CKCTLR
[2:0]
000
001
010
011
100
101
110
111
S C M R [1:0]=
00 or 01
S C M R[1:0]=
10 or 11
fM÷23
fM÷24
fM÷25
fM÷26
fS÷23
fS÷24
fS÷25
fS÷26
fM÷27
fM÷28
fM÷29
fM÷210
fS÷27
fS÷28
fS÷29
fS÷210
Interrupt (overflow) Period
At fMAIN=4.19MHz
At fSUB=32.768kHz
0.488 ms
0.976
1.953
3.906
7.812
15.625
31.250
62.500
62.5 ms
125.0
250.0
500.0
1000.0
2000.0
4000.0
5000.0
Table 11-1 Basic Interval Timer Interrupt Time
fMAIN : main clock frequency (ex: 4.19MHz)
fSUB: sub clock frequency (ex: 32.768kHz)
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MAR. 1999 Ver 1.01
GMS81C3004
7
-
CKCTLR
6
-
5
-
4
-
3
BTCL
2
1
BITCK
0
ADDRESS: 0F9H
INITIAL VALUE: ----0111
Basic Interval Timer source clock select
000: f M÷2 3 or fS÷23
001: f M÷2 4 or fS÷24
f M: main-clock frequency
010: f M÷2 5 or fS÷25
011: f M÷2 6 or fS÷26
fS: sub-clock frequency
100: f M÷2 7 or fS÷27
101: f M÷2 8 or fS÷28
110: f M÷2 9 or fS÷29
111: f M÷2 10 or fS÷210
Caution:
Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.
7
Clear bit
0: Normal operation (free-run)
1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically
after one machine cycle.
6
5
4
3
2
1
0
ADDRESS: 0F9H
INITIAL VALUE: 00000000
BITR
8-BIT BINARY COUNTER
Figure 11-2 BITR: Basic Interval Timer Mode Register
11.2 Timer/Event Counter 1
Timer/Event Counter 1 consists of prescaler, multiplexer,
8-bit compare data register, 8-bit count register, Control
register, and Comparator as shown in Figure 11-3 .
from pin EC1.
The contents of TDR1 are compared with the contents of
up-counter T1. If a match is found, a timer/counter 1 interrupt (T1IF) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared.
The timer/counter 1 has two operating modes. One is the
timer mode which is operated by internal clock, other is
event counter mode which is operated by external clock
[0FAH]
SCMR[1:0]
same address
MPX
0X
SX IN PIN
1X
EC1 PIN
8-bit Timer 1 compare data register
TDR1
PRESCALER
[0E5 H]
Comparator
÷2
÷8
÷32
÷128
÷512
XIN PIN
source
clock
MUX
Timer 1 Interrupt
Match
T1
8-bit up-counter
3
T1CN
Clear
[0E5H]
T1CK
Select Input clock
[0E4 H]
T1ST
TM1
Timer/Counter 1 control register
Caution:
Both register are in same address,
when write, to be a TDR1,
when read, to be a T1.
Figure 11-3 Block Diagram of Timer/Event Counter
MAR. 1999 Ver 1.01
39
GMS81C3004
Note: The content of TDR1 must be initialized (by software) with the value between 1H and 0FFH,not to 0.
TM1
7
-
6
-
R/W
4
5
-
R/W
3
R/W
2
R/W
1
R/W
0
ADDRESS: E4 H
INITIAL VALUE:---0 0000
T1CKS
T1ST T1CN
Timer/Counter 1 source clock select
000: EC1 (External clock from EC1 pin)
001: ÷2
010: ÷8
011: ÷32
100: ÷128
101: ÷512
110: reserved
111: reserved
Reserved
Timer/Counter 1 enable flag
0: Disable count
1: Enable count
Timer/Counter 1 start/stop control flag
0: stop count
1: clearing the T1 counter and start count again
TDR1
or
T1
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
ADDRESS: E5H
INITIAL VALUE: Undefined
KDTR
STATUS
SYMBOL
When read
When write
T1
TDR1
DESCRIPTION
8-bit Timer count register
8-bit comparing data register
Figure 11-4 Timer Mode Register and TDR1, T1 Registers
Timer Mode
(T1IF) is generated and the up-counter is cleared to 0.
Counting up is resumed after the up-counter is cleared.
In the timer mode, the internal clock is used for counting
up. Thus, you can think of it as counting internal clock input. The contents of TDR1 are compared with the contents
of up-counter, T1. If match is found, a timer 1 interrupt
As the value of TDR1 is changeable by software, time interval is set as you want
Start count
1
n
2
3
n-2
n-1
n
0
1
2
3
4
~
~
~ ~
TDR1
0
~
~ ~
~
Up-counter
~
~
Source clock
Match
Detect
T1IF interrupt
Counter
Clear
~
~
Figure 11-5 Timer Mode Timing Chart
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MAR. 1999 Ver 1.01
GMS81C3004
Clock Source
Value of
TM[2:0]
000
001
010
011
100
101
110
111
S C M R[1:0]= 00 or
01
Resolution
S CM R [1:0]= 10 or
11
fEC1
fM÷2
fEC1
fS÷2
fM÷23
fM÷25
fM÷27
fM÷29
Invalid
Invalid
fS÷23
fS÷25
fS÷27
fS÷29
-
Maximum Time Setting
A t f MAIN=4.19M Hz
A t f SUB = 32.768kH z
A t f MAIN = 4.19M H z
A t fSUB = 32.768kH z
1/fEC1 s
0.476 us
1.907 us
7.629 us
30.517 us
122.070 us
1/fEC1 s
61.03 us
244.14 us
976.56 us
3906.25 us
15625.00 us
1/fEC1 x 256 s
122.1 us
488.3 us
1953.1 us
7812.5 us
31250.0 us
1/fEC1 x 256 s
15.6 ms
62.5 ms
250.0 ms
1000.0 ms
4000.0 ms
-
-
-
-
Table 11-2 Timer/Counter 1 Source clock Interrupt Time
fM : main-clock frequency, fS: sub-clock frequency, fEC1: external event from EC1 pin frequency
Event counter Mode
In this mode, counting up is started by an external trigger.
This trigger means falling edge of the EC1 pin input.
Source clock is used as an internal clock selected with
TM1. The contents of TDR1 are compared with the contents of the up-counter. If a match is found, an T1IF interrupt is generated, and the counter is cleared to "0". The
counter is restarted by the falling edge of the EC1 pin input.
The maximum frequency applied to the EC1 pin is fMAIN/
2 [Hz] in main clock mode, and fSUB/2[Hz] is sub clock
mode.
In order to use event counter function, the bit EC1S of the
Port Mode Register PMR0(address 0D9H) is required to be
set to "1".
After reset, the value of TDR1 is undefined, it should be
initialized to between 1H~FFH not to "0" Start count
2
n
n-1
n
0
1
2
~
~ ~
~
TDR1
1
0
~ ~
~
~
Up-counter
~
~
EC1 pin input
T1IF interrupt
~
~
Figure 11-6 Event Counter Mode Timing Chart
The interval period of Timer is calculated as below equation.
1
Period = ---------- × Prescaler ratio × TDR
f XIN
MAR. 1999 Ver 1.01
Example:
Every 1ms interrupt request flag is generated at 4MHz
:
LDM
LDM
LDM
SET1
EI
PCOR,#1
TM1,#1BH
TDR1,#125
T1E
; Enable Peri. Clock
; divide by 8
; 8us x 125= 1ms
; Enable Timer 1 Int.
; Enable Master Int.
41
GMS81C3004
TDR1
TDR1=n
~~
up
-c
ou
nt
PCP
~~
8
~~
n
n-1
n-2
7
6
5
4
3
2
1
0
TIME
Interrupt period
= PCP x n
Timer 1 (T1IF)
Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 11-7 Count Example of Timer / Event counter
TDR1
disable
up
-c
ou
nt
~~
clear & start
enable
stop
~~
TIME
Timer 1 (T1IF)
Interrupt
Occur interrupt
Occur interrupt
T1ST
Start & Stop
T1CN
Control count
T1ST = 1
T1ST = 0
T1CN = 1
T1CN = 0
Figure 11-8 Count Operation of Timer / Event counter
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MAR. 1999 Ver 1.01
GMS81C3004
11.3 Watch Timer
The watch timer consists of the clock selector, 14-bit binary counter and Watch timer mode register. It is a multi-purpose timer. It is generally used for watch design. Since
Sub-frequency keeps running in spite of Stop mode, Watch
Timer continues its operation.
ADDRESS : 0F0 H
RESET VALUE : ----0000
Watch Timer Mode Register
W
WTMR
-
-
Bit 3 of WTMR enables or stops counter, and bit 2 and bit
1 determine the clock source between main or sub frequency. Because in Stop Mode, main-frequency clock stops,
clock source should be sub-frequency clock.
-
W
W
W
Interrupt interval
0: ÷26 (2 Hz)
1: ÷214 (256 Hz)
Reserved
Source clock selection
00: fSUB (sub clock)
01: fMAIN ÷128 (main clock)
10: inhibit
11: inhibit
In case that circuit uses 4.19MHz and Sub-frequency is
32.768kHz, bit 0 of WTMR may choose either 2Hz or
256Hz.
Watch Timer control bit
0: Disable (count stop)
1: Enable
Figure 11-9 Watch Timer Mode Register
Key Scan & LCD clock source
MUX
fSUB
00
fMAIN÷2 7
01
14 BIT COUNTER
÷26
select
source clock
select
2
MUX
WTMR
÷214
Watch Timer Interrupt
EXAMPLE:
WHEN f SUB = 32.768 kHz AND f MAIN=4.19 MHz,
INTERVAL OF TIMER = 2Hz OR 256Hz
[0F0H]
Figure 11-10 Watch Timer Block Diagram
Usage of Watch Timer in STOP mode
When system is off and watch should keep working,
follow the steps below.
1. It determines the mode to perform between main mode
and sub mode when released from Stop mode. and is set
to Sub-frequency operation mode.
5. Repeats 3 and 4.
As mentioned above, by releasing every 0.5 sec., power
consumption can be reduced consideravably.
2. Enters in STOP mode.
3. After released by 0.5 second watch timer interrupt,
count up 1 second and refreshes LCD Display. When
the performing count up and refresh the LCD, the CPU
operates either in main frequency mode or sub frequency mode.
4. Enters in STOP mode again.
MAR. 1999 Ver 1.01
43
GMS81C3004
12. COMPARATOR
The A/D comparator circuit is shown in Figure 12-1 .
The A/D comparator circuit consists of the switch tree, ladder resistor, comparator and control register CMR, CSR
(address 0ECH, 0EDH). The CSR register select normal
port or analog input. The bit 7 of CSR has 1’s written to
them, port can be configured as comparator ports, and in
that state can be used as analog input. The lower 2 bits of
CMR control which port applied into comparator input. As
analog inputs, unselected port can be used digital input
(normal input) as shown in Table 12-2.
Comparator Channel Selection Register
[0EDH]
Comparator Mode Register
CSR
[0ECH]
CMR
voltage select
5-bit DAC
5
VDD
R14/CMP0
R15/CMP1
R16/CMP2
R17/CMP3
CIN0
digital
or
analog
select
enable
result
channel
select
enable
port
select
DAC
CIN1
CIN2
reference voltage
−
+
MUX
CIN3
OUTPUT
LATCH
Comparator
Figure 12-1 Block Diagram of Comparator circuit
Control
struction, not bit manipulation.
The comparator module has four analog inputs for the
GMS81C3004.
Example:
:
LDA
BBC
:
:
The Comparator Register, that is the comparator register
CMR and CSR are shown in Figure 12-2 .
Lower 5 bits of CMR can select voltage as 1/64 VDD step
internal reference voltage, based on the setting of bits 0 to
bit 5. The comparator result between the analog input voltage and the internal reference voltage is stored in bit 6 of
CMR.
Bit 6 of CMR
Description
0
input voltage < reference voltage
1
input voltage > reference voltage
The CMR can be read or tested by byte manipulation in-
44
CMR
A.6,GOTO3
GOTO3:
:
:
:
16 machine cycle (8µs at 4MHz) is required for comparison the result of comparison is stored in the bit 6 of Comparator Mode Register CMR (address 0ECH). The bit 7 is
comparator enable bit. When comparator is enabled, the
current consumption of comparator is typically 0.95mA (to
be defined after).
MAR. 1999 Ver 1.01
GMS81C3004
00000: VDD/64
00001: 3⋅VDD/64
00010: 5⋅VDD/64
00011: 7⋅VDD/64
00100: 9⋅VDD/64
00101: 11⋅VDD/64
00110: 13⋅VDD/64
00111: 15⋅VDD/64
:
:
:
:
11000: 49⋅VDD/64
11001: 51⋅VDD/64
11010: 53⋅VDD/64
11011: 55⋅VDD/64
11100: 57⋅VDD/64
11101: 59⋅VDD/64
11110: 61⋅VDD/64
11111: 63⋅VDD/64
ADDRESS : 0EC H
RESET VALUE : 00-00000
Comparator Mode Register
W
R
W
W
W
W
W
-
CMR
Reference voltage selection
See left Table.
Reserved
Conversion result store bit
0: input < reference
1: input > reference
A/D comparator enable bit
0: Disable
1: Enable
ADDRESS : 0EDH
RESET VALUE : 0-----00
Comparator Selection Register
W
W
-
CSR
-
MSB
Table 12-1 Setting the Reference voltage
-
-
W
LSB
Analog input selection
00: CIN0
01: CIN1
10: CIN2
11: CIN3
Select analog input pin by using bit 1 and bit 0 of the Channel Selection Register CSR (address 0EDH).
The port pins can be configured as analog inputs or as digital I/O by setting the CSR. Refer to Table 12-2.
Port Selection
0: R14,R15,R16,R17
1: Comparator analog input
Figure 12-2 Comparator Registers
CSR[7]
CSR[1:0]
CHANNEL
Remarks
0
XX
-
1
00
CIN0
R15,R16,R17 can be used as digital input
1
01
CIN1
R14,R16,R17 can be used as digital input
1
10
CIN2
R14,R15,R17 can be used as digital input
1
11
CIN3
R14,R15,R16 can be used as digital input
R14,R15,R16,R17
Table 12-2 Pin Configuration of Analog input
MAR. 1999 Ver 1.01
45
GMS81C3004
13. INTERRUPTS
The GMS81C3004 interrupt circuits consist of Interrupt
enable register (IENH, IENL), Interrupt request flags of
IRQH, IRQL, Priority circuit, and Master enable flag ("I"
flag of PSW). 9 interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 13-1 .
Below table shows the Interrupt priority
Reset/Interrupt
Hardware Reset
Basic Interval Timer
External Interrupt 0
External Interrupt 1
Timer/Counter 1
External Interrupt 2
Watchdog Timer
Watch Timer
Key Scan interrupt
Symbol
Priority
RESET
BIT
INT0
INT1
Timer 1
INT2
WDT
WT
KS
1
2
3
4
5
6
7
8
The External Interrupts INT0, INT1, INT2 each can be
transition-activated (1-to-0 or 0-to-1 transition).
The flags that actually generate these interrupts are bit
INT0F, INT1F and INT2F in register IRQH. When an external interrupt is generated, the flag that generated it is
cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated.
The Timer 1 Interrupts are generated by T1IF which is set
by a match in their respective timer/counter register.
The Basic Interval Timer Interrupt is generated by BITIF
which is set by an overflow in the timer register.
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IENH, IENL), and the interrupt request flags (in IRQH
and IRQL) except Power-on reset and software BRK interrupt.
Internal bus line
[0DBH]
Interrupt Enable
Register (Higher byte)
IENH
IRQH
[0DDH]
BITIF
INT0
INT0F
INT1
INT1IF
INT2
INT2IF
Timer 1
Release STOP
Priority Control
BIT
T1IF
IRQL [0DCH]
WDT
WTIF
KS
KSIF
To CPU
I Flag
Interrupt Master
Enable Flag
WDTIF
WT
I-flag is in PSW, it is cleared by "DI", set by
"EI" instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by "RETI" instruction, I-flag is set to
"1" by hardware.
Interrupt
Vector
Address
Generator
[0DAH]
IENL
Interrupt Enable
Register (Lower byte)
Internal bus line
Figure 13-1 Block Diagram of Interrupt
46
MAR. 1999 Ver 1.01
GMS81C3004
Interrupt enable registers are shown in Figure 13-3 . These
registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a
-
IRQH
-
R/W
R/W
INT2IF
T1IF
R/W
-
corresponding interrupt source is prohibited. Note that
PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
R/W
R/W
INT1IF INT0IF BITIF
MSB
ADDRESS: 0DDH
INITIAL VALUE: --00 -000
LSB
Basic Interval Timer interrupt request flag
External interrupt 0 request flag
External interrupt 1 request flag
Timer/Counter 1 interrupt request flag
External interrupt 2 request flag
-
IRQL
-
R/W
R/W
KSIF
WTIF
R/W
-
-
-
WDTIF
MSB
ADDRESS: 0DCH
INITIAL VALUE: --00 ---0
LSB
Watchdog timer interrupt request flag
Watch Timer interrupt request flag
Key scan interrupt request flag
Figure 13-2 Interrupt Request Flag
R/W
-
IENH
-
R/W
INT2EN T1EN
R/W
-
R/W
R/W
IN T1EN INT0EN BITEN
MSB
ADDRESS: 0DBH
INITIAL VALUE: --00 -000
LSB
Basic Interval Timer interrupt enable flag
External interrupt 0 enable flag
External interrupt 1 enable flag
Timer/Counter 2 Interrupt enable flag
External interrupt 2 enable flag
R/W
-
IENL
MSB
-
R/W
KSEN WTEN
R/W
-
-
-
W D TEN
VALUE
0: Disable
1: Enable
ADDRESS: 0DAH
INITIAL VALUE: --00 ---0
LSB
Watchdog Timer interrupt enable flag
Watch Timer Interrupt enable flag
Key Scan Interrupt enable flag
Figure 13-3 Interrupt Enable Flag
MAR. 1999 Ver 1.01
47
GMS81C3004
13.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 fOSC (2
µs at fMAIN=4.19MHz) after the completion of the current
instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction
[RETI].
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to "0"
to temporarily disable the acceptance of any following
maskable interrupts. When a non-maskable interrupt is
accepted, the acceptance of any following interrupts is
temporarily disabled.
2. Interrupt request flag for the interrupt source accepted is
cleared to "0".
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
5. The instruction stored at the entry address of the interrupt service program is executed.
System clock
Instruction Fetch
SP
Address Bus
PC
Data Bus
Not used
SP-1
PCH
PCL
SP-2
PSW
V.L.
V.L.
ADL
V.H.
ADH
New PC
OP code
Internal Read
Internal Write
Interrupt Processing Step
Interrupt Service Task
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 13-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Basic Interval Timer
Vector Table Address
0FFE6 H
0FFE7H
012 H
0E3H
Entry Address
0E312 H
0E313H
When nested interrupt service is required, the I-flag should
be set to "1" by “EI” instruction in the interrupt service
program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
0EH
2EH
Saving/Restoring General-purpose Register
Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.
A interrupt request is not accepted until the I-flag is set to
"1" even if a requested interrupt has higher priority than
that of the current interrupt being serviced.
48
During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but accumulator and other registers are
not saved itself. These registers are saved by the software
if necessary. Also, when multiple interrupt services are
nested, it is necessary to avoid using the same data memory
MAR. 1999 Ver 1.01
GMS81C3004
area for saving registers.
13.2 BRK Interrupt
The following method is used to save/restore the generalpurpose registers.
Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.
Example: Register save using push and pop instructions
Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0.
INTxx:
PUSH
PUSH
LDA
PUSH
A
X
RPR
A
;SAVE ACC.
;SAVE X REG.
;SAVE RPR
Each processing step is determined by B-flag as shown in
Figure 13-5 .
interrupt processing
POP
STA
POP
POP
RETI
A
PRP
X
A
;RESTORE RPR
;RESTORE X REG.
;RESTORE ACC.
;RETURN
General-purpose register save/restore using push and pop
instructions;
B-FLAG
BRK or
TCALL0
=0
=1
BRK
INTERRUPT
ROUTINE
TCALL0
ROUTINE
RETI
RET
main task
acceptance of
interrupt
interrupt
service task
saving
registers
Figure 13-5 Execution of BRK/TCALL0
restoring
registers
interrupt return
MAR. 1999 Ver 1.01
49
GMS81C3004
13.3 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence determines by hardware which request is serviced.
Main Program
service
Example: Even though Timer1 interrupt is in progress,
INT0 interrupt serviced without any suspend.
TIMER 1
service
enable INT0
disable other
INT0
service
EI
Occur
TIMER1 interrupt
However, multiple processing through software for special
features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.
Occur
INT0
enable INT0
enable other
TIMER1: PUSH
PUSH
PUSH
LDM
LDM
EI
:
:
:
:
:
:
LDM
LDM
POP
POP
POP
RETI
A
X
Y
IENH,#2
IENL,#0
IENH,#37H
IENL,#31H
Y
X
A
;Enable INT0 only
;Disable other
;Enable Interrupt
;Enable all interrupts
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.
Figure 13-6 Execution of Multi Interrupt
50
MAR. 1999 Ver 1.01
GMS81C3004
13.4 External Interrupt
The external interrupt on INT0, INT1 and INT2 pins are
edge triggered depending on the edge selection register
IESR (address 0D8H) as shown in Figure 13-7 .
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
INT0, INT1 and INT2 are multiplexed with general I/O
ports (R10~R12). To use external interrupt pin, the bit of
R0 port mode register PMR0 should be set to "1" correspondingly.
Port Mode Register 0
ADDRESS : 0D9H
RESET VALUE : ----0000
PMR0
INT0 pin
0: R00
1: INT0
INT0IF
INT0 INTERRUPT
0: R01
1: INT1
edge selection
INT1 pin
INT2 pin
0: R02
1: INT2
INT1IF
INT1 INTERRUPT
0: R03
1: EC1
INT2IF
INT2 INTERRUPT
Figure 13-9 PMR0: R0 Port Mode Register
Example: To use as an INT0 and INT2
IESR
[0DCH]
Figure 13-7 External Interrupt Block Diagram
Ext. Interrupt Edge Selection
Register
W
W
IESR
ADDRESS : 0D8H
RESET VALUE : --000000
W
W
W
W
INT0 edge select
00: Int. disable
01: falling
10: rising
11: both
INT1 edge select
00: Int. disable
01: falling
10: rising
11: both
INT2 edge select
00: Int. disable
01: falling
10: rising
11: both
:
:
;**** Set port as an input port R00,R02
LDM
R0DD,#1111_1010B
;
;**** Set port as an interrupt port
LDM
PMR0,#05H
;
;**** Set Falling-edge Detection
LDM
IESR,#0001_0001B
:
:
:
Response Time
The INT0, INT1 and INT2 edge are latched into INT1IF,
INT1IF and INT2IF at every machine cycle. The values
are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right
for it to be acknowledged, a hardware subroutine call to the
requested service routine will be the next instruction to be
executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between
activation of an external interrupt request and the beginning of execution of the first instruction of the service routine.
Figure 13-8 External Interrupt Edge Selection Register
MAR. 1999 Ver 1.01
51
GMS81C3004
shows interrupt response timings.
max. 12 fOSC
Interrupt Interrupt
goes
latched
active
8 fOSC
Interrupt
processing
Interrupt
routine
Figure 13-10 Interrupt Response Timing Diagram
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MAR. 1999 Ver 1.01
GMS81C3004
14. KEY SCAN
The key-scan block consists of Port selection Multiplexer,
Interrupt controller, 4-bit binary counter and Key scan control register, and Key data register.
16 outputs (SEG16~SEG31). Number of key inputs are defined by the key scan control register (KSCR[6:5]). Output
signal that are strobe are fixed as SEG16 to SEG31.
When the key scan interrupt is used, key scan register
KSCR (address 0F4H) should be set properly as shown in
Figure 14-2 .
If key scan is detected at any one or more of these pins, the
KSIF request flag is set to "1". This generates an interrupt
request. It also can be used in the way of release from
STOP mode.
Key Scan matrix is configured by 8 inputs (KS0~KS7) and
SEG31
SEG30
SEG29
SEG28
SEG17
SEG16
16 pins strobe signal output
strobe out controller
KSCR[3:0]
KSCR[4]
WTMR[2:1]
4
count value
overflow
00
f SUB
01
fMAIN÷27
R11/KS1
8 pins
data input
R16/KS6
Port Selection
R10/KS0
Key Input Latch
4 bit Counter
overflow
MUX
Key Scan Interrupt
"1"
key input
detect
KSIF
"0"
select interrupt
R17/KS7
Selection 2
Port
KSCR[6:5]
8 key input
data
KSCR[7]
KDTR[7:0]
Figure 14-1 Key Scan Interrupt Block Diagram
Strobe output signals are generated according to 4-bit
count value. The relation between Key scan register value
and strobe signal is shown as below table.
Counter
value
Strobe Pin
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
MAR. 1999 Ver 1.01
Once key scan interrupt occurs, key scan interrupt is disabled. To accept next interrupt, the KDTR has to be read
by software. Otherwise, key-scan is not enabled.
At every 8th clock, one strobe output is generated. There
are 16 pins in all, therefore total key scan time is 3900µs
(244µs x 16) Refer to Figure 14-3 .
Example: The registers should be defined properly to use
key scan input function.
:
:
LDM
LDM
LDM
EI
:
:
PUR1,#0
;For disabling pull-ups
KSCR,#0E0H ;For using 8 inputs
IENL,#20H
;Enable Keyscan
Note: When R1 is used as key scan port, there should be
no pull-up. PUR1 should be written to '0' in order not to
operate pull-up. Otherwise, VCLn voltage is changed and
may occur flicker in LCD panel display.
53
GMS81C3004
6. In case that these 2 values are not equal
If KDTR value is different, it means 2 keys are pressed
successively. And if KSCR value is different, it means
more than 2 keys are pressed simultaneously.
Usage of Key Scan
1. Clear bit 7 of the KSCR, interrupt activate on Key Scan.
2. Specify bit 5 and bit 6 of the KSCR properly by selecting what port you want as key scan input.
In case that these 2 values are equal;
If the number of bit ‘0’ in KSCR values is over 2, more
than 2keys are pressed.
And if the number of bit "0" is one, it indicates the key
input pin of bit "0"and seg pin number of strobe point as
Counter Value.
Therefore, it is possible to distinguish which key is
pressed.
3. Enable key scan interrupt.
4. When interrupt occurs, store the 4-bit counter value
(lower 4-bit of KSCR) and key input data (KDTR) into
user RAM area.
5. When the next interrupt occurs, compare the 4-bit
counter values of KSCR and KDTR with RAM value
stored before
MSB
R/W
KSCR
INSL
R/W
R/W
KPS
R
R
R
R
LSB
R
KSCNT
KOV
ADDRESS: 0F4H
INITIAL VALUE: 0000 0000
4-bit binary counter value
Counter Overflow Flag
Port Selection
00: R10~R17 (Key Scan Disable, No strobe output)
01: R14~R17, KS0~KS3
10: R10~R13, KS4~KS7
11: KS0~KS7
Interrupt source selection
0: Interrupt occurs by Key-scan input only.
1: Interrupt occurs by either Keyscan input or Counter overflow.
MSB
R
R
R
KDTR
R
R
R
R
LSB
R
KDTR
ADDRESS: 0F5H
INITIAL VALUE: 0000 0000
Figure 14-2 Key Scan Registers
30.5µs
CLOCK SOURCE
244.0µs
KEY SCAN CLOCK
STROBE OUTPUT
228.75µs
15.25µs
15.27µs
KEY SCAN
(INPUT LATCH)
20ns
Figure 14-3 Key Scan Timing
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MAR. 1999 Ver 1.01
GMS81C3004
15. LCD DRIVER
In addition, VCLn pin is provided as the drive power pin.
The GMS81C3004 has the circuit that directly drives the
liquid crystal display (LCD) and its control circuit.
The devices that can be directly driven are shown below.
The GMS81C3004 has the following pins connected with
LCD.
1/8 duty (1/4 Bias) LCD............Max. 320 Segment
By short between pin VCL2 and VCL3, 1/4 bias is used in
GMS81C3004.
➀ Segment output port 40 pins (SEG0-SEG39)
➁ Common output port 8 pins (COM0-COM7)
15.1 Configuration of LCD driver
Figure 15-1 shows the configuration of the LCD driver.
SEG0/R40
R4 or Segment
Select
SEG or Normal port
by LPMR [0F3H]
SEG7/R47
(40 bytes)
LPMR[3:2]
“Same with above”
LPMR[5:4]
fSUB
00
÷8
MUX
clock
÷ 64
SEG23/R67
Select clock
SEG31/R77
SEG32
LCDCK
SEG39
LCDEN
1
Select port
R06/LCDCK
0
R06
COM7
Common Driver
COM0
Power &
Bias control
VCL1
3
Enable LCD
Bias control
VCL5
LCR
[0F1H]
LCD
Timing Control
LPMR[7:6]
÷ 32
SEG16/R60
SEG24/R70
MUX
÷ 16
SEG15/R57
“Same with above”
fMAIN÷2 7
01
Prescaler
INTERNAL BUS LINE
WTMR[2:1]
SEG8/R50
“Same with above”
Segment Driver
Display Memory
Display Data Buffer register
Display Data Select Control
LPMR[1:0]
Figure 15-1 LCD Driver Block Diagram
MAR. 1999 Ver 1.01
55
GMS81C3004
15.2 Control of LCD Driver Circuit
The LCD driver is controlled by the LCD control register,
LCR. Further, when the LCD is accessed, the most signif-
LCR
R/W
7
6
LCDEN
-
R/W
5
R/W
4
3
icant bit of the LCR must be cleared to "0" (Blanking).
R/W
2
R/W
1
R/W
0
ADDRESS: 0F1H
INITIAL VALUE:0-00 -000
-
Clock source selection
00: f SUB ÷ 64
01: f SUB ÷ 32
10: f SUB ÷ 16
11: f SUB ÷ 8
Reserved
Note
LCD clock output
0: R06 port
1: LCD clock output
Bias resistor control
0: Use internal resistor
1: Use external resistor
Bias transistor control
0: off
1: on
LCD display control
0: Disable (LCD blanking)
1: Enable LCD display (Blanking is released)
NOTE:
Bit 6 is fixed to ‘0’ in GMS81C3004. In the Emulator if it is written to "1", then it operates as 16-common operation mode with
COM0~COM15
Figure 15-2 LCD Control Register
Selecting Frame Frequency
Frame frequency is set to the base frequency as shown in
the following Table 15-1.
LCR[1:0]
LCD clock
00
01
10
11
fSUB ÷ 64
fSUB ÷ 32
fSUB ÷ 16
fSUB ÷ 8
Frame Frequency (Hz)
(When fSUB = 32.768 kHz)
64
128
256
512
Table 15-1 Setting of LCD Frame Frequency
The LCR[1:0] determines the frequency of COM signal
scanning of each segment output. This is also referred to as
the LCD clock signal pin, LCDCK. Since LCDCK is generated by dividing the watch timer clock(fW), the watch
timer must be enabled when the LCD display is turned on.
RESET clears the LCD control register LCR values to logic zero. When Bit 2 of LCR is ‘1’, this clock outputs to R06
pin
The LCD display can continue to operate during SLEEP
and STOP modes if a sub-frequency clock is used as system clock source.
one frame
56
MAR. 1999 Ver 1.01
GMS81C3004
Display On/Off
Blanking is applied by setting LCDEN (bit 7 of LCR) to
"0" and turns off the LCD by outputting the non light op-
eration level to the COM pin. When setting Frame frequency or changing operating mode, LCD display should be off
before operation, to prevent display flickering.
15.3 Bias Resistor
To operate LCD, built-in Bias resistor dividing VDD to VSS
section into several stages generates necessary voltage.
Bit 5 of LCR switches Transistor supplying voltage to serially connected Bias resistor. If it is '1', it turns on, and if
it is ‘0', it turns off. When the system needs adjusting the
contrast of LCD, the bit 5 of LCR should be clear to “0”
always. Then power is supplied through the external resistor as shown in Figure 15-3 .
MCU Internal
VDD
LCDEN
LCR.4
VDD
LCDEN
LCR.4
VDD
LCR.5 = “0”
Internal Bias resistors
VCL1
LCR.4 = “0”
VCL1
LCR.4 = “1”
LCR.5 = “0”
VCL2
VCL2
VCL3
Two pins are connected
each other
VCL3
VCL4
VCL4
VCL5
LCDEN
VCL5
LCDEN
LCR.5
Adjust Contrast
LCR.5
VSS
VSS
Adjust Contrast
When LCD turns on, output “Low”
When LCD turns off, output “High”
R Port
(a) Internal Bias Resistors
External Bias resistors
MCU Internal
Note: Since the GMS81C3004 using 1/8 duty, so recommend to use 1/4 Bias. To use 1/4 Bias, VCL 2 pin and VCL
3 pin should be shorted externally as shown in Figure 15-3
(a). Furthermore, in case that user wants to use the specific
voltage instead of voltage of internal Bias resistor, external
Bias resistor can be used as shown in Figure 15-3 (b).
To use external Bias resistor, Bit 4 and Bit 5 of LCR should
be set.
When LCD turns on, output “Low”
When LCD turns off, output “High”
R Port
(b) External Bias Resistors
Figure 15-3 Application Example of Adjusting the Contrast
MAR. 1999 Ver 1.01
57
GMS81C3004
MCU Internal
VDD
LCDEN
LCR.4
VDD
LCDEN
LCR.4
VDD
LCR.5 = “1”
Internal Bias resistors
VCL1
LCR.4 = “0”
VCL1
LCR.4 = “1”
LCR.5 = “1”
VCL2
VCL2
VCL3
Two pins are connected
each other
VCL3
VCL4
VCL4
VCL5
LCDEN
LCDEN
LCR.5
LCR.5
VCL5
VSS
VSS
When LCD turns on, “LCR.5=1”
When LCD turns off, “LCR.5=0”
(a) Internal Bias Resistors
External Bias resistors
MCU Internal
When LCD turns on, “LCR.5=1”
When LCD turns off, “LCR.5=0”
(b) External Bias Resistors
Figure 15-4 Application Example for No Adjusting of Contrast
58
MAR. 1999 Ver 1.01
GMS81C3004
15.4 LCD Display Memory
Display data are stored to the display data area (page 12) in
the data memory.
The display data stored to the display data area (address
0C00H-0C47H) are read automatically and sent to the LCD
driver by the hardware. The LCD driver generates the segment signals and common signals in accordance with the
display data and drive method.
SEG39
SEG38
0C47
0C46
0C45
0C44
0C43
0C42
SEG35
0C41
SEG36
0C40
SEG37
SEG34
SEG33
SEG32
SEG31
SEG30
0C37
0C36
0C35
0C34
0C33
0C32
SEG27
0C31
SEG28
0C30
SEG29
SEG26
SEG25
SEG24
SEG23
SEG22
0C22
0C23
0C24
0C25
0C12
0C13
0C14
0C15
0C16
0C02
0C03
0C04
0C05
0C06
0C07
COM2
COM3
COM4
COM5
COM6
COM7
0C27
0C21
0C11
0C01
COM1
0C26
0C20
0C10
SEG19
0C00
SEG20
COM0
SEG21
SEG18
SEG17
SEG16
SEG15
SEG14
SEG12
SEG11
0C17
SEG13
SEG10
SEG9
SEG8
7
SEG7
6
SEG6
SEG3
4
2
SEG2
3
SEG4
5
SEG5
1
SEG1
Bit 0
SEG0
Figure 15-5 LCD Display Memory
MAR. 1999 Ver 1.01
59
GMS81C3004
Therefore, display patterns can be changed by only overwriting the contents of the display data area with a program. The table look up instruction is mainly used for this
overwriting.
Figure 15-5 shows the correspondence between the display
data area and the SEG/COM pins. The LCD lights when
the display data is "1" and turn off when "0".
LCD display memory in this location that are not used for
LCD display can be allocated for general purpose use.
15.5 LCD Port Selection
Segment pins are also used for normal I/O pins. The LCD
port selection register LPMR is used to set Rn pin for ordi-
LPMR
R/W R/W
7
6
R7LPMR
R/W R/W
5
4
R6LPMR
R/W R/W
3
2
R5LPMR
nary digital input.
R/W R/W
1
0
R4LPMR
ADDRESS: 0F3H
INITIAL VALUE:0000 0000
R4 port selection
00:SEG0~SEG7
01:SEG4~SEG7,R40~R43
10:SEG0~SEG3,R44~R47
11:R40~R47
R5 port selection
00:SEG8~SEG15
01:SEG12~SEG15,R50~R53
10:SEG8~SEG11,R54~R57
11:R50~R57
R6 port selection
00:SEG16~SEG23
01:SEG20~SEG23,R60~R63
10:SEG16~SEG19,R64~R67
11:R60~R67
R7 port selection
00:SEG24~SEG31
01:SEG28~SEG31,R70~R73
10:SEG24~SEG27,R74~R77
11:R70~R77
Figure 15-6 LCD Port Selection Register
15.6 Control Method of LCD Driver
Initial Setting
Flow chart of initial setting is shown in Figure 15-7 .
Example: Driving of LCD
Select Frame Frequency
Clear
LCD Display
Memory
Turn on LCD
60
LDM
:
SETG
LDM
LDX
C_LCD1: LDA
STA
CMPX
BNE
CLRG
LDM
:
SET1B
:
:
LCR,#23H
;fF=512Hz (f SUB= 32.768kHz)
RPR,#12
;Select LCD Memory
;area (Bank C)
#0
#0
;RAM Clear
;(0C00H->0C47H)
{X}+
#048H
C_LCD1
RPR,#00
;Bank=0
LCR.7
;Enable display
MAR. 1999 Ver 1.01
GMS81C3004
SEG3
SEG4
SEG5
SEG6
SEG5
Enable display
(Release of blanking)
SEG2
Initialize of display memory
SEG1
Setting of LCD drive method
SEG0
.
Data
Address
COM0
1
1
1
1
0
0
0
0
0FH
0C0H
COM1
1
0 0
0
1
0
0
0
11H
0C1H
COM2
1
0 0
0
1
0
0
0
11H
0C2H
COM3
1
1
1
1
0
0
0
0
0FH
0C3H
COM4
1
0
1
0
0
0
0
0
05H
0C4H
COM5
1
0
0
1
0
0
0
09H
0C5H
COM6
1
0
0
0
0
1
0
0
0
11H
0C6H
COM7
0
0
0
0
0
0
0
0
00H
0C7H
bit 0
bit 7
Figure 15-8 Example of Connection COM & SEG
Figure 15-7 Initial Setting of LCD Driver
Display Data
Normally, display data are kept permanently in the program memory and then stored at the display data area by
the table look-up instruction. This can be explained using
5x7 dot matrix character display with 1/8 duty LCD as an
Write into the
LP:
LCD Memory
Font data
DTBL:
MAR. 1999 Ver 1.01
example as well as any LCD panel. The COM and SEG
connections to the LCD and display data are the same as
those shown is Figure 15-8 . Programming example for
displaying character is shown below.
:
:
SETG
LDM
LDX
LDY
LDA
STA
INC
CMPY
BNE
CLRG
:
:
RPR,#12
#0
#0
!DTBL+Y
{X}+
Y
#8
LP
DB
DB
0FH,11H,11H,0FH
05H,09H,11H,00H
;Set G-flag
;Select Bank C to access LCD
;Load font data
;Clear G-flag
61
GMS81C3004
15.7 LCD Waveform
0
FRAME
1
2
3
4
5
6
7
0
1
2
COM0
COM1
COM2
SEG0
SEG1
SEG2
SEG3
SEG4
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
4
5
6
7
One Frame
1/8 Duty, 1/4 Bias Drive
In this case, VCL2 and VCL3 pins
are shorted each other (VCL2=VCL3)
to use as 1/4 bias.
3
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
COM3
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
SEG0
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
SEG1
SEG2
SEG0 - COM0
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
VDD
VCL1
VCL2=VCL3
VCL4
0
-VCL4
-VCL2=VCL3
-VCL1
-VDD
Figure 15-9 Example of LCD drive output
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MAR. 1999 Ver 1.01
GMS81C3004
0
FRAME
1
2
3
4
5
6
7
0
1
2
COM0
COM1
COM2
SEG0
SEG1
SEG2
SEG3
SEG4
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
4
5
6
7
One Frame
1/8 Duty, 1/4 Bias Drive
In this case, VCL2 and VCL3 pins
are shorted each other (VCL2=VCL3)
to use as 1/4 bias.
3
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
COM3
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
SEG0
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
SEG1
SEG2
SEG0 - COM0
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
VDD
VCL1
VCL2=VCL3
VCL4
VCL5
VDD
VCL1
VCL2=VCL3
VCL4
0
-VCL4
-VCL2=VCL3
-VCL1
-VDD
Figure 15-10 Example of LCD drive output
MAR. 1999 Ver 1.01
63
GMS81C3004
16. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and resumes the CPU to the normal state.
The watchdog timer signal for detecting malfunction can
be selected either a reset CPU or a interrupt request.
When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals.
6-bit up-counter
Clock source
(BIT overflow)
clear
WDT
clear
comparator
WDTIF
Watchdog Timer interrupt
to reset CPU
6-bit compare data
clear
enable
5
WDTCL
WDTR[5:0]
WDTON
WDTR
[0DFH]
Watchdog Timer Register
Figure 16-1 Block Diagram of Watchdog Timer
Watchdog Timer Control
er output will become active at the rising overflow from
the binary counters unless the binary counter is cleared. At
this time, when WDTON=1, a reset is generated, which
drives the RESET pin to low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (WDTIF) is
generated.
Figure 16-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
The CPU malfunction is detected during setting of the detection time, selecting of output, and clearing of the binary
counter. Clearing the binary counter is repeated within the
detection time.
The watchdog timer temporarily stops counting in the
STOP mode, and when the STOP mode is released, it automatically restarts (continues counting).
If the malfunction occurs for any cause, the watchdog tim-
WDTR
W
W
7
6
WDTON WDTCL
W
5
W
4
W
3
W
2
W
1
W
0
ADDRESS: 0DFH
INITIAL VALUE:0011 1111
6-bit compare data
Clear count flag
0: Free-run count
1: When the WDTCL is set to ""1", binary counter
is cleared to "0". And the WDTCL becomes "0" automatically
after one machine cycle. Counter count up again.
WDT enable flag
0: 6-bit Timer
1: Watchdog timer on
Figure 16-2 WDTR: Watchdog Timer Data Register
64
MAR. 1999 Ver 1.01
GMS81C3004
Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz
Within WDT
detection time
Within WDT
detection time
LDM
LDM
CKCTLR,#0EH
WDTR,#0CFH
;Select 1/512 clock source
;WDTON ← 1, Clear Counter
LDM
:
:
:
:
LDM
:
:
:
:
LDM
WDTR,#0CFH
;Clear counter
WDTR,#0CFH
;Clear counter
WDTR,#0CFH
;Clear counter
Enable and Disable Watchdog
Watchdog Timer Interrupt
Watchdog timer is enabled by setting WDTON (bit 7 in
WDTR) to "1". WDTON is initialized to "0" during reset
and it should be set to "1" to operate after reset is released.
The watchdog timer can be also used as a simple 6-bit timer by clearing bit 7 of WDTR to "0". The interval of watchdog timer interrupt is decided by Basic Interval Timer.
Example: Enables watchdog timer reset
Interval equation is shown as below.
:
LDM
:
:
T = WDTR × Interval of BIT
WDTR,#0FFH ;WDTON ← 1
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
The watchdog timer is disabled by clearing bit 7 (WDTON) of WDTR. The watchdog timer is halted in STOP
mode and restarts automatically after STOP mode is released.
Example: 6-bit timer interrupt set up.
LDX
TXSP
LDM
:
#03FH
WDTR,#3FH
;SP ← 3F
;WDTON ← 0
;WDTCL ← 0
:
Source clock
BIT overflow
Binary-counter
2
1
3
0
1
2
3
0
Counter
Clear
WDTR
n
3
Match
Detect
WDTIF interrupt
WDTR ← "1100_0011"
WDT reset
reset
Figure 16-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to reset the internal hardware.
MAR. 1999 Ver 1.01
The main clock oscillator also turns on when a watchdog
timer reset is generated in sub clock mode.
65
GMS81C3004
17. BUZZER DRIVER
The buzzer driver block consists of 6-bit binary counter,
buzzer register, and clock source selector. It generates
square-wave which has very wide range frequency (500Hz
~ 125kHz at fMAIN = 4MHz) by user software.
The port mode register PMR1 (address 0F6H) should be set
to "1", the R13 will be configured as BUZ pin regardless
of port direction register R1DD.
The frequency of output signal is controlled by the buzzer
control register BUR.
A 50% duty pulse can be output to R13/BUZ pin to use for
piezo-electric buzzer drive.
R13 port data
SCMR[1:0]
÷8
SXIN PIN
1X
main or
sub clock
Counter
Multiplexer
0X
Prescaler
MPX
XIN PIN
6-bit binary
÷16
÷32
÷64
0
÷2
R13/BUZ PIN
F/F
1
Comparator
Compare data
2
6
PMR1
BUR
[0F6 H]
[0F7 H]
Internal bus line
Figure 17-1 Block Diagram of Buzzer Driver
The bit 0 to bit 5 of BUR determine output frequency for
buzzer driving.
Note that BUR is a write-only register.
Equation of frequency calculation is shown below.
The 6-bit counter is cleared and starts the counting by writing signal at BUR register. It is incremental from 00H until
it matches 6-bit BUR value.
Oscillator frequency
fBUZ ( Hz ) = ----------------------------------------------------------------------------------------------2 × Prescaler ratio × ( BUR value + 1 )
BUR is undefined after reset, so it must be initialized to between 1H and 3FH by software.
fBUZ: BUZ pin frequency
Prescaler ratio: Prescaler divide ratio by BUR[7:6]
BUR value: 6-bit compare data, BUR[5:0]
ADDRESS : 0F6H
RESET VALUE : ---- ---0H
Port 1 Mode Register
W
R/W
PMR1
-
-
-
-
-
-
-
ADDRESS : 0F7H
RESET VALUE : 0FFH
Buzzer Register
W
W
W
W
W
W
W
BUR
Port select
"0": R13 port
"1": BUZ port
Buzzer counter
compare data
Source clock select
00: ÷8
01: ÷16
10: ÷32
11: ÷64
Figure 17-2 PMR1 and Buzzer Register
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MAR. 1999 Ver 1.01
GMS81C3004
When main-frequency is 4.194304MHz, buzzer frequency
is shown as below and if sub-frequency is selected as clock
BUR
[5:0]
Output frequency (kHz)
÷8
÷16
÷32
÷64
source, buzzer frequency is used after dividing by 128.
BUR
[5:0]
Output frequency (kHz)
÷8
÷16
÷32
÷64
01
02
03
04
05
06
07
131.072
87.381
65.536
52.429
43.691
37.338
32.768
65.536
43.691
32.768
26.214
21.845
18.725
16.384
32.768
21.846
16.384
13.107
10.923
9.362
8.192
16.384
10.923
8.192
6.554
5.462
4.682
4.096
20
21
22
23
24
25
26
27
7.944
7.710
7.490
7.282
7.085
6.899
6.722
6.554
3.972
3.855
3.745
3.641
3.542
3.449
3.361
3.277
1.986
1.928
1.873
1.821
1.771
1.725
1.681
1.639
0.993
0.964
0.936
0.910
0.885
0.862
0.840
0.819
08
09
0A
0B
0C
0D
0E
0F
29.127
26.214
23.831
21.845
20.165
18.725
17.476
16.384
14.564
13.107
11.916
10.923
10.082
9.362
8.738
8.192
7.282
6.554
5.958
5.462
5.041
4.681
4.369
4.096
3.641
3.277
2.979
2.731
2.521
2.341
2.185
2.048
28
29
2A
2B
2C
2D
2E
2F
6.394
6.242
6.096
5.958
5.825
5.699
5.578
5.461
3.197
3.121
3.048
2.979
2.913
2.849
2.789
2.731
1.599
1.561
1.524
1.490
1.457
1.425
1.395
1.366
0.799
0.780
0.762
0.745
0.728
0.712
0.697
0.683
10
11
12
13
14
15
16
17
15.420
14.564
13.797
13.107
12.483
11.916
11.398
10.923
7.710
7.282
6.899
6.554
6.242
5.958
5.699
5.461
3.855
3.641
3.450
3.277
3.121
2.979
2.850
2.731
1.928
1.821
1.725
1.639
1.561
1.490
1.425
1.366
30
31
32
33
34
35
36
37
5.350
5.243
5.140
5.041
4.946
4.855
4.766
4.681
2.675
2.621
2.570
2.521
2.473
2.427
2.383
2.341
1.338
1.311
1.285
1.261
1.237
1.214
1.192
1.171
0.669
0.655
0.642
0.630
0.618
0.607
0.596
0.585
18
19
1A
1B
1C
1D
1E
1F
10.486
10.082
9.709
9.362
9.039
8.738
8.456
8.192
5.243
5.041
4.855
4.681
4.520
4.369
4.228
4.096
2.622
2.251
2.428
2.341
2.260
2.185
2.114
2.048
1.311
1.261
1.214
1.171
1.130
1.093
1.057
1.024
38
39
3A
3B
3C
3D
3E
3F
4.599
4.520
4.443
4.369
4.297
4.228
4.161
4.069
2.300
2.260
2.222
2.185
2.149
2.114
2.081
2.048
1.150
1.130
1.111
1.093
1.075
1.057
1.041
1.024
0.575
0.565
0.555
0.546
0.537
0.528
0.520
0.512
MAR. 1999 Ver 1.01
67
GMS81C3004
18. POWER DOWN OPERATION
GMS81C3004 has 2 power-down mode. In power-down
mode, power consumption is reduced considerably that in
Battery operation Battery life can be extended a lot.
Sleep mode is entered by setting bit 0 of Sleep Mode Register, and STOP Mode is entered by STOP instruction.
18.1 SLEEP Mode
In this mode, the internal oscillation circuits remain active.
Oscillation continues and peripherals are operate normally
but CPU stops. Movement of all Peripherals is shown in
Table 18-1. Sleep mode is entered by setting bit 0 of SMR
(address 0DEH).
ADDRESS : 0DEH
RESET VALUE : -------0
Sleep Mode Register
SMR
0: Release Sleep Mode
1: Enter Sleep Mode
It is released by RESET or interrupt. To be release by interrupt, interrupt should be enabled before Sleep mode.
Figure 18-1 SLEEP Mode Register
~
~
Oscillator
(XIN or SXIN pin)
Internal CPU Clock
~
~
Interrupt
Release
Set bit 0 of SMR
Normal Operation
Stand-by Mode
Normal Operation
Figure 18-2 Sleep Mode Release Timing by External Interrupt
.
~
~
~
~
Oscillator
(XIN or SXIN pin)
Internal CPU Clock
Release
Set bit 0 of SMR
Normal Operation
Stand-by Mode
0
1
2
Clear & Start
~
~
~ ~
~
~ ~
~
BIT Counter
~ ~
~
~
~
~
RESET
FE
FF
0
1
2
t ST = 62.5ms
Normal Operation
at 4.19MHz by hardware
tST =
1
fMAIN ÷1024
x 256
Figure 18-3 SLEEP Mode Release Timing by RESET pin
68
MAR. 1999 Ver 1.01
GMS81C3004
18.2 STOP Mode
For applications where power consumption is a critical
factor, device provides reduced power of STOP.
Start The Stop Operation
An instruction that STOP causes to be the last instruction
is executed before going into the STOP mode. In the Stop
Peripheral
mode, the on-chip main-frequency oscillator is stopped.
With the clock frozen, all functions are stopped, but the onchip RAM and Control registers are held. The port pins
output the values held by their respective port data register,
the port direction registers. The status of peripherals during
Stop mode is shown below.
STOP Mode
Sleep Mode
CPU
All CPU operations are disabled
All CPU operations are disabled
RAM
Retain
Retain
LCDdriver operates continuously
LCD driver operates continuously
Halted
BIT operates continuously
Halted (Only when the Event counter mode
is enabled, Timer 1 operates normally)
Timer/Event counter 1 operates continuously
Watch Timer operates continuously
Watch Timer operates continuously
Key Scan
Active
Active
XIN PIN
LOW
Oscillation
XOUT PIN
LOW
Oscillation
Main-oscillation
Stop
Oscillation
Sub-oscillation
Oscillation
Oscillation
I/O ports
Retain
Retain
Control Registers
Retain
Retain
Release method
by RESET, by Key Scan interrupt, Watch
Timer interrupt, Timer interrupt (EC1), by
External interrupt
by RESET, All interrupts
LCD driver
Basic Interval Timer
Timer/Event counter 1
Watch Timer
Table 18-1 Peripheral Operation during Power Down Mode
Note: Since the XIN pin is connected internally to GND to
avoid current leakage due to the crystal oscillator in STOP
mode, do not use STOP instruction when an external clock
is used as the main system clock.
In the Stop mode of operation, VDD can be reduced to minimize power consumption. Be careful, however, that VDD
is not reduced before the Stop mode is invoked, and that
VDD is restored to its normal operating level before the
Stop mode is terminated.
The reset should not be activated before VDD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
And after STOP instruction, at least two or more NOP instruction should be written as shown in example below.
Example)
MAR. 1999 Ver 1.01
:
LDM
STOP
NOP
NOP
:
CKCTLR,#0000_1110B
The Interval Timer Register CKCTLR should be initialized (0FH or 0EH) by software in order that oscillation stabilization time should be longer than 20ms before STOP
mode.
Release the STOP mode
The exit from STOP mode is using hardware reset or external interrupt, watch timer, key scan or timer/counter.
To release STOP mode, corresponding interrupt should be
enabled before STOP mode.
Specially as a clock source of Timer/Event counter, EC1
pin can release it by Timer/Event counter Interrupt re-
69
GMS81C3004
quest
Start-up is performed to acquire the time for stabilizing oscillation. During the start-up, the internal operations are all
stopped.
Reset redefines all the control registers but does not change
the on-chip RAM. External interrupts allow both on-chip
RAM and Control registers to retain their values.
~ ~
~
~
~
~
Oscillator
(XIN pin)
~
~
Internal Clock
~
~
~
~
~
~
External Interrupt
STOP Instruction
Executed
n+1 n+2
n+3
1
0
~
~
~ ~
n
~
~ ~
~
BIT Counter
FE
FF
0
1
2
Clear
Normal Operation
Stop Operation
Normal Operation
tST > 20ms
by software
Before executing Stop instruction, Basic Interval Timer must be set
properly by software to get stabilization time which is longer than 20ms.
Figure 18-4 STOP Mode Release Timing by External Interrupt
~ ~
~
~
~
~
Oscillator
(XIN pin)
~
~
~
~
Internal Clock
~
~
STOP Instruction
Executed
n+1 n+2
n+2
n+3
1
0
~
~
~ ~
n
~
~ ~
~
BIT Counter
~
~
RESET
FE
FF
0
1
2
Clear
Normal Operation
Stop Operation
Normal Operation
tST > 62.5ms
at 4.19MHz by hardware
tST =
1
fMAIN ÷1024
x 256
Figure 18-5 STOP Mode Release Timing by RESET
70
MAR. 1999 Ver 1.01
GMS81C3004
Minimizing Current Consumption
The Stop mode is designed to reduce power consumption.
To minimize current drawn during Stop mode, the user
should turn-off output drivers that are sourcing or sinking
current, if it is practical.
Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation
of the STOP feature. This point should be little current flows
when the input level is stable at the power voltage level
(VDD /VSS); however, when the input level becomes higher
than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means.
It should be set properly that current flow through port
doesn't exist.
First consider the setting to input mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing
from external MCU is very high that the current doesn’t
flow.
But input voltage level should be VSS or VDD. Be careful
that if unspecified voltage, i.e. if unfirmed voltage level
(not V SSor VDD) is applied to input pin, there can be little
current (max. 1mA at around 2V) flow.
If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there
is external pull-down register, it is set to low.
VDD
INPUT PIN
INPUT PIN
VDD
VDD
internal
pull-up
VDD
i=0
O
OPEN
O
i
i
GND
X
Weak pull-up current flows
Very weak current flows
VDD
X
GND
O
OPEN
O
i=0
When port is configured as an input, input level should
be closed to 0V or 5V to avoid power consumption.
Figure 18-6 Application Example of Unused Input Port
MAR. 1999 Ver 1.01
71
GMS81C3004
OUTPUT PIN
OUTPUT PIN
VDD
ON
OPEN
OFF
ON
OFF
O
OFF
VDD
GND
X
ON
i
ON
OFF
L
OFF
ON
i
GND
X
O
VDD
L
i=0
GND
O
In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port .
In the left case, much current flows from port to GND.
Figure 18-7 Application Example of Unused Output Port
72
MAR. 1999 Ver 1.01
GMS81C3004
19. OSCILLATOR CIRCUIT
The GMS81C3004 has two oscillation circuits internally.
XIN and X OUT are input and output for main frequency and
SXIN and SX OUT are input and output for sub frequency,
C1
respectively, inverting amplifier which can be configured
for being used as an on-chip oscillator, as shown in Figure
19-1 .
C1
XOUT
C2
4.19MHz
SXOUT
C2
XIN
32.768KHz
VSS
SXIN
VSS
Recommend
C1,C2 = 100~120pF
Recommend
Crystal Oscillator
C1,C2 = 20pF
Ceramic Resonator
C1,C2 = 30pF
Crystal or Ceramic Oscillator
Open
XOUT
XOUT
REXT
External Clock
XIN
XIN
External Oscillator
For selection R value,
Refer to AC Characteristics
RC Oscillator (mask option)
Figure 19-1 Oscillation Circuit
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
values of external components.
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
values of external components.
XOUT
XIN
In addition, see Figure 19-2 for the layout of the crystal.
Note: Minimize the wiring length. Do not allow the wiring to
intersect with other signal conductors. Do not allow the wiring to come near changing high current. Set the potential of
the grounding position of the oscillator capacitor to that of
VSS. Do not ground it to any ground pattern where high current is present. Do not fetch signals from the oscillator.
MAR. 1999 Ver 1.01
Figure 19-2 Layout of Oscillator PCB circuit
73
GMS81C3004
20. RESET
The GMS81C3004 have two types of reset generation procedures; one is an external reset input, the other is a watchOn-chip Hardware
Program counter
RAM page register
G-flag
Initial Value
dog timer reset. Table 20-1 shows on-chip hardware initialization by reset action.
On-chip Hardware
Initial Value
(FFFFH) - (FFFEH)
Peripheral clock
Off
(RPR)
0
Watchdog timer
Disable
(G)
0
Control registers
Refer to Table 8-1 on page 22
(PC)
Operation mode
Main-frequency clock
Power fail detector
Disable
Table 20-1 Initializing Internal Status by Reset Action
20.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, it is applied,
and the internal state is initialized. After reset, 64ms (at 4
MHz) add with 7 oscillator periods are required to start execution as shown in Figure 20-2 .
A connection for simple power-on-reset is shown in Figure
20-1 .
VDD
VDD
Typical 60kΩ at VDD=3V
RESET
Internal RAM is not affected by reset. When VDD is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.
+
−
MCU
GND
When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH.
Figure 20-1 Simple Power-on-Reset Circuit
1
3
?
?
4
5
6
7
~
~
2
System Clock
~
~
RESET
?
?
FFFE FFFF Start
~
~ ~
~
?
?
?
?
FE
ADL
ADH
OP
~
~
DATA
BUS
~
~
ADDRESS
BUS
Stabilization Time
tST = 62.5mS at 4.19MHz
RESET Process Step
tST =
1
fMAIN ÷1024
MAIN PROGRAM
x 256
Figure 20-2 Timing Diagram after RESET
20.2 Watchdog Timer Reset
Refer to “16. WATCHDOG TIMER” on page 64.
74
MAR. 1999 Ver 1.01
GMS81C3004
21. POWER FAIL PROCESSOR
In the in-circuit emulator, power fail function is not implemented and user can not experiment with it. Therefore, after final development of user program, this function may
be experimented or evaluated.
The GMS81C3004 has an on-chip low voltage detection
circuitry to detect the VDD voltage. A configuration register, LVDR, can enable or disable the low voltage detect
circuitry. Whenever VDD falls close to or below 3.4V, the
LVD flag1, LVDF0 is just set to "1", and if it recovering
3.4V, LVDF0 is holded to "1". If VDD falls below around
2.2V range, the low voltage situation may reset MCU according to setting of LVDR. Refer to “7.3 DC Electrical
Characteristics” on page 10.
7
LVDR
6
5
Note: Power fail processor function is not available on 3V
operation, because this function will detect power fail at all
the time.
R/W R/W R/W R/W R/W
4
3
2
1
0
LVDM LVDF1 LVDE LVDRST LVDF0
ADDRESS: 0FEH
INITIAL VALUE: ---1 0000
LVD flag 0 (typ. 2.2V)
0: Not detect low voltage (Normal)
1: Detect low voltage
Reset by LVD
0: Disable
1: Enable
Operation Mode
0 : Normal operation regardless of power fail
1 : MCU will be reset by power fail detection
LVD flag 1 (typ. 3.4V)
0: VDD is above 3.4V
1: VDD is below 3.4V
Freeze by LVD
0: Disable
1: Enable
Figure 21-1 Low Voltage Detector Register
RESET VECTOR
YES
LVDF =1
NO
RAM CLEAR
INITIALIZE RAM DATA
Skip the
initial routine
INITIALIZE ALL PORTS
INITIALIZE REGISTERS
FUNTION
EXECUTION
Figure 21-2 Example S/W of RESET by Power fail
MAR. 1999 Ver 1.01
75
GMS81C3004
VDD
LVDVDD MAX
LVDVDDMIN
64mS
Internal
RESET
VDD
LVDVDD MAX
LVDVDDMIN
When LVDM = 1
Internal
RESET
64mS
t <64mS
VDD
Internal
RESET
64mS
LVDVDD MAX
LVDVDDMIN
Figure 21-3 Power Fail Processor Situations
76
MAR. 1999 Ver 1.01
APPENDIX
GMS81C3004
A. CONTROL REGISTER LIST
Address
Register Name
Symbol
R/W
Initial Value
Page
7 6 5 4 3 2 1 0
00C0
R0 port data register
R0
R/W
Undefined
30
00C1
R1 port data register
R1
R/W
Undefined
30
00C2
R2 port data register
R2
R/W
Undefined
31
00C4
R4 port data register
R4
R/W
Undefined
31
00C5
R5 port data register
R5
R/W
Undefined
31
00C6
R6 port data register
R6
R/W
Undefined
32
00C7
R7 port data register
00C8
R0 port I/O direction register
R7
R/W
Undefined
32
R0DD
W
0 0 0 0 0 0 0 0
30
00C9
R1 port I/O direction register
R1DD
W
0 0 0 0 0 0 0 0
30
00CA
R2 port I/O direction register
R2DD
W
- - - - - 0 0 0
31
00CC
R4 port I/O direction register
R4DD
W
0 0 0 0 0 0 0 0
31
00CD
R5 port I/O direction register
R5DD
W
0 0 0 0 0 0 0 0
31
00CE
R6 port I/O direction register
R6DD
W
0 0 0 0 0 0 0 0
32
00CF
R7 port I/O direction register
R7DD
W
0 0 0 0 0 0 0 0
32
00D4
R0 port pull-up resistor selection register
PUR0
W
0 0 0 0 0 0 0 0
30
00D5
R1 port pull-up resistor selection register
PUR1
W
0 0 0 0 0 0 0 0
30
00D6
R2 port pull-up resistor selection register
PUR2
W
- - - - - 0 0 0
31
00D8
External Interrupt Edge selection register
IESR
W
- - 0 0 0 0 0 0
51
00D9
R0 port mode register
PMR0
W
- - - - 0 0 0 0
51
00DA
Interrupt enable low register
IENL
R/W
- - - 0 - - - 0
47
00DB
Interrupt enable high register
IENH
R/W
- - 0 0 - 0 0 0
47
00DC
Interrupt request flag low register
IRQL
R/W
- - - 0 - - - 0
47
00DD
Interrupt request flag high register
IRQH
R/W
- - 0 0 - 0 0 0
47
00DE
Sleep mode register
SMR
W
- - - - - - - 0
68
WDTR
W
0 0 1 1 1 1 1 1
64
TM1
R/W
- - - 0 0 0 0 0
40
00DF
Watchdog Timer Register
00E4
Timer 1 mode register
Timer 1 count register
T1
R
0 0 0 0 0 0 0 0
40
Timer 1 data register
TDR1
W
Undefined
40
00EC
Comparator mode register
CMR
W
0 0 - 0 0 0 0 0
45
00ED
Comparator channel selection register
CSR
W
0 - - - - - 0 0
45
00E5
00F0
Watch timer mode register
00F1
LCD control register
WTMR
W
- - - - 0 0 0 0
43
LCR
R/W
0 - 0 0 - 0 0 0
56
00F3
00F4
LCD port selection register
LPMR
R/W
0 0 0 0 0 0 0 0
60
Key Scan control register
KSCR
R/W
0 0 0 0 0 0 0 0
54
00F6
R1 port mode register
PMR1
R/W
- - - - - - - 0
66
00F7
Buzzer register
BUR
W
0 0 0 0 0 0 0 0
66
RAM paging register
RPR
R/W
0 0 0 0 0 0 0 0
25
Basic interval timer mode register
BITR
R
Undefined
39
00F8
00F9
CKCTLR
W
- - - - 0 1 1 1
39
System clock mode register
SCMR
R/W
- - - - 0 0 0 0
34
00FB
Peripheral clock control register
PCOR
W
- - - - - - - 0
34
00FE
LVD mode register
LVDR
R/W
- - - 1 0 0 0 0
75
00FA
Clock control register
MAR. 1999 Ver 1.01
i
GMS81C3004
B. PAD COORDINATION
Device
GMS81C3004
Chip size
2670µm × 2980µm
Pad Size
95µm × 95µm
B.1 Pad Layout
Y
2
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
54
11
53
12
52
X
(0, 0)
13
51
14
50
15
49
16
48
17
47
18
46
19
20
45
21
44
22
43
23
ii
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
MAR. 1999 Ver 1.01
GMS81C3004
B.2 Bonding Pad Coordination
Pad No.
Pin Name
Pad Coordination (X,Y)
Pad No.
Pin Name
Pad Coordination (X,Y)
1
2
3
4
5
R76 / SEG30
R77 / SEG31
SEG32
SEG33
SEG34
(-1077.5, 1412.5)
(-1257.5, 1412.5)
(-1257.5, 1232.5)
(-1257.5, 1082.5)
(-1257.5, 935.0)
41
42
43
44
45
R20
R21
R22
RESET
TEST
(1077.5, -1412.5)
(1257.5, -1412.5)
(1257.5, -1232.5)
(1257.5, -1082.5)
(1257.5, -935.0)
6
7
8
9
10
SEG35
SEG36
SEG37
SEG38
SEG39
(-1257.5,
(-1257.5,
(-1257.5,
(-1257.5,
(-1257.5,
815.0)
695.0)
575.0)
455.0)
335.0)
46
47
48
49
50
VDD
XOUT
XIN
SXOUT
SXIN
(1257.5, -780.0)
(1257.5, -625.0)
(1257.5, -505.0)
(1257.5, -385.0)
(1257.5, -265.0)
11
12
13
14
15
VSS
COM0
COM1
COM2
COM3
(-1257.5, 180.0)
(-1257.5, 25.0)
(-1257.5, -95.0)
(-1257.5, -215.0)
(-1257.5, -335.0)
51
52
53
54
55
SEG0 / R40
SEG1 / R41
SEG2 / R42
SEG3 / R43
SEG4 / R44
(1257.5, -145.0)
(1257.5, -25.0)
(1257.5, 95.0)
(1257.5, 215.0)
(1257.5, 335.0)
16
17
18
19
20
COM4
COM5
COM6
COM7
VCL1
(-1257.5,
(-1257.5,
(-1257.5,
(-1257.5,
(-1257.5,
-455.0)
-575.0)
-695.0)
-815.0)
-935.0)
56
57
58
59
60
SEG5 / R45
SEG6 / R46
SEG7 / R47
SEG8 / R50
SEG9 / R51
(1257.5, 455.0)
(1257.5, 575.0)
(1257.5, 695.0)
(1257.5, 815.0)
(1257.5, 935.0)
21
22
23
24
25
VCL2
VCL3
VCL4
VCL5
R10 / KS0
(-1257.5, -1082.5)
(-1257.5, -1232.5)
(-1257.5, -1412.5)
(-1077.5, -1412.5)
(-922.5, -1412.5)
61
62
63
64
65
SEG10 / R52
SEG11 / R53
SEG12 / R54
SEG13 / R55
SEG14 / R56
(1257.5, 1082.0)
(1257.5, 1232.5)
(1257.5, 1412.5)
(1077.5, 1412.5)
(922.5, 1412.5)
26
27
28
29
30
R11 / KS1
R12 / KS2
R13 / KS3
R14/ CMP0 / KS4
R15 / CMP1 / KS5
(-780.0, -1412.5)
(-660.0, -1412.5)
(-540.0, -1412.5)
(-420.0, -1412.5)
(-300.0, -1412.5)
66
67
68
69
70
SEG15 / R57
SEG16 / R60
SEG17 / R61
SEG18 / R62
SEG19 / R63
(780.0, 1412.5)
(660.0, 1412.5)
(540.0, 1412.5)
(420.0, 1412.5)
(300.0, 1412.5)
31
32
33
34
35
R16 / CMP2 / KS6
R17 / CMP3 / KS7
R00 / INT0
R01 / INT1
R02 /INT2
(-180.0, -1412.5)
(-60.0, -1412.5)
(60.0, -1412.5)
(180.0, -1412.5)
(300.0, -1412.5)
71
72
73
74
75
SEG20 / R64
SEG21 / R65
SEG22 / R66
SEG23 / R67
SEG24 / R70
(180.0, 1412.5)
(60.0, 1412.5)
(-60.0, 1412.5)
(-180.0, 1412.5)
(-300.0, 1412.5)
36
37
38
39
40
R03 / EC1
R04
R05
R06 / LCDCK
R07
(420.0, -1412.5)
(540.0, -1412.5)
(660.0, -1412.5)
(780.0, -1412.5)
(922.5, -1412.5)
76
77
78
79
80
SEG25 / R71
SEG26 / R72
SEG27 / R73
SEG28 / R74
SEG29 / R75
(-420.0, 1412.5)
(-540.0, 1412.5)
(-660.0, 1412.5)
(-780.0, 1412.5)
(-922.5, 1412.5)
MAR. 1999 Ver 1.01
iii
GMS81C3004
C. INSTRUCTION
C.1 Terminology List
Terminology
Description
A
Accumulator
X
X - register
Y
Y - register
PSW
Program Status Word
#imm
8-bit Immediate data
dp
!abs
Direct Page Offset Address
Absolute Address
[]
Indirect expression
{}
Register Indirect expression
{ }+
Register Indirect expression, after that, Register auto-increment
.bit
Bit Position
A.bit
Bit Position of Accumulator
dp.bit
Bit Position of Direct Page Memory
M.bit
Bit Position of Memory Data (000 H~0FFF H)
rel
upage
Relative Addressing Data
U-page (0FF00H~0FFFFH) Offset Address
n
Table CALL Number (0~15)
+
Addition
Upper Nibble Expression in Opcode
0
x
Bit Position
Upper Nibble Expression in Opcode
1
y
Bit Position
iv
−
Subtraction
×
Multiplication
/
Division
()
Contents Expression
∧
AND
∨
OR
⊕
Exclusive OR
~
NOT
←
Assignment / Transfer / Shift Left
→
Shift Right
↔
Exchange
=
Equal
≠
Not Equal
MAR. 1999 Ver 1.01
GMS81C3004
C.2 Instruction Map
LOW 00000
00
HIGH
00001
01
SET1
dp.bit
00010
02
00011
03
BBS
BBS
A.bit,rel dp.bit,rel
00100
04
00101
05
00110
06
00111
07
01000
08
01001
09
01010
0A
01011
0B
01100
0C
01101
0D
01110
0E
01111
0F
ADC
#imm
ADC
dp
ADC
dp+X
ADC
!abs
ASL
A
ASL
dp
TCALL
0
SETA1
.bit
BIT
dp
POP
A
PUSH
A
BRK
000
-
001
CLRC
SBC
#imm
SBC
dp
SBC
dp+X
SBC
!abs
ROL
A
ROL
dp
TCALL CLRA1
2
.bit
COM
dp
POP
X
PUSH
X
BRA
rel
010
CLRG
CMP
#imm
CMP
dp
CMP
dp+X
CMP
!abs
LSR
A
LSR
dp
TCALL
4
NOT1
M.bit
TST
dp
POP
Y
PUSH
Y
PCALL
Upage
011
DI
OR
#imm
OR
dp
OR
dp+X
OR
!abs
ROR
A
ROR
dp
TCALL
6
OR1
OR1B
CMPX
dp
POP
PSW
PUSH
PSW
RET
100
CLRV
AND
#imm
AND
dp
AND
dp+X
AND
!abs
INC
A
INC
dp
TCALL AND1
8
AND1B
CMPY
dp
CBNE
dp+X
TXSP
INC
X
101
SETC
EOR
#imm
EOR
dp
EOR
dp+X
EOR
!abs
DEC
A
DEC
dp
TCALL EOR1
10
EOR1B
DBNE
dp
XMA
dp+X
TSPX
DEC
X
110
SETG
LDA
#imm
LDA
dp
LDA
dp+X
LDA
!abs
TXA
LDY
dp
TCALL
12
LDC
LDCB
LDX
dp
LDX
dp+Y
XCN
DAS
111
EI
LDM
dp,#imm
STA
dp
STA
dp+X
STA
!abs
TAX
STY
dp
TCALL
14
STC
M.bit
STX
dp
STX
dp+Y
XAX
STOP
10011
13
10100
14
10101
15
10110
16
10111
17
11000
18
11001
19
11010
1A
11011
1B
11100
1C
11101
1D
11110
1E
11111
1F
ADC
{X}
ADC
!abs+Y
ADC
[dp+X]
ADC
[dp]+Y
ASL
!abs
ASL
dp+X
TCALL
1
JMP
!abs
BIT
!abs
ADDW
dp
LDX
#imm
JMP
[!abs]
TEST
!abs
SUBW
dp
LDY
#imm
JMP
[dp]
TCLR1 CMPW
!abs
dp
CMPX
#imm
CALL
[dp]
LOW 10000
HIGH
10
10001
11
10010
12
000
BPL
rel
001
BVC
rel
SBC
{X}
SBC
!abs+Y
SBC
[dp+X]
SBC
[dp]+Y
ROL
!abs
ROL
dp+X
TCALL
3
CALL
!abs
010
BCC
rel
CMP
{X}
CMP
!abs+Y
CMP
[dp+X]
CMP
[dp]+Y
LSR
!abs
LSR
dp+X
TCALL
5
MUL
011
BNE
rel
OR
{X}
OR
!abs+Y
OR
[dp+X]
OR
[dp]+Y
ROR
!abs
ROR
dp+X
TCALL
7
DBNE
Y
CMPX
!abs
LDYA
dp
CMPY
#imm
RETI
100
BMI
rel
AND
{X}
AND
!abs+Y
AND
[dp+X]
AND
[dp]+Y
INC
!abs
INC
dp+X
TCALL
9
DIV
CMPY
!abs
INCW
dp
INC
Y
TAY
101
BVS
rel
EOR
{X}
EOR
!abs+Y
EOR
[dp+X]
EOR
[dp]+Y
DEC
!abs
DEC
dp+X
TCALL
11
XMA
{X}
XMA
dp
DECW
dp
DEC
Y
TYA
110
BCS
rel
LDA
{X}
LDA
!abs+Y
LDA
[dp+X]
LDA
[dp]+Y
LDY
!abs
LDY
dp+X
TCALL
13
LDA
{X}+
LDX
!abs
STYA
dp
XAY
DAA
111
BEQ
rel
STA
{X}
STA
!abs+Y
STA
[dp+X]
STA
[dp]+Y
STY
!abs
STY
dp+X
TCALL
15
STA
{X}+
STX
!abs
CBNE
dp
XYX
NOP
CLR1
BBC
BBC
dp.bit
A.bit,rel
dp.bit,rel
MAR. 1999 Ver 1.01
v
GMS81C3004
C.3 Instruction Set
Arithmetic / Logic Operation
No.
1
vi
Mnemonic
ADC #imm
Op
Code
Byte
No
Cycle
No
04
2
2
Add with carry.
A←(A)+(M)+C
2
ADC dp
05
2
3
3
ADC dp + X
06
2
4
4
ADC !abs
07
3
4
5
ADC !abs + Y
15
3
5
6
ADC [ dp + X ]
16
2
6
7
ADC [ dp ] + Y
17
2
6
8
ADC { X }
14
1
3
9
AND #imm
84
2
2
Logical AND
A← (A)∧(M)
10
AND dp
85
2
3
11
AND dp + X
86
2
4
12
AND !abs
87
3
4
13
AND !abs + Y
95
3
5
Flag
Operation
NVGBHIZC
NV--H-ZC
N-----Z-
14
AND [ dp + X ]
96
2
6
15
AND [ dp ] + Y
97
2
6
16
AND { X }
94
1
3
17
ASL A
08
1
2
18
ASL dp
09
2
4
19
ASL dp + X
19
2
5
20
ASL !abs
18
3
5
21
CMP #imm
44
2
2
22
CMP dp
45
2
3
23
CMP dp + X
46
2
4
24
CMP !abs
47
3
4
25
CMP !abs + Y
55
3
5
26
CMP [ dp + X ]
56
2
6
27
CMP [ dp ] + Y
57
2
6
28
CMP { X }
54
1
3
29
CMPX #imm
5E
2
2
30
CMPX dp
6C
2
3
31
CMPX !abs
7C
3
4
32
CMPY #imm
7E
2
2
33
CMPY dp
8C
2
3
34
CMPY !abs
9C
3
4
35
COM dp
2C
2
4
1’S Complement : ( dp ) ← ~( dp )
N-----Z-
36
DAA
DF
1
3
Decimal adjust for addition
N-----ZC
37
DAS
CF
1
3
Decimal adjust for subtraction
N-----ZC
38
DEC A
A8
1
2
Decrement
N-----Z-
39
DEC dp
A9
2
4
40
DEC dp + X
B9
2
5
N-----Z-
41
DEC !abs
B8
3
5
N-----Z-
42
DEC X
AF
1
2
N-----Z-
43
DEC Y
BE
1
2
N-----Z-
Arithmetic shift left
C
7 6 5 4 3 2 1 0
← ←←←←←←←←
N-----ZC
← “0”
Compare accumulator contents with memory contents
(A) -(M)
N-----ZC
Compare X contents with memory contents
(X)-(M)
N-----ZC
Compare Y contents with memory contents
(Y)-(M)
M← (M)-1
N-----ZC
N-----Z-
MAR. 1999 Ver 1.01
GMS81C3004
No.
Mnemonic
Op
Code
Byte
No
Cycle
No
Operation
Flag
NVGBHIZC
44
DIV
9B
1
12
Divide : YA / X Q: A, R: Y
45
EOR #imm
A4
2
2
Exclusive OR
46
EOR dp
A5
2
3
47
EOR dp + X
A6
2
4
48
EOR !abs
A7
3
4
49
EOR !abs + Y
B5
3
5
50
EOR [ dp + X ]
B6
2
6
51
EOR [ dp ] + Y
B7
2
6
52
EOR { X }
B4
1
3
53
INC A
88
1
2
54
INC dp
89
2
4
55
INC dp + X
99
2
5
N-----Z-
56
INC !abs
98
3
5
N-----Z-
57
INC X
8F
1
2
N-----Z-
58
INC Y
9E
1
2
N-----Z-
59
LSR A
48
1
2
60
LSR dp
49
2
4
61
LSR dp + X
59
2
5
NV--H-Z-
A← (A)⊕(M)
N-----Z-
Increment
N-----ZC
M← (M)+1
N-----Z-
Logical shift right
7 6 5 4 3 2 1 0
C
“0” → → → → → → → → → →
62
LSR !abs
58
3
5
63
MUL
5B
1
9
Multiply : YA ← Y × A
64
OR #imm
64
2
2
Logical OR
65
OR dp
65
2
3
66
OR dp + X
66
2
4
67
OR !abs
67
3
4
68
OR !abs + Y
75
3
5
69
OR [ dp + X ]
76
2
6
70
OR [ dp ] + Y
77
2
6
71
OR { X }
74
1
3
72
ROL A
28
1
2
73
ROL dp
29
2
4
74
ROL dp + X
39
2
5
75
ROL !abs
38
3
5
76
ROR A
68
1
2
Rotate right through Carry
77
ROR dp
69
2
4
78
ROR dp + X
79
2
5
7 6 5 4 3 2 1 0
→→→→→→→→
79
ROR !abs
78
3
5
80
SBC #imm
24
2
2
81
SBC dp
25
2
3
82
SBC dp + X
26
2
4
83
SBC !abs
27
3
4
N-----ZC
N-----Z-
A ← (A)∨(M)
N-----Z-
Rotate left through Carry
C
7 6 5 4 3 2 1 0
←←←←←←←←
C
N-----ZC
N-----ZC
Subtract with Carry
A ← ( A ) - ( M ) - ~( C )
NV--HZC
84
SBC !abs + Y
35
3
5
85
SBC [ dp + X ]
36
2
6
86
SBC [ dp ] + Y
37
2
6
87
SBC { X }
34
1
3
88
TST dp
4C
2
3
Test memory contents for negative or zero, ( dp ) - 00H
N-----Z-
5
Exchange nibbles within the accumulator
A 7~A 4 ↔ A3~A 0
N-----Z-
89
XCN
MAR. 1999 Ver 1.01
CE
1
vii
GMS81C3004
Register / Memory Operation
No.
Mnemonic
Op
Code
Byte
No
Cycle
No
1
LDA #imm
C4
2
2
2
LDA dp
C5
2
3
3
LDA dp + X
C6
2
4
4
LDA !abs
C7
3
4
5
LDA !abs + Y
D5
3
5
6
LDA [ dp + X ]
D6
2
6
7
LDA [ dp ] + Y
D7
2
6
8
LDA { X }
D4
1
3
Flag
Operation
NVGBHIZC
Load accumulator
A←(M)
N-----Z-
LDA { X }+
DB
1
4
X- register auto-increment : A ← ( M ) , X ← X + 1
10
LDM dp,#imm
E4
3
5
Load memory with immediate data : ( M ) ← imm
11
LDX #imm
1E
2
2
Load X-register
12
LDX dp
CC
2
3
13
LDX dp + Y
CD
2
4
14
LDX !abs
DC
3
4
15
LDY #imm
3E
2
2
16
LDY dp
C9
2
3
17
LDY dp + X
D9
2
4
18
LDY !abs
D8
3
4
19
STA dp
E5
2
4
20
STA dp + X
E6
2
5
21
STA !abs
E7
3
5
22
STA !abs + Y
F5
3
6
23
STA [ dp + X ]
F6
2
7
24
STA [ dp ] + Y
F7
2
7
9
X ←(M)
-------N-----Z-
Load Y-register
Y←(M)
N-----Z-
Store accumulator contents in memory
(M)←A
--------
25
STA { X }
F4
1
4
26
STA { X }+
FB
1
4
X- register auto-increment : ( M ) ← A, X ← X + 1
27
STX dp
EC
2
4
Store X-register contents in memory
28
STX dp + Y
ED
2
5
29
STX !abs
FC
3
5
30
STY dp
E9
2
4
31
STY dp + X
F9
2
5
32
STY !abs
F8
3
5
33
TAX
E8
1
2
Transfer accumulator contents to X-register : X ← A
N-----Z-
34
TAY
9F
1
2
Transfer accumulator contents to Y-register : Y ← A
N-----Z-
(M)← X
--------
Store Y-register contents in memory
(M)← Y
--------
35
TSPX
AE
1
2
Transfer stack-pointer contents to X-register : X ← sp
N-----Z-
36
TXA
C8
1
2
Transfer X-register contents to accumulator: A ← X
N-----Z-
37
TXSP
8E
1
2
Transfer X-register contents to stack-pointer: sp ← X
N-----Z-
38
TYA
BF
1
2
Transfer Y-register contents to accumulator: A ← Y
N-----Z-
39
XAX
EE
1
4
Exchange X-register contents with accumulator :X ↔ A
--------
40
XAY
DE
1
4
Exchange Y-register contents with accumulator :Y ↔ A
--------
41
XMA dp
BC
2
5
Exchange memory contents with accumulator
42
XMA dp+X
AD
2
6
43
XMA {X}
BB
1
5
44
XYX
FE
1
4
viii
(M)↔A
N-----Z-
Exchange X-register contents with Y-register : X ↔ Y
--------
MAR. 1999 Ver 1.01
GMS81C3004
16-BIT operation
No.
Mnemonic
Op
Code
Byte
No
Cycle
No
Operation
Flag
NVGBHIZC
1
ADDW dp
1D
2
5
16-Bits add without Carry
YA ← ( YA ) ( dp +1 ) ( dp )
NV--H-ZC
2
CMPW dp
5D
2
4
Compare YA contents with memory pair contents :
(YA) − (dp+1)(dp)
N-----ZC
3
DECW dp
BD
2
6
Decrement memory pair
( dp+1)( dp) ← ( dp+1) ( dp) - 1
N-----Z-
4
INCW dp
9D
2
6
Increment memory pair
( dp+1) ( dp) ← ( dp+1) ( dp ) + 1
N-----Z-
5
LDYA dp
7D
2
5
Load YA
YA ← ( dp +1 ) ( dp )
N-----Z-
6
STYA dp
DD
2
5
Store YA
( dp +1 ) ( dp ) ← YA
--------
7
SUBW dp
3D
2
5
16-Bits subtract without carry
YA ← ( YA ) - ( dp +1) ( dp)
NV--H-ZC
Op
Code
Byte
No
Cycle
No
Bit Manipulation
No.
Mnemonic
Operation
Flag
NVGBHIZC
1
AND1 M.bit
8B
3
4
Bit AND C-flag : C ← ( C ) ∧ ( M .bit )
-------C
2
AND1B M.bit
8B
3
4
Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit )
-------C
3
BIT dp
0C
2
4
Bit test A with memory :
MM----Z-
4
BIT !abs
1C
3
5
Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M6 )
5
CLR1 dp.bit
y1
2
4
Clear bit : ( M.bit ) ← “0”
--------
6
CLRA1 A.bit
2B
2
2
Clear A bit : ( A.bit ) ← “0”
--------
7
CLRC
20
1
2
Clear C-flag : C ← “0”
-------0
8
CLRG
40
1
2
Clear G-flag : G ← “0”
--0-----
9
CLRV
80
1
2
Clear V-flag : V ← “0”
-0--0---
10
EOR1 M.bit
AB
3
5
Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit )
-------C
11
EOR1B M.bit
AB
3
5
Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit)
-------C
12
LDC M.bit
CB
3
4
Load C-flag : C ← ( M .bit )
-------C
13
LDCB M.bit
CB
3
4
Load C-flag with NOT : C ← ~( M .bit )
-------C
14
NOT1 M.bit
4B
3
5
Bit complement : ( M .bit ) ← ~( M .bit )
--------
15
OR1 M.bit
6B
3
5
Bit OR C-flag : C ← ( C ) ∨ ( M .bit )
-------C
16
OR1B M.bit
6B
3
5
Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit )
-------C
17
SET1 dp.bit
x1
2
4
Set bit : ( M.bit ) ← “1”
--------
18
SETA1 A.bit
0B
2
2
Set A bit : ( A.bit ) ← “1”
--------
19
SETC
A0
1
2
Set C-flag : C ← “1”
-------1
20
SETG
C0
1
2
Set G-flag : G ← “1”
--1-----
21
STC M.bit
EB
3
6
Store C-flag : ( M .bit ) ← C
-------N-----ZN-----Z-
22
TCLR1 !abs
5C
3
6
Test and clear bits with A :
A - ( M ) , ( M ) ← ( M ) ∧ ~( A )
23
TSET1 !abs
3C
3
6
Test and set bits with A :
A-(M), (M)← (M)∨(A)
MAR. 1999 Ver 1.01
ix
GMS81C3004
Branch / Jump Operation
No.
x
Mnemonic
Op
Code
Byte
No
Cycle
No
Flag
Operation
NVGBHIZC
1
BBC A.bit,rel
y2
2
4/6
Branch if bit clear :
2
BBC dp.bit,rel
y3
3
5/7
if ( bit ) = 0 , then pc ← ( pc ) + rel
3
BBS A.bit,rel
x2
2
4/6
Branch if bit set :
4
BBS dp.bit,rel
x3
3
5/7
if ( bit ) = 1 , then pc ← ( pc ) + rel
5
BCC rel
50
2
2/4
Branch if carry bit clear
if ( C ) = 0 , then pc ← ( pc ) + rel
--------
6
BCS rel
D0
2
2/4
Branch if carry bit set
if ( C ) = 1 , then pc ← ( pc ) + rel
--------
7
BEQ rel
D0
2
2/4
Branch if equal
if ( Z ) = 1 , then pc ← ( pc ) + rel
--------
8
BMI rel
90
2
2/4
Branch if minus
if ( N ) = 1 , then pc ← ( pc ) + rel
--------
9
BNE rel
70
2
2/4
Branch if not equal
if ( Z ) = 0 , then pc ← ( pc ) + rel
--------
10
BPL rel
10
2
2/4
Branch if minus
if ( N ) = 0 , then pc ← ( pc ) + rel
--------
11
BRA rel
2F
2
4
Branch always
pc ← ( pc ) + rel
--------
12
BVC rel
30
2
2/4
Branch if overflow bit clear
if (V) = 0 , then pc ← ( pc) + rel
--------
13
BVS rel
B0
2
2/4
Branch if overflow bit set
if (V) = 1 , then pc ← ( pc ) + rel
--------
14
CALL !abs
3B
3
8
Subroutine call
15
CALL [dp]
5F
2
8
M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1,
if !abs, pc← abs ; if [dp], pc L← ( dp ), pcH ← ( dp+1 ) .
--------
16
CBNE dp,rel
FD
3
5/7
Compare and branch if not equal :
--------
17
CBNE dp+X,rel
8D
3
6/8
18
DBNE dp,rel
AC
3
5/7
Decrement and branch if not equal :
19
DBNE Y,rel
7B
2
4/6
if ( M ) ≠ 0 , then pc ← ( pc ) + rel.
20
JMP !abs
1B
3
3
21
JMP [!abs]
1F
3
5
22
JMP [dp]
3F
2
4
23
PCALL upage
4F
2
6
U-page call
M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ),
sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH” .
--------
24
TCALL n
nA
1
8
Table call : (sp) ←( pcH ), sp ← sp - 1,
M(sp) ← ( pcL ),sp ← sp - 1,
pc L ← (Table vector L), pcH ← (Table vector H)
--------
--------
--------
if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel.
--------
Unconditional jump
pc ← jump address
--------
MAR. 1999 Ver 1.01
GMS81C3004
Control Operation & Etc.
No.
1
Mnemonic
BRK
Op
Code
Byte
No
Cycle
No
Operation
0F
1
8
Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1,
M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1,
pc L ← ( 0FFDEH ) , pc H ← ( 0FFDFH ) .
---1-0--
Flag
NVGBHIZC
2
DI
60
1
3
Disable all interrupts : I ← “0”
-----0--
3
EI
E0
1
3
Enable all interrupt : I ← “1”
-----1--
4
NOP
FF
1
2
No operation
--------
5
POP A
0D
1
4
sp ← sp + 1, A ← M( sp )
6
POP X
2D
1
4
sp ← sp + 1, X ← M( sp )
7
POP Y
4D
1
4
sp ← sp + 1, Y ← M( sp )
8
POP PSW
6D
1
4
sp ← sp + 1, PSW ← M( sp )
M( sp ) ← A , sp ← sp - 1
-------restored
9
PUSH A
0E
1
4
10
PUSH X
2E
1
4
M( sp ) ← X , sp ← sp - 1
11
PUSH Y
4E
1
4
M( sp ) ← Y , sp ← sp - 1
12
PUSH PSW
6E
1
4
M( sp ) ← PSW , sp ← sp - 1
13
RET
6F
1
5
Return from subroutine
sp ← sp +1, pcL ← M( sp ), sp ← sp +1, pcH ← M( sp )
--------
14
RETI
7F
1
6
Return from interrupt
sp ← sp +1, PSW ← M( sp ), sp ← sp + 1,
pc L ← M( sp ), sp ← sp + 1, pcH ← M( sp )
restored
15
STOP
EF
1
3
Stop mode ( halt CPU, stop oscillator )
--------
MAR. 1999 Ver 1.01
--------
xi
D. MASK ORDER SHEET
MASK ORDER & VERIFICATION SHEET
GMS81C3004-LA
Customer should write inside thick line box.
1. Customer Information
Company Name
Application
YYYY
MM
DD
Package
80QFP
DIE
OSC Opt.
Crystal
RC
Mask Data File Name: (
Order Date
Tel:
2. Device Information
Hitel
Fax:
.OTP)
Check Sum: (
)
0000H
Name &
Signature:
Chollian
Set “FF” in
this area
Internet
6FFFH
7000H
.OTP file data
7FFFH
3. Marking Specification
(if 80QFP sale)
(Please check mark into
LGS
)
G M S81C 3004-LAxxx
Y YW W KO REA
#1 index mark
4. Delivery Schedule
Quantity
Date
YYYY
MM
DD
Customer Sample
pcs
YYYY
MM
DD
pcs
Risk Order
5. ROM Code Verification
YYYY
This box is written after “5.Verification”.
MM
DD
Approval Date:
Verification D ate:
Please confirm our verification data.
Fax:
YYYY
MM
DD
I agree w ith your verification data and confirm
you to m ake m ask set.
Tel:
Check Sum:
Tel:
Name &
Signature:
LG Confirmation
Fax:
Name &
Signature:
LG Semicon