Z86L33/L43 CP96LVO1501 PRELIMINAR Y CUSTOMER P ROCUREMENT S PECIFICA TION Z86L33/L43 CMOS Z8® CONSUMER CONTROLLER PROCESSOR FEATURES Part Z86L33 Z86L43 ROM (KB) 4 4 RAM* (Bytes) 237 236 Speed (MHz) 8 8 ■ 32 Input/Output Lines (L43) 24 Input/Output Lines (L33) ■ Vectored, Prioritized Interrupts with Programmable Polarity ■ Two Analog Comparators ■ Two Programmable 8-Bit Counter/Timers, Each with Two 6-Bit Programmable Prescaler * General-Purpose ■ 40-Pin DIP, 44-Pin PLCC and QFP Packages (L43) 28-Pin DIP, 28-Pin SOIC (L33) ■ 2.0- to 3.9-Volt Operating Range ■ Low-Power Consumption ■ Watch-Dog Timer (WDT)/Power-On Reset (POR) ■ 0°C to +70°C Operating Range ■ On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock ■ Expanded Register File (ERF) ■ RAM and ROM Protect GENERAL DESCRIPTION The Z86L33/L43 Consumer Controller Processor (CCP™) is a member of Zilog's Z8® single-chip microcontroller family with enhanced wake-up circuitry, programmable Watch-Dog Timers (WDT), and low-noise/EMI options. These enhancements result in a more efficient, costeffective design and provide the user with increased design flexibility over the standard Z8 microcontroller core. This low-power consumption CMOS microcontroller offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion. The Z86L33/L43 features an Expanded Register File (ERF) to allow access to register-mapped peripheral and I/O circuits. Four basic address spaces are available to support this wide range of configurations: Program Memory, Register File, External Data Memory (L43), and ERF. The Register File is composed of 236 bytes of general-purpose registers, four I/O port registers, and 15 control and status registers. The ERF consists of three control registers (Banks 0,D, and F) For applications demanding powerful I/O capabilities, the Z86L33 provides 24 pins, and the Z86L43 provides 32 pins dedicated to input and output. These lines are configurable CP96LVO1501 (6/96) under software control to provide timing, status signals, parallel I/O with or without handshake, and address/data bus for interfacing external memory. To unburden the system from coping with real-time tasks such as counting/timing and data communication, the Z86L33/L43 offers two on-chip counter/timers with a large number of user-selectable modes. With ROM/ROMless selectivity, the Z86L43 provides both external memory and pre-programmed ROM, which enables this Z8 microcontroller to be used in high-volume applications, or where code flexibility is required. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS 1 Z86L33/L43 CP96LVO1501 GENERAL DESCRIPTION (Continued) (L43 Only) Output Input Vcc GND Machine Timing & Inst. Control Port 3 Counter/ Timers (2) RESET WDT, POR ALU FLAG Interrupt Control Two Analog Comparators Prg. Memory 4K Register Pointer Register File Port 0 Port 2 4 I/O (Bit Programmable) Program Counter Port 1 4 Address or I/O (Nibble Programmable) Functional Block Diagram 2 XTAL /AS /DS R//W /RESET 8 Address/Data or I/O (Byte Programmable) (L43 Only) Z86L33/L43 CP96LVO1501 PIN DESCRIPTION 28-Pin DIP/SOIC Pin Identification P25 1 28 P24 P26 2 27 P23 Pin # Symbol Function Direction P27 3 26 P22 P04 4 25 P21 5 24 P20 Port 2, Pins 5,6,7 Port 0, Pins 4,5,6,7 Power Supply Crystal Oscillator In/Output In/Output P05 1-3 4-7 8 9 P06 6 23 P03 22 VSS 10 XTAL1 11-13 P33-31 14-15 P35-4 16 P37 17 P36 Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pins 4,5 Port 3, Pin 7 Port 3, Pin 6 Input Fixed Input Fixed Output Fixed Output Fixed Output 18 P30 19-21 P02-00 22 VSS 23 P03 24-28 P24-20 Port 3, Pin 0 Port 0, Pins 0,1,2 Ground Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Fixed Input In/Output Z86L33 P07 7 VDD 8 21 P02 XTAL2 9 20 P01 XTAL1 10 19 P00 P31 11 18 P30 P32 12 17 P36 P33 13 16 P37 P34 14 15 P35 P27-25 P07-04 VDD XTAL2 Output In/Output In/Output 28-Pin DIP Pin Configuration P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Z86L33 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 P30 P36 P37 P35 28-Pin SOIC Pin Configuration 3 Z86L33/L43 CP96LVO1501 PIN DESCRIPTION (Continued) R//W 1 40 /DS P25 2 39 P24 P26 3 38 P23 P27 4 37 P22 P04 5 36 P21 P05 6 35 P20 P06 7 34 P03 P14 8 33 P13 P15 9 32 P12 31 GND Z86L43 P07 10 VCC 11 30 P02 P16 12 29 P11 P17 13 28 P10 XTAL2 14 27 P01 XTAL1 15 26 P00 P31 16 25 P30 17 24 P36 P33 18 23 P37 P34 19 22 P35 /AS 20 21 /RESET P32 40-Pin DIP Assignments 40-Pin Dual-In-Line Package Pin Identification 4 Pin # Symbol Function Direction Pin # Symbol Function Direction 1 2-4 5-7 8-9 R//W P25-27 P04-06 P14-15 Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Output In/Output In/Output In/Output 22 23 24 25 P35 P37 P36 P30 Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Output Output Output Input 10 11 12-13 14 P07 VCC P16-17 XTAL2 Port 0, Pin 7 In/Output Power Supply Port 1, Pins 6,7 In/Output Crystal, Oscillator Clock Output 26-27 28-29 30 31 P00-01 P10-11 P02 GND Port 0, Pin 0,1 Port 1, Pin 0,1 Port 0, Pin 2 Ground In/Output In/Output In/Output 15 16-18 19 20 21 XTAL1 P31-33 P34 /AS /RESET Crystal, Oscillator Clock Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe Reset 32-33 34 35-39 40 P12-13 P03 P20-24 /DS Port 1, Pin 2,3 Port 0, Pin 3 Port 2, Pin 0,1,2,3,4 Data Strobe In/Output In/Output In/Output Output Input Input Output Output Input Z86L33/L43 CP96LVO1501 GND GND P02 3 2 1 44 43 42 41 40 P00 P12 4 P01 P13 5 P10 P03 6 P11 P20 PIN DESCRIPTION (Continued) P21 7 39 P30 P22 8 38 P36 P23 9 37 P37 P24 10 36 P35 /DS 11 35 /RESET Z86L43 N/C 12 34 R//RL R//W 13 33 /AS P25 14 32 P34 P26 15 31 P33 P27 16 30 P32 P04 17 29 P31 XTAL1 XTAL2 P17 P16 VCC VCC P07 P15 P14 P06 P05 18 19 20 21 22 23 24 25 26 27 28 44-Pin PLCC Pin Assignments 44-Pin PLCC Pin Identification Pin # Symbol Function Direction Pin # Symbol Function Direction 1-2 3-4 5 6-10 11 GND P12-13 P03 P20-24 /DS Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe In/Output In/Output In/Output Output 28 29-31 32 33 34 XTAL1 P31-33 P34 /AS R//RL Crystal, Oscillator Clock Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless Control Input Input Output Output Input 12 13 14-16 17-19 20-21 N/C R//W P25-27 P04-06 P14-15 Not Connected Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Output In/Output In/Output In/Output 35 36 37 38 39 /RESET P35 P37 P36 P30 Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Input Output Output Output Input 22 23,24 25-26 27 P07 V CC P16-17 XTAL2 Port 0, Pin 7 In/Output Power Supply Port 1, Pins 6,7 In/Output Crystal, Oscillator Clock Output Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 In/Output In/Output In/Output 40-41 P00-01 42-43 P10-11 44 P02 5 Z86L33/L43 CP96LVO1501 P00 P01 P10 P11 P02 GND GND P12 P13 P03 P20 PIN DESCRIPTION (Continued) 33 32 31 30 29 28 27 26 25 24 23 P21 34 22 P30 P22 35 21 P36 P23 36 20 P37 P24 37 19 P35 /DS 38 18 /RESET N/C 39 17 R//RL R//W 40 16 /AS P25 41 15 P34 P26 42 14 P33 P27 43 13 P32 P04 44 12 P31 4 5 6 7 8 9 10 11 P15 P07 VCC VCC P16 P17 XTAL1 3 XTAL2 2 P14 P05 1 P06 Z86L43 44-Pin QFP Pin Assignments 44-Pin QFP Pin Identification 6 Pin # Symbol Function Direction Pin # Symbol Function Direction 1-2 3-4 5 6-7 8-9 P05-06 P14-15 P07 VCC P16-17 Port 0, Pins 5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Port 1 Pins 6,7 In/Output In/Output In/Output In/Output 21 22 23-24 25-26 27 P36 P30 P00-01 P10-11 P02 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Output Input In/Output In/Output In/Output 10 11 12-14 15 16 XTAL2 XTAL1 P31-33 P34 /AS Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe Output Input Input Output Output 28-29 30-31 32 33-37 38 GND P12-13 P03 P20-24 /DS Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe In/Output In/Output In/Output Output 17 18 19 20 R//RL /RESET P35 P37 ROM/ROMless Control Reset Port 3, Pin 5 Port 3, Pin 7 Input Input Output Output 39 40 41-43 44 N/C R//W P25-27 P04 Not Connected Read/Write Port 2, Pins 5,6,7 Port 0, Pin 4 Output In/Output In/Output Z86L33/L43 CP96LVO1501 ABSOLUTE MAXIMUM RATINGS Symbol Description Min Max Units VCC TSTG TA Supply Voltage (*) –0.3 Storage Temp –65 Oper Ambient Temp Power Dissipation +7.0 +150 V C C W 2.2 Notes: * Voltage on all pins with respect to GND. See Ordering Information. Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Test Load Diagram). From Output Under Test 150 pF Test Load Diagram CAPACITANCE TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, Unmeasured pins to GND Parameter Input capacitance Output capacitance I/O capacitance Max 12 pF 12 pF 12 pF 7 Z86L33/L43 CP96LVO1501 DC ELECTRICAL CHARACTERISTICS Sym Parameter Max Input Voltage VCC Note [3] Notes V V IIN < 250 µA IIN < 250 µA 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 V V Driven by External Clock Generator Driven by External Clock Generator 2.0V 3.9V 2.0V 3.9V GND-0.3 GND-0.3 0.7 VCC 0.7 VCC 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 V V V V Driven by External Clock Generator Driven by External Clock Generator 2.0V 3.9V 2.0V 3.9V GND-0.3 0.2 VCC GND-0.3 0.2 VCC VCC-0.4 VCC-0.4 V V V V IOH = -2.0 mA IOH = -2.0 mA [8] [8] V V V V IOL = +4.0 mA IOL = +4.0 mA IOL = +6 mA IOL = +12 mA [8] [8] [8] [8] Clock Input High Voltage 2.0V 3.9V VCL Clock Input Low Voltage VIH Input High Voltage VIL Input Low Voltage VOH1 Output High Voltage VOL1 Output Low Voltage VOL2 Output Low Voltage VRH Reset Input High Voltage 2.0V 3.9V Reset Input Low Voltage 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V VOFFSET Comparator Input Offset Voltage IIL Input Leakage 2.0V 3.9V 2.0V 3.9V IOL Output Leakage IIR Reset Input Current 2.0V 3.9V 2.0V 3.9V ICC Supply Current 2.0V 3.9V ICC1 Standby Current ICC2 Standby Current 8 Typical [13] @ 25°C Units Conditions 7 7 2.0V 3.9V VCH VRl TA = 0° C to +70°C Min Max 0.6 0.4 1.2 1.2 .8 VCC VCC .8 VCC VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC . V V V V 25 25 2 2 10 10 <1 <1 mV mV µA µA 1 1 -130 -180 <1 <1 -25 -40 µA µA µA µA VIN = OV, VCC VIN = OV, VCC 10 17 mA mA @ 8 MHz @ 8 MHz [4] [4] 2.0V 3.9V 2.0V 3.9V 4.0 6.0 3.0 5.0 mA mA mA mA HALT Mode VIN = OV, VCC @ 8 MHz HALT Mode VIN = OV, VCC @ 8 MHz Clock Divide-by-12 @ 8 MHz Clock Divide-by-12 @ 8 MHz [4] [4] [4] [4] 2.0V 8 µA 3.9V 10 µA 2.0V 500 µA 3.9V 800 µA STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is Running STOP Mode VIN = OV, VCC WDT is Running -1 -1 -1 -1 [10] [10] VIN = OV, VCC VIN = OV, VCC [6,11] [6,11] [6,11,14] [6,11,14] Z86L33/L43 CP96LVO1501 DC ELECTRICAL CHARACTERISTICS (Continued) Sym Parameter VCC Note [3] TA = 0° C to +70°C Min Max VICR Input Common Mode Voltage Range 2.0V 3.9V 0 0 VCC-1.0V VCC-1.0V IALL Auto Latch Low Current IALH Auto Latch High Current 2.0V 3.9V 2.0V 3.9V 0.7 1.4 -0.6 -1.0 8 15 -5 -8 VLV VCC Low Voltage Protection Voltage 1.4 2.15 VOH Output High Voltage (Low EMI Mode) 2.0V 3.9V VOL Output Low Voltage (Low EMI Mode) 2.0V 3.9V VCC-0.4 VCC-0.4 0.6 0.4 Typical [13] @ 25°C Units Conditions V V Notes [10] [10] µA µA µA µA OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC [9] [9] [9] [9] V 2 MHz max Int. CLK Freq. [7] 3.1 4.8 V V IOH = -0.5 mA IOH = -0.5 mA 0.2 0.1 V V IOL = 1.0 mA IOL = 1.0 mA 2.4 4.7 -1.8 -3.8 Notes: [1] I CC1 Typ Max Unit Freq Clock-Driven 0.3 mA 5 mA 8 MHz Resonator or Crystal 3.0 mA 5 mA 8 MHz [5] [2] GND = 0V. [3] VCC = 2.0V to 3.9V. [4] All outputs unloaded, I/O pins floating, inputs at rail. [5] CL1 = CL2 = 10 pF. [6] Same as note [4] except inputs at VCC. [7] The VLV voltage increases as the temperature decreases and will overlap lower V CC operating region. [8] Standard Mode (not Low EMI). [9] Auto Latch (Mask Option) selected. [10] For analog comparator, inputs when analog comparators are enabled. [11] Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating. [12] Excludes clock pins. [13] Typicals are at VCC = 3.0V. [14] Internal RC selected. 9 Z86L33/L43 CP96LVO1501 AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram (C43 Only) R//W 13 12 19 Port 0, /DM 16 Port 1 20 3 18 A7 - A0 1 D7 - D0 IN 2 9 /AS 8 11 4 5 /DS (Read) 6 17 10 Port1 A7 - A0 D7 - D0 OUT 14 15 7 /DS (Write) External I/O or Memory Read/Write Timing (Z86L43 Only) 10 Z86L33/L43 CP96LVO1501 AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table (L43 Only) (SCLK/TCLK = XTAL/2) No Symbol Parameter 1 TdA(AS) Address Valid to /AS Rise Delay 2 TdAS(A) /AS Rise to Address Float Delay 3 TdAS(DR) /AS Rise to Read Data Req’d Valid TA=–0°C to 70°C Note [3] 8 MHz V CC Min Max 2.0 3.9 2.0 3.9 35 35 45 45 ns [2] ns ns [2] [1,2] 2.0 3.9 2.0 3.9 55 55 ns ns ns ns 2.0 3.9 2.0 3.9 0 0 200 200 ns ns ns ns 2.0 3.9 2.0 3.9 110 110 ns ns ns ns 2.0 3.9 2.0 3.9 0 0 45 55 ns ns ns ns 2.0 3.9 2.0 3.9 30 45 45 45 ns ns ns ns [2] 2.0 3.9 14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 2.0 3.9 45 45 55 55 ns ns ns ns [2] 15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 2.0 3.9 2.0 3.9 45 45 ns ns ns ns 2.0 3.9 2.0 3.9 65 65 35 35 45 45 45 45 4 TwAS /AS Low Width 5 TdAS(DS) Address Float to /DS Fall 6 TwDSR /DS (Read) Low Width 7 TwDSW /DS (Write) Low Width 8 TdDSR(DR) /DS Fall to Read Data Req’d Valid 9 ThDR(DS) Read Data to /DS Rise Hold Time 10 TdDS(A) /DS Rise to Address Active Delay 11 TdDS(AS) /DS Rise to /AS Fall Delay 12 TdR/W(AS) R//W Valid to /AS Rise Delay 13 TdDS(R/W) /DS Rise to R//W Not Valid 16 TdA(DR) Address Valid to Read Data Req’d Valid 17 TdAS(DS) /AS Rise to /DS Fall Delay 18 TdDM(AS) /DM Valid to /AS Rise Delay 19 TdDS(DM) /DS Rise to DM Valid Delay 20 ThDS(AS) /DS Valid to Address Valid Hold Time Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] VCC = 2.0V to 3.9V. 250 250 Units Notes 150 150 310 310 ns ns ns ns ns ns ns ns [2] [1,2] [1,2] [1,2] [2] [2] [2] [2] [2] [1,2] [2] [2] Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 11 Z86L33/L43 CP96LVO1501 AC ELECTRICAL CHARACTERISTICS Additional Timing Diagram 3 1 Clock 2 7 2 3 7 TIN 4 5 6 IRQN 8 9 Clock Setup 11 Stop Mode Recovery Source 10 Additional Timing 12 Z86L33/L43 CP96LVO1501 AC ELECTRICAL CHARACTERISTICS Additional Timing Table (SCLK/TCLK = XTAL/2) No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 TrTin, TfTin 8A TwIL Timer Input Rise & Fall Timer 8B TwIL Int. Request Low Time 9 Int. Request Input High Time TwIH 10 Twsm Int. Request Low Time TA = 0°C to +70°C VCC 8 MHz Note [6] Min Max 2.0V 3.9V 2.0V 3.9V 83 83 2.0V 3.9V 2.0V 3.9V 41 41 100 70 2.0V 3.9V 2.0V 3.9V 5TpC 5TpC 8TpC 8TpC 2.0V 3.9V 2.0V 3.9V 100 70 2.0V 3.9V 2.0V 3.9V 5TpC 5TpC 5TpC 5TpC 12 12 12 Twdt Watch-Dog Timer Delay Time (Before Refresh is Necessary) 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 7 3.5 14 7 28 14 112 56 13 TPOR Power-On Reset Delay 2.0V 3.9V ns ns ns ns [1] [1] [1] [1] ns ns ns ns [1] [1] [1] [1] [1] [1] [1] [1] 100 100 STOP Mode Recovery Width Spec 2.0V 3.9V Oscillator Startup Time 2.0V 3.9V 11 Tost DC DC 15 15 Units Notes ns ns ns ns [1] [1] [1,2] [1,2] [1,3] [1,3] [1,2] [1,2] ns ns 5TpC 5TpC [4] [4] ms ms ms ms ms ms ms ms 45 25 D1, D0 0, 0 [5] 0, 0 [5] 0, 1 [5] 0, 1 [5] 1, 0 [5] 1, 0 [5] 1, 1 [5] 1, 1 [5] ms ms Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 0. [5] Reg. WDTMR. [6] V CC = 2.0V to 3.9V. 13 Z86L33/L43 CP96LVO1501 AC ELECTRICAL CHARACTERISTICS Additional Timing Table (Divide-By-One Mode, SCLK/TCLK = XTAL) V CC Note [6] No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 Timer Input Rise & Fall Timer 8A TrTin, TfTin TwIL 8B TwIL Int. Request Low Time 9 TwIH Int. Request Input High Time 10 Twsm 11 Tost STOP Mode Recovery Width Spec 2.0V 3.9V Oscillator Startup Time 2.0V 3.9V Int. Request Low Time TA = 0°C to +70°C 4 MHz Min Max 2.0V 3.9V 2.0V 3.9V 250 250 2.0V 3.9V 2.0V 3.9V 125 125 100 70 2.0V 3.9V 2.0V 3.9V 3TpC 3TpC 4TpC 4TpC 2.0V 3.9V 2.0V 3.9V 100 70 2.0V 3.9V 2.0V 3.9V 3TpC 3TpC 3TpC 3TpC Notes ns ns ns ns [1,7,8] [1,7,8] [1,7,8] [1,7,8] ns ns ns ns [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] 100 100 ns ns ns ns [1,7,8] [1,7,8] [1,2,7,8] [1,2,7,8] [1,3,7,8] [1,3,7,8] [1,2,7,8] [1,2,7,8] 12 12 Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 1, POR STOP Mode Delay is on. [5] Reg. WDTMR. [6] VCC = 2.0V to 3.9V. [7] SMR D1 = 0. [8] Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. [9] For RC and LC oscillator, and for oscillator driven by clock driver. 14 DC DC 25 25 Units ns ns 5TpC 5TpC [4,8] [4,8] [4,8,9] [4,8,9] Z86L33/L43 CP96LVO1501 AC ELECTRICAL CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid Next Data In Valid 1 2 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Output Handshake Timing 15 Z86L33/L43 CP96LVO1501 AC ELECTRICAL CHARACTERISTICS Handshake Timing Table No Symbol Parameter 1 TsDI(DAV) Data In Setup Time 2 ThDI(RDY) Data In Hold Time 3 TwDAV Data Available Width 4 TdDAVI(RDY) DAV Fall to RDY Fall Delay 5 TdDAVId(RDY) DAV Out to DAV Fall Delay 6 RDY0d(DAV) RDY Rise to DAV Fall Delay 7 TdD0(DAV) Data Out to DAV Fall Delay 8 TdDAV0(RDY) DAV Fall to RDY Fall Delay 9 TdRDY0(DAV) RDY Fall to DAV Rise Delay 10 TwRDY 11 TdRDY0d(DAV) RDY Rise to DAV Fall Delay RDY Width TA= 0°C to +70°C VCC 8 MHz Note [1] Min Max Direction Data 2.0V 3.9V 2.0V 3.9V 0 0 0 0 IN IN IN IN 2.0V 3.9V 2.0V 3.9V 155 110 IN IN IN IN 0 0 2.0V 3.9V 2.0V 3.9V 0 0 IN IN IN IN 2.0V 3.9V 2.0V 3.9V 63 63 0 0 OUT OUT OUT OUT 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 120 80 160 115 110 80 110 80 OUT OUT OUT OUT OUT OUT Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] VCC = 2.0V to 3.9V. © 1996 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. 16 Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com