Z86C30/C31/C32/C40 CP96DZ82900 ZILOG PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z86C30/C31/C32/C40 CMOS Z8® CONSUMER CONTROLLER PROCESSOR FEATURES ■ 32 Input/Output Lines (C40) 24 Input/Output Lines (C3X) ■ Vectored, Prioritized Interrupts with Programmable Polarity * General-Purpose ■ Two Analog Comparators ■ 28-Pin DIP, 28-Pin SOIC, 28-Pin PLCC Packages (Z86C3X) 40-Pin DIP, 44-Pin PLCC/QFP Packages (Z86C40) ■ Two Programmable 8-Bit Counter/Timers, Each with Two 6-Bit Programmable Prescaler ■ Watch-Dog Timer/Power-On Reset ■ 3.0V to 5.5V Operating Range ■ ■ Low-Power Consumption On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock ■ –40°C to +105°C Operating Range ■ RAM and ROM Protect ■ Expanded Register File (ERF) Part Z86C30 Z86C31 Z86C32 Z86C40 ROM (KB) 4 2 2 4 RAM* (Byte) 237 125 237 236 Speed (MHz) 16 12 12 16 GENERAL DESCRIPTION The Z86C3X/C40 Consumer Controller Processors (CCP) are members of the Z8 ® single-chip microcontroller family offering a unique register-to-register architecture that avoids accumulator bottlenecks and offers fast execution of code. Three address spaces (Program Memory, Register File, and Expanded Register File [ERF]), support a wide range of memory configurations. Through the ERF, the designer has access to three additional control registers that provide extra peripheral devices, I/O ports, and register addresses. The rest of the ERF is not physically implemented and is open for future expansion. For applications demanding powerful I/O capabilities, the Z86C3X/C40's dedicated input and output lines are grouped into three and four ports, respectively, and are configurable under software control to provide timing, status signals, or parallel I/O. CP96DZ82900 Two on-chip counter/timers, with a large number of selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data communications. With ROM/ROMless selectivity, the Z86C40 provides both external memory and pre-programmed ROM, which enables these Z8 microcontrollers to be used in highvolume applications, or where code flexibility is required. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS 1 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG GENERAL DESCRIPTION (Continued) Output Input Vcc GND XTAL /AS /DS R//W /RESET Machine Timing & Instruction Control Port 3 Counter/ Timers (2) RESET WDT, POR ALU FLAGS Prg. Memory 4K Interrupt Control Two Analog Comparators Register Pointer Register File Program Counter Port 0 Port 1 Port 2 4 I/O (Bit Programmable) (Only on Z86C40) 4 Address or I/O (Nibble Programmable) 8 Address/Data or I/O (Byte Programmable) (Only on Z86C40) Functional Block Diagram 2 CP96DZ82900 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG PIN DESCRIPTION 28-Pin DIP/SOIC/PLCC Pin Identification 28 P24 Pin # Symbol Function Direction P26 2 27 P23 P27 3 26 P22 4 25 P21 P27-25 P07-04 VCC XTAL2 Port 2, Pins 5,6,7 Port 0, Pins 4,5,6,7 Power Supply Crystal Oscillator In/Output In/Output P04 1-3 4-7 8 9 P05 5 24 P20 P06 6 23 P03 P07 7 VCC 8 Z86C30 Z86C31 22 Z86C32 21 10 XTAL1 11-13 P33-31 14-15 P35-4 16 P37 17 P36 Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pins 4,5 Port 3, Pin 7 Port 3, Pin 6 Input Fixed Input Fixed Output Fixed Output Fixed Output XTAL2 9 20 P01 XTAL1 10 19 P00 11 18 P30 P32 12 17 P36 Port 3, Pin 0 Port 0, Pins 0,1,2 Ground, VSS Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Fixed Input In/Output P31 18 P30 19-21 P02-00 22 GND 23 P03 24-28 P24-20 P33 13 16 P37 P34 14 15 P35 P02 28-Pin DIP Configuration Z86C30 Z86C31 Z86C32 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 P30 P36 P37 P35 4 1 5 In/Output In/Output 26 25 Z86C30 Z86C31 Z86C32 11 12 P32 P33 P34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 P05 XXX XXX P06 XXX P07 XXX VDD XXX XT2 XXX XT1 XXX P31 Output 19 18 P21 XXX XXX P20 XXX P03 XXX VSS XXX P02 XXX P01 XXX P00 P35 P37 P36 P30 GND P25 P24 P23 P22 1 P04 P27 P26 P25 28-Pin PLCC Configuration 28-Pin SOIC Configuration CP96DZ82900 3 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG PIN DESCRIPTION (Continued) R//W 1 40 /DS P25 2 39 P24 P26 3 38 P23 P27 4 37 P22 P04 5 36 P21 P05 6 35 P20 P06 7 34 P03 P14 8 33 P13 P15 9 32 P12 31 GND Z86C40 P07 10 VCC 11 30 P02 P16 12 29 P11 P17 13 28 P10 XTAL2 14 27 P01 XTAL1 15 26 P00 P31 16 25 P30 P32 17 24 P36 P33 18 23 P37 P34 19 22 P35 20 21 /RESET /AS 40-Pin DIP Assignments 40-Pin Dual-In-Line Package Pin Identification 4 Pin # Symbol Function Direction Pin # Symbol Function Direction 1 2-4 5-7 8-9 R//W P25-27 P04-06 P14-15 Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Output In/Output In/Output In/Output 22 23 24 25 P35 P37 P36 P30 Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Output Output Output Input 10 11 12-13 14 P07 VCC P16-17 XTAL2 Port 0, Pin 7 In/Output Power Supply Port 1, Pins 6,7 In/Output Crystal, Oscillator Clock Output 26-27 28-29 30 31 P00-01 P10-11 P02 GND Port 0, Pin 0,1 Port 1, Pin 0,1 Port 0, Pin 2 Ground, GND In/Output In/Output In/Output 15 16-18 19 20 21 XTAL1 P31-33 P34 /AS /RESET Crystal, Oscillator Clock Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe Reset 32-33 34 35-39 40 P12-13 P03 P20-24 /DS Port 1, Pin 2,3 Port 0, Pin 3 Port 2, Pin 0,1,2,3,4 Data Strobe In/Output In/Output In/Output Output Input Input Output Output Input CP96DZ82900 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG GND GND P02 3 2 1 44 43 42 41 40 P00 P12 4 P01 P13 5 P10 P03 6 P11 P20 PIN DESCRIPTION (Continued) P21 7 39 P30 P22 8 38 P36 P23 9 37 P37 P24 10 36 P35 /DS 11 35 /RESET N/C 12 34 R//RL R//W 13 33 /AS P25 14 32 P34 P26 15 31 P33 P27 16 30 P32 P04 17 29 P31 Z86C40 XTAL1 XTAL2 P17 P16 VCC P07 VCC P15 P14 P06 P05 18 19 20 21 22 23 24 25 26 27 28 44-Pin PLCC Pin Assignments 44-Pin PLCC Pin Identification Pin # Symbol Function Direction Pin # Symbol Function Direction 1-2 3-4 5 6-10 11 GND P12-13 P03 P20-24 /DS Ground, GND Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe In/Output In/Output In/Output Output 28 29-31 32 33 34 XTAL1 P31-33 P34 /AS R//RL Crystal, Oscillator Clock Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless Control Input Input Output Output Input 12 13 14-16 17-19 20-21 N/C R//W P25-27 P04-06 P14-15 Not Connected Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Output In/Output In/Output In/Output 35 36 37 38 39 /RESET P35 P37 P36 P30 Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Input Output Output Output Input 22 23-24 25-26 27 P07 V CC P16-17 XTAL2 Port 0, Pin 7 In/Output Power Supply Port 1, Pins 6,7 In/Output Crystal, Oscillator Clock Output Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 In/Output In/Output In/Output CP96DZ82900 40-41 P00-01 42-43 P10-11 44 P02 5 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG P00 P01 P10 P11 P02 GND GND P12 P13 P03 P20 PIN DESCRIPTION (Continued) 33 32 31 30 29 28 27 26 25 24 23 P21 34 22 P30 P22 35 21 P36 P23 36 20 P37 P24 37 19 P35 /DS 38 18 /RESET N/C 39 17 R//RL R//W 40 16 /AS P25 41 15 P34 P26 42 14 P33 P27 43 13 P32 P04 44 12 P31 P15 P07 VCC 7 8 9 10 11 XTAL1 6 XTAL2 5 P17 4 P16 3 VCC 2 P14 P05 1 P06 Z86C40 44-Pin QFP Pin Assignments 44-Pin QFP Pin Identification 6 Pin # Symbol Function Direction Pin # Symbol Function Direction 1-2 3-4 5 6-7 8-9 P05-06 P14-15 P07 VCC P16-17 Port 0, Pins 5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Port 1 Pins 6,7 In/Output In/Output In/Output In/Output 21 22 23-24 25-26 27 P36 P30 P00-01 P10-11 P02 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Output Input In/Output In/Output In/Output 10 11 12-14 15 16 XTAL2 XTAL1 P31-33 P34 /AS Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe Output Input Input Output Output 28-29 30-31 32 33-37 38 GND P12-13 P03 P20-24 /DS Ground, GND Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe In/Output In/Output In/Output Output 17 18 19 20 R//RL /RESET P35 P37 ROM/ROMless Control Reset Port 3, Pin 5 Port 3, Pin 7 Input Input Output Output 39 40 41-43 44 N/C R//W P25-27 P04 Not Connected Read/Write Port 2, Pins 5,6,7 Port 0, Pin 4 Output In/Output In/Output CP96DZ82900 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG ABSOLUTE MAXIMUM RATINGS Parameter Min Max Units Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS [Note 1] Voltage on V DD Pin with Respect to VSS Voltage on XTAL1 and /RESET Pins with Respect to VSS [Note 2] Total Power Dissipation Maximum Allowable Current out of VSS Maximum Allowable Current into VDD Maximum Allowable Current into an Input Pin [Note 3] Maximum Allowable Current into an Open-Drain Pin [Note 4] Maximum Allowable Output Current Sinked by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin –40 –65 –0.6 –0.3 –0.6 +105 +150 +7 +7 VDD+1 1.21 220 180 +600 +600 25 25 C C V V V W mA mA µA µA mA mA –600 –600 Notes: [1] This applies to all pins except XTAL pins and where otherwise noted. [2] There is no input protection diode from pin to VDD. [3] This excludes XTAL pins. [4] Device pin is not at an output Low state. Notice: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power dissipation should not exceed 1.21 W for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [ IDD – (sum of IOH) ] + sum of [ (VDD – VOH) x I OH ] + sum of (V0L x I0L) STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Test Load). From Output Under Test 150 pF Test Load Diagram CAPACITANCE TA = 25°C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance CP96DZ82900 Min Max 0 0 0 12 pF 12 pF 12 pF 7 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG DC ELECTRICAL CHARACTERISTICS Sym Parameter VCC Note [3] VCH Clock Input High Voltage 3.0V 5.5V VCL Clock Input Low Voltage VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltge Low EMI Mode Output High Voltage VOH1 VOL Notes 1.3 2.5 V V Driven by External Clock Generator Driven by External Clock Generator 3.0V 5.5V 3.0V 5.5V GND-0.3 GND-0.3 0.7 VCC 0.7 VCC 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.7 1.5 1.3 2.5 V V V V Driven by External Clock Generator Driven by External Clock Generator 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V GND-0.3 GND-0.3 VCC–0.4 VCC–0.4 VCC–0.4 VCC–0.4 0.2 VCC 0.2 VCC 0.7 1.5 3.1 4.8 3.1 4.8 V V V V V V IOH = – 0.5 mA IOH = – 0.5 mA IOH = – 2.0 mA IOH = – 2.0 mA [8] [8] 0.6 0.4 0.6 0.4 1.2 1.2 0.3 0.2 0.2 0.1 0.5 0.5 V V V V V V IOL = 1.0 mA IOL = 1.0 mA IOL = + 4.0 mA IOL = + 4.0 mA IOL = + 6 mA IOL = + 12 mA [8] [8] [8] [8] VCC VCC 0.2 VCC 0.2 VCC 0.6 0.6 1.5 2.1 1.1 1.7 0.3 0.2 V V IOL = +1.0 mA IOL = +1.0 mA [7] [7] [7] [7] [7] [7] 10 10 0.064 0.064 mV mV V V µA µA 2 2 –130 –180 0.114 0.114 –62 –112 µA µA µA µA VIN = OV, VCC VIN = OV, VCC 20 25 15 20 7 20 5 15 mA mA mA mA @ 16 MHz @ 16 MHz @ 12 MHz @ 12 MHz VOL2 Output Low Voltage VRH Reset Input High Voltage 3.0V 5.5V Reset Input Low Voltage 3.0V 5.5V Reset Outut Low Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.0V 3.0V 5.5V VOFFSET Comparator Input Offset Voltage VICR Input Common Mode Voltage Range IIL Input Leakage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V IOL Output Leakage IIR Reset Input Current 3.0V 5.5V 3.0V 5.5V ICC Supply Current 8 Conditions VCC+0.3 VCC+0.3 VOL1 VOLR Typical [1] @ 25°C Units 0.7 VCC 0.7 VCC Output Low Voltage Low EMI Mode Output Low Voltage VRL T A = 0°C to +70°C Min Max 3.0V 5.5V 3.0V 5.5V .8 VCC .8 VCC GND–0.3 GND–0.3 25 25 GND-0.3 VCC –1.0V GND-0.3 VCC –1.0V –1 2 –1 2 –1 –1 –20 –20 V V [10] [10] VIN = OV, VCC VIN = OV, VCC [4,5] [4,5] [4,5] [4,5] CP96DZ82900 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG DC ELECTRICAL CHARACTERISTICS (Continued) Sym Parameter ICC1 Standby Current (Halt Mode) ICC2 Standby Current (Stop Mode) IALL Auto Latch Low Current IALH Auto Latch High Current TPOR VLV Power On Reset V CC Note [3] TA = 0°C to +70°C Min Max Typical [1] @ 25°C Units Conditions Notes 3.0V 5.5V 3.0V 5.5V 4.5 8 4 6 2.0 3.7 1.5 3.2 mA mA mA mA VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC @ 12 MHz VIN = 0V, VCC @ 12 MHz [4,5] [4,5] [4,5] [4,5] 3.0V 5.5V 3.0V 5.5V 3.4 7.0 3 5 1.5 2.9 1.2 2.5 mA mA mA mA Clock Divide by 16 @ 16 MHz Clock Divide by 16 @ 16 MHz Clock Divide by 16 @ 12 MHz Clock Divide by 16 @ 12 MHz [4,5] [4,5] [4,5] [4,5] 3.0V 8 2 µA [6,11] 5.5V 10 4 µA 3.0V 500 310 µA 5.5V 800 600 µA VIN = OV, VCC WDT is not Running VIN = OV, VCC WDT is not Running VIN = OV, VCC WDT is Running VIN = OV, VCC WDT is Running [6,11] [6,11] [6,11] 3.0V 0.7 8 2.4 µA OV < VIN < VCC [9] 5.5V 3.0V 1.4 –0.6 15 –5 4.7 –1.8 µA µA OV < VIN < VCC OV < VIN < VCC [9] [9] 5.5V –1 –8 –3.8 µA OV < VIN < VCC [9] 3 2.0 2.05 24 13 2.95 10 4 2.6 mS mS V 6 MHz max INT CLK Freq. [7] 3.0V 5.5V Low Voltage Protection Note: [1] Typicals are at VCC = 5.0V and 3.3V. [2] GND = 0V. [3] The V CC voltage spec. of 3.0V guarantees 3.3V ± 0.3V and the VDD voltage spec. of 5.5V guarantees 5.0V ± 0.5V. [4] All outputs unloaded, I/O pins floating, inputs at rail. [5] CL1= CL2 = 10 pF. [6] Same as note [4] except inputs at VCC. [7] Z86C40 only. [8] STD Mode (not Low-EMI Mode). [9] Auto Latch (mask option) selected. [10] For analog comparator inputs when analog comparators are enabled. [11] Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. CP96DZ82900 9 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG DC ELECTRICAL CHARACTERISTICS Sym Parameter V CC Note [3] VCH Clock Input High Voltage 3.0V 5.5V VCL Clock Input Low Voltage VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage Low EMI Mode Output High Voltage VOH1 VOL Conditions 1.3 2.5 V V Driven by External Clock Generator Driven by External Clock Generator 3.0V 5.5V 3.0V 5.5V GND-0.3 GND-0.3 0.7 VCC 0.7 VCC 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.7 1.5 1.3 2.5 V V V V Driven by External Clock Generator Driven by External Clock Generator 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V GND-0.3 GND-0.3 VCC–0.4 VCC–0.4 VCC–0.4 VCC–0.4 0.2 VCC 0.2 VCC 0.7 1.5 3.1 4.8 3.1 4.8 V V V V V V IOH = – 0.5 mA IOH = – 0.5 mA IOH = – 2.0 mA IOH = – 2.0 mA [8] [8] 0.6 0.4 0.6 0.4 1.2 1.2 0.3 0.2 0.2 0.1 0.5 0.5 V V V V V V IOL = 1.0 mA IOL = 1.0 mA IOL = + 4.0 mA IOL = + 4.0 mA IOL = + 6 mA IOL = + 12 mA [8] [8] [8] [8] VCC VCC 0.2 VCC 0.2 VCC 0.6 0.6 1.5 2.1 1.1 1.7 0.4 0.3 V V IOL = + 1.0 mA IOL = + 1.0 mA [7] [7] [7] [7] [7] [7] 10 10 <1 <1 mV mV V V µA µA VOL2 Output Low Voltage VRH Reset Input High Voltage 3.0V 5.5V Reset Input Low Voltage 3.0V 5.5V Reset Output Low Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.0V 3.0V 5.5V .8 VCC .8 VCC GND–0.3 GND–0.3 V V VOFFSET Comparator Input Offset Voltage VICR Input Common Mode Voltage Range IIL Input Leakage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V GND–0.3 GND–0.3 –1 –1 25 25 VCC –1.5V VCC –1.5V 2 2 IOL Output Leakage IIR Reset Input Current 3.0V 5.5V 3.0V 5.5V –1 –1 –18 –18 2 2 –130 –180 <1 <1 –62 –112 µA µA µA µA VIN = OV, VCC VIN = OV, VCC ICC Supply Current 20 25 15 20 7 20 5 15 mA mA mA mA @ 16 MHz @ 16 MHz @ 12 MHz @ 12 MHz 10 Notes VCC+0.3 VCC+0.3 VOL1 VOLR Typical [1] @ 25°C Units 0.7 VCC 0.7 VCC Output Low Voltage Low EMI Mode Output Low Voltage VRL TA=–40°C to 105°C Min Max 3.0V 5.5V 3.0V 5.5V [10] [10] VIN = OV, VCC VIN = OV, VCC [4,5] [4,5] [4,5] [4,5] CP96DZ82900 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG DC ELECTRICAL CHARACTERISTICS (Continued) Sym Parameter ICC1 ICC2 Standby Current (Halt Mode) Standby Current (Stop Mode) IALL Auto Latch Low Current IALH Auto Latch High Current TPOR Power On Reset VLV Low Voltage Protection VCC Note [3] T A = –40°C Typical [1] to 105°C @ Min Max 25°C Units Conditions Notes 3.0V 5.5V 3.0V 5.5V 4.5 8 4 6 2.0 3.7 1.5 3.2 mA mA mA mA VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC @ 12 MHz VIN = 0V, VCC @ 12 MHz [4,5] [4,5] [4,5] [4,5] 3.0V 5.5V 3.0V 5.5V 3.4 7.0 3 5 1.5 2.9 1.2 2.5 mA mA mA mA Clock Divide by 16 @ 16 MHz Clock Divide by 16 @ 16 MHz Clock Divide by 16 @ 12 MHz Clock Divide by 16 @ 12 MHz [4,5] [4,5] [4,5] [4,5] 3.0V 8 2 µA [6,11] 5.5V 10 4 µA 3.0V 600 310 µA 5.5V 1000 600 µA VIN = OV, VCC WDT is not Running VIN = OV, VCC WDT is not Running VIN = OV, VCC WDT is Running VIN = OV, VCC WDT is Running 3.0V 5.5V 3.0V 5.5V 0.7 1.4 –0.6 –1.0 10 20 –7 –10 2.4 4.7 –1.8 –3.8 µA µA µA µA OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC 3.0V 5.5V 3.0 2.0 1.8 25 14 3.3 7 4 2.6 mS mS V 4 MHz max INT CLK Freq. [6,11] [6,11] [6,11] [9] [9] [9] [9] Note: [1] Typicals are at VCC = 5.0V and 3.3V. [2] GND=0V. [3] The V CC voltage spec. of 3.0V guarantees 3.3V ± 0.3V and the VDD voltage spec. of 5.5V guarantees 5.0V ± 0.5V. [4] All outputs unloaded, I/O pins floating, inputs at rail. [5] CL1= CL2 = 100pF. [6] Same as note [4] except inputs at VCC. [[7] Z86C40 only. [8] STD Mode (not Low EMI Mode). [9] Auto Latch (mask option) selected. [10] For analog comparator inputs when analog comparators are enabled. [11] Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. [7] Z86C40 only. CP96DZ82900 11 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram (Z86C40 Only) R//W, /DM 13 12 19 Port 0 16 Port 1 20 3 18 A7 - A0 1 D7 - D0 IN 2 9 /AS 8 11 4 5 /DS (Read) 6 17 10 Port1 A7 - A0 D7 - D0 OUT 14 15 7 /DS (Write) External I/O or Memory Read/Write Timing (Z86C40 Only) 12 CP96DZ82900 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table (Z86C40 Only) (SCLK/TCLK = XTAL/2) No Symbol Parameter 1 TdA(AS) Address Valid to /AS Rise Delay 2 TdAS(A) /AS Rise to Address Float Delay TA=–40°C to 105°C TA = –40°C to +105°C Note [3] 12 MHz 16 MHz 12 MHz 16 MHz VCC Min Max Min Max Min Max Min Max Units 3 TdAS(DR) /AS Rise to Read Data Req’d Valid 3.0 5.5 3.0 5.5 35 35 45 45 25 25 35 35 [2] 40 40 55 55 40 40 3.0 5.5 3.0 5.5 0 0 200 200 0 0 135 135 0 0 200 200 0 0 135 135 ns ns ns ns 3.0 5.5 3.0 5.5 110 110 80 80 110 110 80 80 ns ns ns ns 3.00 5.5 3.0 5.5 0 0 45 55 0 0 50 50 0 0 45 55 0 0 50 50 ns ns ns ns 3.0 5.5 3.0 5.5 30 45 45 45 35 35 25 25 30 45 45 45 35 55 25 25 ns ns ns ns [2] 3.0 5.5 14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 3.0 5.5 45 45 55 55 35 35 25 25 45 45 55 55 35 35 25 25 ns ns ns ns [2] 15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 3.0 5.5 3.0 5.5 45 45 35 35 45 45 35 35 ns ns ns ns 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 65 65 35 35 45 45 45 45 6 TwDSR /DS (Read) Low Width 7 TwDSW /DS (Write) Low Width 8 TdDSR(DR) /DS Fall to Read Data Req’d Valid 9 ThDR(DS) Read Data to /DS Rise Hold Time 10 TdDS(A) /DS Rise to Address Active Delay 11 TdDS(AS) /DS Rise to /AS Fall Delay 12 TdR/W(AS) R//W Valid to /AS Rise Delay 13 TdDS(R/W) /DS Rise to R//W Not Valid 16 TdA(DR) Address Valid to Read Data Req’d Valid 17 TdAS(DS) /AS Rise to /DS Fall Delay 18 TdDM(AS) /DM Valid to /AS Fall Delay 19 TdDS(DM) /DS Rise to DM Valid Delay 20 ThDS(AS) /DS Valid to Address Valid Hold Time 150 150 310 310 Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] The VCC voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the VDD voltage specification of 5.5V guarantees 5.0V ± 0.5V. CP96DZ82900 75 75 150 150 230 230 45 45 30 30 35 35 35 35 180 180 [2] 55 55 5 TdAS(DS) Address Float to /DS Fall 250 250 ns ns ns ns ns ns ns ns /AS Low Width 180 180 25 25 35 35 3.0 5.5 3.0 5.5 4 TwAS 250 250 35 35 45 45 Notes 75 75 310 310 65 65 35 35 45 45 45 45 230 230 45 45 30 30 35 35 35 35 ns ns ns ns ns ns ns ns [1,2] [2] [1,2] [1,2] [1,2] [2] [2] [2] [2] [2] [1,2] [2] [2] Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0. 13 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG AC ELECTRICAL CHARACTERISTICS Additional Timing Diagram 3 1 Clock 2 7 2 3 7 TIN 4 5 6 IRQN 8 9 Clock Setup 11 Stop Mode Recovery Source 10 Additional Timing 14 CP96DZ82900 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG AC ELECTRICAL CHARACTERISTICS Additional Timing Table (Divide-By-One Mode) TA = 0°C to +70°C VCC Note [6] 4 MHz Min Max 4 MHz Min Max 3.0V 5.5V 3.0V 5.5V 250 250 250 250 3.0V 5.5V 3.0V 5.5V 100 100 100 70 100 100 100 70 3.0V 5.5V 3.0V 5.5V 5TpC 5TpC 8TpC 8TpC 5TpC 5TpC 8TpC 8TpC No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 Timer Input Rise & Fall Timer 8A TrTin, TfTin TwIL 8B TwIL Int. Request Low Time 9 TwIH Int. Request Input High Time 10 Twsm 11 Tost STOP Mode Recovery Width Spec 3.0V 5.5V Oscillator Start-up Time 3.0V 5.5V Int. Request Low Time T A = 40°C to +105°C DC DC 25 25 3.0V 5.5V 3.0V 5.5V 100 100 100 70 100 70 3.0V 5.5V 3.0V 5.5V 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 12 12 12 12 5TpC 5TpC DC DC 25 25 Units Notes ns ns ns ns [1,7,8] [1,7,8] [1,7,8] [1,7,8] ns ns ns ns [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] 100 100 ns ns ns ns [1,7,8] [1,7,8] [1,2,7,8] [1,2,7,8] [1,3,7,8] [1,3,7,8] [1,2,7,8] [1,2,7,8] ns ns 5TpC 5TpC [4,8] [4,8] [4,8,9] [4,8,9] Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 1, POR STOP Mode Delay is on. [5] Reg. WDTMR. [6] The V CC voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the VDD voltage specification of 5.5V guarantees 5.0V ± 0.5V. [7] SMR D1 = 0. [8] Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. [9] For RC and LC oscillator, and for oscillator driven by clock driver. CP96DZ82900 15 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG AC ELECTRICAL CHARACTERISTICS Additional Timing Table No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 TrTin, TfTin 8A TwIL Timer Input Rise & Fall Timer 8B TwIL Int. Request Low Time 9 Int. Request Input High Time TwIH 10 Twsm 11 Tost 12 Twdt VCC Note [6] T A = –40°C to +105°C T A = 0°C to +70°C 16 MHz 12 MHz Min Max Min Max 3.0V 5.5V 3.0V 5.5V 62.5 62.5 DC DC 15 15 83 83 3.0V 5.5V 3.0V 5.5V 31 31 100 70 26 26 100 70 3.0V 5.5V 3.0V 5.5V 5TpC 5TpC 8TpC 8TpC 5TpC 5TpC 8TpC 8TpC 3.0V 5.5V 3.0V 5.5V 100 70 100 70 3.0V 5.5V 3.0V 5.5V 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC STOP Mode Recovery Width Spec 3.0V 5.5V Oscillator Start-up Time 3.0V 5.5V 12 12 12 12 Watch-Dog Timer Delay Time Before Refresh 10 5 20 10 40 20 160 80 Int. Request Low Time 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 100 100 DC DC 15 15 Notes ns ns ns ns [1,7,8] [1,7,8] [1,7,8] [1,7,8] ns ns ns ns [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] 100 100 5TpC 5TpC Units ns ns ns ns [1,7,8] [1,7,8] [1,2,7,8] [1,2,7,8] [1,3,7,8] [1,3,7,8] [1,2,7,8] [1,2,7,8] ns ns [4,8] [4,8] [4,8] [4,8] ms ms ms ms ms ms ms ms D0 = 0 [5,11] D1 = 0 [5,11] D0 = 1 [5,11] D1 = 0 [5,11] D0 = 0 [5,11] D1 = 1 [5,11] D0 = 1 [5,11] D1 = 1 [5,11] 5TpC 5TpC 10 5.0 20 10 40 20 160 80 Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 1, POR STOP Mode Delay is on. [5] Reg. WDTMR. [6] The V CC voltage spec. of 3.0V guarantees 3.3V ± 0.3V and the VDD voltage spec. of 5.5V guarantees 5.0V ± 0.5V. [7] SMR D1 = 0. [8] Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. [9] For RC and LC oscillator, and for oscillator driven by clock driver. [10] Standard Mode (not Low EMI output ports). [11] Using internal RC. 16 CP96DZ82900 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG AC ELECTRICAL CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid 1 Next Data In Valid 2 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Output Handshake Timing © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. CP96DZ82900 Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com 17