Z89319 CPS5TEL0800 P R E L I M I N A R Y PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z89319 DIGITAL TELEVISION CONTROLLER IN-CIRCUIT EMULATOR (ICE) DEVICE FEATURES ■ Part Number ROM (Word) RAM (Word) Speed (MHz) Z89319 0 0 12 ■ Direct Closed Caption Decoding ■ 124-Pin Grid Array (PGA) Package ■ TV Tuner Serial Interface ■ 4.5- to 5.5-Volt Operating Range ■ Customized Character Set ■ Z89C00 RISC Processor Core ■ Character Control Mode ■ 0°C to +70°C Temperature Range ■ Directly Controlled Receiver Functions GENERAL DESCRIPTION The Z89319 is a ROMless ICE chip version of the Z89300 family of Zilog's Digital Television Controllers designed for use in emulators and development boards to provide complete audio and video control of television receivers, video recorders, and advanced on-screen display facilities. The powerful Z89C00 RISC processor core allows users to control on-board peripheral functions and registers using the standard processor instruction set. In closed caption mode, text can be decoded directly from the composite video signal and displayed on the screen with assistance from the processor's digital signal processing capabilities. The character representation in this mode allows for a simple attribute control through the insertion of control characters. The character control mode provides access to the full set of attribute controls. The modification of attributes is allowed on a character-by-character basis. The insertion of control characters permits direction of other character attributes. Display attributes, including underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency, are made possible through a fully customized 512 character set, formatted in two 256 character banks. CP95TEL0800 (6/95) Serial interfacing with the television tuner is provided through the tuner serial port. Digital channel tuning adjustments may be accessed through the industrystandard I2C port. Additional hardware provides the capability to display two to three times normal size characters. The smoothing logic contained in the on-screen display circuit improves the appearance of larger fonts. Special circuitry can be activated to improve the visibiity of text by adding a rightsided shadow effect to the characters. Receiver functions such as color and volume can be directly controlled by six 8-bit pulse width modulated ports. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS 1 Z89319 CP95TEL0800 P R E L I M I N A R Y GENERAL DESCRIPTION (Continued) PWM Capture IRIN CVI Port 17 Port 00 Port 05 Port 04 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 ADC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 Port1 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0A Port 0B Port 0C Port 0D Port 0E Port 0F Control XTAL1 XTAL2 LPF HSYNC HSYNC2 VSYNC /Reset PWM6 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 I2C SCL/MSCL2 SCD/MSCD2 MSCL1 MSCD1 Register Addr/Data OSD V1(R) V2(G) CPU V3(B) RAM 1K x 16 Address ROM Addr Data ROM Data Functional Block Diagram 2 ROM 32K x 16 Port 01/11 Port 02/12 Z89319 CPS5TEL0800 PWM4 PWM3 PWM5 P10/R<0> INT_BUS11 PWM6 INT_BUS10 P13/G<1> P18/G<0> VCC P08/R<1> INT_BUS12 P14/B<0> GND P16/SCLK INT_BUS13 P15/B<1> INT_BUS14 P0C INT_BUS15 IRIN P0A P0B P09 P19 P0D VCC ADDRESS14 ADDRESS13 P07/CSYNC P06/CNTR P R E L I M I N A R Y P03 GND P01 VCC PWM2 VCC GND DATA0 DATA1 ADDRESS12 ADDRESS11 DATA2 PWM1 P02 ADDRESS10 DATA3 ADDRESS9 DATA4 DATA5 ADDRESS8 ADDRESS7 DATA6 SINGLE_STEP ADDRESS6 CVI/ADC0 ADDRESS5 ADDRESS4 ANGNDX STOPWDT DATA7 Z89319 124-Pin PGA VCC GND DATA8 DATA9 _ROMLESS VCC/VDD ADDRESS3 LPF ADDRESS2 _PABUS DATA12 DATA13 DATA14 ADDRESS1 ADDRESS0 IE DATA10 GND R/W ANGNDF SYS_CLK EA0 EA1 EA2 ADC5 P04/ADC4 DATA11 DATA15 GND INT_BUS9 I2MSC1 INT_BUS8 /RESET INT_BUS7 I2MSD1 VCC INT_BUS6 P0E INT_BUS5 P11/I2MSC2 VSYNC P12/I2MSD2 INT_BUS4 GND BLANK HSYNC V2(G) V1(R) ANVCC INT_BUS3 P0F/HB V3(B) VCC INT_BUS2 INT_BUS1 ANGND INT_BUS0 P17/ADC1 P001/ADC2 P05/ADC3 GND XTAL2 XTAL1 124-Pin PGA Configuration 3 Z89319 CP95TEL0800 P R E L I M I N A R Y PIN DESCRIPTION N M L K J H Z89319 G F E D C B A 13 12 11 10 9 8 7 6 5 4 124-Pin PGA Configuration 4 3 2 1 Z89319 CPS5TEL0800 P R E L I M I N A R Y V1, V2, V3 ANALOG OUTPUT Specifications VCC = 5.25 V VCC = 5.25 V Condition Limit Output Voltage Bit = 11 Bit = 10 Bit = 01 Bit = 00 4.30 V ± 3.10 V ± 1.90 V ± 0V± Setting Time 70% of DC Level, 10pf Load < 50 ns VCC = 4.75 V Condition Limit Output Voltage Bit = 11 Bit = 10 Bit = 01 Bit = 00 3.90 V ± 2.80 V ± 1.70 V ± 0V± Setting Time 70% of DC Level, 10pf Load < 50 ns 0.3 V 0.25 V 0.20 V 0.75 V V1, V2, V3 ANALOG OUTPUT Specifications VCC = 4.75 V 0.30 V 0.25 V 0.20 V 0.65 V XTAL1 32.768k 68pF 10 Mohm Z893XX XTAL2 27k 560pF 32K Oscillator Recommended Circuit 5 Z89319 CP95TEL0800 P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units Conditions VCC VID Power Supply Voltage Input Voltage 0 –0.3 7 VCC +0.3 V V Digital Inputs VIA VO IOH IOH IOL IOL Input Voltage Output Voltage Output Current High Output Current High Output Current Low Output Current Low –0.3 –0.3 VCC +0.3 VCC +0.3 –10/–1a –100 20/1b 200 V V mA mA mA mA Analog Inputs (A/D0...A/D4) All Push-Pull Digital Output One Pin All Pins One Pin All Pins TA TA Operating Temperature Storage Temperature 0 –65 70 150 °C °C Notes: a) 1 mA max. when output pad impedance is 600 Ω. b) 1 mA max. when output pad impedance is 600 Ω. DC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5 V to + 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max Typical 0.2 VCC VCC 0.4 3.6 V V 0.4 0.16 4.75 V V 0.3 VCC 0.75 150 1.0 3.5 0.5 90 V V V µA External Clock Generator Driven On XTAL1 Input Pin VRL = 0 V 3.0 100 0.01 60 µA mA @ 0 V and VCC 300 40 100 5 µA µA Sleep Mode @ 32 KHz Stop Mode VIL VIH Input Voltage Low Input Voltage High 0 0.6 VCC VOL VOH Output Voltage Low Output Voltage High VCC –0.9 VXL VXH VHY IIR Input Voltage XTAL1 Low Input Voltage XTAL1 High Schmitt Hysteresis Reset Input Current IIL ICC Input Leakage Supply Current ICC1 ICC2 Supply Current Supply Current 6 VCC –2.0 3.0 –3.0 Units Conditions @ IOL = 1 mA @ IOL = 0.75 mA Z89319 CPS5TEL0800 P R E L I M I N A R Y AC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max Typical Units TPC TRC,TFC Input Clock Period Clock Input Rise and Fall 16 100 32 12 µS µS TDPOR Power On Reset Delay 0.8 1.2 s Note Depends on Crystal AC CHARACTERISTICS* TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max Typical Units TWRES TDHS Power-On Reset Min. Width H_Sync Incoming Signal Width 5.5 5TPC 12.5 11 µS µS TDVS TDES V_Sync Incoming Signal Width Time Delay Between Leading Edge of V_Sync and H_Sync in Even Field 0.15 –12 1.5 +12 1.0 0 mS µS TDOS Time Delay Between Leading Edge of H_Sync in Odd Field H_Sync/V_Sync Edge Width 20 44 32 µS 2.0 0.5 µS TWHVS Notes: All timing of the I2C bus interface are defined by related specifications of the I2C bus interface. 7