ZMD ZADCS0822

ZADCS0882/0842/0822
8-Bit, 300ksps, Serial Output ADC Family
Datasheet
Features
Description
·
Single Supply Operation:
+ 2.7V … + 5.25V
·
Family approach providing
2 / 4 / 8-Channel Single-Ended or
1 / 2 / 4-Channel Differential Inputs
·
Up to 300ksps Conversion Rate
·
± 0.25 LSB INL and DNL
·
No Missing Codes
·
> 49 dB SINAD
·
True fully differential Operation
·
Software-Configurable Unipolar or
Bipolar output coding
·
Internal 3.3MHz oscillator for independent
operation from external clock
·
Internal 2.5V Reference
·
Low Power
< 1.2mA (300ksps, 5V supply)
< 0.5μA (power-down mode)
·
SPITM / QSPITM / MICROWIRETM - compatible
4-Wire Serial Interface
·
14 / 16 / 20-Pin SSOP
The ZADCS08x2 family is a set of low power, 8-bit, successive approximation analog-to-digital (A/D) converters
with up to 300ksps conversion rate, two up to eight input
channels, high-bandwidth track/hold and synchronous
serial interface.
The ADCs operate from a single + 2.7V to + 5.25V supply.
Their analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI™/
(QSPI™ and MICROWIRE™) devices without external
logic.
All family devices can use either the external serialinterface clock or an internal clock to perform successiveapproximation analog-to-digital conversions. The internal
clock can be used to run independent conversions on
more than one device in parallel.
The ZADCS08x2V versions are equipped with a highly
accurate internal 2.5V reference with an additional external
±1.5% voltage adjustment range.
All members of the ZADCS08x2 family provide a hardwired shut-down pin (nSHDN) pin and software-selectable
power-down modes that can be programmed to automatically shut down the IC at the end of a conversion. Accessing the serial interface automatically powers up the IC. A
quick turn-on time allows the device to be shut down between all conversions.
Applications
·
Data Acquisition
·
Industrial Process Control
·
Portable Data Logging
·
Battery-Powered Systems
Starterkit
available
Functional Block Diagram
Available in
ZADCS0822
Available in
ZADCS0842
Available in
ZADCS0882
CH0
CH1
CH2
8-Channel
CH3
Analog
CH4
Input
CH5
Multiplexer
SAR
IN-
CH6
Comparator
IN+
DAC with
inherent
T&H
CH7
+
-
Serial
Interface
and
nCS
SCLK
DIN
DOUT
SSTRB
Control
COM
x 2.000
Internal
+ 1.25V
3.3 MHz
Reference
Oscillator
REFADJ
VREF
State
nSHDN
Machine
VDD
DGND
AGND
Available in ZADCS08x2V versions
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
1/20
Datasheet
ZADCS0882/0842/0822 Family
Table of Contents
1
Page
GENERAL DEVICE SPECIFICATION ....................................................................................................... 3
1.1
ABSOLUTE MAXIMUM RATINGS (NON OPERATING) .................................................................................... 3
1.2
PACKAGE PIN ASSIGNMENT ZADCS0882 / ZADCS0882V ....................................................................... 4
1.3
PACKAGE PIN ASSIGNMENT ZADCS0842 / ZADCS0842V ....................................................................... 5
1.4
PACKAGE PIN ASSIGNMENT ZADCS0822 / ZADCS0822V ....................................................................... 6
1.5
ELECTRICAL CHARACTERISTICS .............................................................................................................. 7
1.5.1
General Parameters ................................................................................................................... 7
1.5.2
Specific Parameters of ZADCS08x2V versions (with Internal Reference) ............................... 8
1.5.3
Specific Parameters of basic ZADCS08x2 versions (without Internal Reference) .................. 9
1.5.4
Digital Pin Parameters ............................................................................................................... 9
1.6
TYPICAL OPERATING CHARACTERISTICS ................................................................................................ 10
2
DETAILED DESCRIPTION ...................................................................................................................... 11
2.1
2.2
2.3
2.4
2.5
GENERAL OPERATION .......................................................................................................................... 11
ANALOG INPUT .................................................................................................................................... 11
INTERNAL & EXTERNAL REFERENCE ...................................................................................................... 13
DIGITAL INTERFACE ............................................................................................................................. 13
POWER DISSIPATION ........................................................................................................................... 17
3
LAYOUT .................................................................................................................................................. 17
4
PACKAGE DRAWING ............................................................................................................................. 19
5
ORDERING INFORMATION.................................................................................................................... 20
6
ZMD DISTRIBUTION PARTNER ............................................................................................................. 20
7
ZMD CONTACT....................................................................................................................................... 20
Important Notice:
The information furnished herein by ZMD is believed to
be correct and accurate as of the publication date. However, ZMD shall not be liable to any party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business, or indirect, special, incidental, or consequential
damages of any kind in connection with or arising out of
the furnishing, performance, or use of the technical data.
No obligation or liability to any third party shall arise from
ZMD's rendering technical or other services.
Products sold by ZMD are covered exclusively by the
ZMD’s standard warranty, patent indemnification, and
other provisions appearing in ZMD’s standard "Terms &
Conditions". ZMD makes no warranty (express, statutory,
implied and/or by description), including without limitation
any warranties of merchantability and/or fitness for a
particular purpose, regarding the information set forth in
the materials pertaining to ZMD products, or regarding
the freedom of any products described in such materials
from patent and/or other infringement.
ZMD reserves the right to discontinue production and
change specifications and prices, make corrections,
modifications, enhancements, improvements and other
changes of its products and services at any time without
notice. ZMD products are intended for use in commercial
applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-support
or life-sustaining equipment, are specifically not recommended without additional mutually agreed-upon processing by ZMD for such applications. ZMD assumes no
liability for application assistance or customer product
design. Customers are responsible for their products and
applications using ZMD components.
SPI and QSPI are registered trademarks of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
Please notice, that values specified as typical may differ
from product to product. The values listed under min or
max are guaranteed by design or test.
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
2/20
Datasheet
ZADCS0882/0842/0822 Family
1 General Device Specification
1.1
Absolute Maximum Ratings (Non Operating)
Table 1: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VDD-GND
VDD to AGND, DGND
-0.3
6
V
VAGND-DGND
AGND to DGND
-0.3
0.3
V
CH0 – CH7, COM to AGND, DGND
-0.3
VDD+0.3
V
VREF, VREFADJ to AGND
-0.3
VDD+0.3
V
Digital Inputs to DGND
-0.3
6
V
Digital Outputs to DGND
-0.3
VDD+0.3
V
25
mA
100
mA
Digital Output Sink Current
Iin
Input current into any pin except supply pins (Latch-Up)
-100
VHBM
Electrostatic discharge – Human Body Model (HBM)
2000
qJCT
Maximum Junction Temperature
qOP
Operating Temperature Range
1
+150°
°C
ZADCS08x2VIS20 / ZADCS08x2IS20
-25
+85
°C
ZADCS08x2VQS20 / ZADCS08x2QS20
-40
+125
°C
-65
+150
°C
qSTG
Storage temperature
qlead
Lead Temperature 100%Sn
H
Humidity non-condensing
Ptot
Total power dissipation
Rthj
Thermal resistance of Package
JEDEC-J-STD-20C 260
SSOP20 / 5.3mm
2
V
Note
1
°C
2
250
mW
100
K/W
HBM: C = 100pF charged to VHBM with resistor R = 1.5kW in series, valid for all pins
Level 4 according to JEDEC-020A is guaranteed
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
3/20
Datasheet
ZADCS0882/0842/0822 Family
1.2
Package Pin Assignment ZADCS0882 / ZADCS0882V
Table 2: Pin list
Package
pin number
Name
Direction
Type
Description
1
nCS
IN
CMOS Digital
Active Low Chip Select
2
DIN
IN
CMOS Digital
Serial Data Input
3
DGND
SUPPLY
Digital Ground
4
AGND
SUPPLY
Analog Ground
5
VREF
I/O
Analog
Reference Buffer Output / External Reference Input
6
COM
IN
Analog
Ground reference for analog inputs in single ended mode
7
CH0
IN
Analog
Analog Input Channel 0
8
CH1
IN
Analog
Analog Input Channel 1
9
CH4
IN
Analog
Analog Input Channel 4
10
CH5
IN
Analog
Analog Input Channel 5
11
CH7
IN
Analog
Analog Input Channel 7
12
CH6
IN
Analog
Analog Input Channel 6
13
CH3
IN
Analog
Analog Input Channel 3
14
CH2
IN
Analog
Analog Input Channel 2
15
REFADJ
I/O
Analog
Input to Reference Buffer Amplifier
16
VDD
SUPPLY
Positive Supply
17
nSHDN
IN
CMOS Digital
Active Low Shutdown
18
DOUT
OUT
CMOS Digital
Serial Data Output
19
SSTRB
OUT
CMOS Digital
Serial Strobe Output
20
SCLK
IN
CMOS Digital
Serial Clock Input
SCLK
DIN
SSTRB
DGND
AGND
VREF
COM
CH0
CH1
CH4
CH5
ZADCS 0882 / ZADCS 0882V
nCS
DOUT
nSHDN
VDD
REFADJ on ZADCS0882V,
No connect on ZADCS0882
CH2
CH3
CH6
CH7
Figure 1: Package Pin Assignment for ZADCS0882 & ZADCS0882V
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
4/20
Datasheet
ZADCS0882/0842/0822 Family
1.3
Package Pin Assignment ZADCS0842 / ZADCS0842V
Table 3: Pin list
Package
pin number
Name
Direction
Type
Description
nCS
IN
CMOS Digital
Active Low Chip Select
2
DIN
IN
CMOS Digital
Serial Data Input
3
DGND
SUPPLY
Digital Ground
4
AGND
SUPPLY
Analog Ground
5
VREF
I/O
Analog
Reference Buffer Output / External Reference Input
6
COM
IN
Analog
Ground reference for analog inputs in single ended mode
7
CH0
IN
Analog
Analog Input Channel 0
8
CH1
IN
Analog
Analog Input Channel 1
9
CH3
IN
Analog
Analog Input Channel 3
10
CH2
IN
Analog
Analog Input Channel 2
11
REFADJ
I/O
Analog
Input to Reference Buffer Amplifier
12
VDD
SUPPLY
Positive Supply
13
nSHDN
IN
CMOS Digital
Active Low Shutdown
14
DOUT
OUT
CMOS Digital
Serial Data Output
15
SSTRB
OUT
CMOS Digital
Serial Strobe Output
16
SCLK
IN
CMOS Digital
Serial Clock Input
nCS
DIN
DGND
AGND
VREF
COM
CH0
CH1
ZADCS 0842 / ZADCS 0842V
1
SCLK
SSTRB
DOUT
nSHDN
VDD
REFADJ on ZADCS0842V,
No connect on ZADCS0842
CH2
CH3
Figure 2: Package Pin Assignment for ZADCS0842 & ZADCS0842V
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
5/20
Datasheet
ZADCS0882/0842/0822 Family
1.4
Package Pin Assignment ZADCS0822 / ZADCS0822V
Table 4: Pin list
Package
pin number
Name
Direction
Type
Description
1
nCS
IN
CMOS Digital
Active Low Chip Select
2
DIN
IN
CMOS Digital
Serial Data Input
3
DGND
SUPPLY
Digital Ground
4
AGND
SUPPLY
Analog Ground
5
VREF
I/O
Analog
Reference Buffer Output / External Reference Input
6
COM
IN
Analog
Ground reference for analog inputs in single ended mode
7
CH0
IN
Analog
Analog Input Channel 0
8
CH1
IN
Analog
Analog Input Channel 1
9
REFADJ
I/O
Analog
Input to Reference Buffer Amplifier
10
VDD
SUPPLY
Positive Supply
11
nSHDN
IN
CMOS Digital
Active Low Shutdown
12
DOUT
OUT
CMOS Digital
Serial Data Output
13
SSTRB
OUT
CMOS Digital
Serial Strobe Output
14
SCLK
IN
CMOS Digital
Serial Clock Input
SCLK
DIN
SSTRB
DGND
AGND
VREF
COM
CH0
ZADCS 0822
ZADCS 0822V
nCS
DOUT
nSHDN
VDD
REFADJ on ZADCS0822V,
No connect on ZADCS0822
CH1
Figure 3: Package Pin Assignment for ZADCS0822 & ZADCS0822V
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
6/20
Datasheet
ZADCS0882/0842/0822 Family
1.5
Electrical Characteristics
1.5.1 General Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 11 clocks/conversion cycle (300 ksps); VREF = 2.500V applied to VREF pin;
qOP = qOPmin … qOPmax)
Parameter
Symbol Conditions
Min
Typ
Max
Unit
DC Accuracy
Resolution
8
Relative Accuracy
INL
No Missing Codes
NMC
Differential Nonlinearity
DNL
ZADCS0882 / ZADCS0882V
ZADCS0842 / ZADCS0842V
ZADCS0822 / ZADCS0822V
Bits
± 0.25 LSB
8
Bits
ZADCS0882 / ZADCS0882V
ZADCS0842 / ZADCS0842V
ZADCS0822 / ZADCS0822V
± 0.25 LSB
Offset Error
± 0.25
± 1.0
LSB
Gain Error
± 0.25
± 1.0
LSB
Gain Temperature Coefficient
± 0.25
ppm/°C
Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 300ksps, 3.3MHz external clock)
Signal-to-Noise + Distortion Ratio
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Small-Signal Bandwidth
49
dB
th
Up to the 5 harmonic
-66
64
-3dB roll off
dB
dB
3.8
MHz
Conversion Rate
Sampling Time
(= Track/Hold Acquisition Time)
tACQ
Conversion Time
tCONV
Ext. Clock = 3.3MHz, 2.5 clocks/ acquisition
0.758
µs
Ext. Clock = 3.3MHz, 8 clocks/ conversion
Int. Clock = 3.3MHz +/- 12% tolerance
2.20
2.43
µs
2.80
µs
Aperture Delay
30
ns
Aperture Jitter
< 50
ps
External Clock Frequency
0.1
Internal Clock Frequency
2.81
3.3
3.3
MHz
3.58
MHz
Analog Inputs
Input Voltage Range, SingleEnded and Differential
Input Capacitance
Unipolar, COM = 0V
0 to VREF
Bipolar, COM = VREF/2
± VREF / 2
16
V
pF
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
7/20
Datasheet
ZADCS0882/0842/0822 Family
1.5.2 Specific Parameters of ZADCS08x2V versions (with Internal Reference)
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 11 clocks/conversion cycle (300 ksps); qOP = qOPmin … qOPmax)
Parameter
Symbol Conditions
Min
Typ
Max
Unit
2.480
2.500
2.520
V
Internal Reference at VREF
VREF Output Voltage
TA = + 25°C
VREF Short-Circuit Current
30
VREF Temperature Coefficient
± 30
Load Regulation
0 to 0.2mA output load
Capacitive Bypass at VREF
Capacitive Bypass at REFADJ
± 50
0.35
mA
ppm/°C
mV
4.7
µF
0.047
µF
± 1.5
REFADJ Adjustment Range
%
External Reference at VREF (internal buffer disabled by V(REFADJ) = VDD)
VREF Input Voltage Range
VDD +
V
50mV
1.0
VREF Input Current
VREF = 2.5V
VREF Input Resistance
180
11.5
215
14
Shutdown VREF Input Current
kW
0.1
VDD0.5
REFADJ Buffer Disable Threshold
µA
µA
V
External Reference at VREF_ADJ
Reference Buffer Gain
2.00
VREF_ADJ Input Current
Full Power Down
VREFADJ Input Current
Full Power-Down mode
±80
µA
0.1
µA
Power Requirements
Positive Supply Voltage
VDD
Positive Supply Current
ZADCS0882VI
ZADCS0842VI
ZADCS0822VI
IDD
ZADCS0882VI
ZADCS0842VI
ZADCS0822VI
Positive Supply Current
IDD
ZADCS0882VQ
ZADCS0842VQ
ZADCS0822VQ
Positive Supply Current
IDD
1)
5.25
V
0.85
1.3
250
1.0
1.4
300
mA
mA
0.5
4.0
1.00
1.40
250
1.3
1.6
300
Full Power-Down
0.5
4.0
Operating Mode ext. VREF
Operating Mode int. VREF
0.85
1.3
1.1
1.51)
Fast Power-Down
250
3501)
Full Power-Down
0.5
15
Operating Mode ext. VREF
1.00
1.41)
mA
Operating Mode int. VREF
1.40
1)
1.7
mA
Fast Power-Down
250
350
Full Power-Down
0.5
201)
Full Power-Down
Positive Supply Current
ZADCS0882VQ
ZADCS0842VQ
ZADCS0822VQ
2.7
Operating Mode ext. VREF
Operating Mode int. VREF
VDD=3.6V
Fast Power-Down
IDD
Operating Mode ext. VREF
Operating Mode int. VREF
VDD=5.2V
Fast Power-Down
VDD=3.6V
VDD=5.2V
1)
1)
µA
mA
mA
µA
mA
mA
µA
1)
µA
relaxed maximum limits are due to wider temperature range of automotive qualified version ZADCS08x2VQ
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
8/20
Datasheet
ZADCS0882/0842/0822 Family
1.5.3 Specific Parameters of basic ZADCS08x2 versions (without Internal Reference)
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 11 clocks/conversion cycle (300 ksps); qOP = qOPmin … qOPmax)
Parameter
Symbol Conditions
Min
Typ
Max
Unit
External Reference at VREF
VREF Input Voltage Range
180
VDD +
V
50mV
215 µA
14
kW
1.0
VREF Input Current
VREF = 2.5V
VREF Input Resistance
11.5
Shutdown VREF Input Current
0.1
Capacitive Bypass at VREF
4.7
µA
µF
Power Requirements
Positive Supply Voltage
Positive Supply Current
ZADCS0882I, ZADCS0842I,
ZADCS0822I
Positive Supply Current
ZADCS0882I, ZADCS0842I,
ZADCS0822I
Positive Supply Current
ZADCS0882Q, ZADCS0842Q,
ZADCS0822Q
Positive Supply Current
ZADCS0882Q, ZADCS0842Q,
ZADCS0822Q
1)
VDD
2.7
IDD
VDD = 3.6V
IDD
VDD = 5.25V
IDD
VDD = 3.6V
IDD
VDD = 5.25V
Operating Mode
0.85
5.25
1.0
Full Power-Down
0.5
4.0
Operating Mode
1.00
1.3
Full Power-Down
0.5
4.0
Operating Mode
0.85
1.01)
Full Power-Down
0.5
151)
Operating Mode
1.00
1.31)
Full Power-Down
0.5
201)
V
µA
µA
µA
µA
relaxed maximum limits are due to wider temperature range of automotive qualified version ZADCS08x2Q
1.5.4 Digital Pin Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 11 clocks/conversion cycle (300 ksps); qOP = qOPmin … qOPmax)
Parameter
Symbol Conditions
Min
Typ
Max
Unit
Digital Inputs (DIN, SCLK, CS, nSHDN)
Logic High Level
VIH
Logic Low Level
VIL
Hysteresis
VHyst
Input Leakage
IIN
Input Capacitance
CIN
VDD = 2.7V
1.9
V
VDD = 5.25V
3.3
V
VDD = 2.7V
0.7
V
VDD = 5.25V
1.4
V
0.7
VIN = 0V or VDD
V
± 0.1
± 1.0
5
µA
pF
Digital Outptus (DOUT, SSTRB)
VDD = 2.7V
3.5
8.5
mA
VDD = 5.25V
5.5
10.8
mA
VDD = 2.7V
4
11.5
mA
VDD = 5.25V
6.4
15.3
mA
± 1.0
µA
Output High Current
IOH
VOH= VDD – 0.5V
Output Low Voltage
IOL
VOL= 0.4V
Three-State Leakage Current
ILeak
nCS = VDD
± 0.1
Three-State Output Capacitance
COUT
nCS = VDD
5
pF
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
9/20
Datasheet
ZADCS0882/0842/0822 Family
1.6
Typical Operating Characteristics
Differential Nonlinearity vs. Code
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
DNL (LSB)
INL (LSB)
Integral Nonlinearity vs. Code
1
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
0
32
64
96
128
160
192
224
256
0
32
64
96
128
Code
160
192
224
256
Code
IDDstatic vs. Temperature
ZADCS12x2V, internal reference active, at VDD = 3.3V
IDD vs. VDD
1500
700
1350
1200
IDDactive (converting)
650
900
IDD (µA)
IDD (µA)
1050
750
600
600
IDDstatic
450
550
300
150
External VREF
Internal VREF
0
500
2.7
3.4
4.1
VDD (V)
4.8
5.5
-40
-20
0
20
40
60
80
100
Temperatur (°C)
IDDactive (converting) vs. Temperature
ZADCS12x2V, internal reference active, at VDD = 3.3V
VREF vs. Temperature
1050
Reference Voltage (v)
2.501
IDD (µA)
1000
950
2.500
2.499
2.498
900
-40
-20
0
20
40
Temperatur (°C)
60
80
100
-25
0
25
50
75
Tem perature (°C)
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
10/20
Datasheet
ZADCS0882/0842/0822 Family
2 DETAILED DESCRIPTION
2.2
2.1
The analog input to the converter is fully differential. Both
converter input signals IN+ and IN– (see Functional Block
diagram at front page) get sampled during the acquisition
period enabling the converter to be used in fully differential applications where both signals can vary over time.
The ZADCS08x2 family converters do not require that the
negative input signal be kept constant within ± 0.5LSB
during the entire conversion as is commonly required by
converters featuring pseudo differential operation only.
The input signals can be applied single ended, referenced to the COM pin, or differential, using pairs of the
input channels. The desired configuration is selectable for
every conversion via the Control-Byte received on DIN
pin of the digital interface (see further description below)
A block diagram of the input multiplexer is shown in
Figure 7. Table 5 and Table 6 show the relationship of the
Control-Byte bits A2, A1, A0 and SGL/DIF to the configuration of the analog multiplexer. The entire table applies
only to ZADCS0882 devices. For ZADCS0842 devices bit
A1 is don’t care, for ZADCS0822 devices A1 and A0 are
don’t care.
Both input signals IN+ and IN– are generally allowed to
swing between –0.2V and VDD+0.2V. However, depending on the selected conversion mode – uniploar or bipolar – certain input voltage relations can limit the output
code range of the converter.
0
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
A2
A1
IN-
0
0
0
IN-
0
0
1
IN-
0
1
0
IN-
0
1
1
IN-
1
0
0
IN-
1
0
1
IN-
1
1
0
IN-
1
1
1
≥ 4.7µF
SCLK 20
2 DIN
SSTRB 19
3 DGND
DOUT 18
4 AGND
nSHDN 17
5 VREF
6 COM
VDD 16
VREFADJ 15
ININ+
ININ+
IN-
IN-
IN+
IN-
IN-
IN+
IN+
IN-
IN+
ZADCS0882
+2.7V to 5.25V
≥ 4.7µF
47nF
0.1µF
10µF
1 nCS
SCLK 20
2 DIN
SSTRB 19
3 DGND
DOUT 18
4 AGND
nSHDN 17
5 VREF
VDD 16
6 COM
n.c. 15
7 CH0
CH2 14
7 CH0
CH2 14
8 CH1
CH3 13
8 CH1
CH3 13
9 CH4
CH6 12
9 CH4
CH6 12
10 CH5
CH7 11
10 CH5
CH7 11
Single-ended or differential
analog inputs, 0V … +2.5V
IN-
IN+
µC
ZADCS0882V
1 nCS
IN+
Figure 5: Basic application schematic for ZADCS0882
MOSI
MISO
SCK
µC
I/O
MOSI
Figure 4: Basic application schematic for ZADCS0882V
A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
I/O
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
Table 6: Channel selection in Differential Mode
(SGL/DIF = LOW)
MISO
The ZADCS08x2 family is a set of classic successive
approximation register (SAR) type converters. The architecture is based on a capacitive charge redistribution
DAC merged with a resistor string DAC building a hybrid
converter with excellent monotonicity and DNL properties.
The Sample & Hold function is inherent to the capacitive
DAC. This avoids additional active components in the
signal path that could distort the input signal or introduce
errors.
All devices in the ZADCS08x2 family build on the same
converter core and differ only in the number of input
channels and the availability of an internal reference
voltage generator. The ZADCS08x2V versions are
equipped with a highly accurate internal 1.25V bandgap
reference which is available at the VREFADJ pin. The
bandgap voltage is further amplified by an internal buffer
amplifier to 2.50V that is available at pin VREF. All other
versions come without the internal reference and the
internal buffer amplifier. They require an external reference supplied at VREF, with the benefit of considerably
lower power consumption.
A basic application schematic for ZADC0882V is shown
in Figure 4, for ZADCS0882 in Figure 5. ZADCS0882V
can also be operated with an external reference, if
VREFADJ is tied to VDD.
Table 5: Channel selection in Single Ended Mode
(SGL/DIF = HIGH)
SCK
General Operation
Analog Input
+2.7V to 5.25V
0.1µF
10µF
Single-ended or differential
analog inputs, 0V … +VREF
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Information furnished in this publication is preliminary and subject to changes without notice.
11/20
Datasheet
ZADCS0882/0842/0822 Family
Figure 7: Block diagram of input multiplexer
Figure 8: Input voltage range in unipolar mode
VIN+
Shown configuration
A2 … A0 = 0x000
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1.5*VREF
0xFF
VREF
Code Range
IN+
0.5*VREF
Converter
0x00
IN0V
VDD-VREF
VIN-
Figure 9: Input voltage range for fully differential signals in bipolar mode
VCM
VREF
¾ VREF
VCM
COM
See Table 5 & Table 6
for Coding Schemes
Range
¼ VREF
SGL/DIF = HIGH
In unipolar mode the voltage at IN+ must exceed the
voltage at IN– to obtain codes unequal to 0x00. The entire
8 bit transfer characteristic is then covered by IN+ if IN+
ranges from IN– to (IN– +Vref). Any voltage on IN+ > (IN–
+ Vref) results in code 0xFF. Code 0xFF is not reached,
if (IN– +Vref) > VDD + 0.2V because the input voltage is
clamped at VDD + 0.2V by ESD protection devices.
The voltage at IN– can range from -0.2V … ½ VREF without limiting the Code Range, assuming the fore mentioned VDD condition is true. See also Figure 8 for input
voltage ranges in unipolar conversion mode.
In bipolar mode, IN+ can range from (IN– - Vref/2) to (IN–
+ Vref/2) keeping the converter out of code saturation.
For instance, if IN– is set to a constant DC voltage of
Vref/2, then IN+ can vary from 0V to VREF to cover the
entire code range. Lower or higher voltages of IN+ keep
the output code at the minimum or maximum code value.
Figure 9 shows the input voltage ranges in bipolar mode
when IN– is set to a constant DC voltage.
As explained before, converters out of the ZADCS08x2
family can also be used to convert fully differential input
signals that change around a common mode input voltage.
The bipolar mode is best used for such purposes since it
allows the input signals to be positive or negative in relation to each other.
The common mode level of a differential input signal is
calculated VCM = (V(IN+)+ V(IN–)) / 2. To avoid code clipping or over steering of the converter, the common mode
level can change from ¼ VREF … ¾ VREF. Within this
0V
-VREF/2
0V
+VREF/2
VDIFF
range the peak to peak amplitude of the differential input
signal can be ± VREF/2.
The average input current on the analog inputs depends
on the conversion rate. The signal source must be capable of charging the internal sampling capacitors (typically
16pF on each input of the converter: IN+ and IN–) within
the acquisition time tACQ to the required accuracy. The
equivalent input circuit in sampling mode is shown in
Figure 6.
The following equation provides a rough hand calculation
for a source impedance RS that is required to settle out a
DC input signal referenced to AGND with 8 bit accuracy
in a given acquisition time
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
Channel
Multiplexer
CHOLD+
IN+ C
IN
4pF 16pF
RSW
3kΩ
AGND
CHOLDIN-
CIN
4pF 16pF
RSW
3kΩ
AGND
Figure 6: Equivalent input circuit during sampling
Copyright © 2008, ZMD AG, Rev. 1.1
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Information furnished in this publication is preliminary and subject to changes without notice.
12/20
VDC
Datasheet
ZADCS0882/0842/0822 Family
RS £
t ACQ
- R SW
6 ´ CIN
For example, if fSCLK = 3.3MHz, the acquisition time is
tACQ = 758ns. Thus the output impedance of the signal
source RS must be less than
RS £
758ns
- 3kΩ = 3.32kΩ
6 ´ 20pF
If the output impedance of the source is higher than the
calculated maximum RS the acquisition time must be
extended by reducing fSCLK to ensure 8 bit accuracy.
Another option is to add a capacitor of >20 nF to the
individual input. Although this limits the bandwidth of the
input signal because an RC low pass filter is build together with the source impedance, it may be useful for
certain applications.
The small-signal bandwidth of the input tracking circuitry
is 3.8 MHz. Hence it is possible to digitize high-speed
transient events and periodic signals with frequencies
exceeding the ADC’s sampling rate. This allows the application of certain under-sampling techniques like down
conversion of modulated high frequency signals.
Be aware that under-sampling techniques still require a
bandwidth limitation of the input signal to less than the
Nyquist frequency of the converter to avoid aliasing effects. Also, the output impedance of the input source
must be very low to achieve the mentioned small signal
bandwidth in the overall system.
2.3
Internal & External Reference
ZADCS08x2V family members are equipped with a highly
accurate internal 2.5V reference voltage source. The
voltage is generated from a trimmed 1.25V bandgap with
an internal buffer that is set to a gain of 2.00. The bandgap voltage is supplied at VREFADJ with an output impedance of 20kΩ. An external capacitor of 47nF at
VREFADJ is useful to further decrease noise on the internal reference.
The VREFADJ pin also provides an opportunity to externally adjust the bandgap voltage in a limited range (see
Figure 10) as well as the possibility to overdrive the internal bandgap with an external 1.25V reference.
Figure 10: Reference Adjust Circuit
VDD = +2.7V … +5.25V
ZADCS08x2V
The internal bandgap reference and the VREF buffer can
be shut down completely by setting VREFADJ to VDD.
This reduces power consumption of the ZADCS08x2V
devices and allows the supply of an external reference at
VREF.
Basic ZADCS08x2 devices do not contain the internal
bandgap or the VREF buffer. An external reference must
be supplied all the time at VREF.
The value of the reference voltage at VREF sets the input
range of the converter and the analog voltage weight of
each digital code. The size of the LSB (least significant
bit) is equal to the value of VREF (reference to AGND)
divided by 256. For example at a reference voltage of
2.500V, the voltage level of a LSB is equal to 9.766mV.
The average current consumption at VREF depends on
the value of VREF and the sampling frequency. Two
effects contribute to the current at VREF, a resistive connection from VREF to AGND and charge currents that
result from the switching and recharging of the capacitor
array (CDAC) during sampling and conversion.
For an external reference of 2.5V the input current at
VREF is approximately 100µA.
2.4
Digital Interface
All devices out of the ZADCS08x2 family are controlled
by a 4-wire serial interface that is compatible to SPI™,
QSPI™ and MICROWIRE™ devices without external
logic.
Any conversion is started by sending a control byte into
DIN while nCS is low. A typical sequence is shown in
Figure 11.
The control byte defines the input channel(s), unipolar or
bipolar operation and output coding, single-ended or
differential input configuration, external or internal conversion clock and the kind of power down that is activated
after the completion of a conversion. A detailed description of the control bits can be obtained from Table 7.
As it can also be seen in Figure 11 the acquisition of the
input signal occurs at the end of the control byte for 2.5
clock cycles. Outside this range, the Track & Hold is in
hold mode.
The conversion process is started, with the falling clock
edge (SCLK) of the eighth bit in the control byte. It takes
twelve clock cycles to complete the conversion and one
additional cycle to shift out the last bit of the conversion
result. During the remaining seven clock cycles the output
is filled with zeros in 24-Clock Conversion Mode.
Depending on what clock mode was selected, either the
external SPI clock or an internal clock is used to drive the
successive approximation. Figure 12 shows the Timing
for Internal Clock Mode.
510kΩ
VREFADJ
47nF
Copyright © 2008, ZMD AG, Rev. 1.1
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Information furnished in this publication is preliminary and subject to changes without notice.
13/20
Datasheet
ZADCS0882/0842/0822 Family
Figure 11: 24-Clock External Clock Mode Timing (SPI™, QSPI™ and MICROWIRE™ compatible, fSCLK ≤ 3.3MHz)
nCS
tACQ
SCLK
8
1
S
DIN
A2
(Start)
A1
1
8
1
8
UNI/ SGL/
A0 BIP DIF PD1 PD0
Idle
Acquire
Conversion
Idle
SSTRB
B7
DOUT
B6
B5
B4
B3
B2
B1
(MSB)
Zero filled
B0
(LSB)
Figure 12: Internal Clock Mode Timing with interleaved Control Byte transmission
nCS
SCLK
8
1
S
DIN
A2
A1
1
8
UNI/ SGL/
A0 BIP DIF PD1 PD0
1
S
8
A2
A1
UNI/ SGL/
A0 BIP DIF PD1 PD0
(Start)
Idle
Acquire
Result Output
Conversion
Acquire
SSTRB
tCONV
B7
DOUT
B6
B5
B4
(MSB)
B3
B2
B1
B0
Zero filled
(LSB)
Table 7: Control Byte Format
BIT
Name
Description
7 (MSB)
START
The Start Bit is defined by the first logic ‘1’ after nCS goes low.
6
5
4
A2
A1
A0
Channel Select Bits. Along with SGL/DIF these bits control the setting of the input multiplexer. For further details on the decoding see also Table 5 and Table 6.
3
UNI/BIP
Output Code Select Bit. The value of the bit determines conversion mode and output code
format.
‘1’ = unipolar - straight binary coding
‘0’ = bipolar - two’s complement coding
2
SGL/DIF
Single-Ended / Differential Select Bit. Along with the Channel Select Bits A2 .. A0 this bit
controls the setting of the input multiplexer
‘1’ = single ended - all channels CH0 … CH7 measured referenced to COM
‘0’ = differential - the voltage between two channels is measured
1
0 (LSB)
PD1
PD0
Power Down and Clock Mode Select Bits
PD1
PD0
Mode
0
0
Full Power-Down
0
1
Fast Power-Down
1
0
Internal clock mode
1
1
External clock mode
Copyright © 2008, ZMD AG, Rev. 1.1
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Information furnished in this publication is preliminary and subject to changes without notice.
14/20
Datasheet
ZADCS0882/0842/0822 Family
Figure 13: 16-Clock External Clock Mode Conversion
nCS
SCLK
1
8
S
DIN
A2
(Start)
A1
1
8
1
UNI/ SGL/
A0 BIP DIF PD1 PD0
Idle
S
Acquire
8
A2
Conversion
A1
1
UNI/ SGL/
A0 BIP DIF PD1 PD0
Idle
Acquire
SSTRB
B7
DOUT
B6
B5
B4
B3
B2
B1
(MSB)
Zero filled
B0
B7
B6
(LSB)
Figure 14: 11-Clock External Clock Mode Conversion
nCS
SCLK
DIN
1
S
8
A2
(Start)
A1
Idle
11
1
UNI/ SGL/
A0 BIP DIF PD1 PD0
S
11
A2
Acquire
A1
UNI/ SGL/
A0 BIP DIF PD1 PD0
Conversion
1
S
A2
A1
UNI/ SGL/
A0 BIP DIF
Conversion
Acquire
SSTRB
DOUT
B7
B6
B5
(MSB)
B4
B3
B2
B1
B0
Zero filled
B7
B6
B5
B4
B3
B2
B1
B0
(LSB)
Internal Clock Mode
16-Clocks per Conversion
In Internal Clock Mode, the conversion starts at the falling
clock edge of the eighth control bit just as in External
Clock Mode. However, there are no further clock pulses
required at SCLK to complete the conversion. The conversion clock is generated by an internal oscillator that
runs at approximately 3.3MHz. While the conversion is
running, the SSTRB signal is driven LOW. As soon as the
conversion is complete, SSTRB is switched to HIGH,
signaling that the conversion result can be read out on
the serial interface.
To shorten cycle times ZADCS08x2 family devices allow
interleaving of the read out process with the transmission
of a new control byte. Thus it is possible to read the conversion result and to start a new conversion with just two
consecutive byte transfers, instead of thee bytes that
would have to be send without the interleaving function.
Interleaving of the data read out process and transmission of a new Control Byte is also supported for External
Clock Mode operation. Figure 13 shows the transmission
timing for conversion runs using 16 clock cycles per run.
While the IC is performing a conversion in Internal Clock
Mode, the Chip Select signal (nCS) may be tied HIGH
allowing other devices to communicate on the bus. The
output driver at DOUT is switched into a high impedance
state while nCS is HIGH. The conversion time tCONV may
vary in the specified limits depending on the actual VDD
and temperature values.
11-Clocks per Conversion
ZADCS08x2 family devices do also support a 11 clock
cycle conversion mode (see Figure 14). This is the fastest
conversion mode possible. In fact, the specified converter
sampling rate of 300ksps will be reached in this mode,
provided the clock frequency is set to 3.3MHz.
Usually micro controllers do not support this kind of 11 bit
serial communication transfers. However, specifically
designed digital state machines implemented in Field
Programmable Gate Arrays (FPGA) or Application Specific Integrated Circuits (ASIC) may use this operation
mode.
Digital Timing
In general the clock frequency at SCLK may vary from
0.1MHz to 3.3MHz. Considering all telegram pauses or
other interruptions of a continuous clock at SCLK, each
conversion must be completed within 1.2ms from the
falling clock edge of the eighth bit in the Control Byte.
Otherwise the signal that was captured during sam-
Copyright © 2008, ZMD AG, Rev. 1.1
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Information furnished in this publication is preliminary and subject to changes without notice.
15/20
Datasheet
ZADCS0882/0842/0822 Family
Table 8: Timing Characterisitics (VDD = +2.7V to + 5.25V; qOP = qOPmin … qOPmax)
Parameter
Symbol Conditions
Min
SCLK Periode
tSCLK
303.0
ns
SCLK Pulse Width High
tSCLKhigh
151.5
ns
SCLK Pulse Width Low
tSCLKlow
151.5
ns
DIN to SCLK Setup
tDinSetup
30
ns
DIN to SCLK Hold
tDinHold
10
ns
nCS Fall to SCLK Setup
tnCSSetup
30
ns
SCLK Fall to
DOUT & SSTRB Hold
tOutHold
CLoad = 20pF
10
ns
SCLK Fall to
DOUT & SSTRB Valid
tOutValid
CLoad = 20pF
nCS Rise to
DOUT & SSTRB Disable
tOutDisable
CLoad = 20pF
nCS Fall to
DOUT & SSTRB Enable
tOutEnable
CLoad = 20pF
nCS Pulse Width High
tnCSHigh
10
100
Typ
Max
Unit
40
ns
60
ns
60
ns
ns
Figure 15: Detailed Timing Diagram
nCS
tnCSSetup
tSCLKhigh
tSCLK
tSCLKlow
tOutValid
SCLK
tDINsetup
tDINhold
DIN
SSTRB
DOUT
tOutEnable
tnCSHigh
tOutEnable
ple/hold may drop to noticeable affect the conversion
result.
Further detailed timing information on the digital interface
is provided in Table 8 and Figure 15.
Output Code Format
tOutDisable
tOutHold
lent to ½ LSB, the last (0xFE à 0xFF) at VREF - 1.5 LSB.
See also Figure 16 for details.
In bipolar mode a two’s complement coding is applied.
Code transitions occur again halfway between successive
integer LSB values. The transfer function is shown in
Figure 17.
ZADCS08x2 family devices do all support unipolar and
bipolar operation modes. The digital output code is
straight binary in unipolar mode. It ranges from 0x00 for
an input voltage difference of 0V to 0xFF for an input
voltage difference of VREF (Full Scale = FS). The first
code transition (0x00 à 0x01) occurs at a voltage equivaCopyright © 2008, ZMD AG, Rev. 1.1
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Information furnished in this publication is preliminary and subject to changes without notice.
16/20
Datasheet
ZADCS0882/0842/0822 Family
Figure 16: Unipolar Transfer Function
Figure 17: Bipolar Transfer Function
Output Code
Output Code
11 … 111
11 … 110
01 … 111
01 … 110
11 … 101
ZS = V(IN-)
FS = VREF +V(IN-)
VREF
1LSB =
256
00 … 011
ZS = V(IN-)
+ FS = ½VREF +V(IN-)
- FS = -½VREF +V(IN-)
VREF
1LSB =
256
00 … 001
00 … 000
11 … 111
11 … 110
11 … 101
00 … 010
00 … 001
10 … 001
00 … 000
10 … 000
-FS
0 1
(ZS)
2.5
2
3
FS
Input Voltage (LSB)
FS-3/2 LSB
Power Dissipation
The ZADCS08x2 family offers three different ways to
save operating current between conversions. Two different software controlled power down modes can be activated to automatically shut-down the device after completion of a conversion. They differ in the amount of circuitry
that is powered down.
Software Power Down
Full Power Down Mode shuts down the entire analog part
of the IC, reducing the static IDD of the device to less
than 0.5µA if no external clock is provided at SCLK.
Fast Power Down mode is only useful with ZADCS08x2V
devices if the internal voltage reference is used. During
Fast Power-Down the bandgap and the VREFADJ output
buffer are kept alive while all other internal analog circuitry is shut down. The benefit of Fast Power Down
mode is a shorter turn on time of the reference compared
to Full Power-Down Mode. This is basically due to the
fact that the low pass which is formed at the VREFADJ
output by the internal 20kΩ resistor and the external
buffer capacitor of 47nF is not discharged in Fast PowerDown Mode.
The settling time of the low pass at VREFADJ is about
6 ms to reach 8 bit accuracy. The Fast Power Down
mode omits this settling and reduces the turn on time to
about 200µs.
To wake up the IC out of either software power down
mode, it is sufficient to send a Start Bit while nCS is
LOW. Since micro controllers can commonly transfer full
bytes per transaction only, a dummy conversion is usually
carried out to wake the device.
In all application cases where an external reference voltage is supplied (basic ZADCS08x2 and ZADCS08x2V
with VREFADJ tied to VDD) there is no turn on time to be
considered. The first conversion is already valid. Fast
Power-Down and Full Power-Down Mode do not show
any difference in this configuration.
ZS
Input Voltage (LSB)
+FS
+FS-3/2 LSB
Hardware Power Down
The third power down mode is called Hardware PowerDown. It is initiated by pulling the nSHDN pin LOW. If this
condition is true, the device will immediately shut down all
circuitry just as in Full Power Down-Mode.
The IC wakes up if nSHDN is tied HIGH. There is no
internal pull-up that would allow nSHDN to float during
normal operation. This ensures the lowest possible power
consumption in power down mode.
General Power Considerations
Even without activating any power down mode, the devices out of the ZADCS08x2 family reduce their power
consumption between conversions automatically. The
comparator, which contributes a considerable amount to
the overall current consumption of the device, is shut off
as soon as a conversion is ended. It gets turned on at the
start of the next acquisition period. This explains the
difference between the IDDstatic and IDDactive measurements shown in chapter 1.6 Typical Operating Characteristics.
The average current consumption of the device depends
very much on the sampling frequency and the type of
protocol used to communicate with the device.
In order to achieve the lowest power consumption at low
sampling frequencies, it is suggested to keep the conversion clock frequency at the maximum level of 3.3MHz and
to power down the device between consecutive conversions. Figure 18 shows the characteristic current consumption of the ZADCS08x2 family with external reference supply versus Sampling Rate
3 Layout
To achieve optimum conversion performance care must
be taken in design and layout of the application board. It
is highly recommended to use printed circuit boards instead of wire wrap designs and to establish a single point
Copyright © 2008, ZMD AG, Rev. 1.1
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17/20
Datasheet
ZADCS0882/0842/0822 Family
Figure 18: Average Supply Current versus Sampling
Rate
Figure 19: Optimal Power-Supply Grounding System
Current consumption vs. Sample Rate
External Clock Mode, External VREF, fSCLK = 3.3MHz
Optional
R = 10Ω
VDD
VDD1
(+2.7 … +5.25V)
ZADCS08x2
Family
1000
AGND
100
COM
DGND
10
1
1
10
100
1000
Other
Digital
Circuitry
Power Supplies
Average Supply Current (µA)
10000
DGND
GND
DVDD
VDD2
Sample Rate (ksps)
star connection ground system towards AGND (see
Figure 19).
For optimal noise performance the star point should be
located very close to the AGND pin of the converter. The
ground return to the power supply should be as short as
possible and low impedance.
All other analog ground points of external circuitry that is
related to the A/D converter as well as the DGND pin of
the device should be connected to this ground point too.
Any other digital ground system should be kept apart as
far as possible and connect on the power supply point
only.
Analog and digital signal domains should also be separated as well as possible and analog input signals should
be shielded by AGND ground planes from electromagnetic interferences. Four-layer PCB boards that allow
smaller vertical distances between the ground plane and
the shielded signals do generally show a better performance than two-layer boards.
The sampling phase is the most critical portion of the
overall conversion timing for signal distortion. If possible,
the switching of any high power devices or nearby digital
logic should be avoided during the sampling phase of the
converter.
The fully differential internal architecture of the
ZADCS08x2 family ensures very good suppression of
power supply noise. Nevertheless, the SAR architecture
is generally sensitive to glitches or sudden changes of the
power supply that occur shortly before the latching of the
comparator output. It is therefore recommended to bypass the power supply connection very close to the device with capacitors of 0.1µF (ceramic) and >1µF (electrolytic).
In case of a noisy supply, an additional series resistor of
5 to 10 ohms can be used to low-pass filter the supply
voltage.
The reference voltage should always be bypassed with
capacitors of 0.1µF (ceramic) and ≥ 4.7µF (electrolytic) as
close as possible to the VREF pin. If VREF is provided by
an external source, any series resistance in the VREF
supply path can cause a gain error of the converter. During conversion, a DC current of about 100µA is drawn
through the VREF pin that could cause a noticeable voltage drop across the resistance.
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
18/20
Datasheet
ZADCS0882/0842/0822 Family
4 Package Drawing
ZADCS0882 devices are delivered in a 20-pin SSOP-package that has the dimensions as shown in Figure 20 and Table 9.
ZADCS0842 and ZADCS0822 devices apply respective 16-pin and 14-pin SSOP-packages. Their dimensions are specified
in Table 10 and Table 11.
Figure 20: Package Outline Dimensions
Table 9: Package Dimensions for ZADC0882 devices (mm)
Symbol
Nominal
Maximum
Minimum
A
1.86
1.99
1.73
A1
0.13
0.21
0.05
A2
1.73
1.78
1.68
bP
0.30
0.38
0.25
c
0.15
0.20
0.09
D
7.20
7.33
7.07
E
5.30
5.38
5.20
enom
E
5.30
5.38
5.20
enom
E
5.30
5.38
5.20
enom
0.65
HE
7.80
7.90
7.65
LP
Z
k
0.74
0.63
0.25
Q
4°
8°
0°
Table 10: Package Dimensions for ZADC0842 devices (mm)
Symbol
Nominal
Maximum
Minimum
A
1.86
1.99
1.73
A1
0.13
0.21
0.05
A2
1.73
1.78
1.68
bP
0.30
0.38
0.25
c
0.15
0.20
0.09
D
6.20
6.07
6.33
0.65
HE
7.80
7.90
7.65
LP
Z
k
0.89
0.63
0.25
Q
4°
10°
0°
Table 11: Package Dimensions for ZADC0822 devices (mm)
Symbol
Nominal
Maximum
Minimum
A
1.86
1.99
1.73
A1
0.13
0.21
0.05
A2
1.73
1.78
1.68
bP
0.30
0.38
0.25
c
0.15
0.20
0.09
D
6.20
6.33
6.07
0.65
HE
7.80
7.90
7.65
LP
Z
k
1.22
0.63
0.25
Q
4°
10°
0°
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
19/20
Datasheet
ZADCS0882/0842/0822 Family
Resolution
[Bit]
Channels
[number]
Sample Rate
[ksps]
Temperature
range
[°C]
QC 100
Qualified
Internal Vref
INL
DNL
Pins
[number]
Package
[Type]
packing
5 Ordering Information
ZADCS0882VIS20T
ZADCS0882IS20T
ZADCS0842VIS16T
ZADCS0842IS16T
ZADCS0822VIS14T
ZADCS0822IS14T
8
8
8
8
8
8
8
8
4
4
2
2
300
300
300
300
300
300
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-------
ü
-ü
-ü
--
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
20
20
16
16
14
14
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
Tube
Tube
Tube
Tube
Tube
Tube
ZADCS0882VQS20T
ZADCS0882QS20T
ZADCS0842VQS16T
ZADCS0842QS16T
ZADCS0822VQS14T
ZADCS0822QS14T
8
8
8
8
8
8
8
8
4
4
2
2
300
300
300
300
300
300
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
ü
ü
ü
ü
ü
ü
ü
-ü
-ü
--
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
± 0,25 LSB
20
20
16
16
14
14
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
Tube
Tube
Tube
Tube
Tube
Tube
Order Code
6 ZMD Distribution Partner
ZMD ADC products as well as the ZADCS1282 Starterkit can be purchased from RUTRONIK Elektronische Bauelemente
GmbH.
RUTRONIK Elektronische Bauelemente GmbH
Industriestrasse 2
78228 Ispringen, Germany
Phone:
+49 7231 801-0
Fax:
+49 7231 82282
E-mail: [email protected]
Internet: www.rutronik.com
7 ZMD Contact
ZMD AG, Headquarters
Grenzstraße 28
D-01109 Dresden
Phone:
Fax:
+49 351 88227 -ADC
(-232)
+49 351 882278 -ADC
(-232)
E-mail: [email protected]
Internet: www.zmd.biz/ADC
ZMD America Inc., New York
ZMD Far East, Hsinchu City
ZMD AG, Tokyo
201 Old Country Road, Suite 204
1F, No14, Lane 268
212-0061
Melville, NY 11747
Sec. 1 Guangfu Rd.
7-6-10-103
Hsinchu City 300, Taiwan
Hanahata, Adachi
Tokyo, Japan
Phone.:
+1 631 549 2666
Phone:
+886 03 563 1388
Phone:
+81 3 6805 0669
Fax:
+1 631 549 2882
Fax:
+886 03 563 6385
Fax:
+81 2 6805 0669
For the most current revision of this document and for additional product information please visit www.zmd.biz/ADC.
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
20/20