MAXIM MAX1302

19-6249; Rev 0; 3/12
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
The MAX1302 multirange, low-power, 16-bit, successive-approximation, analog-to-digital converter (ADC)
operates from a single +5V supply and achieves
throughput rates up to 115ksps. A separate digital supply allows digital interfacing with a 2.7V to 5.25V system
using the SPI-/QSPI™-/MICROWIRE®-compatible serial
interface. Partial power-down mode reduces the supply
current to 1.3mA (typ). Full power-down mode reduces
the power-supply current to 1µA (typ).
The MAX1302 provides eight (single-ended) or four
(true differential) analog input channels. Each analog
input channel is independently software programmable
for seven single-ended input ranges (0V to +VREF/2,
-V REF /2 to 0V, 0V to +V REF , -V REF to 0V, ±V REF /4,
±V REF /2, and ±V REF ), and three differential input
ranges (±VREF/2, ±VREF, ±2 x VREF).
An on-chip +4.096V reference offers a small convenient
ADC solution. The MAX1302 also accepts an external
reference voltage between 3.800V and 4.136V.
The MAX1302 is available in a 24-pin TSSOP package
and is specified for operation from -40°C to +85°C.
Applications
Industrial Control Systems
Data-Acquisition Systems
Features
o Software-Programmable Input Range for Each
Channel
o Single-Ended Input Ranges
0V to +VREF/2, -VREF/2 to 0V, 0V to +VREF,
-VREF to 0V, ±VREF/4, ±VREF/2, and ±VREF
o Differential Input Ranges
±VREF/2, ±VREF, and ±2 x VREF
o Eight Single-Ended or Four Differential Analog
Inputs (MAX1302)
o ±6V Overvoltage Tolerant Inputs
o Internal or External Reference
o 115ksps Maximum Sample Rate
o Single +5V Power Supply
o 24-Pin TSSOP Package
Ordering Information
PART
PIN-PACKAGE
MAX1302AEUG+
CHANNELS
24 TSSOP
8
MAX1302BEUG+
24 TSSOP
8
Note: All devices are specified over the -40°C to +85°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Avionics
Robotics
Pin Configuration
TOP VIEW
AVDD1 1
+
24 AGND1
CH0 2
23 AGND2
CH1 3
22 AVDD2
CH2 4
CH3 5
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
21 AGND3
MAX1302
20 REF
CH4 6
19 REFCAP
CH5 7
18 DVDD
CH6 8
17 DVDDO
CH7 9
16 DGND
CS 10
15 DGNDO
DIN 11
14 DOUT
SSTRB 12
13 SCLK
TSSOP
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX1302
General Description
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
ABSOLUTE MAXIMUM RATINGS
AVDD1 to AGND1 ....................................................-0.3V to +6V
AVDD2 to AGND2 ....................................................-0.3V to +6V
DVDD to DGND ........................................................-0.3V to +6V
DVDDO to DGNDO ..................................................-0.3V to +6V
DVDD to DVDDO......................................................-0.3V to +6V
DVDD, DVDDO to AVDD1 ........................................-0.3V to +6V
AVDD1, DVDD, DVDDO to AVDD2 ..........................-0.3V to +6V
DGND, DGNDO, AGND3, AGND2 to AGND1 ......-0.3V to +0.3V
CS, SCLK, DIN, DOUT, SSTRB to
DGNDO............................................-0.3V to (VDVDDO + 0.3V)
CH0–CH7 to AGND1 ...................................................-6V to +6V
REF, REFCAP to AGND1 ......................-0.3V to (VAVDD1 + 0.3V)
Continuous Current (any pin) ...........................................±50mA
Continuous Power Dissipation (Multilayer board, TA = +70°C)
24-Pin TSSOP (derate 13.9mW/°C above +70°C).....1111.1mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Notes 1, 2)
Resolution
16
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Transition Noise
Bits
MAX1302A
±1.0
±2
MAX1302B
±1.0
±4
No missing codes
-1
External or internal reference
Single-ended inputs
Offset Error
Differential inputs
(Note 3)
+2
1
Unipolar
LSB
LSB
LSBRMS
0
±7.5
Bipolar
-1.0
±7.5
Bipolar
-2.0
±10
mV
Channel-to-Channel Gain
Matching
Unipolar or bipolar
0.025
%FSR
Channel-to-Channel Offset Error
Matching
Unipolar or bipolar
1.0
mV
Offset Temperature Coefficient
Gain Error
Unipolar
3
Bipolar
1
Fully differential
2
Unipolar
±0.5
Bipolar
±0.8
Fully differential
Gain Temperature Coefficient
µV/°C
%FSR
±1
Unipolar
1.5
Bipolar
1.0
ppm/°C
DYNAMIC SPECIFICATIONS fIN(SINE-WAVE) = 5kHz, VIN = FSR - 0.05dB, fSAMPLE = 130ksps (Notes 1, 2)
Signal-to-Noise Plus Distortion
SINAD
Differential inputs, FSR = 2 x VREF
90
Single-ended inputs, FSR = VREF
88
Single-ended inputs, FSR = VREF/2
85
Single-ended inputs, FSR = VREF/4
2
80
82
_______________________________________________________________________________________
dB
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Differential inputs, FSR = 2 x VREF
Signal-to-Noise Ratio
SNR
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
Spurious-Free Dynamic Range
SFDR
TYP
MAX
UNITS
90
Single-ended inputs, FSR = VREF
88
Single-ended inputs, FSR = VREF/2
85
Single-ended inputs, FSR = VREF/4
82
90
dB
-98
dB
99
dB
Aperture Delay
tAD
Figure 21
15
ns
Aperture Jitter
tAJ
Figure 21
100
ps
105
dB
Channel-to-Channel Isolation
CONVERSION RATE
External clock mode, Figure 2
Byte-Wide Throughput Rate
fSAMPLE
114
External acquisition mode, Figure 3
84
Internal clock mode, Figure 4
106
ksps
ANALOG INPUTS (CH0–CH7 MAX1302, AGND1)
Small-Signal Bandwidth
All input ranges, VIN = 100mVP-P (Note 2)
1.5
MHz
Full-Power Bandwidth
All input ranges, VIN = 4VP-P (Note 2)
700
kHz
R[2:1] = 001
-VREF/4
R[2:1] = 010
-VREF/2
R[2:1] = 011
Input Voltage Range (Table 6)
VCH_
True-Differential Analog CommonMode Voltage Range
VCMDR
Common-Mode Rejection Ratio
CMRR
+VREF/4
0
0
+VREF/2
R[2:1] = 100
-VREF/2
R[2:1] = 101
-VREF
0
R[2:1] = 110
0
+VREF
R[2:1] = 111
-VREF
+VREF
DIF/SGL = 1 (Note 4)
-4.75
+5.50
DIF/SGL = 1, input voltage range = ±VREF/4
-VREF < VCH_ < +VREF
+VREF/2
75
-1500
V
V
dB
Input Current
ICH_
+650
Input Capacitance
CCH_
5
µA
pF
Input Resistance
RCH_
6
kΩ
_______________________________________________________________________________________
3
MAX1302
ELECTRICAL CHARACTERISTICS (continued)
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4.096
4.136
V
INTERNAL REFERENCE (Bypass REFCAP with 0.1µF to AGND1 and REF with 1.0µF to AGND1)
Reference Output Voltage
VREF
Reference Temperature
Coefficient
TCREF
Reference Short-Circuit Current
IREFSC
Reference Load Regulation
4.056
±30
REF shorted to AGND1
10
REF shorted to AVDD
-1
IREF = 0 to 0.5mA
0.1
ppm/°C
mA
10
mV
EXTERNAL REFERENCE (REFCAP = AVDD)
Reference Input Voltage Range
REFCAP Buffer Disable
Threshold
Reference Input Current
Reference Input Resistance
VREF
3.800
4.136
V
VRCTH
VAVDD1
- 0.4
VAVDD1
- 0.1
V
IREF
RREF
(Note 5)
VREF = +4.096V, external clock mode,
external acquisition mode, internal clock
mode, or partial power-down mode
90
200
VREF = +4.096V, full power-down mode
±0.1
±10
External clock mode, external acquisition
mode, internal clock mode, or partial
power-down mode
20
Full power-down mode
µA
45
kΩ
40
MΩ
DIGITAL INPUTS (DIN, SCLK, CS)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
0.7 x
VDVDDO
VHYST
Input Leakage Current
IIN
Input Capacitance
CIN
V
0.3 x
VDVDDO
V
+10
µA
0.2
VIN = 0V to VDVDDO
-10
V
10
pF
DIGITAL OUTPUTS (DOUT, SSTRB)
VDVDDO = 4.75V, ISINK = 10mA
0.4
VDVDDO = 2.7V, ISINK = 5mA
0.4
Output Low Voltage
VOL
Output High Voltage
VOH
ISOURCE = 0.5mA
DOUT Three-State Leakage
IDDO
CS = DVDDO
VDVDDO
- 0.4
-10
V
V
+10
µA
POWER REQUIREMENTS (AVDD1 and AGND1, AVDD2 and AGND2, DVDD and DGND, DVDDO and DGNDO)
Analog Supply Voltage
VAVDD1
4.75
5.25
V
Digital Supply Voltage
VDVDD
4.75
5.25
V
4
_______________________________________________________________________________________
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Preamplifier Supply Voltage
VAVDD2
4.75
5.25
V
Digital I/O Supply Voltage
VDVDDO
2.70
5.25
V
AVDD1 Supply Current
IAVDD1
External clock mode, Internal reference
external acquisition
mode, or internal
External reference
clock mode
3
3.5
mA
2.5
3
DVDD Supply Current
IDVDD
External clock mode, external acquisition
mode, or internal clock mode
0.9
2
mA
AVDD2 Supply Current
IAVDD2
External clock mode, external acquisition
mode, or internal clock mode
12
20
mA
DVDDO Supply Current
IDVDDO
External clock mode, external acquisition
mode, or internal clock mode
0.2
1
mA
Partial power-down mode
1.3
Total Supply Current
Power-Supply Rejection Ratio
PSRR
mA
Full power-down mode
2
µA
All analog input ranges
±0.5
LSB
TIMING CHARACTERISTICS (Figures 15 and 16)
SCLK Period
tCP
SCLK High Pulse Width (Note 6)
tCH
External clock mode
0.272
62
External acquisition mode
0.228
62
Internal clock mode
0.1
External clock mode
109
External acquisition mode
92
Internal clock mode
40
External clock mode
109
External acquisition mode
92
µs
ns
ns
SCLK Low Pulse Width (Note 6)
tCL
DIN to SCLK Setup
tDS
40
DIN to SCLK Hold
tDH
0
SCLK Fall to DOUT Valid
tDO
40
ns
CS Fall to DOUT Enable
tDV
40
ns
Internal clock mode
40
ns
ns
_______________________________________________________________________________________
5
MAX1302
ELECTRICAL CHARACTERISTICS (continued)
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CS Rise to DOUT Disable
CONDITIONS
MIN
TYP
MAX
UNITS
40
ns
tTR
CS Fall to SCLK Rise Setup
CS High Minimum Pulse Width
SCLK Fall to CS Rise Hold
tCSS
40
ns
tCSPW
40
ns
tCSH
0
ns
40
ns
SSTRB Rise to CS Fall Setup
(Note 4)
DOUT Rise/Fall Time
CL = 50pF
10
ns
SSTRB Rise/Fall Time
CL = 50pF
10
ns
Parameter tested at VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V.
See definitions in the Parameter Definitions section at the end of the data sheet.
Guaranteed by correlation with single-ended measurements.
Not production tested. Guaranteed by design.
To ensure external reference operation, VREFCAP must exceed (VAVDD1 - 0.1V). To ensure internal reference operation, VREFCAP
must be below (VAVDD1 - 0.4V). Bypassing REFCAP with a 0.1µF or larger capacitor to AGND1 sets VREFCAP ≈ 4.096V. The transition point between internal reference mode and external reference mode lies between the REFCAP buffer disable threshold
minimum and maximum values (Figures 17 and 18).
Note 6: The SCLK duty cycle can vary between 40% and 60%, as long as the tCL and tCH timing requirements are met.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Typical Operating Characteristics
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.)
2.55
EXTERNAL CLOCK MODE
23
22
TA = +85°C
IAVDD2 (mA)
TA = +25°C
2.45
2.40
EXTERNAL CLOCK MODE
0.85
TA = +85°C
21
2.50
0.90
IDVDD (mA)
EXTERNAL CLOCK MODE
MAX1302 toc02
24
MAX1302 toc01
2.60
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
PREAMPLIFIER SUPPLY CURRENT
vs. PREAMPLIFIER SUPPLY VOLTAGE
20
19
TA = +25°C
TA = +85°C
0.80
TA = +25°C
0.75
TA = -40°C
18
TA = -40°C
MAX1302 toc03
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
IAVDD1 (mA)
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
17
TA = -40°C
2.35
0.70
16
4.75
4.85
4.95
5.05
VAVDD1 (V)
6
0.65
15
2.30
5.15
5.25
4.75
4.85
4.95
5.05
VAVDD2 (V)
5.15
5.25
4.75
4.85
4.95
5.05
VDVDD (V)
_______________________________________________________________________________________
5.15
5.25
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
DIGITAL I/O SUPPLY CURRENT
vs. DIGITAL I/O SUPPLY VOLTAGE
0.26
0.53
TA = +85°C
TA = +85°C
0.20
PARTIAL POWER-DOWN MODE
IAVDD1 (mA)
IDVDDO (mA)
0.24
MAX1302 toc05
EXTERNAL CLOCK MODE
0.22
0.55
MAX1302 toc04
0.28
TA = +25°C
0.18
0.16
0.51
TA = +25°C
0.49
TA = -40°C
TA = -40°C
0.14
0.47
0.12
0.10
0.45
4.75
4.85
4.95
5.05
5.15
4.75
4.85
4.95
5.05
5.15
VDVDDO (V)
VAVDD1 (V)
PREAMPLIFIER SUPPLY CURRENT
vs. PREAMPLIFIER SUPPLY VOLTAGE
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
TA = +85°C
0.18
0.136
PARTIAL POWER-DOWN MODE
0.134
TA = +85°C
IDVDD (mA)
0.132
0.16
TA = +25°C
0.14
5.25
MAX1302 toc07
PARTIAL POWER-DOWN MODE
MAX1302 toc06
0.20
IAVDD2 (mA)
5.25
0.130
0.128
0.126
TA = -40°C
TA = -40°C
0.124
0.12
TA = +25°C
0.122
0.120
0.10
4.75
4.85
4.95
5.05
VAVDD2 (V)
5.15
5.25
4.75
4.85
4.95
5.05
5.15
5.25
VDVDD (V)
_______________________________________________________________________________________
7
MAX1302
Typical Operating Characteristics (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.)
PREAMPLIFIER SUPPLY CURRENT
vs. CONVERSION RATE
ANALOG SUPPLY CURRENT
vs. CONVERSION RATE
MAX1302 toc09
EXTERNAL CLOCK MODE
2.5
25
MAX1302 toc08
3.0
fCLK = 7.5MHz (NOTE 6)
20
EXTERNAL CLOCK MODE
15
FULL POWER-DOWN MODE,
PARTIAL POWER-DOWN MODE
IAVDD2 (mA)
PARTIAL
POWER-DOWN MODE
1.5
1.0
FULL
POWER-DOWN MODE
0.5
10
5
0
0
0
50
100
150
200
50
100
150
CONVERSION RATE (ksps)
DIGITAL SUPPLY CURRENT
vs. CONVERSION RATE
DIGITAL I/O SUPPLY CURRENT
vs. CONVERSION RATE
fCLK = 7.5MHz (NOTE 6)
1.4
200
0.6
MAX1302 toc10
1.8
1.6
0
CONVERSION RATE (ksps)
MAX1302 toc11
IAVDD1 (mA)
2.0
fCLK = 7.5MHz (NOTE 6)
0.5
EXTERNAL CLOCK MODE
IDVDDO (mA)
EXTERNAL CLOCK MODE,
PARTIAL POWER-DOWN MODE
1.2
IDVDD (mA)
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
1.0
0.8
0.6
0.4
0.3
0.2
0.4
FULL POWER-DOWN MODE
0.1
0.2
0
0
0
50
100
150
CONVERSION RATE (ksps)
Note 6:
8
FULL POWER-DOWN MODE,
PARTIAL POWER-DOWN MODE
200
0
50
100
150
200
CONVERSION RATE (ksps)
For partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples.
Partial power-down or full power-down modes were entered thereafter. By using this method, the conversion rate was found
by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down
or full power-down modes.
_______________________________________________________________________________________
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
EXTERNAL REFERENCE INPUT CURRENT
vs. EXTERNAL REFERENCE INPUT VOLTAGE
+VREF/2 BIPOLAR
0.02
0
-0.02
-0.04
0.13
0.6
±VREF/4 BIPOLAR
3.85
3.90
3.95
4.00
4.05
4.10
-0.4
-0.08
-0.8
±VREF BIPOLAR
-1.0
-40
4.15
-15
10
35
60
-40
85
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL ISOLATION
vs. INPUT FREQUENCY
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
fSAMPLE = 115ksps
±VREF BIPOLAR RANGE
-10
-20
85
2.0
MAX1302 toc17
0
MAX1302 toc15
fSAMPLE = 115ksps
±VREF BIPOLAR RANGE
CH0 TO CH2
fSAMPLE = 115ksps
±VREF BIPOLAR RANGE
1.5
1.0
-30
-60
-40
INL (LSB)
CMRR (dB)
-40
-80
-50
-60
0.5
0
-0.5
-70
-1.0
-80
-100
-1.5
-90
-120
-2.0
-100
10
100
1000
10
1
100
1000
0
10,000
16,384
32,768
49,152
FREQUENCY (kHz)
FREQUENCY (kHz)
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
FFT AT 5kHz
SNR, SINAD, ENOB
vs. ANALOG INPUT FREQUENCY
0
MAX1302 toc18
2.0
fSAMPLE = 115ksps
±VREF BIPOLAR RANGE
1.5
10,000
fSAMPLE = 115ksps
fIN(SINE WAVE) = 5kHz
±VREF BIPOLAR RANGE
-20
1.0
90
80
0
-0.5
SNR, SINAD (dB)
MAGNITUDE (dB)
-40
0.5
-60
-80
-1.0
70
SNR
60
SINAD
50
40
ENOB
30
-100
65,535
MAX1302 toc20
100
MAX1302 toc19
1
DNL (LSB)
0
-0.2
EXTERNAL REFERENCE VOLTAGE (V)
0
-20
0.2
-0.6
MAX1302 toc16
3.80
+VREF/4 BIPOLAR RANGE
0.4
-0.06
-0.10
0.12
ISOLATION (dB)
0.04
0.8
OFFSET ERROR (mV)
GAIN DRIFT (%)
0.15
0.14
±VREF BIPOLAR RANGE
0.06
1.0
MAX1302 toc14
0.08
MAX1302 toc13
ALL MODES
EXTERNAL REFERENCE CURRENT (mA)
0.10
MAX1302 toc12
0.16
OFFSET DRIFT
vs. TEMPERATURE
GAIN DRIFT
vs. TEMPERATURE
20
-120
-1.5
-140
-2.0
0
16,384
32,768
49,152
DIGITAL OUTPUT CODE
65,535
fSAMPLE = 115ksps
±VREF BIPOLAR RANGE
10
0
0
10
20
30
TEMPERATURE (°C)
40
50
1
10
100
1000
FREQUENCY (kHz)
_______________________________________________________________________________________
9
MAX1302
Typical Operating Characteristics (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.)
-SFDR, THD
vs. SAMPLE RATE
SNR, SINAD, ENOB
vs. SAMPLE RATE
SNR, SINAD (dB)
ENOB
12
40
10
20
-20
14
60
8
Q VREF BIPOLAR RANGE
MAX1302 toc22
80
0
16
-40
-SFDR, THD (dB)
SNR, SINAD
ENOB (bits)
MAX1302 toc21
100
-60
-80
THD
-100
-SFDR
INPUT FREQUENCY = 5kHz
0
-120
6
1
10
100
1000
0.1
1
10
1000
100
SAMPLE RATE (ksps)
SAMPLE RATE (ksps)
-SFDR, THD
vs. ANALOG INPUT FREQUENCY
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
SAMPLE RATE = 115ksps
-20
1.5
-40
-60
-80
THD
-100
SFDR
MAX1302 toc24
Q VREF BIPOLAR RANGE
ANALOG INPUT CURRENT (mA)
0
MAX1302 toc23
0.1
-SFDR, THD (dB)
1.0
0.5
0
-0.5
-1.0
-120
-1.5
1
10
1000
100
-6
-4
FREQUENCY (kHz)
-2
0
2
4
ANALOG INPUT VOLTAGE (V)
SMALL-SIGNAL BANDWIDTH
MAX1302 toc25
0
-5
ATTENUATION (dB)
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
-10
-15
-20
-25
-30
1
10
100
1000
10,000
FREQUENCY (kHz)
10
______________________________________________________________________________________
6
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
-10
-20
-30
-40
65,534 SAMPLES
30,000
NUMBER OF HITS
ATTENUATION (dB)
35,000
MAX1302 toc26
0
MAX1302 toc27
NOISE HISTOGRAM
(CODE EDGE)
FULL-POWER BANDWIDTH
25,000
20,000
15,000
10,000
-50
5000
-60
0
10
1
1000
10,000
32,769 32,770 32,771 32,772 32,773 32,774
FREQUENCY (kHz)
CODE
NOISE HISTOGRAM
(CODE CENTER)
REFERENCE VOLTAGE vs. TIME
MAX1302 toc29
MAX11302 toc28
40,000
100
65,534 SAMPLES
35,000
NUMBER OF HITS
30,000
25,000
1V/div
20,000
15,000
10,000
0V
5000
0
32,767
32,768
32,769
32,770
CODE
32,771
32,772
32,773
4ms/div
______________________________________________________________________________________
11
MAX1302
Typical Operating Characteristics (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.)
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
MAX1302
Pin Description
12
PIN
NAME
FUNCTION
1
AVDD1
Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD1
to AGND1 with a 0.1µF capacitor.
2
CH0
Analog Input Channel 0
3
CH1
Analog Input Channel 1
4
CH2
Analog Input Channel 2
5
CH3
Analog Input Channel 3
6
CH4
Analog Input Channel 4
7
CH5
Analog Input Channel 5
8
CH6
Analog Input Channel 6
9
CH7
Analog Input Channel 7
10
CS
Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the rising
edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK. When CS is high,
activity on SCLK and DIN is ignored and DOUT is high impedance.
11
DIN
Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is high,
transitions on DIN are ignored.
12
SSTRB
Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that data is
ready to be read from the device. When operating in external clock mode, SSTRB is always low. SSTRB
does not tri-state, regardless of the state of CS, and therefore requires
a dedicated I/O line.
13
SCLK
Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT. When CS
is high, transitions on SCLK are ignored.
14
DOUT
Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK transition.
When CS is high, DOUT is high impedance.
15
DGNDO
16
DGND
17
DVDDO
18
DVDD
19
REFCAP
20
REF
Digital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
Digital I/O Supply Voltage Input. Connect DVDDO to a +2.7V to +5.25V power-supply voltage. Bypass
DVDDO to DGNDO with a 0.1µF capacitor.
Digital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage. Bypass
DVDD to DGND with a 0.1µF capacitor.
Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD. For
internal reference operation, bypass REFCAP with a 0.01µF capacitor to AGND1 (VREFCAP ≈ 4.096V).
Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an external
reference voltage from 3.800V to 4.136V to REF. For internal reference operation, bypassing REF with a
1µF capacitor to AGND1 sets VREF = 4.096V ±1%.
______________________________________________________________________________________
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
PIN
NAME
FUNCTION
21
AGND3
Analog Signal Ground 3. AGND3 is the ADC negative reference potential. Connect AGND3 to AGND1.
DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
22
AVDD2
Analog Supply Voltage 2. Connect AVDD2 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD2
to AGND2 with a 0.1µF capacitor.
23
AGND2
Analog Ground 2. This ground carries approximately five times more current than AGND1. DGND,
DGNDO, AGND3, AGND2, and AGND1 must be connected together.
24
AGND1
Analog Ground 1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
5.0V
0.1µF
5.0V
5.0V
0.1µF
AVDD2
0.1µF
AVDD1
DVDD
CHO
4–20mA
CH1
PLC
CH2
ACCELERATION
CH3
PRESSURE
CH4
TEMPERATURE
CH5
WHEATESTONE
CH6
WHEATESTONE
DVDD0
SCLK
MAX1302
MC68HCXX
µC
SCK
CS
I/O
CH7
DIN
MOSI
REF
SSTRB
DOUT
AGND2 AGND3
I/O
MISO
VSS
REFCAP
0.1µF
VDD
0.1µF
AGND1
1µF
3.3V
DGND
DGNDO
Figure 1. Typical Application Circuit
Detailed Description
The MAX1302 multirange, low-power, 16-bit successiveapproximation ADC operates from a single +5V supply
and has a separate digital supply allowing digital interface with 2.7V to 5.25V systems. This 16-bit ADC has
internal track-and-hold (T/H) circuitry that supports singleended and fully differential inputs. For single-ended conversions, the valid analog input voltage range spans from
-VREF below ground to +VREF above ground. The maximum allowable differential input voltage spans from -2 x
VREF to +2 x VREF. Data can be converted in a variety of
software-programmable channel and data-acquisition
configurations. Microprocessor (µP) control is made easy
through an SPI-/QSPI-/MICROWIRE-compatible serial
interface.
The MAX1302 has eight single-ended analog input
channels or four differential channels (see the Block
Diagram). Each analog input channel is independently
software programmable for seven single-ended input
ranges (0V to +VREF/2, -VREF/2 to 0V, 0V to +VREF, -VREF
to 0V, ±VREF/4, ±VREF/2, and ±VREF) and three differential
input ranges (±V REF /2, ±V REF , and ±2 x V REF ).
Additionally, all analog input channels are fault tolerant to
±6V. A fault condition on an idle channel does not affect
the conversion result of other channels.
______________________________________________________________________________________
13
MAX1302
Pin Description (continued)
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
Power Supplies
Track-and-Hold Circuitry
To maintain a low-noise environment, the MAX1302
provides separate power supplies for each section of
circuitry. Table 1 shows the four separate power supplies. Achieve optimal performance using separate
AVDD1, AVDD2, DVDD, and DVDDO supplies.
Alternatively, connect AVDD1, AVDD2, and DVDD
together as close to the device as possible for a convenient power connection. Connect AGND1, AGND2,
AGND3, DGND, and DGNDO together as close as possible to the device. Bypass each supply to the corresponding ground using a 0.1µF capacitor (Table 1). If
significant low-frequency noise is present, add a 10µF
capacitor in parallel with the 0.1µF bypass capacitor.
The MAX1302 features a switched-capacitor T/H architecture that allows the analog input signal to be stored as
charge on sampling capacitors. See Figures 2, 3, and 4
for T/H timing and the sampling instants for each operating mode. The MAX1302 analog input circuitry buffers
the input signal from the sampling capacitors, resulting
in a constant analog input impedance with varying input
voltage (Figure 5).
Converter Operation
Figure 6 shows the simplified analog input circuit. The
analog inputs are ±6V fault tolerant and are protected
by back-to-back diodes. The summing junction voltage,
VSJ, is a function of the channel’s input common-mode
voltage:
Analog Input Circuitry
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2).
The analog input signal source must be capable of driving the ADC’s 6kΩ input resistance (Figure 6).
The MAX1302 ADC features a fully differential, successive-approximation register (SAR) conversion technique and an on-chip T/H block to convert voltage
signals into a 16-bit digital result. Both single-ended
and differential configurations are supported with programmable unipolar and bipolar signal ranges.
⎛
R1 ⎞
R1 ⎞ ⎞
⎛
⎛
VSJ = ⎜
⎟ × 2.375V + ⎜1 + ⎜
⎟ × VCM
⎝ R1 + R2 ⎠
⎝
R1 + R2 ⎠ ⎟⎠
⎝
Table 1. MAX1302 Power Supplies and Bypassing
POWER
SUPPLY/GROUND
SUPPLY VOLTAGE
RANGE (V)
TYPICAL SUPPLY
CURRENT (mA)
DVDDO/DGNDO
2.7 to 5.25
0.2
AVDD2/AGND2
4.75 to 5.25
17.5
Analog Circuitry
0.1µF to AGND2
AVDD1/AGND1
4.75 to 5.25
3.0
Analog Circuitry
0.1µF to AGND1
DVDD/DGND
4.75 to 5.25
0.9
Digital Control Logic and
Memory
0.1µF to DGND
CIRCUIT SECTION
Digital I/O
BYPASSING
0.1µF to DGNDO
Table 2. Analog Input Configuration Byte
BIT
NUMBER
7
START
6
C2
5
C1
4
C0
14
NAME
3
DIF/SGL
2
R2
1
R1
0
R0
DESCRIPTION
Start Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte.
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).
Differential or Single-Ended Configuration Bit. DIF/SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/SGL = 1 configures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.
______________________________________________________________________________________
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
MAX1302
CS
32
31
30
BYTE 3
29
28
27
26
25
24
23
22
BYTE 2
21
20
19
18
17
16
15
14
13
BYTE 1
12
11
9
10
8
7
6
5
4
3
2
1
SCLK
BYTE 4
SSTRB
DIN
S
C2
C1
C0
0
0
0
0
fSAMPLE ≈ fSCLK / 32
SAMPLING INSTANT
tACQ
ANALOG INPUT
TRACK AND HOLD*
DOUT
HOLD
TRACK
HIGH
IMPEDANCE
HOLD
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
HIGH
IMPEDANCE
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
Figure 2. External Clock-Mode Conversion (Mode 0)
As a result, the analog input impedance is relatively
constant over the input voltage as shown in Figure 5.
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When configuring differential channels, the differential pair follows
the analog configuration byte for the positive channel.
For example, to configure CH2 and CH3 for a ±VREF differential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±VREF range
(1010 1100). To initiate a conversion for the CH2 and
CH3 differential pair, issue the command 1010 0000.
Analog Input Bandwidth
The MAX1302 input-tracking circuitry has a 1.5MHz
small-signal bandwidth. The 1.5MHz input bandwidth
makes it possible to digitize high-speed transient events.
Harmonic distortion increases when digitizing signal frequencies above 15kHz as shown in the -SFDR, THD vs.
Analog Input Frequency plot in the Typical Operating
Characteristics.
Analog Input Range and Fault Tolerance
Figure 7 illustrates the software-selectable singleended analog input voltage range that produces a valid
digital output. Each analog input channel can be independently programmed to one of seven single-ended
input ranges by setting the R[2:0] control bits with
DIF/SGL = 0.
______________________________________________________________________________________
15
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
CS
SSTRB
32
31
30
BYTE 3
29
28
27
26
25
24
23
0
22
BYTE 2
21
20
19
0
18
0
17
C0
16
C1
15
C2
14
S
13
DIN
12
BYTE 1
11
9
10
8
7
6
5
4
3
2
1
SCLK
BYTE 4
0
DOUT
HIGH IMPEDANCE
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
fSAMPLE ≈ fSCLK / 32 + fINTCLK / 17
SAMPLING INSTANT
tACQ
ANALOG INPUT
TRACK AND HOLD*
HOLD
TRACK
HOLD
100ns to 400ns
17
16
15
14
3
2
1
INTCLK**
fINTCLK ≈ 4.5MHz
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
Figure 3. External Acquisition-Mode Conversion (Mode 1)
Figure 8 illustrates the software-selectable differential
analog input voltage range that produces a valid digital
output. Each analog input differential pair can be independently programmed to one of three differential input
ranges by setting the R[2:0] control bits with DIF/SGL = 1.
Regardless of the specified input voltage range and
whether the channel is selected, each analog input is
±6V fault tolerant. The analog input fault protection is
active whether the device is unpowered or powered.
16
Any voltage beyond FSR, but within the ±6V fault-tolerant range, applied to an analog input results in a fullscale output voltage for that channel.
Clamping diodes with breakdown thresholds in excess
of 6V protect the MAX1302 analog inputs during ESD
and other transient events (Figure 6). The clamping
diodes do not conduct during normal device operation,
nor do they limit the current during such transients.
When operating in an environment with the potential for
high-energy voltage and/or current transients, protect
the MAX1302 externally.
______________________________________________________________________________________
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
MAX1302
CS
SSTRB
24
23
0
22
BYTE 2
21
0
20
0
19
C0
18
C1
17
C2
16
S
15
DIN
14
BYTE 1
13
12
11
9
10
8
7
6
5
4
3
2
1
SCLK
BYTE 3
0
DOUT
B15
HIGH IMPEDANCE
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
fSAMPLE ≈ fSCLK / 24 + fINTCLK / 28
SAMPLING INSTANT
tACQ
ANALOG INPUT
TRACK AND HOLD*
TRACK
HOLD
HOLD
100ns to 400ns
28
27
26
25
14
13
12
11
10
3
2
1
INTCLK**
fINTCLK ≈ 4.5MHz
*TRACK AND HOLD TIMING IS CONTROLLED BY INTCLK, AND IS NOT ACCESSIBLE TO THE USER.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
Figure 4. Internal Clock-Mode Conversion (Mode 2)
R2
MAX1302
ANALOG INPUT CURRENT (mA)
1.5
*RSOURCE
1.0
IN_+
ANALOG
SIGNAL
SOURCE
0.5
R1
VSJ
R2
0
-0.5
*RSOURCE
-1.0
ANALOG
SIGNAL
SOURCE
-1.5
-6
-4
-2
0
2
4
IN_+
R1
VSJ
6
ANALOG INPUT VOLTAGE (V)
*MINIMIZE RSOURCE TO AVOID GAIN ERROR AND DISTORTION.
Figure 5. Analog Input Current vs. Input Voltage
Figure 6. Simplified Analog Input Circuit
______________________________________________________________________________________
17
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
Table 3. Input Data Word Formats
DATA BIT
OPERATION
D7
(START)
D6
D5
D4
D3
D2
D1
D0
Conversion-Start Byte
(Tables 4 and 5)
1
C2
C1
C0
0
0
0
0
Analog-Input Configuration Byte
(Table 2)
1
C2
C1
C0
DIF/SGL
R2
R1
R0
Mode-Control Byte
(Table 7)
1
M2
M1
M0
1
0
0
0
CH6
CH7
Table 4. Channel Selection in Single-Ended Mode (DIF/SGL = 0)
CHANNEL-SELECT BIT
CHANNEL
C2
C1
C0
CH0
0
0
0
+
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CH1
CH2
CH3
CH4
CH5
AGND1
-
+
+
+
+
+
+
+
-
CH6
CH7
AGND1
+
-
Table 5. Channel Selection in True-Differential Mode (DIF/SGL = 1)
CHANNEL-SELECT BIT
CHANNEL
C2
C1
C0
CH0
CH1
CH2
CH3
+
-
0
0
0
+
-
0
0
1
0
1
0
0
1
1
1
0
0
+
1
0
1
RESERVED
1
1
0
1
1
1
RESERVED
-
RESERVED
Differential Common-Mode Range
(CH _ +) + (CH _ −)
2
In addition to the common-mode input voltage limita18
CH5
RESERVED
The MAX1302 differential common-mode range
(VCMDR) must remain within -4.75V to +5.5V to obtain
valid conversion results. The differential common-mode
range is defined as:
VCMDR =
CH4
tions, each individual analog input must be limited to
±6V with respect to AGND1.
The range-select bits R[2:0] in the analog input configuration bytes determine the full-scale range for the corresponding channel (Tables 2 and 6). Figures 9, 10,
and 11 show the valid analog input voltage ranges for
the MAX1302 when operating with FSR = VREF/2, FSR
= VREF, and FSR = 2 x VREF, respectively. The shaded
area contains the valid common-mode voltage ranges
that support the entire FSR.
______________________________________________________________________________________
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
+3/4 VREF
+3/2 VREF
FSR = VREF
+2 x VREF
INPUT RANGE SELECTION BITS, R[2:0]
EACH INPUT IS FAULT TOLERANT TO ±6V.
Figure 7. Single-Ended Input Voltage Ranges
Digital Interface
The MAX1302 features a serial interface that is compatible with SPI/QSPI and MICROWIRE devices. DIN,
DOUT, SCLK, CS, and SSTRB facilitate bidirectional
communication between the MAX1302 and the master
at SCLK rates up to 10MHz (internal clock mode,
mode 2), 3.67MHz (external clock mode, mode 0), or
4.39MHz (external acquisition mode, mode 1). The
master, typically a microcontroller, should use the
CPOL = 0, CPHA = 0, SPI transfer format, as shown in
the timing diagrams of Figures 2, 3, and 4.
The digital interface is used to:
• Select single-ended or true-differential input channel
configurations
• Select the unipolar or bipolar input range
111
110
101
100
011
111
110
101
100
011
-2 x VREF
010
-VREF
010
-VREF
-3/2 VREF
001
FSR = 4 x VREF
-VREF/2
-3/4 VREF
• Select the mode of operation:
External clock (mode 0)
External acquisition (mode 1)
Internal clock (mode 2)
Reset (mode 4)
Partial power-down (mode 6)
Full power-down (mode 7)
• Initiate conversions and read results
FSR = VREF
0
FSR = 2 x VREF
+VREF/2
001
-VREF/2
(CH_+) - (CH_-) (V)
FSR = 2 x VREF
FSR = VREF / 2
+VREF
FSR = VREF
-VREF/4
FSR = VREF
0
FSR = VREF / 2
+VREF/4
FSR = VREF / 2
(CH_) - AGND1 (V)
+VREF/2
MAX1302
+VREF
INPUT RANGE SELECTION BITS, R[2:0]
EACH INPUT IS FAULT TOLERANT TO ±6V.
Figure 8. Differential Input Voltage Ranges
Chip Select (CS)
CS enables communication with the MAX1302. When CS
is low, data is clocked into the device from DIN on the rising edge of SCLK and data is clocked out of DOUT on
the falling edge of SCLK. When CS is high, activity on
SCLK and DIN is ignored and DOUT is high impedance
allowing DOUT to be shared with other peripherals.
SSTRB is never high impedance and therefore cannot be
shared with other peripherals.
Serial Strobe Output (SSTRB)
As shown in Figures 3 and 4, the SSTRB transitions high
to indicate that the ADC has completed a conversion
and results are ready to be read by the master. SSTRB
remains low in the external clock mode (Figure 2) and
consequently may be left unconnected. SSTRB is driven high or low regardless of the state of CS, therefore
SSTRB cannot be shared with other peripherals.
______________________________________________________________________________________
19
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
Table 6. Range-Select Bits
DIF/SGL
R2
R1
R0
0
0
0
0
No Range Change*
MODE
TRANSFER FUNCTION
0
0
0
1
Single-Ended
Bipolar -VREF/4 to +VREF/4
Full-Scale Range (FSR) = VREF/2
Figure 12
0
0
1
0
Single-Ended
Unipolar -VREF/2 to 0V
FSR = VREF/2
Figure 13
0
0
1
1
Single-Ended
Unipolar 0V to +VREF/2
FSR = VREF/2
Figure 14
0
1
0
0
Single-Ended
Bipolar -VREF/2 to +VREF/2
FSR = VREF
Figure 12
0
1
0
1
Single-Ended
Unipolar -VREF to 0V
FSR = VREF
Figure 13
0
1
1
0
Single-Ended
Unipolar 0V to +VREF
FSR = VREF
Figure 14
Figure 12
—
0
1
1
1
DEFAULT SETTING
Single-Ended
Bipolar -VREF to +VREF
FSR = 2 x VREF
1
0
0
0
No Range Change**
1
0
0
1
Differential
Bipolar -VREF/2 to +VREF/2
FSR = VREF
1
0
1
0
Reserved
—
1
0
1
1
Reserved
—
1
1
0
0
Differential
Bipolar -VREF to +VREF
FSR = 2 x VREF
1
1
0
1
Reserved
—
1
1
1
0
Reserved
—
1
1
1
1
Differential
Bipolar -2 x VREF to +2 x VREF
FSR = 4 x VREF
—
Figure 12
Figure 12
Figure 12
*Conversion-Start Byte (see Table 3).
**Mode-Control Byte (see Table 3).
20
______________________________________________________________________________________
6
4
4
COMMON-MODE VOLTAGE (V)
6
2
0
-2
-4
MAX1302
COMMON-MODE VOLTAGE (V)
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
2
0
-2
-4
VREF = 4.096V
VREF = 4.096V
-6
-6
-8
-6
-4
-2
0
2
4
6
8
-8
-6
-4
INPUT VOLTAGE (V)
Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = VREF)
0
2
4
6
8
Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 2 x
VREF)
Output Data Format
Output data is clocked out of DOUT in offset binary format on the falling edge of SCLK, MSB first (B15). For
output binary codes, see the Transfer Function section
and Figures 12, 13, and 14.
6
COMMON-MODE VOLTAGE (V)
-2
INPUT VOLTAGE (V)
4
2
Configuring Analog Inputs
Each analog input has two configurable parameters:
• Single-ended or true-differential input
0
-2
-4
VREF = 4.096V
-6
-8
-6
-4
-2
0
2
4
6
8
INPUT VOLTAGE (V)
Figure 11. Common-Mode Voltage vs. Input Voltage (FSR = 4 x
VREF)
Start Bit
Communication with the MAX1302 is accomplished
using the three input data word formats shown in
Table 3. Each input data word begins with a start bit.
The start bit is defined as the first high bit clocked into
DIN with CS low when any of the following are true:
• Data conversion is not in process and all data from
the previous conversion has clocked out of DOUT.
• The device is configured for operation in external
clock mode (mode 0) and previous conversion-result
bits B15–B3 have clocked out of DOUT.
• The device is configured for operation in external
acquisition mode (mode 1) and previous conversionresult bits B15–B7 have clocked out of DOUT.
• The device is configured for operation in internal
clock mode, (mode 2) and previous conversionresult bits B15–B4 have clocked out of DOUT.
• Input voltage range
These parameters are configured using the analog input
configuration byte as shown in Table 2. Each analog
input has a dedicated register to store its input configuration information. The timing diagram of Figure 15 shows
how to write to the analog input configuration registers.
Figure 16 shows DOUT and SSTRB timing.
Transfer Function
An ADC’s transfer function defines the relationship
between the analog input voltage and the digital output
code. Figures 12, 13, and 14 show the MAX1302 transfer
functions. The transfer function is determined by the following characteristics:
• Analog input voltage range
• Single-ended or differential configuration
• Reference voltage
The axes of an ADC transfer function are typically in least
significant bits (LSBs). For the MAX1302, an LSB is calculated using the following equation:
1 LSB =
FSR × VREF
2N × 4.096V
where N is the number of bits (N = 16) and FSR is the
full-scale range (see Figures 7 and 8).
______________________________________________________________________________________
21
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
FSR
FSR
FFFF
FFFE
FFFD
8001
8000
7FFF
8001
FSR
BINARY OUTPUT CODE (LSB [hex])
FFFE
FFFD
FSR
BINARY OUTPUT CODE (LSB [hex])
FFFF
8000
7FFF
0003
0003
0002
1 LSB =
0001
0002
FSR x VREF
65,536 x 4.096V
1 LSB =
0001
FSR x VREF
65,536 x 4.096V
0000
0000
-32,768 -32,766
-1 0 +1
0
+32,765 +32,767
1
2
3
32,768
65,533 65,535
INPUT VOLTAGE (LSB [DECIMAL])
(AGND1)
AGND1 (DIF/SGL = 0)
0V (DIF/SGL = 1)
Figure 13. Ideal Unipolar Transfer Function, Single-Ended
Input, -FSR to 0
INPUT VOLTAGE (LSB [DECIMAL])
Figure 12. Ideal Bipolar Transfer Function, Single-Ended or
Differential Input
FSR
FFFF
FFFE
FFFD
Selecting the Conversion Method
The conversion method is selected using the mode-control byte (see the Mode Control section), and the conversion is initiated using a conversion start command (Table
3, and Figures 2, 3, and 4). The MAX1302 converts analog signals to digital data using one of three methods:
8001
FSR
BINARY OUTPUT CODE (LSB [hex])
•
8000
7FFF
0003
0002
1 LSB =
0001
FSR x VREF
65,536 x 4.096V
•
• CS remains low during the conversion
• User supplies SCLK throughout the ADC conversion and reads data at DOUT
External Acquisition Mode, Mode 1 (Figure 3)
• Lowest maximum throughput (see the Electrical
Characteristics table)
0000
0
1
2
3
32,768
65,533 65,535
INPUT VOLTAGE (LSB [DECIMAL])
(AGND1)
Figure 14. Ideal Unipolar Transfer Function, Single-Ended
Input, 0 to +FSR
Mode Control
The MAX1302 contains one byte-wide mode-control
register. The timing diagram of Figure 15 shows how to
use the mode-control byte, and the mode-control byte
format is shown in Table 7. The mode-control byte is
used to select the conversion method and to control the
power modes of the MAX1302.
22
External Clock Mode, Mode 0 (Figure 2)
• Highest maximum throughput (see the Electrical
Characteristics table)
• User controls the sample instant
•
• User controls the sample instant
• User supplies two bytes of SCLK, then drives
CS high to relieve processor load while the
ADC converts
• After SSTRB transitions high, the user supplies
two bytes of SCLK and reads data at DOUT
Internal Clock Mode, Mode 2 (Figure 4)
• High maximum throughput (see the Electrical
Characteristics table)
• The internal clock controls the sampling instant
______________________________________________________________________________________
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
MAX1302
tCSPW
tCSS
CS
tCL
SCLK
tCH
tCSH
1
8
tCP
tDS
DIN
START
SEL2
SEL1
SEL0
1
8
tDH
DIF/SGL
R2
R1
R0
START
M2
ANALOG INPUT CONFIGURATION BYTE
tDV
DOUT
M1
M0
1
0
0
0
MODE CONTROL BYTE
tTR
HIGH
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing
SSTRB
tSSCS
CS
tCSS
SCLK
tDO
DOUT
HIGH IMPEDANCE
MSB
NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
External Clock Mode (Mode 0)
The MAX1302’s fastest maximum throughput rate is
achieved operating in external clock mode. SCLK controls both the acquisition and conversion of the analog
signal, facilitating precise control over when the analog
signal is captured. The analog input sampling instant is
at the falling edge of the 14th SCLK (Figure 2).
Since SCLK drives the conversion in external clock
mode, the SCLK frequency should remain constant
while the conversion is clocked. The minimum SCLK
frequency prevents droop in the internal sampling
capacitor voltages during conversion.
SSTRB remains low in the external clock mode, and as a
result may be left unconnected if the MAX1302 will
always be used in the external clock mode.
Figure 16. DOUT and SSTRB Timing
• User supplies one byte of SCLK, then drives CS
high to relieve processor load while the ADC
converts
• After SSTRB transitions high, the user supplies
two bytes of SCLK and reads data at DOUT
Table 7. Mode-Control Byte
BIT NUMBER
BIT NAME
7
START
DESCRIPTION
6
M2
5
M1
4
M0
3
1
Bit 3 must be a logic 1 for the mode-control byte.
2
0
Bit 2 must be a logic 0 for the mode-control byte.
1
0
Bit 1 must be a logic 0 for the mode-control byte.
0
0
Bit 0 must be a logic 0 for the mode-control byte.
Start Bit. The first logic 1 after CS goes low defines the beginning of the mode-control byte.
Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.
______________________________________________________________________________________
23
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
Table 8. Mode-Control Bits M[2:0]
M2
M1
M0
0
0
0
External Clock (DEFAULT)
MODE
0
0
1
External Acquisition
0
1
0
Internal Clock
0
1
1
Reserved
1
0
0
Reset
1
0
1
Reserved
1
1
0
Partial Power-Down
1
1
1
Full Power-Down
External Acquisition Mode (Mode 1)
The slowest maximum throughput rate is achieved with
the external acquisition method. SCLK controls the
acquisition of the analog signal in external acquisition
mode, facilitating precise control over when the analog
signal is captured. The internal clock controls the conversion of the analog input voltage. The analog input
sampling instant is at the falling edge of the 16th SCLK
(Figure 3).
For the external acquisition mode, CS must remain low
for the first 15 clock cycles and then rise on or after the
falling edge of the 16th SCLK cycle as shown in Figure
3. For optimal performance, idle DIN and SCLK during
the conversion. With careful board layout, transitions at
DIN and SCLK during the conversion have a minimal
impact on the conversion result.
After the conversion is complete, SSTRB asserts high
and CS can be brought low to read the conversion
result. SSTRB returns low on the rising SCLK edge of
the subsequent start bit.
Internal Clock Mode (Mode 2)
In internal clock mode, the internal clock controls both
acquisition and conversion of the analog signal. The internal clock starts approximately 100ns to 400ns after the
falling edge of the eighth SCLK and has a rate of about
4.5MHz. The analog input sampling instant occurs at the
falling edge of the 11th internal clock signal (Figure 4).
For the internal clock mode, CS must remain low for the
first seven SCLK cycles and then rise on or after the
falling edge of the eighth SCLK cycle. After the conversion is complete, SSTRB asserts high and CS can be
brought low to read the conversion result. SSTRB returns
low on the rising SCLK edge of the subsequent start bit.
24
Reset (Mode 4)
As shown in Table 8, set M[2:0] = 100 to reset the
MAX1302 to its default conditions. The default conditions are full power operation with each channel configured for ±V REF , bipolar, single-ended conversions
using external clock mode (mode 0).
Partial Power-Down Mode (Mode 6)
As shown in Table 8, when M[2:0] = 110, the device
enters partial power-down mode. In partial powerdown, all analog portions of the device are powered
down except for the reference voltage generator and
bias supplies.
To exit partial power-down, change the mode by issuing one of the following mode-control bytes (see the
Mode Control section):
• External-clock-mode control byte
• External-acquisition-mode control byte
• Internal-clock-mode control byte
• Reset byte
• Full power-down-mode control byte
This prevents the MAX1302 from inadvertently exiting
partial power-down mode because of a CS glitch in a
noisy digital environment.
Full Power-Down Mode (Mode 7)
When M[2:0] = 111, the device enters full power-down
mode and the total supply current falls to 1µA (typ). In
full power-down, all analog portions of the device are
powered down. When using the internal reference,
upon exiting full power-down mode, allow 10ms for the
internal reference voltage to stabilize prior to initiating a
conversion.
To exit full power-down, change the mode by issuing
one of the following mode-control bytes (see the Mode
Control section):
• External-clock-mode control byte
______________________________________________________________________________________
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
• Partial power-down-mode control byte
This prevents the MAX1302 from inadvertently exiting
full power-down mode because of a CS glitch in a noisy
digital environment.
Power-On Reset
The MAX1302 powers up in normal operation configured
for external clock mode with all circuitry active (Tables 7
and 8). Each analog input channel (CH0–CH7) is set for
single-ended conversions with a ±VREF bipolar input
range (Table 6).
Allow the power supplies to stabilize after power-up. Do
not initiate any conversions until the power supplies
have stabilized. Additionally, allow 10ms for the internal
reference to stabilize when CREF = 1.0µF and CRECAP
= 0.1µF. Larger reference capacitors require longer
stabilization times.
Internal or External Reference
The MAX1302 operates with either an internal or external
reference. The reference voltage impacts the ADC’s FSR
(Figures 12, 13, and 14). An external reference is recommended if more accuracy is required than the internal reference provides, and/or multiple converters require the
same reference voltage.
Internal Reference
The MAX1302 contains an internal 4.096V bandgap reference. This bandgap reference is connected to REFCAP
through a nominal 5kΩ resistor (Figure 17). The voltage at
REFCAP is buffered creating 4.096V at REF. When using
4.096V
SAR
ADC REF
REF
1.0µF
External Reference
For external reference operation, disable the internal
reference and reference buffer by connecting REFCAP
to AVDD1. With AVDD1 connected to REFCAP, REF
becomes a high-impedance input and accepts an
external reference voltage. The MAX1302 external reference current varies depending on the applied reference voltage and the operating mode (see the External
Reference Input Current vs. External Reference Input
Voltage in the Typical Operating Characteristics).
Applications Information
Noise Reduction
Additional samples can be taken and averaged (oversampling) to remove the effect of transition noise on
conversion results. The square root of the number of
samples determines the improvement in performance.
For example, with 2/3 LSBRMS (4 LSBP-P) transition
noise, 16 (42 = 16) samples must be taken to reduce
the noise to 1 LSBP-P.
Interface with 4–20mA Signals
Figure 19 illustrates a simple interface between the
MAX1302 and a 4–20mA signal. 4–20mA signaling can
be used as a binary switch (4mA represents a logic-low
signal, 20mA represents a logic-high signal), or for precision communication where currents between 4mA
and 20mA represent intermediate analog data. For
binary switch applications, connect the 4–20mA signal
to the MAX1302 with a resistor to ground. For example,
a 200Ω resistor converts the 4–20mA signal to a 0.8V to
4V signal. Adjust the resistor value so the parallel combination of the resistor and the MAX1302 source
impedance is 200Ω. In this application, select the single-ended 0V to VREF range (R[2:0] = 011, Table 6).
For applications that require precision measurements
of continuous analog currents between 4mA and 20mA,
use a buffer to prevent the MAX1302 input from diverting current from the 4–20mA signal.
1x
REFCAP
MAX1302
0.1µF
5kΩ
VRCTH
4.096V
BANDGAP
REFERENCE
AGND1
Figure 17. Internal Reference Operation
______________________________________________________________________________________
25
MAX1302
the internal reference, bypass REFCAP with a 0.1µF or
greater capacitor to AGND1 and bypass REF with a
1.0µF or greater capacitor to AGND1.
• External-acquisition-mode control byte
• Internal-clock-mode control byte
• Reset byte
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
V+
1.0µF
IN
4.096V
SAR
ADC REF
REF
OUT
1.0µF
MAX6341
AVDD1
1x
REFCAP
MAX1302
GND
5kΩ
VRCTH
4.096V
BANDGAP
REFERENCE
AGND1
Figure 18. External Reference Operation
Bridge Application
Layout, Grounding, and Bypassing
The MAX1302 converts 1kHz signals more accurately
than a similar sigma-delta converter that might be considered in bridge applications. The input impedance of
the MAX1302, in combination with the current-limiting
resistors, can affect the gain of the MAX1302. In many
applications this error is acceptable, but for applications that cannot tolerate this error, the MAX1302 inputs
can be buffered (Figure 20). Connect the bridge to a
low-offset differential amplifier and then the true differential inputs of the MAX1302. Larger excitation voltages
take advantage of more of the ±VREF/2 differential input
voltage range. Select an input voltage range that
matches the amplifier output. Be aware of the amplifier
offset and offset-drift errors when selecting an appropriate amplifier.
Careful PCB layout is essential for best system performance. Boards should have separate analog and digital
ground planes and ensure that digital and analog signals are separated from each other. Do not run analog
and digital (especially clock) lines parallel to one another, or digital lines underneath the device package.
Figure 1 shows the recommended system ground connections. Establish an analog ground point at AGND1
and a digital ground point at DGND. Connect all analog
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground plane to the analog ground plane at one point.
For lowest noise operation, make the ground return to
the star ground’s power-supply low impedance and as
short as possible.
Dynamically Adjusting the Input Range
High-frequency noise in the AVDD1 power supply
degrades the ADC’s high-speed comparator performance. Bypass AVDD1 to AGND1 with a 0.1µF ceramic
surface-mount capacitor. Make bypass capacitor connections as short as possible.
Software control of each channel’s analog input range
and the unipolar endpoint overlap specification make it
possible for the user to change the input range for a
channel dynamically and improve performance in some
applications. Changing the input range results in a
small LSB step-size over a wider output voltage range.
For example, by switching between a -VREF/2 to 0V
range and a 0V to VREF/2 range, an LSB is:
(VREF 2) × VREF
65, 536 × 4.096
but the input voltage range effectively spans from
-VREF/2 to +VREF/2 (FSR = +VREF).
26
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. This straight line is either a
best straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain
errors have been nullified. The MAX1302 INL is measured using the endpoint method.
______________________________________________________________________________________
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
MAX1302
4–20mA INPUT
CH0
µC
200Ω
MAX1302
4–20mA INPUT
CH8
200Ω
Figure 19. 4–20mA Application
LOW-OFFSET
DIFFERENTIAL
AMPLIFIER
CH0
µP
CH1
MAX1302
REF
BRIDGE
Figure 20. Bridge Application
Differential Nonlinearity (DNL)
Channel-to-Channel Isolation
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
greater than -1 LSB guarantees no missing codes and
a monotonic transfer function.
Channel-to-channel isolation indicates how well each
analog input is isolated from the others. The channel-tochannel isolation for these devices is measured by
applying a near full-scale magnitude 5kHz sine wave to
the selected analog input channel while applying an
equal magnitude sine wave of a different frequency to
all unselected channels. An FFT of the selected channel output is used to determine the ratio of the magnitudes of the signal applied to the unselected channels
and the 5kHz signal applied to the selected analog
input channel. This ratio is reported, in dB, as channelto-channel isolation.
Transition Noise
Transition noise is the amount of noise that appears at a
code transition on the ADC transfer function. Conversions
performed with the analog input right at the code transition can result in code flickering in the LSBs.
______________________________________________________________________________________
27
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
Unipolar Offset Error
-FSR to 0V
When a zero-scale analog input voltage is applied to
the converter inputs, the digital output is all ones
(0xFFFF). Ideally, the transition from 0xFFFF to 0xFFFE
occurs at AGND1 - 0.5 LSB. Unipolar offset error is the
amount of deviation between the measured zero-scale
transition point and the ideal zero-scale transition point,
with all untested channels grounded.
0V to +FSR
When a zero-scale analog input voltage is applied to
the converter inputs, the digital output is all zeros
(0x0000). Ideally, the transition from 0x0000 to 0x0001
occurs at AGND1 + 0.5 LSB. Unipolar offset error is the
amount of deviation between the measured zero-scale
transition point and the ideal zero-scale transition point,
with all untested channels grounded.
Bipolar Offset Error
When a zero-scale analog input voltage is applied to
the converter inputs, the digital output is a one followed
by all zeros (0x8000). Ideally, the transition from
0x7FFF to 0x8000 occurs at (2N-1 - 0.5) LSB. Bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale
transition point, with untested channels grounded.
Gain Error
When a positive full-scale voltage is applied to the converter inputs, the digital output is all ones (0xFFFF). The
transition from 0xFFFE to 0xFFFF occurs at 1.5 LSB
below full scale. Gain error is the amount of deviation
between the measured full-scale transition point and
the ideal full-scale transition point with the offset error
removed and all untested channels grounded.
Unipolar Endpoint Overlap
Unipolar endpoint overlap is the change in offset when
switching between complementary input voltage
ranges. For example, the difference between the voltage that results in a 0xFFFF output in the -VREF/2 to 0V
input voltage range and the voltage that results in a
0x0000 output in the 0V to +VREF/2 input voltage range
is the unipolar endpoint overlap. The unipolar endpoint
overlap is positive for the MAX1302, preventing loss of
signal or a dead zone when switching between adjacent analog input voltage ranges.
Small-Signal Bandwidth
A 100mVP-P sine wave is applied to the ADC, and the
input frequency is then swept up to the point where the
amplitude of the digitized conversion result has
decreased by -3dB.
28
Full-Power Bandwidth
A 95% of full-scale sine wave is applied to the ADC,
and the input frequency is then swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ability of a device to reject a signal that is
“common” to or applied to both input terminals. The
common-mode signal can be either an AC or a DC signal or a combination of the two. CMR is expressed in
decibels. Common-mode rejection ratio is the ratio of
the differential signal gain to the common-mode signal
gain. CMRR applies only to differential operation.
Power-Supply Rejection Ratio (PSRR)
PSRR is the ratio of the output-voltage shift to the
power-supply-voltage shift for a fixed input voltage. For
the MAX1302, AVDD1 can vary from 4.75V to 5.25V.
PSRR is expressed in decibels and is calculated using
the following equation:
⎛
⎞
5.25V − 4.75V
PSRR[dB] = 20 × log⎜
⎟
⎝ VOUT (5.25V) − VOUT (4.75V) ⎠
For the MAX1302, PSRR is tested in bipolar operation
with the analog inputs grounded.
Aperture Jitter
Aperture jitter, tAJ, is the statistical distribution of the
variation in the sampling instant (Figure 21).
Aperture Delay
Aperture delay, tAD, is the time from the falling edge of
SCLK to the sampling instant (Figure 21).
Signal-to-Noise Ratio (SNR)
SNR is computed by taking the ratio of the RMS signal
to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency excluding the fundamental and the
DC offset.
⎛ SignalRMS ⎞
SINAD(dB) = 20 × log⎜
⎟
⎝ NoiseRMS ⎠
______________________________________________________________________________________
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
⎛ SINAD − 1.76 ⎞
ENOB = ⎜
⎟
⎝
⎠
6.02
SCLK
(MODE 0)
13
14
SCLK
(MODE 1)
15
16
INTCLK
(MODE 2)
10
11
MAX1302
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. With an
input range equal to the ADC’s full-scale range, calculate the ENOB as follows:
15
12
Total Harmonic Distortion (THD)
For the MAX1302, THD is the ratio of the RMS sum of
the input signal’s first four harmonic components to the
fundamental itself. This is expressed as:
⎛
V2 2 + V3 2 + V4 2 + V5 2
THD = 20 × log⎜
⎜
V1
⎝
⎞
⎟
⎟
⎠
tAJ
tAD
SAMPLE INSTANT
ANALOG INPUT
TRACK AND HOLD
TRACK
HOLD
Figure 21. Aperture Diagram
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonic components.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next-largest spectral component.
______________________________________________________________________________________
29
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
MAX1302
Block Diagram
CONTROL LOGIC AND REGISTERS
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND1
DVDD0
CS
DIN
SSTRB
DOUT
SCLK
DGNDO
SERIAL I/O
AVDD2
CLOCK
ANALOG
INPUT MUX
AND
MULTIRANGE
CIRCUITRY
PGA
IN
SAR
ADC
DVDD
FIFO
OUT
DGND
AVDD1
AGND3
REF
AGND2
4.096V
BANDGAP
REFERENCE
5kΩ
1x
AVDD2
AGND2
MAX1302
REFCAP
REF
Package Information
Chip Information
PROCESS: BiCMOS
30
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
24 TSSOP
U24+1
21-0066
90-0118
______________________________________________________________________________________
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
REVISION
NUMBER
REVISION
DATE
0
3/12
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
31 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX1302
Revision History