ZILOG ZLP12840H2064G

Crimzon™ Infrared Microcontrollers
ZLP12840 OTP MCU
with Learning Amplification
Product Specification
PS024406-0106
PRELIMINARY
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or
to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126-3432
Telephone: 408.558.8500
Fax: 408.558.8300
www.zilog.com
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service
names mentioned herein may be trademarks of the companies with which they are associated.
Document Disclaimer
©2006 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology
described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR
PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
IN TH IS DOCUM EN T. Zi LO G A LSO DO ES NO T ASSU ME LI ABILITY FO R I NTELLECTU AL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing
in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose.
Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life
support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual
property rights.
PS024406-0106
P R E L I M I N A R Y
ZLP12840 OTP MCU
Product Specification
iii
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I/O Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparator Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Configuration Register (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 0 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 3 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
12
13
14
19
19
20
21
22
23
24
25
26
Memory and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OTP Program/Constant Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Pointer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linear Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory Paging Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
29
30
33
33
36
37
38
38
Register File Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Infrared Learning Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PS024406-0106
P R E L I M I N A R Y
Table of Contents
ZLP12840 OTP MCU
Product Specification
iv
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitting Data Using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitting Data Using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . .
Receiving Data Using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiving Data Using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . . .
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Receive Data Register/UART Transmit Data Register . . . . . . . . . . . . . . . . . . . .
UART Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Generator Constant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
44
44
45
46
47
47
48
50
52
53
54
55
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T8 Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T8 Demodulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T16 Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T16 Demodulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ping-Pong Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 8 Capture High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 8 Capture Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 16 Capture High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 16 Capture Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer 16 High Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer 16 Low Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer 8 High Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer 8 Low Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer 8 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T8 and T16 Common Functions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 16 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 8/Timer 16 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
58
58
59
62
66
67
68
69
70
71
71
72
72
73
73
74
74
75
77
80
81
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Priority Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
87
88
90
PS024406-0106
P R E L I M I N A R Y
Table of Contents
ZLP12840 OTP MCU
Product Specification
v
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal 1 Oscillator Pin (XTAL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal 2 Oscillator Pin (XTAL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Clock Signals (SCLK and TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
91
92
92
92
Resets and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Power-On Reset Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Reset/Stop-Mode Recovery Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Voltage Brown-Out/Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Fast Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Stop Mode Recovery Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Stop Mode Recovery Event Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SMR Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SMR1 Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SMR2 Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
SMR3 Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Stop-Mode Recovery Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Z8 LXM CPU Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z8 LXM CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
112
112
115
116
117
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
124
124
125
125
126
128
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
PS024406-0106
P R E L I M I N A R Y
Table of Contents
ZLP12840 OTP MCU
Product Specification
vi
Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
PS024406-0106
P R E L I M I N A R Y
Table of Contents
ZLP12840 OTP MCU
Product Specification
vii
List of Figures
Figure 1. ZLP12840 MCU Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. ZLP12840 MCU 20-Pin PDIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . 5
Figure 3. ZLP12840 MCU 28-Pin PDIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . 8
Figure 4. Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Program/Constant Memory Map (128KB Device) . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. Register File 8-Bit Banked Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Register Pointer—Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. Register File LDX, LDXI Linear 12-Bit Address Map . . . . . . . . . . . . . . . . . 35
Figure 12. Learning Amplification Circuitry with the ZLP12840 MCU . . . . . . . . . . . . 42
Figure 13. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 14. UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . . . . . . 45
Figure 15. UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 16. UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17. Counter/Timers Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 18. Counter/Timer Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 19. Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 20. 8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 21. T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 22. T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 23. Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 24. Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 25. Demodulation Mode Flowchart with Bit 4 of CTR3 Set . . . . . . . . . . . . . . . . 65
Figure 26. 16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 27. T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 28. T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PS024406-0106
P R E L I M I N A R Y
List of Figures
ZLP12840 OTP MCU
Product Specification
viii
Figure 29. Ping-Pong Mode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 30. Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 31. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 32. Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 33. SCLK/TCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 34. Resets and Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 35. SMR Register-Controlled Event Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 36. SMR1 Register-Controlled Event Sources . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 37. SMR2 Register-Controlled Event Sources . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 38. SMR3 Register-Controlled Event Sources . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 39. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 40. AC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 41. 28-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 42. 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 43. 28-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 44. 20-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 45. 20-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 46. 20-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 47. Part Number Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 48. Document Number Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
PS024406-0106
P R E L I M I N A R Y
List of Figures
ZLP12840 OTP MCU
Product Specification
ix
List of Tables
Table 1. ZLP12840 OTP MCU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Power Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 3. ZLP12840 MCU 20-Pin PDIP/SOIC/SSOP Sequential Pin Identification . . . . . 5
Table 4. ZLP12840 MCU 20-Pin PDIP/SOIC/SSOP Functional Pin Identification . . . . . 7
Table 5. ZLP12840 MCU 28-Pin PDIP/SOIC/SSOP Sequential Pin Identification . . . . . 9
Table 6. ZLP12840 MCU 28-Pin PDIP/SOIC/SSOP Functional Pin Identification . . . . 10
Table 7. I/O Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. Summary of Port 3 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Port Configuration Register (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Port 0 Mode Register (P01M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Port 0 Register (P0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Port 2 Mode Register (P2M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Port 2 Register (P2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. Port 3 Mode Register (P3M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Port 3 Register (P3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Program Memory Paging Register (PMPR). . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. Register Pointer Register (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 18. User Data Register (USER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 19. Stack Pointer Register (SPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 20. Register File Address Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 21. UART Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 22. BCNST Register Settings Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 23. UART Receive/Transmit Data Register (URDATA/UTDATA). . . . . . . . . . . 52
Table 24. UART Status Register (UST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 25. UART Control Register (UCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 26. Baud Rate Generator Constant Register (BCNST) . . . . . . . . . . . . . . . . . . . . . 55
Table 27. Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 28. Timer 8 Capture High Register (HI8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
PS024406-0106
P R E L I M I N A R Y
List of Tables
ZLP12840 OTP MCU
Product Specification
x
Table 29. Timer 8 Capture Low Register (L08). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 30. Timer 16 Capture High Register (HI16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 31. Timer 16 Capture Low Register (L016). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 32. Counter/Timer 16 High Hold Register (TC16H) . . . . . . . . . . . . . . . . . . . . . . . 73
Table 33. Counter/Timer 16 Low Hold Register (TC16L) . . . . . . . . . . . . . . . . . . . . . . . 73
Table 34. Counter/Timer 8 High Hold Register (TC8H) . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 35. Counter/Timer 8 Low Hold Register (TC8L) . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 36. Counter/Timer 8 Control Register (CTR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 37. Timer 8 and Timer 16 Common Functions Register (CTR1) . . . . . . . . . . . . . 77
Table 38. Counter/Timer 16 Control Register (CTR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 39. Timer 8/Timer 16 Control Register (CTR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 40. Interrupt Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 41. Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 42. Interrupt Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 43. Interrupt Priority Register (IPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 44. Interrupt Request Register (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 45. Interrupt Mask Register (IMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 46. Reset and Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 47. Low-Voltage Detection Register (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 48. Stop-Mode Recovery Register (SMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 49. Stop-Mode Recovery Register 1 (SMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 50. Stop-Mode Recovery Register 2 (SMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 51. Stop-Mode Recovery Register 3 (SMR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 52. Stop-Mode Recovery Register 4 (SMR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 53. Watch-Dog Timer Mode Register (WDTMR). . . . . . . . . . . . . . . . . . . . . . . . 110
Table 54. Symbolic Notation for Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 55. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 56. Flags Register (FLAGS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 57. Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 58. Z8 LXM CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PS024406-0106
P R E L I M I N A R Y
List of Tables
ZLP12840 OTP MCU
Product Specification
xi
Table 59. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 60. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 61. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 62. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 63. ZLP12840 OTP MCU Part Numbers Description . . . . . . . . . . . . . . . . . . . . . 137
PS024406-0106
P R E L I M I N A R Y
List of Tables
ZLP12840 OTP MCU
Product Specification
1
Architectural Overview
The ZLP12840 OTP MCU is a member of the Crimzon™ family of infrared microcontrollers. It provides a directly-compatible code upgrade path to other Crimzon™ MCUs,
offers a robust learning function, and features up to 128 KB one-time-programmable
(OTP) read-only memory (ROM) and 1004 bytes of general-purpose random-access memory (RAM). Two timers allow the generation of complex signals while performing other
counting operations. A UART allows the ZLP12840 MCU to be a slave/master database
chip. When the UART is not in use, the Baud Rate Generator can be used as a third timer.
Enhanced stop-mode recovery (SMR) features allow the ZLP12840 MCU to awaken from
STOP mode on any change of logic, and on any combination of the 12 SMR inputs. The
SMR source can also be used as an interrupt source.
Many high-end remote control units offer a learning function. Simply stated, a learning
function allows a replacement remote unit to learn most infrared signals from the original
remote unit and regenerate the signal. However, the amplifying circuits of many learning
remotes are expensive, are not tuned well, and result in frustrated users. ZiLOG’s
ZLP12840 MCU is the first chip dedicated to solving this problem because it offers a
built-in tuned amplification circuit in a wide range of positions and battery voltages. The
only external component required is a photodiode.
The ZLP12840 MCU greatly reduces system cost, yet improves learning function reliability. Best of all, however, will be the user experience promised by ZiLOG’s superior learning function. With all new features, the ZLP12840 MCU is excellent for infrared remote
control and other MCU applications.
Features
Table 1 lists the memory, I/O, and power features of the ZLP12840 one-time-programmable microcontroller. Additional features are listed below the table.
Table 1. ZLP12840 OTP MCU Features
Device
OTP ROM (KB)
RAM* (Bytes)
I/O Lines
Voltage
Range
ZLP12840 MCU
32, 64, 96, 128
1004
24 or 16
2.0–3.6 V
Note: *General-purpose registers implemented as random-access memory.
PS024406-0106
P R E L I M I N A R Y
Architectural Overview
ZLP12840 OTP MCU
Product Specification
2
The ZLP12840 MCU supports 20 interrupt sources with 6 interrupt vectors, as follows:
•
•
•
•
2 from T8, T16 time-out and capture
3 from UART Tx, UART Rx, UART BRG
1 from LVD
14 from SMR source P20-P27, P30-P33, P00, P07
– Any change of logic from P20-P27, P30-P33 can generate an interrupt or SMR
Additional features include:
•
•
•
PS024406-0106
IR learning amplifier
Low power consumption—11 mW (typical)
Three standby modes:
– STOP—1.7 A (typical)
– HALT—0.6 mA (typical)
– Low voltage reset
•
Intelligent counter/timer architecture to automate generation or reception and demodulation of complex waveform and pulsed signals:
– One programmable 8-bit counter/timer with two capture registers and two load
registers
– One programmable 16-bit counter/timer with one 16-bit capture register pair and
one 16-bit load register pair
– Programmable input glitch filter for pulse reception
– The UART baud rate generator can be used as another 8-bit timer when the UART
is not in use.
•
Six priority interrupts
– Three external/UART interrupts
– Two assigned to counter/timers
– One low-voltage detection interrupt
•
8-bit UART
– RX, TX interrupts
– 4800, 9600, 19200 and 38400 baud rates
– Parity Odd/Even/None
– Stop bits 1/2
P R E L I M I N A R Y
Features
ZLP12840 OTP MCU
Product Specification
3
Note:
•
•
•
Low voltage detection and high voltage detection flags
•
One-time programmable EPROM option bits (On/Off)
– Port 0 pins 0–3 pull-up transistors
– Port 0 pins 4–7 pull-up transistors
– Port 2 pins 0–7 pull-up transistors
– EPROM Protection
– Watch-dog timer enabled at Power-on reset
Programmable Watch-Dog Timer/Power-On Reset circuits
Two on-board analog comparators with independent reference voltages and programmable interrupt polarity
All signals with an overline, “ ”, are active Low. For example, B/W, in which WORD is
active Low, and B/W, in which BYTE is active Low.
Power connections use the conventional descriptions listed in Table 2.
Table 2. Power Connections
PS024406-0106
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
P R E L I M I N A R Y
Features
ZLP12840 OTP MCU
Product Specification
4
Functional Block Diagram
Figure 1 illustrates the functional blocks of the ZLP12840 microcontroller.
Z8 LXM
Core
ÑÌÐ
Ë° ¬± ïîèÕ ¨ è
Þ«-
Register/Peripheral Bus
Register File
Banks 0–3
P30/PRef1
4 x 256 x 8
Watch-Dog
Timer
UART &
BRG Timer
Register File
Banks D & F
2 x 16 x 8
2 Comparators
IR Learning
Amplifier
High/Low
Voltage Detect
Counter/Timers
8-Bit/16-bit
Power-On
Reset
Figure 1. ZLP12840 MCU Functional Block Diagram
PS024406-0106
P R E L I M I N A R Y
Functional Block Diagram
ZLP12840 OTP MCU
Product Specification
5
Pin Description
Figure 2 details the pin configuration of the ZLP12840 device in the 20-pin PDIP, SOIC,
and SSOP packages.
P25
P26
P27
P07
VDD
XTAL2
XTAL1
P31
P32
P33
1
2
3
4
5
6
7
8
9
10
20-Pin
PDIP
SOIC
SSOP
20
19
18
17
16
15
14
13
12
11
P24
P23
P22
P21
P20
VSS
P01
P00/P30
P36
P34
Figure 2. ZLP12840 MCU 20-Pin PDIP/SOIC/SSOP Pin Configuration
Table 3 identifies the functions and signal directions of each pin within the 20-pin PDIP,
SOIC, and SSOP packages sequentially by pin.
Table 3. ZLP12840 MCU 20-Pin PDIP/SOIC/SSOP Sequential Pin Identification
Pin #
Symbol
Function
Direction
1
P25
Port 2, bit 5
Input/Output
2
P26
Port 2, bit 6
Input/Output
3
P27
Port 2, bit 7
Input/Output
4
P07
Port 0, bit 7
Input/Output
5
VDD
Power Supply
6
XTAL2
Crystal oscillator
Output
7
XTAL1
Crystal oscillator
Input
8
P31
Port 3, bit 1
Input
9
P32
Port 3, bit 2
Input
10
P33
Port 3, bit 3
Input
11
P34
Port 3, bit 4
Output
12
P36
Port 3, bit 6
Output
Note: When the Port 0 high-nibble pull-up option is enabled and the P30 input is Low, current flows
through the pull-up to Ground.
PS024406-0106
P R E L I M I N A R Y
Pin Description
ZLP12840 OTP MCU
Product Specification
6
Table 3. ZLP12840 MCU 20-Pin PDIP/SOIC/SSOP Sequential Pin Identification
Pin #
1
13
Symbol
Function
Direction
P00
Port 0, bit 0
Input/Output
P30
Port 3, bit 0
Input
14
P01
Port 0, bit 1
Input/Output
15
VSS
Ground
16
P20
Port 2, bit 0
Input/Output
17
P21
Port 2, bit 1
Input/Output
18
P22
Port 2, bit 2
Input/Output
19
P23
Port 2, bit 3
Input/Output
20
P24
Port 2, bit 4
Input/Output
Note: When the Port 0 high-nibble pull-up option is enabled and the P30 input is Low, current flows
through the pull-up to Ground.
PS024406-0106
P R E L I M I N A R Y
Pin Description
ZLP12840 OTP MCU
Product Specification
7
Table 4 identifies the functions and signal direction of each pin within the 20-pin PDIP,
SOIC, and SSOP packages by function.
Table 4. ZLP12840 MCU 20-Pin PDIP/SOIC/SSOP Functional Pin Identification
Pin #
Symbol
Function
Direction
131
P00
Port 0, bit 0
Input/Output
P30
Port 3, bit 0
Input
14
P01
Port 0, bit 1
Input/Output
4
P07
Port 0, bit 7
Input/Output
16
P20
Port 2, bit 0
Input/Output
17
P21
Port 2, bit 1
Input/Output
18
P22
Port 2, bit 2
Input/Output
19
P23
Port 2, bit 3
Input/Output
20
P24
Port 2, bit 4
Input/Output
1
P25
Port 2, bit 5
Input/Output
2
P26
Port 2, bit 6
Input/Output
3
P27
Port 2, bit 7
Input/Output
8
P31
Port 3, bit 1
Input
9
P32
Port 3, bit 2
Input
10
P33
Port 3, bit 3
Input
11
P34
Port 3, bit 4
Output
12
P36
Port 3, bit 6
Output
5
VDD
Power Supply
15
VSS
Ground
7
XTAL1
Crystal oscillator
Input
6
XTAL2
Crystal oscillator
Output
Note: When the Port 0 high-nibble pull-up option is enabled and the P30 input is Low, current flows
through the pull-up to Ground.
PS024406-0106
P R E L I M I N A R Y
Pin Description
ZLP12840 OTP MCU
Product Specification
8
Figure 3 details the pin configuration of the ZLP12840 device in the 28-pin PDIP, SOIC,
and SSOP packages.
P25
P26
P27
P04
P05
P06
P07
VDD
XTAL2
XTAL1
P31
P32
P33
P34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-Pin
PDIP
SOIC
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P24
P23
P22
P21
P20
P03
VSS
P02
P01
P00
P30
P36
P37
P35
Figure 3. ZLP12840 MCU 28-Pin PDIP/SOIC/SSOP Pin Configuration
PS024406-0106
P R E L I M I N A R Y
Pin Description
ZLP12840 OTP MCU
Product Specification
9
Table 5 identifies the functions and signal directions of each pin within the 28-pin PDIP,
SOIC, and SSOP packages sequentially by pin.
Table 5. ZLP12840 MCU 28-Pin PDIP/SOIC/SSOP Sequential Pin Identification
PS024406-0106
Pin
Symbol
Function
Direction
1
P25
Port 2, bit 5
Input/Output
2
P26
Port 2, bit 6
Input/Output
3
P27
Port 2, bit 7
Input/Output
4
P04
Port 0, bit 4
Input/Output
5
P05
Port 0, bit 5
Input/Output
6
P06
Port 0, bit 6
Input/Output
7
P07
Port 0, bit 7
Input/Output
8
VDD
Power supply
9
XTAL2
Crystal oscillator
Output
10
XTAL1
Crystal oscillator
Input
11
P31
Port 3, bit 1
Input
12
P32
Port 3, bit 2
Input
13
P33
Port 3, bit 3
Input
14
P34
Port 3, bit 4
Output
15
P35
Port 3, bit 5
Output
16
P37
Port 3, bit 7
Output
17
P36
Port 3, bit 6
Output
18
P30
Port 3, bit 0; connect to VCC if
not used
Input
19
P00
Port 0, bit 0
Input/Output
20
P01
Port 0, bit 1
Input/Output
21
P02
Port 0, bit 2
Input/Output
22
VSS
Ground
23
P03
Port 0, bit 3
Input/Output
24
P20
Port 2, bit 0
Input/Output
25
P21
Port 2, bit 1
Input/Output
26
P22
Port 2, bit 2
Input/Output
27
P23
Port 2, bit 3
Input/Output
28
P24
Port 2, bit 4
Input/Output
P R E L I M I N A R Y
Pin Description
ZLP12840 OTP MCU
Product Specification
10
Table 6 identifies the functions and signal directions of each pin within the 28-pin PDIP,
SOIC, and SSOP packages by function.
Table 6. ZLP12840 MCU 28-Pin PDIP/SOIC/SSOP Functional Pin Identification
PS024406-0106
Pin
Symbol
Function
Direction
19
P00
Port 0, bit 0
Input/Output
20
P01
Port 0, bit 1
Input/Output
21
P02
Port 0, bit 2
Input/Output
23
P03
Port 0, bit 3
Input/Output
4
P04
Port 0, bit 4
Input/Output
5
P05
Port 0, bit 5
Input/Output
6
P06
Port 0, bit 6
Input/Output
7
P07
Port 0, bit 7
Input/Output
24
P20
Port 2, bit 0
Input/Output
25
P21
Port 2, bit 1
Input/Output
26
P22
Port 2, bit 2
Input/Output
27
P23
Port 2, bit 3
Input/Output
28
P24
Port 2, bit 4
Input/Output
1
P25
Port 2, bit 5
Input/Output
2
P26
Port 2, bit 6
Input/Output
3
P27
Port 2, bit 7
Input/Output
18
P30
Port 3, bit 0; connect to VCC if
not used
Input
11
P31
Port 3, bit 1
Input
12
P32
Port 3, bit 2
Input
13
P33
Port 3, bit 3
Input
14
P34
Port 3, bit 4
Output
15
P35
Port 3, bit 5
Output
17
P36
Port 3, bit 6
Output
16
P37
Port 3, bit 7
Output
8
VDD
Power supply
22
VSS
Ground
10
XTAL1
Crystal oscillator
Input
9
XTAL2
Crystal oscillator
Output
P R E L I M I N A R Y
Pin Description
ZLP12840 OTP MCU
Product Specification
11
I/O Port Pin Functions
The ZLP12840 MCU features three 8-bit ports, which are described below.
•
•
•
Note:
Port 0 is nibble-programmable as either input or output
Port 2 is bit-programmable as either input or output
Port 3 features four inputs on the lower nibble and four outputs on the upper nibble
Port 0 and 2 internal pull-ups are disabled on any pin or group of pins when programmed
into output mode.
Caution: The CMOS input buffer for each port 0 or 2 pin is always connected to the pin, even
when the pin is configured as an output. If the pin is configured as an open-drain output
and no external signal is applied, a High output state can cause the CMOS input buffer
to float. This might lead to excessive leakage current of more than 100 A. To prevent
this leakage, connect the pin to an external signal with a defined logic level or ensure its
output state is Low, especially during STOP mode.
Port 0, 1, and 2 have both input and output capability. The input logic is always present
no matter whether the port is configured as input or output. When doing a READ instruction, the MCU reads the actual value at the input logic but not from the output buffer. In addition, the instructions of OR, AND, and XOR have the Read-Modify-Write
sequence. The MCU first reads the port, and then modifies the value and load back to
the port.
Precaution must be taken if the port is configured as open-drain output or if the port is
driving any circuit that makes the voltage different from the desired output logic. For
example, pins P00–P07 are not connected to anything else. If it is configured as opendrain output with output logic as ONE, it is a floating port and reads back as ZERO. The
following instruction sets P00-P07 all LOW.
ßÒÜ ÐðôýûÚð
Table 7 summarizes the registers used to control I/O ports. Some port pin functions can
also be affected by control registers for other peripheral functions.
Table 7. I/O Port Control Registers
Address (Hex)
12-Bit
Bank 8-Bit
Register Description
Mnemonic Reset
000
0–3
00
Port 0
P0
XXh
22
002
0–3
02
Port 2
P2
XXh
24
PS024406-0106
P R E L I M I N A R Y
Page #
I/O Port Pin Functions
ZLP12840 OTP MCU
Product Specification
12
Table 7. I/O Port Control Registers (Continued)
Address (Hex)
12-Bit
Bank 8-Bit
Register Description
Mnemonic Reset
Page #
003
0–3
03
Port 3
P3
0Xh
26
0F6
All
F6
Port 2 Mode Register
P2M
FFh
23
0F7
All
F7
Port 3 Mode Register
P3M
XXXX_X000b
25
0F8
All
F8
Port 0 Mode Register
P01M
X1 XX_XXX1b
21
F00
F
00
Port Configuration Register
PCON
XXXX_X1X0b
20
Port 0
Port 0 is an 8-bit, bidirectional, CMOS-compatible port. Its eight I/O lines are configured
under software control to create a nibble I/O port. The output drivers are push/pull or
open-drain, controlled by bit 2 of the PCON register.
If one or both nibbles are required for I/O operation, they must be configured by writing to
the Port 0 Mode Register (P01M). After a hardware reset or a stop-mode recovery (SMR),
Port 0 is configured as an input port.
Port 0, bit 7 is used as the transmit output of the UART when UART Tx is enabled.The I/O
function of Port 0, bit 7 is overridden by the UART serial output (TxD) when UART Tx is
enabled (UCTL[7] = 1). The pin must be configured as an output for TxD data to reach the
pin (P0M[6] = 0).
An optional pull-up transistor is available as an OTP option on all Port 0 bits with nibble
select. See the configuration illustration in Figure 4.
PS024406-0106
P R E L I M I N A R Y
Port 0
ZLP12840 OTP MCU
Product Specification
13
ì
ÆÔÐïîèìð
ÑÌÐ ÓÝË
ᮬ ð ø×ñÑ÷
ì
Ñ°»²óÜ®¿·²
ÊÝÝ
λ-·-¬·ª» Ы´´óË°
Ì®¿²-·-¬±®
øÑÌÐ Ñ°¬·±²÷
×ñÑ
п¼
Ñ«¬
ײ
Figure 4. Port 0 Configuration
Port 2
Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port. Its eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. An EPROM option bit is available to connect eight pull-up
transistors on this port. Bits programmed as outputs are globally programmed as either
push/pull or open-drain. The Power-On Reset function resets with the eight bits of Port 2
[P27:20] configured as inputs.
Port 2 also has an 8-bit input OR and AND gate and edge detection circuitry, which can be
used to wake up the part. P20 can be programmed to access the edge-detection circuitry in
demodulation mode. See the configuration illustration in Figure 5.
PS024406-0106
P R E L I M I N A R Y
Port 2
ZLP12840 OTP MCU
Product Specification
14
ÆÔÐïîèìð
ÑÌÐ ÓÝË
ᮬ î ø×ñÑ÷
Ñ°»²óÜ®¿·²
ÊÝÝ
λ-·-¬·ª» Ы´´óË°
Ì®¿²-·-¬±®
øÑÌÐ Ñ°¬·±²÷
×ñÑ
п¼
Ñ«¬
ײ
Figure 5. Port 2 Configuration
Port 3
Port 3 is a 8-bit, CMOS-compatible fixed I/O port (see Figure 6). Port 3 consists of four
fixed inputs (P33:P30) and four fixed outputs (P37:P34). P30, P31, P32, and P33 are standard CMOS inputs, and can be configured under software control as interrupts, as receive
data input to the UART block, as input to comparator circuits, or as input to the IR learning AMP. P34, P35, P36, and P37 are push/pull outputs, and can be configured as outputs
from the counter/timers. See the configuration illustration in Figure 6.
PS024406-0106
P R E L I M I N A R Y
Port 3
ZLP12840 OTP MCU
Product Specification
15
Ðíð
Ðíï
Ðíî
Ðíí
ÆÔÐïîèìð
ÑÌÐ ÓÝË
ᮬ í ø×ñÑ÷
Ðíì
Ðíë
Ðíê
Ðíé
ÐíÓ Î»¹·-¬»®ô ðÚé¸
Üî Üï
ï ã ß²¿´±¹å ×Î ß³° Ѳ
ð ã Ü·¹·¬¿´å ×Î ß³° Ѻº
Ü·¹·¬¿´
Üï
Ðíï øßÒï÷
õ
P
Ðíð øÐÎÛÚï÷
×ÎÏîô Ðíï Ü¿¬¿ Ô¿¬½¸
ݱ³°ï
Ðíï
×ÎÛÚ
õ
P
×Îï
Ô»¿®²·²¹ ß³°´·º·»®
×ÎÏðô Ðíî Ü¿¬¿ Ô¿¬½¸
õ
P
ݱ³°î
Ú®±³ ͬ±°óÓ±¼»
λ½±ª»®§ ͱ«®½» ±º ÍÓÎ
×ÎÏïô Ðíí Ü¿¬¿ Ô¿¬½¸
Figure 6. Port 3 Configuration
P31 can be used as an interrupt, analog comparator input, infrared learning amplifier
input, normal digital input pin and as a stop-mode recovery source. When bit 2 of the Port
3 Mode Register (P3M) is set, P31 is used as the infrared learning amplifier, IR1. The reference source for IR1 is GND. The infrared learning amplifier is disabled during STOP
mode. When bit 1 of P3M is set, the part is in ANALOG mode and the analog comparator,
COMP1 is used. The reference voltage for COMP1 is P30 (PREF1). When in ANALOG
mode, P30 cannot be read as a digital input when the CPU reads bit 0 of the Port 3 Regis-
PS024406-0106
P R E L I M I N A R Y
Port 3
ZLP12840 OTP MCU
Product Specification
16
ter; such reads always return a value of 1. Also, when in ANALOG mode, P31 cannot be
used as a stop-mode recovery source because in STOP mode, the comparator is disabled,
and its output will not toggle. The programming of Bit 2 of the P3M register takes precedence over the programming of Bit 1 in determining the function of P31. If both bits are
set, P31 functions as an IR learning amplifier instead of an analog comparator. As shown
in Figure 6, the output of the function selected for P31 can be used as a source for IRQ2
interrupt assertion. The IRQ2 interrupt can be configured to be based upon detecting a rising, falling, or edge-triggered input change using Bits 6 and 7 of the IRQ register. The P31
output stage signal also goes to the Counter/Timer edge detection circuitry in the same
way that P20 does.
P32 can be used as an interrupt, analog comparator, UART receiver, normal digital input
and as a stop-mode recovery source. When bit 6 of UCTL is set, P32 functions as a receive
input for the UART. When bit 1 of the P3M Register is set, thereby placing the part into
ANALOG mode, P32 functions as an analog comparator, Comp2. The reference voltage
for Comp2 is P33 (PREF2). P32 can be used as a rising, falling or edge-triggered interrupt,
IRQ0, using IRQ register bits 6 and 7. If UART receiver interrupts are not enabled, the
UART receive interrupt is used as the source of interrupts for IRQ0 instead of P32. When
in ANALOG mode P32 cannot be used as a stop-mode recovery source because the comparators are turned OFF in STOP mode.
When in ANALOG mode, P33 cannot be read through bit 3 of the Port 3 Register as a digital input by the CPU. In this case, a read of bit 3 of the Port 3 Register indicates whether a
Stop-mode recovery condition exists. Reading a value of 0 indicates that a Stop-mode
recovery condition does exist; if the ZLP12840 MCU is presently in STOP mode, it will
exit STOP mode. Reading a value of 1 indicates that no condition exists to remove the
ZLP12840 from STOP mode. Additionally, when in ANALOG mode, P33 cannot be used
as an interrupt source. Instead, the existence of a Stop-mode recovery condition can generate an interrupt, if enabled. P33 can be used as a falling-edge interrupt, IRQ1, when not in
ANALOG mode. IRQ1 is also used as the UART TX interrupt and the UART BRG interrupt. Only one source is active at a time. If bits 7 and 5 of UCTL are set to 1, IRQ1 will
transmit an interrupt when the Transmit Shift Register is empty. If bits 0 and 5 of UCTL
are set to 1 and bit 6 of UCTL is cleared to 0, the BRG interrupts will activate IRQ1.
Note:
PS024406-0106
Comparators and the IR amplifier are powered down by entering STOP mode. For
P30:P33 to be used as a stop-mode recovery source during STOP mode, these inputs must
be placed into digital mode. When in analog mode, do not configure any Port 3 input as a
stop-mode recovery source. The configuration of these inputs must be re-initialized after
stop-mode recovery or power-on reset.
P R E L I M I N A R Y
Port 3
ZLP12840 OTP MCU
Product Specification
17
Table 8. Summary of Port 3 Pin Functions
2
Pin
I/O
P30
IN
P31
IN
P32
Counter/Timers
Comparator
Interrupt
IRAMP
AN1
IRQ2
IR1
IN
AN2
IRQ0
P33
IN
REF2
IRQ1
P34
OUT
T8
P35
OUT
T16
P36
OUT
T8/T16
P37
OUT
UART
REF1
IN
AO1
UART Rx
IROUT
AO2
Port 3 also provides output for each of the counter/timers and the AND/OR Logic (see
Figure 7). Control is performed by programming CTR1 bits 5 and 4, CTR0 bit 0, and
CTR2 bit 0.
PS024406-0106
P R E L I M I N A R Y
Port 3
ZLP12840 OTP MCU
Product Specification
18
ÝÌÎðô ¾·¬ ð
ÐÝÑÒô ¾·¬ ð
Ðíì Ü¿¬¿
ÊÜÜ
ÓËÈ
ÌèÁÑ«¬
ÓËÈ
п¼
ÐíÓ Üî
Ðíï
× ÎÛÚ
Ðíì
õ
P
×Îï
ÐíÓ Üï
ÝÌÎîô ¾·¬ ð
Ðíð
õ
P
ݱ³°ï
Ðíë Ü¿¬¿
ÊÜÜ
ÓËÈ
ÌïêÁÑ«¬
п¼
Ðíë
ÝÌÎïô ¾·¬ ê
Ðíê Ü¿¬¿
ÌèñïêÁÑ«¬
ÊÜÜ
ÓËÈ
п¼
Ðíê
ÐÝÑÒô ¾·¬ ð
ÊÜÜ
Ðíé Ü¿¬¿
ÐíÓ Üï
ÓËÈ
Ðíî
Ðíî
Ðíí
п¼
Ðíé
õ
P
ݱ³°î
Figure 7. Port 3 Counter/Timer Output Configuration
PS024406-0106
P R E L I M I N A R Y
Port 3
ZLP12840 OTP MCU
Product Specification
19
Comparator Inputs
In analog mode, P31 and P32 have a comparator front end. The comparator reference is
supplied by P33 and PREF1. In this mode, the P33 internal data latch and its corresponding
IRQ1 are diverted to the stop-mode recovery sources (excluding P31, P32, and P33) as
indicated in Figure 6 on page 15. In digital mode, P33 is used as bit 3 of the Port 3 input
register, which then generates IRQ1.
Note:
Comparators are powered down by entering STOP mode. For P30:P33 to be used as a
stop-mode recovery source, these inputs must be placed into digital mode.
Comparator Outputs
The comparators can be programmed to be output on P34 and P37 by setting bit 0 of the
PCON Register.
PS024406-0106
P R E L I M I N A R Y
Port 3
ZLP12840 OTP MCU
Product Specification
20
Port Configuration Register (PCON)
The Port Configuration (PCON) register, shown in Table 9, configures the Port 0 output
mode and the comparator output on Port 3. The PCON register is located in expanded register Bank F, address 00h.
Table 9. Port Configuration Register (PCON)
Bit
7
6
5
4
3
Reserved
Field
Reset
X
X
R/W
X
X
—
Address
Bit
Position
[7:3]
1
0
Port 0 Output Mode
Reserved
Comp./IR Amp. Output Port 3
1
X
0
W
—
W
Bank F: 00h; Linear: F00h
Value Description
—
Reserved—Writes have no effect; reads 11111b.
0
1
Port 0 Output Mode—Controls the output mode of port 0. Write only; reads return 1.
Open-drain
Push/pull
—
Reserved—Writes have no effect; reads 1.
[2]
[1]
X
2
Comparator or IR Amplifier Output Port 3—Select digital outputs or comparator and
[0]
IR amplifier outputs on P34 and P37. Write only; reads return 1.
0
1
Note:
PS024406-0106
P34 and P37 outputs are digital.
P34 is Comparator 1 or IR Amplifier output, P37 is Comparator 2 output.
This register is not reset after a stop-mode recovery.
P R E L I M I N A R Y
Port Configuration Register (PCON)
ZLP12840 OTP MCU
Product Specification
21
Port 0 Mode Register
The Port 0 Mode Register determines the I/O direction of Port 0. The Port 0 direction is
nibble-programmable. Bit 6 controls the upper nibble of Port 0, bits [7:3]. Bit 0 controls
the lower nibble of Port 0, bits [3:0]. See Table 11.
Table 10. Port 0 Mode Register (P01M)
Bit
7
6
Field
Reserved
P07:P04 Mode
Reset
X
1
X
X
X
X
X
1
R/W
—
W
—
—
—
—
—
W
Address
Bit
Position
4
3
2
1
Reserved
0
P03:P00 Mode
Bank Independent: F8h; Linear: 0F8h
Value Description
7
0
Reserved—Writes have no effect. Reads 1b.
0
1
P07:P04 Mode
Output.
Input.
—
Reserved—Writes have no effect. Reads 11111b.
0
1
P00:P03 Mode
Output.
Input.
[6]
[5:1]
5
[0]
Note:
PS024406-0106
Only P00, P01, and P07 are available on Crimzon™ ZLP12840 MCU 20-pin configurations.
P R E L I M I N A R Y
Port 0 Mode Register
ZLP12840 OTP MCU
Product Specification
22
Port 0 Register
The Port 0 Register allows read and write access to the Port 0 pins. See Table 11.
Table 11. Port 0 Register (P0)
Bit
7
6
5
4
3
2
1
0
Field
P07
P06
P05
P04
P03
P02
P01
P00
Reset
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bank 0–3: 00h; Linear: 000h
Bit
Position R/W
Description
[7]
Read:
0
1
Write:
0
1
Port 0 Pin 7—Available for I/O if UART Tx is disabled.
(Pin configured as input or output in P01M register.)
Pin level is Low.
Pin level is High.
(Pin configured as output in P01M register, UCTL[7]=0.)
Assert pin Low.
Assert pin High if configured as push-pull; make pin high-impedance if it is open drain.
Read:
0
1
Write:
0
1
Port 0 Pins 6–0—Each bit provides access to the corresponding Port 0 pin.
(Pin configured as input or output in P01M register.)
Pin level is Low.
Pin level is High.
(Pin configured as output in P01M register.)
Assert pin Low.
Assert pin High if configured as push-pull; make pin high-impedance if it is open drain.
[6:0]
Note:
PS024406-0106
Only P00, P01, and P07 are available on Crimzon™ ZLP12840 MCU 20-pin configurations.
P R E L I M I N A R Y
Port 0 Register
ZLP12840 OTP MCU
Product Specification
23
Port 2 Mode Register
The Port 2 Mode Register determines the I/O direction of each bit on Port 2. Bit 0 of the
Port 3 Mode Register determines whether the output drive is push/pull or open-drain. See
Table 12.
Table 12. Port 2 Mode Register (P2M)
Bit
7
6
Field
P27 I/O
Definition
P26 I/O
Definition
Reset
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bit
Position
5
4
P25 I/O
P24 I/O
Definition Definition
3
2
1
P23 I/O
P22 I/O
P21 I/O
Definition Definition Definition
0
P20 I/O
Definition
Bank Independent: F6h; Linear: 0F6h
Value Description
[7]
0
1
Defines P27 as output.
Defines P27 as input.
[6]
0
1
Defines P26 as output.
Defines P26 as input.
[5]
0
1
Defines P25 as output.
Defines P25 as input.
[4]
0
1
Defines P24 as output.
Defines P24 as input.
[3]
0
1
Defines P23 as output.
Defines P23 as input.
[2]
0
1
Defines P22 as output.
Defines P22 as input.
[1]
0
1
Defines P21 as output.
Defines P21 as input.
[0]
0
1
Defines P20 as output.
Defines P20 as input.
Note:
PS024406-0106
This register is not reset after a stop-mode recovery.
P R E L I M I N A R Y
Port 2 Mode Register
ZLP12840 OTP MCU
Product Specification
24
Port 2 Register
The Port 2 Register allows read and write access to the Port 2 pins. See Table 13.
Table 13. Port 2 Register (P2)
Bit
7
6
5
4
3
2
1
0
Field
P27
P26
P25
P24
P23
P22
P21
P20
Reset
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bit
Position
Bank 0–3: 02h; Linear: 002h
Value Description
[7:0]
Read:
0
1
Write:
0
1
PS024406-0106
Port 2 Pins 7–0—Each bit provides access to the corresponding Port 2 pin.
(Pin configured as input or output in P2M register.)
Pin level is Low.
Pin level is High.
(Pin configured as output in P2M register.)
Assert pin Low.
Assert pin High if configured as push-pull; make pin high-impedance if it is open drain.
P R E L I M I N A R Y
Port 2 Register
ZLP12840 OTP MCU
Product Specification
25
Port 3 Mode Register
The Port 3 Mode Register is used primarily to configure the functionality of the Port 3
inputs. When bit 2 is set, the IR Learning Amplifier is used instead of the COMP1 comparator, regardless of the value of bit 1. See Table 14.
Table 14. Port 3 Mode Register (P3M)
Bit
7
6
5
4
3
Reserved
Field
2
1
0
IR Learning
Amplifier
Digital/Analog
Mode
Port 2 OpenDrain
Reset
X
X
X
X
X
0
0
0
R/W
—
—
—
—
—
W
W
W
Address
Bit
Position
Bank Independent: F7h; Linear 0F7h
R/W
Value Description
[7:3]
—
—
Reserved—Writes have no effect. Reads return 11111b.
[2]
W
0
1
IR Learning Amplifier disabled.
IR Learning Amplifier enabled with P31 configured as amplifier input.
[1]
W
0
1
Digital/Analog Mode
P30, P31, P32, P33 are digital inputs.
P30, P32, and P33 are comparator inputs. If P3M[2]=0, P31 is also a
comparator input. If P3M[2]=1, P31 is the IR amplifier input.
0
1
Port 2 open-drain.
Port 2 push/pull.
W
[0]
Note:
PS024406-0106
This register is not reset after a stop-mode recovery.
P R E L I M I N A R Y
Port 3 Mode Register
ZLP12840 OTP MCU
Product Specification
26
Port 3 Register
The Port 3 Register allows read access to port pins P33 through P30 and write access to
the port pins P37 through P34. See Table 15.
Table 15. Port 3 Register (P3)
Bit
7
6
5
4
3
2
1
0
Field
P37
P36
P35
P34
P33
P32
P31
P30
Reset
0
0
0
0
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bit
Position
Banks 0–3: 03h; Linear: 003h
Value Description
[7]
Port 3, pin 7 Output—Writes to this bit do not affect the pin state if write-only register
bit PCON[0] has been written with a 1, which configures P37 as the Comparator 1 or
Write: IR Amplifier output.
0
P37 asserted Low if PCON[0]=0.
1
P37 asserted High if PCON[0]=0.
A read returns the last value written to this bit.
[6]
Port 3, pin 6 Output—Writes to this bit do not affect the pin state if register bits
Write: CTR1[7:6]=01, which configures P36 as the Timer 8 and Timer 16 combined logic
0
output.
1
P36 asserted Low.
P36 asserted High.
A read returns the last value written to this bit.
[5]
Port 3, pin 5 Output—Writes to this bit do not affect the pin state if register bit
Write: CTR2[0]=1, which configures P35 as the Timer 16 output.
0
P35 asserted Low.
1
P35 asserted High.
A read returns the last value written to this bit.
[4]
Port 3, pin 4 Output—Writes to this bit do not affect the pin state if write only register bit
PCON[0]=1, which configures P34 as Comparator 2 output, or register bit CTR0[0]=1,
Write: which configures P34 as Timer 8 output.
0
P34 asserted Low.
1
P34 asserted High.
A read returns the last value written to this bit.
PS024406-0106
P R E L I M I N A R Y
Port 3 Register
ZLP12840 OTP MCU
Product Specification
27
Bit
Position
Value Description
[3]
Read: Port 3, pin 3 Input—Writing this bit has no effect.
If P3M[1]=0:
P33 is Low.
0
P33 is High.
1
If P3M[1]=1 or SMR4[4]=1:
SMR condition exists.
0
SMR condition does not exist.
1
[2]
Read: Port 3, pin 2 Input—Writing this bit has no effect.
If P3M[1]=0:
0
P32 input is Low.
1
P32 input is High.
If P3M[1]=1:
0
Comparator 2 output is Low.
1
Comparator 2 output is High.
[1]
Read: Port 3, pin 1 Input—Writing this bit has no effect.
If P3M[2:1]=00:
0
P31 input is Low.
1
P31 input is High.
If P3M[2:1]=01:
0
Comparator 1 output is Low.
1
Comparator 1 output is High.
If P3M[2:1]=10 or 11:
0
IR amplifier output is Low.
1
IR amplifier output is High.
[0]
Read: Port 3, pin 0 Input—Writing this bit has no effect.
If P3M[1]=00:
0
P30 input is Low.
1
P30 input is High.
If P3M[1]=1:
1
Reads as 1.
Note:
PS024406-0106
This register is not reset after a stop-mode recovery.
P R E L I M I N A R Y
Port 3 Register
ZLP12840 OTP MCU
Product Specification
28
Memory and Registers
The Z8 LXM CPU used in the ZLP12840 family of devices incorporates special features
to extend the available memory space while maintaining the benefits of a Z8® CPU core in
consumer and battery-operated applications.
OTP Program/Constant Memory
The ZLP12840 family of devices can address up to 128 KB of one-time programmable
(OTP) memory, used for object code (program instructions and immediate data) and constant data (ROM tables and data constants). The amount of OTP implemented depends on
the specific device. The OTP memory space is organized in 64KB pages with the following characteristics:
Page 0 can contain up to 64KB of program instructions and constant data. The first 12
bytes of Page 0 are reserved for the six available 16-bit interrupt request (IRQ) vectors.
Upon reset, program execution begins at address 000Ch in Page 0. Execution rolls over to
the bottom of Page 0 if the program counter exceeds the highest Page 0 address (FFFFh).
Page 1, if implemented, can contain up to 64KB of data constants and tables only. Page 1
cannot contain program instructions or immediate data. Constant data in either page can
be accessed only by the Load Constant (LDC and LDCI) instructions. LDC and LDCI use
16-bit addresses to access OTP memory.
For example, if a ZLP12840 family device contains 96 KB of OTP memory, only the first
64 KB (Page 0) can contain object code; the remaining 32 KB (in Page 1) is available for
constant data. For a ZLP12840 family device with 64 KB or less of total OTP memory, all
OTP memory is available for object code or constant data.
The page accessed by LDC or LDCI depends on the value of Program Memory Page Register bit 0 (PMPR[0]). Page 0 is accessed if PMPR[0]=0; Page 1 is accessed if
PMPR[0]=1. PMPR[7] enables the page toggle feature. For example, if PMPR[0]=0,
PMPR[7]=1, and a Load Constant and Increment (LDCI) instruction address increments
past FFFFh, the state of PMPR[0] is toggled from 0 to 1, and the next LDCI instruction
addresses 0000h on Page 1.
Figure 8 on page 29 illustrates the Program/Constant memory map for a 128KB device.
PS024406-0106
P R E L I M I N A R Y
Memory and Registers
ZLP12840 OTP MCU
Product Specification
29
Page 0
{0, FFFFh} FFFFh
Page 1
{1, FFFFh} FFFFh
Program
or
Constants
000Ch (Reset)
IRQ 0–5
Vectors
{0, 0000h}
Constants
Only
{1, 0000h} 0000h
0000h
= 16-bit Address (In Page)
{0, 0000h} = {PMPR[0], 16-bit address} (LDC, LDCI Only)
Not to Scale
Figure 8. Program/Constant Memory Map (128KB Device)
Register File
This device features 1056 bytes of register file space, organized in 256-byte banks. Bank 0
contains 237 bytes of RAM addressed as general-purpose registers, 4 port addresses (of
which one is reserved), and 16 control register addresses. Banks 1, 2, and 3 each contain
256 general-purpose register bytes. Banks D and F each contain 16 addresses for control
registers. All other banks are reserved and must not be selected.
The current bank is selected for 8-bit direct or indirect addressing by writing Register
Pointer bits RP[3:0]. In the current bank, a 16-byte working register group (addressed as
R0–R15) is selected by writing RP[7:4]. A working register operand requires only 4 bits
of program memory. There are 16 working register groups per bank. See Figure 9 on
page 31 and Figure 10 on page 32.
PS024406-0106
P R E L I M I N A R Y
Register File
ZLP12840 OTP MCU
Product Specification
30
8-bit addresses in the range F0h–FFh (and the equivalent 4-bit addresses) are bank-independent, meaning they always access the control registers in Bank 0, regardless of the
RP[3:0] value. Addresses in the range 00h–03h always access the Bank 0 Port registers
unless Bank D or F is selected. (Port 01h is not implemented in this device.) When Bank D
or F is selected, addresses 10h–EFh access the Bank 0 general-purpose registers.
The LDX and LDXI instructions or indirect addressing can be used to access the Bank 1–
3 registers not accessible by 8-bit or working register addresses (12-bit addresses 100h–
103h, 1F0h–1FFh, 200h–203h, 2F0h–2FFh, 300h–303h, and 3F0h–3FFh). See Linear
Memory Addressing on page 33.
Stack
The Stack Pointer register (SPL) is Bank 0 register FFh. Operations that use the stack
pointer always addresses Bank 0, regardless of the RP[3:0] setting. For details about the
stack, see the Z8 LXM CPU Core User Manual (UM0183).
This device does not use a stack pointer high byte. Bank 0 register FEh can be used to
store user data, see User Data Register on page 38.
PS024406-0106
P R E L I M I N A R Y
Register File
ZLP12840 OTP MCU
Product Specification
31
Banks 1–3
Bank 0
CPU Control
F0h–FFh
General
Purpose
Registers
04h–EFh
Ports 00h–03h
CPU Control
F0h–FFh
CPU Control
F0h–FFh
Bank D
Bank F
CPU Control
F0h–FFh
CPU Control
F0h–FFh
CPU Control
F0h–FFh
General
Purpose
Registers
04h–EFh
Bank 0
General
Purpose
Registers
10h–EFh
Bank 0
General
Purpose
Registers
10h–EFh
Ports 00h–03h
Peripheral
Control
00h–0Fh
Peripheral
Control
00h–0Fh
= Bank-Independent Address (Always Accesses Bank 0)
* Compiler’s default interrupt service routine working registers.
Not to Scale
Figure 9. Register File 8-Bit Banked Address Map
PS024406-0106
P R E L I M I N A R Y
Register File
ZLP12840 OTP MCU
Product Specification
32
ß½¬·ª» Ù®±«°
ß½¬·ª» Þ¿²µ
Îé Îê Îë Îì
Îí Îî Îï Îð
λ¹·-¬»® б·²¬»® øÎÐ÷ô ðÚܸ
̸» «°°»® ²·¾¾´» ±º ¬¸» ®»¹·-¬»® º·´» ¿¼¼®»-°®±ª·¼»¼ ¾§ ¬¸» ®»¹·-¬»® °±·²¬»® -°»½·º·»¬¸» ¿½¬·ª» ©±®µ·²¹ ®»¹·-¬»® ¹®±«°ò
ÚÚ
λ¹·-¬»® Ù®±«° Ú
Úð
ÛÚ
Ûð
ÜÚ
Üð
ìÚ
ìð
íÚ
íð
îÚ
Í°»½·º·»¼ ɱ®µ·²¹
λ¹·-¬»® Ù®±«°
̸» ´±©»® ²·¾¾´» ±º ¬¸» ®»¹·-¬»®
º·´» ¿¼¼®»-- °®±ª·¼»¼ ¾§ ¬¸»
·²-¬®«½¬·±² °±·²¬- ¬± ¬¸» -°»½·º·»¼
®»¹·-¬»®
λ¹·-¬»® Ù®±«° î
îð
ïÚ
ïð
ðÚ
λ¹·-¬»® Ù®±«° ï
Îïë ¬± Îð
λ¹·-¬»® Ù®±«° ð
땑 ± 듚
×ñÑ Ð±®¬- øÞ¿²µ- ðPí Ѳ´§÷
Îí ¬± Îðö
ðð
ö ÎÐ ã ððæ -»´»½¬- λ¹·-¬»® Þ¿²µ ðô ɱ®µ·²¹ λ¹·-¬»® Ù®±«° ð
Figure 10. Register Pointer—Detail
PS024406-0106
P R E L I M I N A R Y
Register File
ZLP12840 OTP MCU
Product Specification
33
Register Pointer Example
Îîëí
Îð ã
Îï ã
Îî ã
Îí ã
ÎÐ ã
ᮬ
ᮬ
ᮬ
ᮬ
ðð¸
ð
ï
î
í
But if:
Îîëí
Îð ã
Îï ã
Îî ã
Îí ã
ÎÐ ã ðܸ
ÝÌÎð
ÝÌÎï
ÝÌÎî
ÝÌÎí
The counter/timers are mapped into ERF group D. Access is easily performed using the
following code segment.
ÔÜ ÎÐô ýðܸ
ÔÜ Îðôý¨¨
ÔÜ ïô ý¨¨
ÔÜ Îïô î
ÔÜ ÎÐô ýéܸ
ÔÜ éï¸ô î
ÔÜ Îïô î
å
å
å
å
å
Í»´»½¬ ÛÎÚ Ü º±® ¿½½»-- ¬± Þ¿²µ Ü
ø©±®µ·²¹ ®»¹·-¬»® ¹®±«° ð÷
´±¿¼ ÝÌÎð
´±¿¼ ÝÌÎï
ÝÌÎî
ÝÌÎï
å
å
å
å
Í»´»½¬ Û¨°¿²¼»¼ λ¹·-¬»® Þ¿²µ Ü ¿²¼ ©±®µ·²¹
®»¹·-¬»® ¹®±«° é ±º Þ¿²µ 𠺱® ¿½½»--ò
ÝÌÎî
®»¹·-¬»® éï¸
ÝÌÎî
®»¹·-¬»® éï¸
Linear Memory Addressing
In addition to using the RP Register to designate a bank and working register group for 8bit or 4-bit addressing, programs can use 12-bit linear addressing to load a register in any
other bark to or from a register in the current bank. Linear addressing is implemented in
the LDX and LDXI instructions only. Linear addressing treats the register file as if all of
the registers are logically ordered end-to-end, as opposed to being grouped into banks and
working register groups, as shown in Figure 11 on page 35. For linear addressing, register
file addresses are numbered sequentially from Bank 0, register 00h to Bank 0, register
FFh, then continuing with Bank 1, register 00h, and so on up to Bank F, register FFh.
Using the LDX and/or the LDXI instructions, either the target or destination register location can be addressed through a 12-bit linear address value stored in a general-purpose
register pair. For example, the following code uses linear addressing for the source of a
register transfer operation and uses a working register address for the target.
PS024406-0106
P R E L I M I N A R Y
Register File
ZLP12840 OTP MCU
Product Specification
34
ÍÎÐ ýûîí
ÔÜ Îðô ýûëë
ÍÎÐ ýûïî
ÔÜ Îêô ýûðí
ÔÜ Îéô ýûîð
ÔÜ Îðô àÎÎê
åÍ»¬ ©±®µ·²¹ ®»¹·-¬»® ¹®±«° î ·² ¾¿²µ í
åÔ±¿¼ ëë ·²¬± ©±®µ·²¹ ®»¹·-¬»® Îð ·² ¬¸» ½«®®»²¬
å¹®±«° ¿²¼ ¾¿²µ ø´·²»¿® ¿¼¼®»-- íîð¸÷
åÍ»¬ ©±®µ·²¹ ®»¹·-¬»® ¹®±«° ï ·² ¾¿²µ î
åÔ±¿¼ ¸·¹¸ ¾§¬» ±º -±«®½» ´·²»¿® ¿¼¼®»-- øðíîð¸÷
åÔ±¿¼ ´±© ¾§¬» ±º -±«®½» ´·²»¿® ¿¼¼®»-- øðíîð¸÷
åÔ±¿¼ ´·²»¿® ¿¼¼®»-- íî𸠽±²¬»²¬- øëë¸÷ ·²¬±
婱®µ·²¹ ®»¹·-¬»® Îð ·² ¬¸» ½«®®»²¬ ¹®±«° ¿²¼
徿²µ ø´·²»¿® ¿¼¼®»-- îïð¸÷
As it can be seen in the above example, the source register is referenced via a linear
address value contained within registers R6 and R7, whereas the destination is referenced
via the SRP setting and a working register. Further explanation of the use of the LDX and
LDXI instructions can be found in the Z8 LXM CPU Core User Manual (UM0183).
Note:
PS024406-0106
The LDE and LDEI instructions that existed in the Z8 CPU are no longer valid; they have
been replaced by the LDX and LDXI instructions.
P R E L I M I N A R Y
Register File
ZLP12840 OTP MCU
Product Specification
35
Banks 1–3
Bank 0
Bank D
Bank F
Reserved
D10h–DFFh
Reserved
F10h–FFFh
Peripheral
Control
D00h–D0Fh
Peripheral
Control
F00h–F0Fh
CPU Control
0F0h–0FFh
Typical Stack
Below 0D0h
General
Purpose
Registers
004h–0EFh
General Purpose
Registers
100h–3FFh
Ports 000h–003h
Not to Scale
Figure 11. Register File LDX, LDXI Linear 12-Bit Address Map
PS024406-0106
P R E L I M I N A R Y
Register File
ZLP12840 OTP MCU
Product Specification
36
Program Memory Paging Register
Bit 0 of the Program Memory Paging Register determines which 64 KB bank of program
memory is read during the execution of the LDC and LDCI instructions. See Table 16.
Table 16. Program Memory Paging Register (PMPR)
Bit
7
6
5
4
3
2
1
Field
Page Toggle Enable
Reset
0
X
X
X
X
X
X
0
R/W
—
—
—
—
—
—
R/W
R/W
Address
Bit
Position
Page Register
Bank Independent: F0h; Linear: 0F0h
Value Description
[7]
0
1
[6:1]
Reserved
0
—
[0]
0
1
PS024406-0106
Page Toggle Enable
PMPR[0] changes only when written by software.
If PMPR[0]=0, the CPU toggles PMPR[0] when LDCI increments past FFFFh.
Reserved—Reads 111111b; write 000000b for compatibility with possible future
devices.
Page Register
LDC, LDCI instructions access Page 0.
LDC, LDCI instructions access Page 1.
P R E L I M I N A R Y
Program Memory Paging Register
ZLP12840 OTP MCU
Product Specification
37
Register Pointer Register
The upper nibble of the register pointer (see Table 17) selects which working register
group, of 16 bytes in the register file, is accessed out of the possible 256. The lower nibble
selects the expanded register file bank and, in the case of the Crimzon™ ZLP12840 MCU
family, banks 0, 1, 2, 3, F, and D are implemented. A ð¸ in the lower nibble allows the
normal register file (Bank 0) to be addressed. Any other value from ðï¸ to ðÚ¸ exchanges
the lower 16 registers to an expanded register bank. See Table 17.
Table 17. Register Pointer Register (RP)
Bit
7
6
4
3
Working Register Group Pointer
Field
Reset
R/W
2
1
0
Register Bank Pointer
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bit
Position
5
Bank Independent: FDh; Linear 0FDh
Value Description
[7:4]
Working Register Group Pointer
0h–Fh Determines which 16-byte working group is addressed.
[3:0]
Register Bank Pointer
0h–Fh Determines which bank is active.
PS024406-0106
P R E L I M I N A R Y
Register Pointer Register
ZLP12840 OTP MCU
Product Specification
38
User Data Register
Bank-independent register FEh is available for user data storage. See Table 18.
Do not use register FEh as a counter for the DJNZ instruction.
Note:
Table 18. User Data Register (USER)
Bit
7
6
5
4
Reset
R/W
1
0
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
[7:0]
2
User Data
Field
Bit
Position
3
Bank Independent: FEh; Linear: 0FEh
Value
Description
00h–FFh User Data
Stack Pointer Register
The Stack Pointer Register contains the 8-bit address of the stack pointer. The stack pointer
resides in Bank 0 of RAM. The stack address is decremented prior to a PUSH operation and
incremented after a POP operation. The stack address always points to the data stored at the
“top” of the stack (the lowest stack address). During a call instruction, the contents of the Program Counter are saved on the stack. Interrupts cause the contents of the Program Counter
and Flags registers to be saved on the stack. An overflow or underflow can occur when the
stack address is incremented or decremented during normal operations. The programmer
must prevent this occurrence or unpredictable operations will result. See Table 19.
Table 19. Stack Pointer Register (SPL)
Bit
7
6
5
4
3
2
1
0
Stack Pointer
Field
Reset
R/W
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bank Independent: FFh; Linear: 0FFh
Bit
Position Description
[7:0]
Stack Pointer
PS024406-0106
P R E L I M I N A R Y
User Data Register
ZLP12840 OTP MCU
Product Specification
39
Register File Summary
Table 20 maps each linear (12-bit) register file address to the associated register, mnemonic, and reset value. The table also lists the register bank (or banks) and corresponding
8-bit address, if any, for each register, plus a page link to the detailed register diagram.
Throughout this book, an “X” in a number denotes an undefined digit. A “—” (dash) in a
table cell indicates that the corresponding attribute does not apply to the listed item. Reset
value digits highlighted in grey are not reset by a stop-mode recovery. Register bit
SMR[7] (shown in boldface) is set to 1 instead of reset by a stop-mode recovery.
Table 20. Register File Address Summary
Address (Hex)
12-Bit
Bank 8-Bit
Register Description
Mnemonic Reset
000
0–3
00
Port 0
P0
XXh
22
001
0–3
01
Reserved
—
—
—
002
0–3
02
Port 2
P2
XXh
24
003
0–3
03
Port 3
P3
0Xh
26
04–0F General-Purpose Registers (Bank 0 Only) —
XXh
—
010–0EF 0,D,F 10–EF General-Purpose Registers (Banks 0, D, F) —
XXh
—
0F0
All
F0
Program Memory Paging Register
PMPR
0 XXX_XXX0 b
36
0F1
All
F1
UART Receive/Transmit Data Register
URDATA/
UTDATA
XXh
52
0F2
All
F2
UART Status Register
UST
0 0 0 0 _0 0 1 0 b
53
0F3
All
F3
UART Control Register
UCTL
00h
54
0F4
All
F4
UART Baud Rate Generator Constant
BCNST
FFh
55
0F5
All
F5
Reserved
—
—
—
0F6
All
F6
Port 2 Mode Register
P2M
FFh
23
0F7
All
F7
Port 3 Mode Register
P3M
XXXX_X0 0 0 b
25
0F8
All
F8
Port 0 Mode Register
P01M
X1 XX_XXX1 b
21
0F9
All
F9
Interrupt Priority Register
IPR
XXh
88
0FA
All
FA
Interrupt Request Register
IRQ
00h
90
0FB
All
FB
Interrupt Mask Register
IMR
0 XXX_XXXXb
87
0FC
All
FC
Flags Register
FLAGS
XXh
115
004–00F 0
PS024406-0106
P R E L I M I N A R Y
Page #
Register File Summary
ZLP12840 OTP MCU
Product Specification
40
Table 20. Register File Address Summary (Continued)
Address (Hex)
12-Bit
Bank 8-Bit
Register Description
Mnemonic Reset
0FD
All
FD
Register Pointer
RP
00h
37
0FE
All
FE
User Data Register
USER
XXh
38
0FF
All
FF
Stack Pointer Register
SPL
XXh
38
100–103 —
—
General-Purpose Registers (12-Bit Only)
—
XXh
—
104–1EF 1
04–EF General-Purpose Registers
—
XXh
—
1F0–203 —
—
—
XXh
—
204–2EF 2
04–EF General-Purpose Registers
—
XXh
—
2F0–303 —
—
—
XXh
—
304–3EF 3
04–EF General-Purpose Registers
—
XXh
—
3F0–3FF —
—
General-Purpose Registers (12-Bit Only)
—
XXh
—
400–CFF —
—
Reserved
—
—
—
D00
D
00
Counter/Timer 8 Control Register
CTR0
0 0 0 0 _0 0 0 0 b
75
D01
D
01
Timer 8 and Timer 16 Common Functions CTR1
0 0 0 0 _0 0 0 0 b
77
D02
D
02
Counter/Timer 16 Control Register
CTR2
0 0 0 0 _0 0 0 0 b
80
D03
D
03
Timer 8/Timer 16 Control Register
CTR3
0 0 0 0 _0 XXXb
81
D04
D
04
Counter/Timer 8 Low Hold Register
TC8L
00h
74
D05
D
05
Counter/Timer 8 High Hold Register
TC8H
00h
74
D06
D
06
Counter/Timer 16 Low Hold Register
TC16L
00h
73
D07
D
07
Counter/Timer 16 High Hold Register
TC16H
00h
73
D08
D
08
Timer 16 Capture Low Register
LO16
00h
72
D09
D
09
Timer 16 Capture High Register
HI16
00h
72
D0A
D
0A
Timer 8 Capture Low Register
LO8
00h
71
D0B
D
0B
Timer 8 Capture High Register
HI8
00h
71
D0C
D
0C
Low-Voltage Detection Register
LVD
1 1 1 1 _1 0 0 0 b
96
General-Purpose Registers (12-Bit Only)
General-Purpose Registers (12-Bit Only)
Page #
D0D–D0F D
0D–0F Reserved
—
—
—
D10–DFF —
—
Reserved (8-Bit access goes to Bank 0)
—
—
—
F00
00
Port Configuration Register
PCON
XXXX_X1 X0 b
20
01–09
Reserved
—
—
—
F
F01–F09 F
PS024406-0106
P R E L I M I N A R Y
Register File Summary
ZLP12840 OTP MCU
Product Specification
41
Table 20. Register File Address Summary (Continued)
Address (Hex)
12-Bit
Bank 8-Bit
Register Description
Mnemonic Reset
F0A
F
0A
Stop-Mode Recovery Register 4
SMR4
XXX0 _0 0 0 0 b
109
F0B
F
0B
Stop-Mode Recovery Register
SMR
0 0 1 0 _0 0 0 0 b
100
F0C
F
0C
Stop-Mode Recovery Register 1
SMR1
00h
103
F0D
F
0D
Stop-Mode Recovery Register 2
SMR2
X0 X0 _0 0 XXb
105
F0E
F
0E
Stop-Mode Recovery Register 3
SMR3
X0h
108
F0F
F
0F
Watch-Dog Timer Mode Register
WDTMR
XXXX_1 1 0 1 b
110
—
Reserved (8-Bit access goes to Bank 0)
—
—
—
F10–FFF —
PS024406-0106
P R E L I M I N A R Y
Page #
Register File Summary
ZLP12840 OTP MCU
Product Specification
42
Infrared Learning Amplifier
The ZLP12840 MCU’s infrared learning amplifier allows the user to detect and decode
infrared transmissions directly from the output of the receiving diode without the need for
external circuitry. See Port 3 on page 14.
An IR diode can be connected to the IR amp as shown in Figure 12. When the IR amp is
enabled and an input current is detected on Port 3, pin 1 (P31), the IR amp outputs a logical High value. When the input current is below the switching threshold of the IR amp, the
amp outputs a logical Low value.
Within the MCU, the IR amp output goes to the capture/timer logic, which can be programmed to demodulate the IR signal. The IR amp output can also be read by the CPU, or
drive the Port 3, pin 4 (P34) output if write-only register bit PCON[0] is written with a 1.
The IR learning amp can demodulate signals up to a frequency of 500 KHz. A special
mode exists that allows the user to capture the third, fourth, and fifth edges of the IR amp
output and generate an interrupt.
VCC
D1
Photodiode
P31 of MCU
Figure 12. Learning Amplification Circuitry with the ZLP12840 MCU
See Timers on page 57 for details about programming the timers to demodulate a received
signal.
PS024406-0106
P R E L I M I N A R Y
Infrared Learning Amplifier
ZLP12840 OTP MCU
Product Specification
43
UART
The universal asynchronous receiver/transmitter (UART) is a full-duplex communication
channel capable of handling asynchronous data transfers. The two UARTs use a single
8-bit data mode with selectable parity. Features of the UARTs include:
•
•
•
•
•
•
•
•
•
8-bit asynchronous data transfer
Selectable even- and odd-parity generation and checking
One or two Stop bits
Separate transmit and receive interrupts
Framing, overrun, and break detection
Separate transmit and receive enables
8-bit Baud Rate Generator (BRG)
Baud Rate Generator timer mode
UART operational during HALT mode
Table 21. UART Control Registers
Address (Hex)
12-Bit
Bank 8-Bit
Register Description
Mnemonic Reset
Page #
0F1
All
F1
UART Receive/Transmit Data Register
URDATA/
UTDATA
XXh
52
0F2
All
F2
UART Status Register
UST
0000_0010b
53
0F3
All
F3
UART Control Register
UCTL
00h
54
0F4
All
F4
UART Baud Rate Generator Constant
BCNST
FFh
55
Architecture
The UARTs consist of three primary functional blocks: transmitter, receiver, and Baud
Rate Generator. The UART transmitter and receiver function independently, but employ
the same baud rate and data format. Figure 13 illustrates the UART architecture.
PS024406-0106
P R E L I M I N A R Y
UART
ZLP12840 OTP MCU
Product Specification
44
RxD
Receive Shifter
Receive Data
Register
Control Registers
System Bus
Transmit Data
Register
Status Register
Baud Rate
Generator
Transmit Shift
Register
TxD
Transmitter Control
Parity Generator
Figure 13. UART Block Diagram
Operation
The UART channel can be used to communicate with a master microprocessor or as a
slave microprocessor, both of which exhibit transmit and receive functionality. A user can
either operate the UART channel by polling the UART Status register or via interrupts.
The UART remains active during HALT mode. If neither the transmitter nor the receiver is
enabled, the UART baud rate generator can be used as an additional timer. The UART
contains a noise filter for the receiver that can be enabled by the user.
Data Format
The UART always transmits and receives data in an 8-bit data format, with the least-significant bit occurring first. An even or odd parity bit can be optionally added to the data
stream. Each character begins with an active Low Start bit and ends with either 1 or 2
active High Stop bits. Figures 14 and 15 illustrate the asynchronous data format employed
by the UARTs without parity and with parity, respectively.
PS024406-0106
P R E L I M I N A R Y
Operation
ZLP12840 OTP MCU
Product Specification
45
1
Data field
Idle state
of line
lsb
Start
msb
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Stop bit(s)
Bit 7
0
1
2
Figure 14. UART Asynchronous Data Format without Parity
1
Data field
Idle state
of line
lsb
Start
Bit 0
Stop bit(s)
msb
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
Bit 7
1
2
Figure 15. UART Asynchronous Data Format with Parity
Transmitting Data Using the Polled Method
Follow the steps below to transmit data using the polled method of operation:
1. Write to the baud rate generator constant (BCNST) register, address ðÚì¸, to set the
appropriate baud rate.
2. Write a 0 to bit 6 of the P01M register.
3. Write to the UART control register (UCTL) to:
a. Set the transmit enable bit, UCTL[7], to enable the UART for data transmission.
b. If parity is appropriate, set the parity enable bit, UCTL[4] to 1 and select either
Even or Odd parity (UCTL[3]).
4. Check the Transmit Status register bit, UST[2], to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data register is full (indicated by a 0), continue to monitor the UST[2] bit until the Transmit
Data register becomes available to receive new data.
5. Write the data byte to the UART Transmit Data register, ðÚï¸. The transmitter automatically transfers the data to the internal transmit shift register and transmits the data.
6. To transmit additional bytes, return to Step 4.
PS024406-0106
P R E L I M I N A R Y
Operation
ZLP12840 OTP MCU
Product Specification
46
7. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If
UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all
data in the Transmit Data and internal shift registers has been transmitted.
Caution: Data written while the transmit enable bit is clear (UCTL[7]=0) will not be transmitted.
Data written while the transmit data status bit is clear (UST[2]=0) overwrites the previous value written, so the previous written value will not be transmitted. Disabling the
UART transmitter while the transmit completion status bit is clear (UST[1]=0) can corrupt the byte being transmitted.
Transmitting Data Using the Interrupt-Driven Method
The UART transmitter interrupt indicates the availability of the Transmit Data register to
accept new data for transmission. Follow these steps to configure the UART for interruptdriven data transmission:
1. Write to the BCNST register to set the appropriate baud rate.
2. Write a 0 to bit 6 of the P01M register.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and
set the appropriate priority.
5. Write to the UART Control register to:
a. Set the transmit enable bit (UCTL bit 7) to enable the UART for data transmission.
b. Enable parity, if appropriate, and select either even or odd parity.
6. Execute an EI instruction to enable interrupts.
7. Because the transmit buffer is empty, an interrupt is immediately executed.
8. Write the data byte to the UART Transmit Data register. The transmitter automatically
transfers the data to the internal transmit shift register and transmits the data.
9. Execute the IRET instruction to return from the interrupt-service routine and wait for
the Transmit Data register to again become empty.
10. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If
UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all
data in the Transmit Data and internal shift registers has been transmitted.
Caution: Data written while the transmit enable bit is clear (UCTL[7]=0) will not be transmitted.
Data written while the transmit data status bit is clear (UST[2]=0) overwrites the previous value written, so the previous written value will not be transmitted. Disabling the
UART transmitter while the transmit completion status bit is clear (UST[1]=0) can corrupt the byte being transmitted.
PS024406-0106
P R E L I M I N A R Y
Operation
ZLP12840 OTP MCU
Product Specification
47
Receiving Data Using the Polled Method
Follow these steps to configure the UART for polled data reception:
1. Write to the BCNST register to set the appropriate baud rate.
2. Write to the UART control register (UCTL) to:
a. Set the receive enable bit (UCTL[6]) to enable the UART for data reception
b. Enable parity, if appropriate and select either even or odd parity
3. Check the receive status bit in the UART Status register, bit UST[7], to determine if
the Receive Data register contains a valid data byte (indicated by a 1). If UST[7] is set
to 1 to indicate available data, continue to Step 4. If the Receive Data register is empty
(indicated by a 0), continue to monitor the UST[7] bit awaiting reception of the valid
data.
4. Read data from the UART Receive Data register.
5. Return to Step 3 to receive additional data.
Receiving Data Using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error conditions). Follow these steps to configure the UART receiver for interrupt-driven operation:
1. Write to the UART BRG Constant registers to set the appropriate baud rate.
2. Execute a DI instruction to disable interrupts.
3. Write to the interrupt control registers to enable the UART receiver interrupt and set
the appropriate priority.
4. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
5. Write to the UART Control register (UCTL) to:
a. Set the receive enable bit (UCTL[6]) to enable the UART for data reception
b. Enable parity, if appropriate, and select either even or odd parity
6. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data reception. When the UART
Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the
following:
1. Checks the UART Status register to determine the source of the interrupt, whether it is
an error, break, or received data.
2. Reads the data from the UART Receive Data register if the interrupt was caused by
data available.
3. Clears the UART receiver interrupt in the applicable Interrupt Request register.
PS024406-0106
P R E L I M I N A R Y
Operation
ZLP12840 OTP MCU
Product Specification
48
4. Executes the IRET instruction to return from the interrupt service routine and await
more data.
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also function as a basic timer with interrupt capability.
Note:
When the UART is set to run at higher baud rates, the UART receiver’s service routine
might not have enough time to read and manipulate all bits in the UART Status register
(especially bits generating error conditions) for a received byte before the next byte is
received. Users are encouraged to devise their own hand-shaking protocol to prevent the
transmitter from transmitting more data while current data is being serviced.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Status bit, UST[2], is set
to 1. This indicates that the transmitter is ready to accept new data for transmission. The
Transmit Status interrupt occurs after the internal transmit shift register has shifted the first
bit of data out. At this point, the Transmit Data register can be written with the next character to send. This provides 7 bit periods of latency to load the Transmit Data register
before the transmit shift register completes shifting the current character. Writing to the
UART Transmit Data register clears the UST[2] bit to 0. The interrupt is cleared by writing a 0 to the Transmit Data register.
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
PS024406-0106
•
A data byte has been received and is available in the UART Receive Data register.
This interrupt can be disabled independent of the other receiver interrupt sources. The
received data interrupt occurs once the receive character has been received and placed
in the Receive Data register. Software must respond to this received data available
condition before the next character is completely received to avoid an overrun error.
The interrupt is cleared by reading from the UART Receive Data register.
•
A break is received. A break is detected when a 0 is sent to the receiver for the full
byte plus the parity and stop bits. After a break is detected, it will interrupt
immediately if there is no valid data in the Receive Data register. If data is present in
the Receive Data register, an interrupt will occur after the UART Receive Data
register is read.
•
An overrun is detected. An overrun occurs when a byte of data is received while there
is valid data in the UART Receive Data register that has not been read by the user. The
interrupt will be generated when the user reads the UART Receive Data register. The
interrupt is cleared by reading the UART Receive Data register. When an overrun
P R E L I M I N A R Y
Operation
ZLP12840 OTP MCU
Product Specification
49
error occurs, the additional data byte will not overwrite the data currently stored in the
UART Receive Data register.
•
Note:
A data framing error is detected. A data framing error is detected when the first stop
bit is 0 instead of 1. When configured for 2 stop bits, a data framing error is only
detected when the first stop bit is 0. A framing error interrupt is generated when the
framing error is detected. Reading the UART Receive Data register clears the
interrupt.
It is important to ensure that the transmitter uses the same stop bit configuration as the
receiver.
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data register. The Break Detect and Overrun status bits are not
displayed until after the valid data has been read.
After the valid data has been read, the UART Status (UST) register is updated to indicate
the overrun condition (and Break Detect, if applicable). The UST[7] bit is set to 1 to indicate that the Receive Data register contains a data byte. However, because the overrun
error occurred, this byte may not contain valid data and should be ignored. The Break
Detect bit, UST[3], indicates if the overrun was caused by a break condition on the line.
After reading the status byte indicating an overrun error, the Receive Data register must be
read again to clear the error bits is the UART Status 0 register. Updates to the Receive
Data register occur only when the next data word is received.
UART Data and Error Handling Procedure
Figure 16 illustrates the recommended procedure for use in UART receiver interrupt service routines.
PS024406-0106
P R E L I M I N A R Y
Operation
ZLP12840 OTP MCU
Product Specification
50
Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read data that clears
the RDA bit and
resets the error bits
Read Data
Discard Data
Figure 16. UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts
If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt
asserts when the UART Baud Rate Generator reloads. This action allows the Baud Rate
Generator to function as an additional counter if the UART functionality is not employed.
UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data transmission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate
Constant register contains an 8-bit baud rate divisor value (BCNST[7:0]) that sets the data
PS024406-0106
P R E L I M I N A R Y
Operation
ZLP12840 OTP MCU
Product Specification
51
transmission rate (baud rate) of the UART. For programmed register values other than
ðð¸, the UART data rate is calculated using the following equation:
UART Data Rate (bits/s) =
System Clock Frequency (Hz)
16 x UART Baud Rate Divisor Value (BCNST)
When the UART Baud Rate Low Register is programmed to ðð¸, the UART data rate is
calculated as follows:
UART Data Rate (bits/s) =
System Clock Frequency (Hz)
4096
When the UART Baud Rate Generator is used as a general-purpose counter, the counters
time out period can be computed as follows based upon the counters clock input being a
divide by 16 of the system clock and the maximum count value being 255:
Time Out Period: (us)
Note:
=
16 x UART Baud Rate Divisor Value (BCNST)
System Clock Frequency (Mhz)
In general, the system clock frequency is the XTAL clock frequency divided by 2.
When the UART is disabled, the Baud Rate Generator can function as a basic 8-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, perform the following procedure:
1. Disable the UART by clearing the receive and transmit enable bits, UCTL[7:6] to 0.
2. Load the appropriate 8-bit count value into the UART Baud Rate Generator Constant
register. The count frequency is the system clock frequency in Hz divided by 16.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
Baud Rate Generator bit (UCTL bit 0) in the UART Control Register to 1. When configured as an 8-bit timer, the count value, instead of the reload value, is read, and the
counter begins counting down from its initial programmed value. Upon timing out
(reaching a value of 1), if the time-out interrupt is enabled, an interrupt will be produced. The counter will then reload its programmed start value and begin counting
down again.
Table 22 lists a number of BCNST register settings at various baud rates and system clock
frequencies.
PS024406-0106
P R E L I M I N A R Y
Operation
ZLP12840 OTP MCU
Product Specification
52
Table 22. BCNST Register Settings Examples
Target UART Data
Rate (baud)
System Clock = 4 MHz,
Crystal Clock = 8 MHz
System Clock = 3 MHz,
Crystal Clock = 6 MHz
2400
BCNST = 01101000
Actual baud rate = 2403
BCNST = 01001110
Actual baud rate = 2403
4800
BCNST = 00110100
Actual baud rate = 4807
BCNST = 00100111
Actual baud rate = 4807
9600
BCNST = 00011010
Actual baud rate = 9615
BCNST = 00010100
Actual baud rate = 9375
19200
BCNST = 00001101
Actual baud rate = 19230
BCNST = 00001010
Actual baud rate = 18750
UART Receive Data Register/UART Transmit Data Register
The UART Receive/Transmit Data Register is used to send and retrieve data from the
UART channel. When the UART receives a byte of data, it can be read from this register.
The UART receive interrupt is cleared when this register is used. Data written to this register is transmitted by the UART. See Table 23.
Table 23. UART Receive/Transmit Data Register (URDATA/UTDATA)
Bit
7
6
5
4
3
2
1
0
UART Receive/Transmit
Field
Reset
R/W
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bank Independent: F1h; Linear: 0F1h
Bit
Position Description
[7:0]
UART Receive/Transmit
When read, returns received data.
When written, transmits written data.
PS024406-0106
P R E L I M I N A R Y
UART Receive Data Register/UART
ZLP12840 OTP MCU
Product Specification
53
UART Status Register
The UART Status Register shows the status of the UART. Bits [6:3] are cleared by reading
the UART Receive/Transmit Register (Úï¸). See Table 24.
Table 24. UART Status Register (UST)
Bit
Field
7
6
5
4
3
2
1
0
Receive
Status
Parity
Error
Overrun
Error
Framing
Error
Break
Transmit
Data
Transmit
Complete
Noise
Filter
Reset
R/W
0
0
0
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bit
Position
Bank Independent: F2h; Linear: 0F2h
Value Description
[7]
0
1
Receive Status—Set when data is received; cleared when URDATA is read.
UART Receive Data Register empty.
UART Receive Data Register full.
0
1
Parity—Set when a parity error occurs; cleared when URDATA is read.
No parity error occurs.
Parity error occurs.
0
1
Overrun—Set when an overrun error occurs; cleared when URDATA is read.
No overrun error occurs.
Overrun error occurs.
0
1
Framing—Set when a framing error occurs; cleared when URDATA is read.
No framing error occurs.
Framing error occurs.
0
1
Break—Set when a break is detected; cleared when URDATA is read.
No break occurs.
Break occurs.
0
1
Transmit Data Status—Set when the UART is ready to transmit; cleared when
TRDATA is written.
Do not write to the UART Transmit Data Register.
UART Transmit Data Register ready to receive additional data.
0
1
Transmit Completion Status
Data is currently transmitting.
Transmission is complete.
[6]
[5]
[4]
[3]
[2]
[1]
PS024406-0106
P R E L I M I N A R Y
UART Status Register
ZLP12840 OTP MCU
Product Specification
54
Bit
Position
Value Description
Read: Noise Filter—Detects noise during data reception.
No noise detected.
0
Noise detected.
1
[0]
Write:
0
Turn off noise filter.
1
Turn on noise filter.
UART Control Register
As its name implies, the UART Register controls the UART. In addition to setting bit 5,
the user must also set appropriate bit in the Interrupt Mask Register (Table 45, Interrupt
Mask Register (IMR), on page 90). See Table 25.
This register is not reset after a stop-mode recovery.
Note:
Table 25. UART Control Register (UCTL)
Bit
Field
7
6
Transmitter Receiver
Enable
Enable
Reset
R/W
5
4
3
2
UART
Interrupts
Enable
Parity
Enable
Parity
Select
Send
Break
1
0
Stop Bits Baud Rate
Generator
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bank Independent: F3h; Linear: 0F3h
Bit
Position Value Description
[7]
0
1
Transmitter disabled.
Transmitter enabled.
[6]
0
1
Receiver disabled.
Receiver enabled.
[5]
0
1
UART Interrupts disabled.
UART Interrupts enabled.
[4]
0
1
Parity disabled.
Parity enabled.
[3]
0
1
Even parity selected.
Odd parity selected.
PS024406-0106
P R E L I M I N A R Y
UART Control Register
ZLP12840 OTP MCU
Product Specification
55
Bit
Position Value Description
[2]
0
1
No break is sent.
Send Break (force Tx output to 0).
[1]
0
1
One stop bit.
Two stop bits.
0
1
Baud Rate Generator—When the transmitter and receiver are disabled, the BRG can
be used as an additional timer. When setting this bit, clear bits [7:6] in this register. Also
set bit [5] if an interrupt is desired when the BRG is reloaded.
BRG used as Baud Rate Generator for UART.
BRG used as timer.
[0]
Baud Rate Generator Constant Register
The UART baud rate generator determines the frequency at which UART data is received
and transmitted. This baud rate is determined by the following formula:
UART Data Rate (bits/s) =
System Clock Frequency (Hz)
16 x UART Baud Rate Divisor Value (BCNST)
The system clock is usually the crystal clock divided by 2.
When the UART baud rate generator is used as an additional timer, a Read from this register will return the actual value of the count of the BRG in progress and not the reload
value. See Table 26.
Note:
This register is not reset after a stop-mode recovery.
Table 26. Baud Rate Generator Constant Register (BCNST)
Bit
7
6
5
R/W
3
2
1
0
Baud Rate Generator Constant
Field
Reset
4
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bank Independent: F4h; Linear: 0F4h
PS024406-0106
P R E L I M I N A R Y
Baud Rate Generator Constant Register
ZLP12840 OTP MCU
Product Specification
56
Bit
Position
[7:0]
Description
BRG Constant
When read, returns the actual timer count value (when UCTL[0]=1).
When written, sets the Baud Rate Generator Constant. The actual baud rate frequency =
XTAL ÷ (32 x BCNST).
PS024406-0106
P R E L I M I N A R Y
Baud Rate Generator Constant Register
ZLP12840 OTP MCU
Product Specification
57
Timers
The Crimzon™ ZLP12840 MCU infrared timer contains a 16-bit and an 8-bit counter/
timer, each of which can be used simultaneously for transmitting. In addition, both timers
can be used for demodulating an input carrier wave. Both timers share a single input pin.
Figure 17 on page 57 illustrates the counter/timer architecture, which is designed to help
unburden the program from coping with such real-time problems as generating complex
waveforms or receiving and demodulating complex waveforms and pulses.
In addition to the 16-bit and 8-bit timers, the UART’s baud rate generator can be used as
an additional 8-bit timer when the UART receiver is not in use. See UART on page 43.
Ø×ïê
ÔÑïê
è
è
ïêóÞ·¬ Ì·³»® ïê
ï
î
ì
è
Ì·³»® ïê
ïê
è
è
Ý´±½µ
Ü·ª·¼»®
ÍÝÔÕ
ÌÝïêØ
ÌÝïêÔ
ßÒÜñÑÎ
Ô±¹·½
Ø×è
ÔÑè
è
Ù´·¬½¸
Ú·´¬»®
Û¼¹»
Ü»¬»½¬
Ý·®½«·¬
è
Ì·³»® è
èóÞ·¬ Ì·³»® è
è
ÌÝèØ
Ì·³»® èñïê
è
ÌÝèÔ
Figure 17. Counter/Timers Block Diagram
PS024406-0106
P R E L I M I N A R Y
Timers
ZLP12840 OTP MCU
Product Specification
58
Table 27 Summarizes the registers used to control timers. Some timer functions can also
be affected by control registers for other peripheral functions.
Table 27. Timer Control Registers
Address (Hex)
12-Bit
Bank 8-Bit
Register Description
Mnemonic Reset
Page #
D00
D
00
Counter/Timer 8 Control Register
CTR0
0000_00 0 0 b
75
D01
D
01
Timer 8 and Timer 16 Common Functions
CTR1
0000_00 0 0 b
77
D02
D
02
Counter/Timer 16 Control Register
CTR2
0000_00 0 0 b
80
D03
D
03
Timer 8/Timer 16 Control Register
CTR3
0000_0XXXb
81
D04
D
04
Counter/Timer 8 Low Hold Register
TC8L
00h
74
D05
D
05
Counter/Timer 8 High Hold Register
TC8H
00h
74
D06
D
06
Counter/Timer 16 Low Hold Register
TC16L
00h
73
D07
D
07
Counter/Timer 16 High Hold Register
TC16H
00h
73
D08
D
08
Timer 16 Capture Low Register
LO16
00h
72
D09
D
09
Timer 16 Capture High Register
HI16
00h
72
D0A
D
0A
Timer 8 Capture Low Register
LO8
00h
71
D0B
D
0B
Timer 8 Capture High Register
HI8
00h
71
Counter/Timer Functional Blocks
The Crimzon™ ZLP12840 MCU infrared timer contains a glitch filter for removing noise
from the input when demodulating an input carrier. Each timer features its own demodulating mode. The T8 timer has the ability to capture only one cycle of a carrier wave of a
high-frequency waveform. Each timer can be simultaneously used to generate a signal
output.
Input Circuit
Depending on the setting of register bits P3M[2:1] and CTR1[6], the timer/counter input
monitors one of the following conditions:
•
•
•
•
PS024406-0106
The P31 digital signal, if CTR1[6]=0 and P3M[2:1]=00.
The P31 analog comparator output, if CTR1[6]=0 and P3M[2:1]=01.
The P31 IR amplifier output, if CTR1[6]=0 and P3M[2]=1.
The P20 digital signal, if CTR16=1.
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
59
Based on register bits CTR1[5:4], a pulse is generated at when a rising edge, falling edge,
or any edge is detected. Glitches in the input signal are filtered out if they are shorter than
the glitch filter width specified in register bits CTR1[3:2]. The input circuit is illustrated in
Figure 18.
ÐíÓÅïÃ
ð
Ðíï
ÐíÓÅîÃ
õ
Ðíð
ݱ³°ò
P
ð
ÝÌÎïÅêÃ
ÝÌÎïÅíæîÃ
ï
Û¼¹» Ü»¬»½¬·±²
ð
×ÎÛÚ
ÝÌÎïÅëæìÃ
õ
×Î
ß³°ò
P
Ù´·¬½¸ Ú·´¬»®
ðð
ðð
ì ÍÝÔÕ
ðï
ïð
è ÍÝÔÕ
ïð
ðï
λ-»®ª»¼
ïï
ïï
ï
ï
Ðîð
Ú¿´´·²¹ Û¼¹»
ÝÌÎïÅðÃ
η-·²¹ Û¼¹»
ÝÌÎïÅïÃ
λ-»®ª»¼
Figure 18. Counter/Timer Input Circuit
T8 Transmit Mode
Before T8 is enabled, the output of T8 depends on CTR1, bit 1. If it is 0, T8_OUT is 1; if
it is 1, T8_OUT is 0. See Figure 19.
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
60
Ìè øèóÞ·¬÷
Ì®¿²-³·¬ Ó±¼»
Ò±
ÌèÁÛ²¿¾´» Þ·¬ Í»¬
ÝÌÎðô ¾·¬ é
λ-»¬ ÌèÁÛÒßÞÔÛ Þ·¬
Ç»ð
ï
ÝÌÎïô ¾·¬ ï
Ê¿´«»
Ô±¿¼ ÌÝèÔ
λ-»¬ ÌèÁÑËÌ
Ô±¿¼ ÌÝèØ
Í»¬ ÌèÁÑËÌ
Í»¬ Ì·³»óÑ«¬ ͬ¿¬«- Þ·¬
øÝÌÎð ¾·¬ ë÷ ¿²¼ ¹»²»®¿¬»
Ì×ÓÛÑËÌÁ×ÒÌ ·º »²¿¾´»¼
Û²¿¾´» Ìè
Ò±
ÌèÁÌ×ÓÛÑËÌ
Ç»-
Í·²¹´» п--
Ç»-
Í·²¹´» п--á
Ó±¼«´±óÒ
Ò±
ï
ð
ÌèÁÑËÌ Ê¿´«»
Ô±¿¼ ÌÝèÔ
λ-»¬ ÌèÁÑËÌ
Ô±¿¼ ÌÝèØ
Í»¬ ÌèÁÑËÌ
Û²¿¾´» Ìè
Ò±
Í»¬ Ì·³»óÑ«¬ ͬ¿¬«- Þ·¬
øÝÌÎðô ¾·¬ ë÷ ¿²¼ ¹»²»®¿¬»
Ì×ÓÛÑËÌÁ×ÒÌ ·º »²¿¾´»¼
ÌèÁÌ×ÓÛÑËÌ
Ç»-
Figure 19. Transmit Mode Flowchart
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
61
When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, bit 1). If the
initial value (CTR1, bit 1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the
counter. In SINGLE-PASS mode (CTR0, Bit 6), T8 counts down to 0 and stops, T8_OUT
toggles, the time-out status bit (CTR0, bit 5) is set, and a time-out interrupt can be generated if it is enabled (CTR0, bit 1). In MODULO-N mode, upon reaching terminal count,
T8_OUT is toggled, but no interrupt is generated. From that point, T8 loads a new count
(if the T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts
down to 0, toggles T8_OUT, and sets the time-out status bit (CTR0, bit 5), thereby generating an interrupt if enabled (CTR0, bit 1). One cycle is thus completed. T8 then loads
from TC8H or TC8L according to the T8_OUT level and repeats the cycle. See Figure 20.
Æè ÔÈÓ Ü¿¬¿ Þ«-
ÝÌÎ𠼿¬¿ ¾·¬ î
б-·¬·ª» Û¼¹»
×ÎÏì
Ò»¹¿¬·ª» Û¼¹»
Ø×è
ÔÑè
ÝÌÎ𠼿¬¿ ¾·¬- ÅìæíÃ
ÍÝÔÕ
ÝÌÎ𠼿¬¿ ¾·¬ ï
Ý´±½µ
Í»´»½¬
Ý´±½µ
èóÞ·¬
ݱ«²¬»® Ìè
øÌÝè÷
ÌÝèØ
ÌèÁÑËÌ
ÌÝèÔ
Æè ÔÈÓ Ü¿¬¿ Þ«-
Figure 20. 8-Bit Counter/Timer Circuits
You can modify the values in TC8H or TC8L at any time. The new values take effect
when they are loaded.
Caution: An initial count of 1 is not allowed (a non-function occurs). An initial count of 0 causes
TC8 to count from 0 to ÚÚ¸ to ÚÛ¸.
Note:
The “h” suffix denotes hexadecimal values.
Note:
Transition from 0 to ÚÚ¸ is not a time-out condition.
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
62
Caution:
Using the same instructions for stopping the counter/timers and setting the status bits is
not recommended.
Two successive commands are necessary. First, the counter/timers must be stopped. Second, the status bits must be reset. These commands are required because it takes one
counter/timer clock interval for the initiated event to actually occur. See Figures 21 and
22.
ÌÝèØ Ý±«²¬-
ݱ«²¬»® Û²¿¾´» ½±³³¿²¼å
ÌèÁÑËÌ -©·¬½¸»- ¬± ·¬·²·¬·¿´ ª¿´«» øÝÌÎï ¼¿¬¿ ¾·¬ ï÷
ÌèÁÑËÌ ¬±¹¹´»-å
¬·³»ó±«¬ ·²¬»®®«°¬
Figure 21. T8_OUT in Single-Pass Mode
ÌèÁÑËÌ ¬±¹¹´»-
ÌèÁÑËÌ
ÌÝèÔ
ÌÝèØ
ݱ«²¬»® Û²¿¾´» ½±³³¿²¼ô
ÌèÁÑËÌô -©·¬½¸»- ¬± ·¬·²·¬·¿´ ª¿´«» øÝÌÎï ¼¿¬¿ ¾·¬ ï÷
ÌÝèÔ
Ì·³»ó±«¬ ·²¬»®®«°¬
ÌÝèØ
ÌÝèÔ
Ì·³»ó±«¬ ·²¬»®®«°¬
Figure 22. T8_OUT in Modulo-N Mode
T8 Demodulation Mode
The user must program TC8L and TC8H to ÚÚ¸. After T8 is enabled, when the first edge
(rising, falling, or both depending on CTR1 bits [5:4]) is detected, it starts to count down.
When a subsequent edge (rising, falling, or both depending on CTR1 bits [5:4]) is detected
during counting, the current value of T8 is complemented and put into one of the capture
registers. If it is a positive edge, data is put into LO8; if it is a negative edge, data is put
into HI8. From that point, one of the edge detect status bits (CTR1, bits [1:0]) is set, and
an interrupt can be generated if enabled (CTR0, bit 2). Meanwhile, T8 is loaded with ÚÚ¸
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
63
and starts counting again. If T8 reaches 0, the time-out status bit (CTR0, bit 5) is set, and
an interrupt can be generated if enabled (CTR0, bit 1). T8 then continues counting from
ÚÚ¸. See Figure 23.
Ìè øèó¾·¬÷
ݱ«²¬ Ý¿°¬«®»
Ò±
ÌèÁÛ²¿¾´»
øÍ»¬ Þ§ Ë-»®÷
Ç»-
Û¼¹» Ю»-»²¬á
Ò±
Ç»-
Ò»¹
бɸ¿¬ Õ·²¼ Ѻ Û¼¹»á
Ìè
ÔÑè
Ìè
ûÚÚ
Ø×è
Ìè
Figure 23. Demodulation Mode Count Capture Flowchart
When bit 4 of CTR3 is enabled, the flow of the demodulation sequence is altered. The
third edge makes T8 active, and the fourth and fifth edges are captured. The capture interrupt is activated after the fifth event occurs. This mode is useful for capturing the carrier
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
64
duty cycle as well as the frequency at which the first cycle is corrupted. See Figures 24
and 25.
Ìè øèóÞ·¬÷
Ü»³±¼«´¿¬·±² Ó±¼»
Ò±
ÌèÁÛ²¿¾´»
ÝÌÎðô Üéá
Ç»-
ûÚÚ
Ò±
ÌÝè
Ú·®-¬
Û¼¹» Ю»-»²¬á
Ç»-
Û²¿¾´» ÌÝè
Ü·-¿¾´» Ìè
ÌèÁÛ²¿¾´» Þ·¬ Í»¬á
Ò±
Ç»-
Û¼¹» Ю»-»²¬á
Ò±
Ç»Ìè Ì·³» Ñ«¬á
Í»¬ Û¼¹» Ю»-»²¬ ͬ¿¬«Þ·¬ ¿²¼ Ì®·¹¹»® Ü¿¬¿
Ý¿°¬«®» ײ¬ò ·º Û²¿¾´»¼
Ò±
ǻͻ¬ Ì·³»óÑ«¬ ͬ¿¬«Þ·¬ ¿²¼ Ì®·¹¹»® Ì·³»
Ñ«¬ ײ¬ò ·º Û²¿¾´»¼
ݱ²¬·²«» ݱ«²¬·²¹
Figure 24. Demodulation Mode Flowchart
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
65
Ìè øèóÞ·¬÷
Ü»³±¼«´¿¬·±² Ó±¼»
Ò±
ÌèÁÛ²¿¾´»
ÝÌÎð ¾·¬ é
Ç»-
ÚÚ¸
Ò±
ÌÝè
̸·®¼
Û¼¹» Ю»-»²¬
Ç»-
Û²¿¾´» ÌÝè
Ü·-¿¾´» Ìè
ÌèÁÛ²¿¾´» Þ·¬ Í»¬
Ò±
Ç»-
Ú±«®¬¸
Û¼¹» Ю»-»²¬
Ç»-
Ò±
Ú·º¬¸
Û¼¹» Ю»-»²¬
ǻͻ¬ Û¼¹» Ю»-»²¬ ͬ¿¬«Ý¿°¬«®» ·²¬»®®«°¬
·º »²¿¾´»¼
Í»¬ Û¼¹» Ю»-»²¬ ͬ¿¬«Þ·¬ ¿²¼ Ì®·¹¹»® Ü¿¬¿
Ìè Ì·³» Ñ«¬
Ò±
ǻͻ¬ Ì·³»óÑ«¬ ͬ¿¬«Þ·¬ ¿²¼ Ì®·¹¹»® Ì·³»
Ñ«¬ ײ¬»®®«°¬ ·º »²¿¾´»¼
ݱ²¬·²«» ݱ«²¬·²¹
Figure 25. Demodulation Mode Flowchart with Bit 4 of CTR3 Set
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
66
T16 Transmit Mode
In NORMAL or PING-PONG mode, the output of T16 when not enabled, is dependent on
CTR1, bit 0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can force the output of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 bits [3:2]
to a 10 or 11.
When bit 4 of CTR3 is set, the T16 output does not update. However, time-out interrupts
(flags) are still updated. In addition, the T8 carrier is not disrupted by timing out of the
T16 timer.
When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its
initial value (CTR1, bit 0). When T16 counts down to 0, T16_OUT is toggled (in NORMAL or PING-PONG mode), an interrupt (CTR2, bit 1) is generated (if enabled), and a
status bit (CTR2, bit 5) is set. See Figure 26.
Æè ÔÈÓ Ü¿¬¿ Þ«-
ÝÌÎî ¼¿¬¿ ¾·¬ î
б-·¬·ª» Û¼¹»
×ÎÏí
Ò»¹¿¬·ª» Û¼¹»
Ø×ïê
ÔÑïê
ÝÌÎî ¼¿¬¿ ¾·¬- ÅìæíÃ
ÝÌÎî ¼¿¬¿ ¾·¬ ï
Ý´±½µ
Í»´»½¬
ÍÝÔÕ
Ý´±½µ
ÌÝïê
ïêóÞ·¬
ݱ«²¬»® Ìïê
øÌÝïê÷
ÌïêÁÑËÌ
ÌÝïê
Æè ÔÈÓ Ü¿¬¿ Þ«-
Figure 26. 16-Bit Counter/Timer Circuits
Note:
Global interrupts override this function as described in the Interrupts chapter on page 83.
If T16 is in SINGLE-PASS mode, it is stopped at this point (see Figure 27). If it is in
MODULO-N mode, it is loaded with TC16H * 256 + TC16L, and the counting continues
(see Figure 28).
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
67
You can modify the values in TC16H and TC16L at any time. The new values take effect
when they are loaded.
Caution: Do not load these registers at the time the values are to be loaded into the counter/timer
to ensure known operation. An initial count of 1 is not allowed. An initial count of 0
causes T16 to count from 0 to ÚÚÚÛ¸. Transition from 0 to ÚÚÚÚ¸ is not a time-out condition.
ÌÝïêØ ö îëê õ ÌÝïêÔ Ý±«²¬-
ݱ«²¬»® Û²¿¾´» ½±³³¿²¼ô
ÌïêÁÑËÌô -©·¬½¸»- ¬± ·¬·²·¬·¿´ ª¿´«» øÝÌÎï ¼¿¬¿ ¾·¬ ð÷
ÌïêÁÑËÌ ¬±¹¹´»-ô
Ì·³»ó±«¬ ·²¬»®®«°¬
Figure 27. T16_OUT in Single-Pass Mode
ÌÝïêØ ö îëê õ ÌÝïêÔ
ÌïêÁÑËÌ
ÌÝïêØ ö îëê õ ÌÝïêÔ
ÌÝïêØ ö îëê õ ÌÝïêÔ
ݱ«²¬»® Û²¿¾´» ½±³³¿²¼ô
ÌïêÁÑËÌô -©·¬½¸»- ¬± ·¬·²·¬·¿´ ª¿´«» øÝÌÎï ¼¿¬¿ ¾·¬ ð÷
ÌïêÁÑËÌ ¬±¹¹´»-ô
Ì·³»ó±«¬ ·²¬»®®«°¬
ÌïêÁÑËÌ ¬±¹¹´»-ô
Ì·³»ó±«¬ ·²¬»®®«°¬
Figure 28. T16_OUT in Modulo-N Mode
T16 Demodulation Mode
The user must program TC16L and TC16H to ÚÚ¸. After T16 is enabled, and the first
edge (rising, falling, or both depending on CTR1 bits [5:4]) is detected, T16 captures HI16
and LO16, reloads, and begins counting.
If Bit 6 of CTR2 Is 0. When a subsequent edge (rising, falling, or both depending on
CTR1 bits [5:4]) is detected during counting, the current count in T16 is complemented
and put into HI16 and LO16. When data is captured, one of the edge detect status bits
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
68
(CTR1, bit 1; bit 0) is set, and an interrupt is generated if enabled (CTR2, Bit 2). T16 is
loaded with ÚÚÚÚ¸ and starts again.
This T16 mode is generally used to measure space time, the length of time between bursts
of carrier signal (marks).
If Bit 6 of CTR2 Is 1. T16 ignores the subsequent edges in the input signal and continues
counting down. A time-out of T8 causes T16 to capture its current value and generate an
interrupt if enabled (CTR2, Bit 2). In this case, T16 does not reload and continues counting. If CTR2 bit 6 is toggled (by writing a 0 then a 1 to it), T16 captures and reloads on the
next edge (rising, falling, or both depending on CTR1 bits [5:4]), continuing to ignore subsequent edges.
This T16 mode generally measures mark time, the length of an active carrier signal burst.
If T16 reaches 0, T16 continues counting from ÚÚÚÚ¸. Meanwhile, a status bit (CTR2 bit
5) is set, and an interrupt time-out can be generated if enabled (CTR2 bit 1).
Ping-Pong Mode
This operation mode is only valid in TRANSMIT mode. T8 and T16 must be programmed
in SINGLE-PASS mode (CTR0, bit 6; CTR2, bit 6), and Ping-Pong mode must be programmed in CTR1 bits [3:2]. The user can begin the operation by enabling either T8 or
T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial
value (CTR1, bit 1). According to T8_OUT's level, TC8H or TC8L is loaded into T8.
After the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT then
switches to its initial value (CTR1, bit 0), data from TC16H and TC16L is loaded, and T16
starts to count. After T16 reaches the terminal count, it stops, T8 is enabled again, repeating the entire cycle. Interrupts can be allowed when T8 or T16 reaches terminal control
(CTR0, bit 1; CTR2, bit 1). To stop the ping-pong operation, write 00 to bits CTR1 bits
[3:2]. See Figure 29.
Note:
PS024406-0106
Enabling ping-pong operation while the counter/timers are running might cause intermittent counter/timer function. Disable the counter/timers and reset the status flags before
instituting this operation.
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
69
Û²¿¾´»
ÌÝè
Ì·³»óÑ«¬
Û²¿¾´»
з²¹óб²¹
ÝÌÎï ¼¿¬¿ ¾·¬- ÅíæîÃ
ÌÝïê
Ì·³»óÑ«¬
Figure 29. Ping-Pong Mode Diagram
Initiating PING-PONG Mode
First, ensure that both counter/timers are not running. Set T8 into SINGLE-PASS mode
(CTR0, bit 6), set T16 into SINGLE-PASS mode (CTR2, bit 6), and set the Ping-Pong
mode (CTR1 bits [3:2]). These instructions are not consecutive and can occur in random
order. Finally, start PING-PONG mode by enabling either T8 (CTR0, D7) or T16 (CTR2,
D7). The initial value of T8 or T16 must not be ï. If you stop the timer and restart the
timer, reload the initial value to avoid an unknown previous value.
During PING-PONG Mode
The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by
hardware. The time-out bits (CTR0, bit 5; CTR2, bit 5) are set every time the counter/timers reach the terminal count.
Timer Output
The output logic for the timers is illustrated in Figure 30. P34 is used to output T8_OUT
when bit 0 of CTR0 is set. P35 is used to output the value of T16_OUT when bit 0 of
CTR2 is set. When bit 6 of CTR1 is set, P36 outputs the logic combination of T8_OUT
and T16_OUT via bits [4:5] of CTR1.
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Functional Blocks
ZLP12840 OTP MCU
Product Specification
70
ÐíìÁ×ÒÌÛÎÒßÔ
ÓËÈ
Ðíì
ÝÌÎ𠼿¬¿ ¾·¬ ð
ÌèÁÑËÌ
ÌïêÁÑËÌ
ÝÌÎï ¼¿¬¿ ¾·¬ î
ÐíêÁ×ÒÌÛÎÒßÔ
ßÒÜñÑÎñÒÑÎñÒßÒÜ
Ô±¹·½
ÓËÈ
Ðíê
ÓËÈ
ÝÌÎï ¼¿¬¿ ¾·¬ ê
ÝÌÎï ¼¿¬¿ ¾·¬- ÅëæìÃ
ÝÌÎï ¼¿¬¿ ¾·¬ í
ÐíëÁ×ÒÌÛÎÒßÔ
ÓËÈ
Ðíë
ÝÌÎî ¼¿¬¿ ¾·¬ ð
Figure 30. Output Circuit
Counter/Timer Registers
The following sections describe each of the Timer/Counter registers in detail.
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
71
Timer 8 Capture High Register
The Timer 8 Capture High Register holds the captured data from the output of the 8-bit
Counter/Timer 0. Typically, this register contains the number of counts when the input signal is 1.
This register is not reset after a stop-mode recovery.
Note:
Table 28. Timer 8 Capture High Register (HI8)
Bit
7
6
5
4
3
2
1
0
T8_Capture_HI
Field
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Bank D: 0Bh; Linear: D0Bh
Bit
Position
[7:0]
Value
Description
0hh–FFh T8_Capture_HI—Reads return captured data. Writes have no effect.
Timer 8 Capture Low Register
The Timer 8 Capture Low Register holds the captured data from the output of the 8-bit
Counter/Timer 0. Typically, this register contains the number of counts when the input signal is 0.
This register is not reset after a stop-mode recovery.
Note:
Table 29. Timer 8 Capture Low Register (L08)
Bit
7
6
5
4
3
2
1
0
T8_Capture_LO
Field
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Bit
Position
[7:0]
Bank D: 0Ah; Linear: D0Ah
Value
Description
0hh–FFh T8_Capture_LO—Read returns captured data. Writes have no effect.
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
72
Timer 16 Capture High Register
The Timer 16 Capture High Register holds the captured data from the output of the 16-bit
Counter/Timer 16. This register contains the most significant byte (MSB) of the data.
This register is not reset after a stop-mode recovery.
Note:
Table 30. Timer 16 Capture High Register (HI16)
Bit
7
6
5
4
3
2
1
0
T16_Capture_HI
Field
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Bank D: 09h; Linear: D09h
Bit
Position
[7:0]
Value
Description
0hh–FFh T16_Capture_HI—Read returns captured data. Writes have no effect.
Timer 16 Capture Low Register
The Timer 16 Capture Low Register holds the captured data from the output of the 16-bit
Counter/Timer 16. This register contains the LSB of the data.
This register is not reset after a stop-mode recovery.
Note:
Table 31. Timer 16 Capture Low Register (L016)
Bit
7
6
5
4
3
2
1
0
T16_Capture_LO
Field
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Bit
Position
[7:0]
Bank D: 08h; Linear: D08h
Value
Description
0hh–FFh T16_Capture_LO—Read returns captured data. Writes have no effect.
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
73
Counter/Timer 16 High Hold Register
The Counter/Timer 16 High Hold Register contains the high byte of the value loaded into
the T16 timer.
This register is not reset after a stop-mode recovery.
Note:
Table 32. Counter/Timer 16 High Hold Register (TC16H)
Bit
7
6
5
4
3
2
1
0
T16_Data_HI
Field
Reset
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bank D: 07h; Linear: D07h
Bit
Position
[7:0]
Value
Description
0hh–FFh T16_Data_HI—Read/Write Data.
Counter/Timer 16 Low Hold Register
The Counter/Timer 16 Low Hold Register contains the low byte of the value loaded into
the T16 timer.
This register is not reset after a stop-mode recovery.
Note:
Table 33. Counter/Timer 16 Low Hold Register (TC16L)
Bit
7
6
5
Reset
R/W
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
[7:0]
3
T16_Data_LO
Field
Bit
Position
4
Bank D: 06h; Linear: D06h
Value
Description
0hh–FFh T16_Data_LO—Read/Write Data.
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
74
Counter/Timer 8 High Hold Register
The Counter/Timer 8 High Hold Register contains the value to be counted while the T8
output is 1.
This register is not reset after a stop-mode recovery.
Note:
Table 34. Counter/Timer 8 High Hold Register (TC8H)
Bit
7
6
5
4
3
2
1
0
T8_Level_HI
Field
Reset
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bank D: 05h; Linear: D05h
Bit
Position
Value
[7:0]
Description
0hh–FFh T8_Level_HI—Read/Write Data.
Counter/Timer 8 Low Hold Register
The Counter/Timer 8 Low Hold Register contains the value to be counted while the T8
output is 0.
This register is not reset after a stop-mode recovery.
Note:
Table 35. Counter/Timer 8 Low Hold Register (TC8L)
Bit
7
6
5
Reset
0
0
0
R/W
2
1
0
0
0
0
0
0
R/W
R/W
R/W
Bank D: 04h; Linear: D04h
Address
[7:0]
3
T8_Level_LO
Field
Bit
Position
4
R/W
Value
R/W
R/W
R/W
R/W
Description
0hh–FFh T8_Level_LO—Read/Write Data.
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
75
Counter/Timer 8 Control Register
The Counter/Timer 8 Control Register controls the timer function of the T8 timer. This
Bank D register is described in Table 36.
Caution: Writing a 1 to CTR0[5] is the only way to reset the Terminal Count status condition. Reset this bit before using/enabling the counter/timers.
Be careful when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1,
bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write sequence
in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the
designated value and then written back into the registers.
Note:
Example: When the status of bit 5 is 1, a timer reset condition occurs.
Table 36. Counter/Timer 8 Control Register (CTR0)
Bit
7
6
Field
T8_Enable
Single/
Modulo-N
Reset
0
0
0
R/W
R/W
R/W
R/W
Address
Bit
Position
4
3
2
1
0
Capture_INT_M Counter_INT_M
Time_Out T8 _Clock
P34_Out
ask
ask
0
0
R/W R/W
0
0
0
R/W
R/W
R/W
Bank D: 00h; Linear: D00h
Value Description
[7]
0
1
T8_Enable—Disable/enable the T8 counter.
Disable counter.
Enable counter. Configure T8 properly before enabling it.
0
1
Single Pass/Modulo-N
MODULO-N mode. Counter reloads the initial value when terminal count is reached
Single-Pass mode. Counter stops when the terminal count is reached
[6]
[5]
5
Read:
0
1
Write:
0
1
PS024406-0106
Time_Out—This bit is set when the T8 terminal count is reached.
No counter time-out occurs.
Counter time-out occurred.
No effect.
Reset flag to 0. Software must reset this flag before using counter/timers.
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
76
Bit
Position
Value Description
00
01
10
11
T8 _Clock—Select the T8 input clock frequency.
These bits are not reset upon stop-mode recovery.
SCLK.
SCLK ÷ 2.
SCLK ÷ 4.
SCLK ÷ 8.
0
1
Capture_INT_Mask—Disable/enable interrupt when data is captured into either LO8
or HI8 upon a positive or negative edge detection in demodulation mode.
This bit is not reset upon stop-mode recovery.
Disable data capture interrupt.
Enable data capture interrupt.
0
1
Counter_INT_Mask—Disable/enable T8 time-out interrupt.
This bit is not reset upon stop-mode recovery.
Disable time-out interrupt.
Enable time-out interrupt.
0
1
P34_Out—Select normal I/O or T8 output function for Port 3, pin 4.
P34 as port output.
T8 output on P34.
[4:3]
[2]
[1]
[0]
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
77
T8 and T16 Common Functions Register
The T8 and T16 Common Functions Register (CTR1) controls the functions in common
with Timer 8 and Timer 16. Table 37 describes the bits for this register.
Be careful to differentiate TRANSMIT mode from DEMODULATION mode, as set by
CTR1[7]. The functions of CTR1[6:0] and CTR2[6] are different depending on which
mode is selected. Do not change from one mode to another without first disabling the
counter/timers.
Note:
Table 37. Timer 8 and Timer 16 Common Functions Register (CTR1)
Bit
7
6
5
4
P36 Out/
T8/T16 Logic/
Demodulator Input Edge Detect
3
2
1
0
Transmit Submode/ Initial Timer 8 Out/ Initial Timer 16 Out/
Glitch Filter
Rising Edge
Falling Edge
Field
Mode
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bank D: 01h; Linear: D01h
Bit
Position
Description
[7]
Mode—Selects the timer mode for signal transmission or demodulation.
0
1
[6]
Transmit mode.
Demodulation mode.
Transmit Mode:
P36 Out—Select normal I/O or timer output on Port 3, Pin 6.
0
1
P36 acts as normal I/O port output.
P36 acts as combined Timer 8/Timer 16 output.
Demodulation Mode:
Demodulator Input—Select Port 2, Pin 0 or Port 3, Pin 1 as the counter/timer input.
0
1
PS024406-0106
P31 acts as the demodulator input. If IMR[2] = 1, a P31 event can also generate
an IRQ1 interrupt. To prevent this, clear IMR[2] or select P20 as input instead.
P20 acts as the demodulator input.
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
78
Bit
Position
[5:4]
Description
Transmit Mode:
T8/T16 Logic—Defines how the Timer 8/Timer 16 outputs are combined logically.
These bits are not reset upon stop-mode recovery.
00
01
10
11
Output is T8 AND T16.
Output is T8 OR T16.
Output is T8 NOR T16.
Output is T8 NAND T16.
Demodulation Mode:
Edge Detect—Define the behavior of the edge detector.
00
01
10
11
[3:2]
Falling edge detection.
Rising edge detection.
Falling and rising edge detection.
Reserved.
Transmit Mode:
Submode Selection—Select normal or Ping-pong mode operation, or force T16 output.
When these bits are written to 00b (Normal mode) or 01b (Ping-pong mode), T16_OUT
assumes the opposite state of bit CTR1[0] until the timer begins counting.
00
01
10
11
Normal operation. Writing 00 terminates Ping-pong mode, if it is active.
Ping-pong mode.
Force T16_OUT = 0.
Force T16_OUT = 1.
Demodulation Mode:
Glitch Filter—Define the maximum glitch width to be rejected by the counter/timer.
00
01
10
11
PS024406-0106
No filter.
4 SCLK cycle filter.
8 SCLK cycle filter.
Reserved.
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
79
Bit
Position
[1]
Description
Transmit Mode:
Initial Timer 8 Out—Select the initial T8_OUT state when Timer 8 is enabled. While the
timer is disabled, the opposite state is asserted on the pin to ensure that a transition
occurs when the timer is enabled. Changing this bit while the counter is enabled can
cause unpredictable output on T8_OUT.
0
1
T8_OUT transitions from High to Low when Timer 8 is enabled.
T8_OUT transitions from Low to High when Timer 8 is enabled.
Demodulation Mode:
Rising Edge—Indicates whether a rising edge was detected on the input signal. Write 1 to
this flag to reset it.
Read:
0
1
Write:
0
1
[0]
No rising edge detection.
Rising edge detection.
No effect.
Reset flag to 0.
Transmit Mode:
Initial Timer 16 Out—In Normal or Ping-pong mode, this bit selects the initial T16_OUT
state when Timer 16 is enabled. While the timer is disabled, the opposite state is asserted
on the pin to ensure that a transition occurs when the timer is enabled. Changing this bit
while the counter is enabled can cause unpredictable output on T16_OUT.
0
1
If CTR1[3]=0, T16_OUT transitions from High to Low when Timer 16 is enabled.
If CTR1[3]=0, T16_OUT transitions from Low to High when Timer 16 is enabled.
Demodulation Mode:
Falling Edge—Indicates whether a falling edge was detected on the input signal. Write 1
to this flag to reset it.
Read:
0
1
Write:
0
1
PS024406-0106
No falling edge detection.
Falling edge detection.
No effect.
Reset flag to 0.
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
80
Timer 16 Control Register
Table 38 describes the bits for the Timer 16 Control Register (CTR2).
Table 38. Counter/Timer 16 Control Register (CTR2)
Bit
7
6
5
4
Single/
Time_Out
Modulo-N
3
1
Capture_INT Counter_INT
_Mask
_Mask
0
Field
T16_Enable
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
T16 _Clock
2
P35_Out
Bank D: 02h; Linear: D02h
Bit
Position Description
[7]
T16_Enable—Disable/enable the T16 counter.
0
1
[6]
Disable T16 counter.
Enable T16 counter.
Transmit Mode (CTR1[7]=0):
Single/Modulo-N—Selects Timer 16 terminal count action.
0
1
MODULO-N mode. T16 reloads the initial value when terminal count is reached
Single-Pass mode. T16 stops when the terminal count is reached
Demodulation Mode (CTR1[7]=1):
Enable single-edge capture. See T16 Demodulation Mode on page 67.
0
1
[5]
Time_Out—This bit is set when the T16 terminal count is reached.
Read:
0
1
Write:
0
1
[4:3]
Timer 16 captures and reloads on all edges.
Timer 16 captures and reloads on first edge only.
Time_Out—This bit is set when the T16 terminal count is reached.
No counter time-out occurs.
Counter time-out occurred.
No effect.
Reset flag to 0. Software must reset this flag before using counter/timers.
T16 _Clock—Select T16 input clock frequency. These bits are not reset upon stop-mode recovery.
00
01
10
11
PS024406-0106
SCLK.
SCLK ÷ 2.
SCLK ÷ 4.
SCLK ÷ 8.
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
81
Bit
Position Description
[2]
Capture_INT_Mask—Disable/enable interrupt when data is captured into either LO16 or HI16
upon a positive or negative edge detection in demodulation mode. This bit is not reset upon
stop-mode recovery.
0
1
[1]
Disable data capture interrupt.
Enable data capture interrupt.
Counter_INT_Mask—Disable/enable T16 time-out interrupt.
0
1
[0]
Disable T16 time-out interrupt.
Enable T16 time-out interrupt.
P35_Out—Select normal I/O or T8 output function for Port 3, pin 5.
0
1
P35 as port output.
P35 is T16 output.
Timer 8/Timer 16 Control Register
The Timer 8/Timer 16 Counter/Timer Register allows the T8 and T16 counters to be synchronized. It also can freeze the T16 output value and change T8 demodulation mode to
capture one cycle of a carrier. Table 39 briefly describes the bits for this Bank D register. A
description of each bit follows the table.
Table 39. Timer 8/Timer 16 Control Register (CTR3)
Bit
7
6
5
4
3
Field
T16_Enable
T8_Enable
Sync_Mode
T16_Out
Disable
T8
Demodulate
Reset
0
0
0
0
0
X
X
X
R/W
R/W
R/W
R/W
R/W
—
—
—
R/W
Address
1
0
Reserved
Bank D: 03h; Linear: D03h
Bit
Position Value
Description
[7]
0
1
Disable T16 counter.
Enable T16 counter. Configure T16 properly before enabling it.
[6]
0
1
Disable T8 counter.
Enable T8 counter.
PS024406-0106
2
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
82
Bit
Position Value
[5]
0
1
[4]
T16 toggles normally.
T16 toggle is disabled.
T8 Demodulate—(Capture one cycle.) This bit is not reset upon stop-mode recovery.
0
1
[2:0]
Disable SYNC mode.
Enable SYNC mode.
T16_Out Disable—Set this bit to disable toggling of the Timer 16 output. Time-out interrupts
are still generated. This bit is not reset upon stop-mode recovery.
0
1
[3]
Description
SYNC Mode—When enabled, the first pulse of Timer 8 (the carrier) is always synchronized
with Timer 16 (the demodulated signal). It can always provide a full carrier pulse. This bit is not
reset upon stop-mode recovery.
T8 captures events normally.
T8 becomes active on the third edge, captures events on the fourth and fifth edges,
and generates an interrupt on the fifth edge. After a T8 time-out the event count
resets to 0 and the fourth and fifth edges are captured again.
Reserved—Always reads 111b. Writes have no effect.
PS024406-0106
P R E L I M I N A R Y
Counter/Timer Registers
ZLP12840 OTP MCU
Product Specification
83
Interrupts
The Crimzon™ ZLP12840 MCU features six different interrupts (see Table 41 on page
85). The interrupts are maskable and prioritized (see Figure 31). The six sources are
divided as follows: three sources are claimed by Port 3 lines P33:P31, two by the counter/
timers (Table 41) and one for low voltage detection. P32 and the UART receiver share the
same interrupt. Only one interrupt can be selected as a source. When the UART receiver is
enabled P32 is no longer used as an interrupt source. The UART transmit interrupt and
UART baud rate interrupt use the same interrupt as the P33 interrupt. The user selects
which source triggers the interrupt. When bit 7 of UTCL is 1, the UART transmit interrupt
is the source. When bit 7 of UCTL is 0 and bit 5 of UCTL is 1, the BRG interrupt is
selected. The Interrupt Mask Register (globally or individually) enables or disables the six
interrupt requests.
The source for IRQ1 is determined by bit 1 of the Port 3 Mode Register (P3M) and bit 4 of
the SMR4 register. If P3M[1]=0 (digital mode) and SMR4[4]=0, pin P33 is the IRQ1
source. If P3M[1]=1 (analog mode) or SMR4[4]=1 (SMR interrupt enabled), the output of
the Stop-mode recovery source logic is used as the source for the interrupt. See Stop Mode
Recovery Interrupt on page 97.
Table 40. Interrupt Control Registers
Address (Hex)
12-Bit
Bank 8-Bit
Register Description
Mnemonic Reset
0F9
All
F9
Interrupt Priority Register
IPR
XXh
88
0FA
All
FA
Interrupt Request Register
IRQ
00h
90
0FB
All
FB
Interrupt Mask Register
IMR
0XXX_XXXXb
87
PS024406-0106
P R E L I M I N A R Y
Page #
Interrupts
ZLP12840 OTP MCU
Product Specification
84
Ðíî
ËÝÌÔ ¾·¬- ë ú ê ã ïï
ËßÎÌ ÎÈ
ð
Ðíí
ï
ð
ͬ±°óÓ±¼» λ½±ª»®§ ͱ«®½»
ï
ÐíÓÅïà ÑÎ ÍÓÎìÅìÃ
ËßÎÌ ÞÎ٠ײ¬»®®«°¬
ð
ï
ËÝÌÔ ¾·¬- éô êô ¿²¼ ð ã ððï
ð
ï
ËÝÌÔ ¾·¬- ë ¿²¼ é ã ïï
ËßÎÌ ÌÈ
Ðíï
×ÎÏ Î»¹·-¬»® ø¾·¬- ê ú é÷
ײ¬»®®«°¬ Û¼¹»
Í»´»½¬
×ÎÏî
×ÎÏð
Ì·³»® ïê
×ÎÏï
×ÎÏí
Ô±©óʱ´¬¿¹»
Ü»¬»½¬·±²
Ì·³»® è
×ÎÏì
×ÎÏë
ײ¬»®®«°¬ λ¯«»-¬
ײ¬»®®«°¬ Ó¿-µ
λ¹·-¬»®
ë
Ù´±¾¿´
ײ¬»®®«°¬
Û²¿¾´»
ײ¬»®®«°¬
λ¯«»-¬
ײ¬»®®«°¬ Ю·±®·¬§
λ¹·-¬»®
Ю·±®·¬§ Ô±¹·½
Ê»½¬±® Í»´»½¬
Figure 31. Interrupt Block Diagram
PS024406-0106
P R E L I M I N A R Y
Interrupts
ZLP12840 OTP MCU
Product Specification
85
Table 41. Interrupt Types, Sources, and Vectors
Name
Source
Vector Location
(Program Memory) Comments
IRQ0
P32, UART Rx
0,1
External (P32), Rising, Falling
Edge Triggered
IRQ1
P33, UART Tx, BRG,
SMR Event
2,3
External (P33), Falling Edge
Triggered
IRQ2
P31
4,5
External (P31), Rising, Falling
Edge Triggered
IRQ3
Timer 16
6,7
Internal
IRQ4
Timer 8
8,9
Internal
IRQ5
Low Voltage Detection 10,11
Internal
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle activates when an interrupt request is granted. As a result, all subsequent interrupts are
disabled, and the Program Counter and Status Flags are saved. The cycle then branches to
the program memory vector location reserved for that interrupt. All Crimzon™ ZLP12840
MCU interrupts are vectored through locations in the program memory. This memory
location and the next byte contain the 16-bit address of the interrupt service routine for
that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs
are masked, and the Interrupt Request Register is polled to determine which of the interrupt requests require service.
An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is
mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge triggered. These interrupts are programmable by the user. The software can poll to identify the
state of the pin.
PS024406-0106
P R E L I M I N A R Y
Interrupts
ZLP12840 OTP MCU
Product Specification
86
Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250),
bits D7 and bit 6. The configuration is indicated in Table 42.
Table 42. Interrupt Request Register
IRQ Bit
Interrupt Edge
7
6
IRQ2 (P31)
IRQ0 (P32)
0
0
F
F
0
1
F
R
1
0
R
F
1
1
R/F
R/F
Note: F = Falling Edge; R = Rising Edge
PS024406-0106
P R E L I M I N A R Y
Interrupts
ZLP12840 OTP MCU
Product Specification
87
Interrupt Priority Register
The Interrupt Priority Register (Table 43) defines which interrupts hold the highest priority. Interrupts are divided into three groups of two—Group A, Group B, and Group C.
IPR bits 4, 3, and 0 determine which interrupt group has priority. For example, if interrupts
IRQ5, IRQ1, and IRQ0 occur simultaneously when IPR[4:3, 0]=001b, the interrupts are
serviced in the following order: IRQ1, IRQ0, IRQ5.
IPR bits 5, 2, and 1 determine which interrupt within each group has higher priority.
Table 43. Interrupt Priority Register (IPR)
Bit
7
6
Reserved
Field
Reset
X
R/W
5
Group A
Priority
X
—
X
[7:6]
3
Group Priority
[2:1]
X
W
Address
Bit
Position
4
2
1
0
Group B
Priority
Group C
Priority
Group Priority
[0]
X
X
X
W
W
W
X
W
Bank Independent: F9h; Linear: 0F9h
Value Description
—
[5]
0
1
{[4:3], [0]}
000
001
010
011
100
101
110
111
[2]
Group A Priority (IRQ3, IRQ5)
IRQ5 > IRQ3
IRQ3 > IRQ5
Group Priority
Reserved
C>A>B
A>B>C
A>C>B
B>C>A
C>B>A
B>A>C
Reserved
0
1
Group B Priority (IRQ0, IRQ2)
IRQ2 > IRQ0
IRQ0 > IRQ2
0
1
Group C Priority (IRQ1, IRQ4)
IRQ1 > IRQ4
IRQ4 > IRQ1
[1]
PS024406-0106
Reserved
Reads are undefined; writes must be 00b.
P R E L I M I N A R Y
Interrupt Priority Register
ZLP12840 OTP MCU
Product Specification
88
Interrupt Request Register
Bits 7 and 6 of the Interrupt Request Register are used to configure the edge detection of
the interrupts for Port 3, bit 1 and Port 3, bit 2. The remaining bits, 5 through 0, indicate
the status of the interrupt. When an interrupt is serviced, the hardware automatically clears
the bit to 0. Writing a 1 to any of these bits generates an interrupt if the appropriate bits in
the Interrupt Mask Register are enabled. Writing a 0 to these bits clears the interrupts. See
Table 44.
Table 44. Interrupt Request Register (IRQ)
Bit
7
6
Interrupt Edge
Field
Reset
R/W
5
4
3
2
1
0
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bank Independent: FAh; Linear: 0FAh
Bit
Position Value Description
[7:6]
00
01
10
11
[5]
[4]
[3]
Interrupt Edge
P31 P32
P31 P32
P31 P32
P31
P32
Read:
0
1
Write:
0
1
IRQ5 (Low Voltage Detection)
Interrupt did not occur.
Interrupt occurred.
Read:
0
1
Write:
0
1
IRQ4 (T8 Counter)
Interrupt did not occur.
Interrupt occurred.
Read:
0
1
Write:
0
1
IRQ3 (T16 Counter)
Interrupt did not occur.
Interrupt occurred.
PS024406-0106
Clear interrupt.
Set interrupt.
Clear interrupt.
Set interrupt.
Clear interrupt.
Set interrupt.
P R E L I M I N A R Y
Interrupt Request Register
ZLP12840 OTP MCU
Product Specification
89
Bit
Position Value Description
[2]
[1]
[0]
Read:
0
1
Write:
0
1
IRQ2 (Port 3 Bit 1 Input)
Interrupt did not occur.
Interrupt occurred.
Read:
0
1
Write:
0
1
IRQ1 (Port 3 Bit 3 Input/SMR Event/UART TX/UART BRG)
Interrupt did not occur.
Interrupt occurred.
Read:
0
1
Write:
0
1
IRQ0 (Port 3 Bit 2 Input/UART RX)
Interrupt did not occur.
Interrupt occurred.
Note:
PS024406-0106
Clear interrupt.
Set interrupt.
Clear interrupt.
Set interrupt.
Clear interrupt.
Set interrupt.
The IRQ register is protected from change until an EI instruction is executed once.
P R E L I M I N A R Y
Interrupt Request Register
ZLP12840 OTP MCU
Product Specification
90
Interrupt Mask Register
Bits [5:0] are used to enable the interrupt. Bit 7 is the status of the master interrupt. When
reset, all interrupts are disabled. When writing a 1 to bit 7, the user must also execute the
EI instruction to enable interrupts. See Table 45.
Table 45. Interrupt Mask Register (IMR)
Bit
Field
7
Master Interrupt Reserved
Enable
Reset
R/W
5
4
3
2
1
0
IRQ5
Enable
IRQ4
Enable
IRQ3
Enable
IRQ2
Enable
IRQ1
Enable
IRQ0
Enable
0
X
X
X
X
X
X
X
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bit
Position
6
Bank Independent: FBh; Linear: 0FBh
Value Description
[7]
0
1
Master Interrupt Enable
Use only the DI and EI instructions to alter this bit. Always disable interrupts (DI
instruction) before writing this register.
All interrupts are disabled.
Interrupts are enabled/disabled individually in bits [5:0].
[6]
0
Reserved
Reads are undefined; writes must be 0.
[5]
0
1
Disables IRQ5.
Enables IRQ5.
[4]
0
1
Disables IRQ4.
Enables IRQ4.
[3]
0
1
Disables IRQ3.
Enables IRQ3.
[2]
0
1
Disables IRQ2.
Enables IRQ2.
[1]
0
1
Disables IRQ1.
Enables IRQ1.
[0]
0
1
Disables IRQ0.
Enables IRQ0.
PS024406-0106
P R E L I M I N A R Y
Interrupt Mask Register
ZLP12840 OTP MCU
Product Specification
91
Clock
The device’s on-chip oscillator has a high-gain, parallel-resonant amplifier, for connection
to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = Input,
XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series
resistance (RS) less than or equal to 100 . The on-chip oscillator can be driven with a
suitable external clock source.
The crystal must be connected across XTAL1 and XTAL2 using the recommended capacitors from each pin to ground. The typical capacitor value is 10 pF for 8 MHz. Also check
with the crystal supplier for the optimum capacitance.
Figure 32. Oscillator Configuration
ZiLOG IR MCU supports crystal, resonator, and oscillator. Most resonators have a frequency tolerance of less than ±0.5%, which is enough for remote control application. Resonator has a very fast startup time, which is around few hundred microseconds. Most
crystals have a frequency tolerance of less than 50 ppm (±0.005%). However, crystal
needs longer startup time than the resonator. The large loading capacitance slows down the
oscillation startup time. ZiLOG suggests not to use more than 10pF loading capacitor for
the crystal. If the stray capacitance of the PCB or the crystal is high, the loading capacitance C1 and C2 must be reduced further to ensure stable oscillation before the TPOR
(Power-On Reset time is typically 5-6 ms. Refer to the AC Characteristics table).
For Stop Mode Recovery operation, bit 5 of SMR register allows you to select the STOP
mode recovery delay, which is the TPOR. If STOP mode recovery delay is not selected, the
MCU executes instruction immediately after it wakes up from the STOP mode. If resona-
PS024406-0106
P R E L I M I N A R Y
Clock
ZLP12840 OTP MCU
Product Specification
92
tor or crystal is used as a clock source then STOP mode recovery delay needs to be
selected (bit 5 of SMR = 1).
For both resonator and crystal oscillator, the oscillation ground must go directly to the
ground pin of the microcontroller. The oscillation ground must use the shortest distance
from the microcontroller ground pin and it must be isolated from other connections.
Crystal 1 Oscillator Pin (XTAL1)
The Crystal 1 Oscillator time-based input pin connects a parallel-resonant crystal or
ceramic resonator to the on-chip oscillator input. Additionally, an optional external singlephase clock can be connected to the on-chip oscillator input.
Crystal 2 Oscillator Pin (XTAL2)
The Crystal 2 Oscillator time-based output pin connects a parallel-resonant, crystal, or
ceramic resonant to the on-chip oscillator output.
Internal Clock Signals (SCLK and TCLK)
The CPU and internal peripherals are driven by the internal SCLK signal during normal
execution. During HALT mode, the interrupt logic is driven by the internal TCLK signal.
These signals are produced by dividing the on-chip oscillator signal by a factor of two, and
optionally by applying an additional divide-by-16 prescaler enabled in register bit SMR[0]
(described in Table 48 on page 100). This is shown in Figure 33.
Selecting the divide-by-16 prescaler reduces device power draw during normal operation
and HALT mode. The prescaler is disabled by a power-on reset or stop-mode recovery.
ÑÍÝ
ñî
ÍÓÎÅðÃ
ð
ñïê
ï
ÍÝÔÕ
ÌÝÔÕ
Figure 33. SCLK/TCLK Circuit
PS024406-0106
P R E L I M I N A R Y
Crystal 1 Oscillator Pin (XTAL1)
ZLP12840 OTP MCU
Product Specification
93
Resets and Power Management
The ZLP12840 provides the following reduced-power modes, power monitoring, and reset features:
Note:
•
Power-On Reset—Starts the oscillator and internal clock and initializes the system to
its power-on reset defaults.
•
Voltage Brown-Out Standby—Stops the oscillator and internal clock if a low-voltage
condition occurs. Initiates a power-on reset when power is restored.
•
Voltage Detection—Optionally sets a flag if a low- or high-voltage condition occurs.
The low-voltage detection flag can generate an interrupt request, if enabled.
•
Halt Mode—Stops the internal clock to the CPU until an enabled interrupt request is
received.
•
Stop Mode—Stops the clock and oscillator, reducing the MCU supply current to a very
low level until a power-on reset or stop-mode recovery occurs.
•
Stop Mode Recovery—Restarts the oscillator and internal clock and initializes most of
the system to its power-on reset defaults. Some register values are not reset by a stopmode recovery.
•
Watch-Dog Timer—Optionally generates a power-on reset if the program fails to execute the WDT instruction within a specified time interval.
For supply current values under various conditions, see DC Characteristics on page 126.
Figure 34 on page 94 illustrates the Power-On Reset sources. Table 46 lists control registers for reset and power management features. Some features are affected by registers
described in other chapters.
Table 46. Reset and Power Management Registers
Address (Hex)
12-Bit
Bank 8-Bit
Register Description
Mnemonic Reset
D0C
D
0C
Low-Voltage Detection Register
LVD
1 1 1 1 _100 0 b
96
F0A
F
0A
Stop-Mode Recovery Register 4
SMR4
XXX0 _000 0 b
109
F0B
F
0B
Stop-Mode Recovery Register
SMR
0 0 1 0 _000 0 b
100
F0C
F
0C
Stop-Mode Recovery Register 1
SMR1
00h
103
F0D
F
0D
Stop-Mode Recovery Register 2
SMR2
X0 X0 _00XXb
105
F0E
F
0E
Stop-Mode Recovery Register 3
SMR3
X0h
108
F0F
F
0F
Watch-Dog Timer Mode Register
WDTMR
XXXX_110 1 b
110
PS024406-0106
P R E L I M I N A R Y
Page #
Resets and Power Management
ZLP12840 OTP MCU
Product Specification
94
ëóÝ´±½µ
Ú·´¬»®
ÝÔÎîö
ÎÛÍÛÌ
ïèóÝ´±½µ λ-»¬
Ù»²»®¿¬±®
ÎÛÍÛÌ
ײ¬»®²¿´
ÎÛÍÛÌ
ß½¬·ª»
Ø·¹¸
ÈÌßÔ
ÉÜÌ ÌßÐ Í»´»½¬
ÐÑÎñÉÜÌ
ÝÔÕ
ײ¬»®²¿´
ÎÝ
Ñ-½·´´¿¬±®
Ê ÜÜ
õ
ÊÞÑ
O
î
í
ì
ÝÔÎï
Ô±© Ñ°»®¿¬·²¹
ʱ´¬¿¹» Ü»¬»½¬·±²
ÊÝÝ
ÉÜÌ
ïî ²Ù´·¬½¸ Ú·´¬»®
Ú®±³ ͬ±°óÓ±¼»
λ½±ª»®§ ͱ«®½»
ï
ÉÜÌñÐÑΠݱ«²¬»® ݸ¿·²
ï
ð
ÍÓÎÅëÃ
öÝÔÎï ¿²¼ ÝÔÎî »²¿¾´» ¬¸» ÉÜÌñÐÑÎ ¿²¼ ïè Ý´±½µ λ-»¬ ¬·³»®-ô ®»-°»½¬·ª»´§ô «°±² ¿ Ô±©ó¬±óØ·¹¸ ·²°«¬ ¬®¿²-´¿¬·±²ò
Figure 34. Resets and Watch-Dog Timer
Power-On Reset Timer
When power is initially applied to the device, a timer circuit clocked by a dedicated onboard RC-oscillator provides the Power-On Reset (POR) timer function.
The POR timer circuit is a one-shot timer that keeps the internal reset signal asserted long
enough for VDD and the oscillator circuit to stabilize before instruction execution begins.
The reset timer is triggered by one of three conditions:
•
•
•
Initial power-on or recovery from a voltage brown-out/standby condition.
Stop-Mode Recovery (if register bit SMR[5] = 1)
Watch-Dog Timer time-out.
SMR[5] can be cleared to 0 to bypass the POR timer upon a stop-mode recovery. This
should only be done when using an external clock that does not require a start-up delay.
PS024406-0106
P R E L I M I N A R Y
Power-On Reset Timer
ZLP12840 OTP MCU
Product Specification
95
Reset/Stop-Mode Recovery Status
Read-only bit SMR[7]=0 if the previous reset was initiated by a power-on reset (including
brown-out or WDT resets). SMR[7]=1 if the previous reset was initiated by a stop-mode
recovery.
A power-on, brown-out, or WDT reset restores all registers to their power-on reset
defaults. A stop-mode recovery restores most registers to their power-on reset defaults.
Register bits not reset by a stop-mode recovery are highlighted in grey in the register
tables. Register bit SMR[7] is set to 1 instead of reset by a Stop-mode recovery.
Voltage Brown-Out/Standby
An on-chip Voltage Comparator checks that the VDD is at the required level for correct
operation of the device. Reset is globally driven when VDD falls below VBO. A small drop
in VDD causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. If
the VDD is allowed to stay above VRAM , the RAM content is preserved. When the power
level is returned to above VBO, the device performs a power-on reset and functions normally.
Voltage Detection
The Voltage Detection register (LVD, register ðݸ at the expanded register bank ðܸ)
offers an option of monitoring the VCC voltage. The Voltage Detection is enabled when bit
0 of LVD register is set. After Voltage Detection is enabled, the VCC level is monitored in
real time. The HVD flag (bit 2 of the LVD register) is set only if VCC is higher than VHVD.
The LVD flag (bit 1 of the LVD register) is set only if VCC is lower than the VLVD. When
Voltage Detection is enabled, the LVD flag also triggers IRQ5. The IRQ bit 5 latches the
low voltage condition until it is cleared by instructions or reset. The IRQ5 interrupt is
served if it is enabled in the IMR register. Otherwise, bit 5 of IRQ register is latched as a
flag only.
Note:
Do not modify register P01M while checking a low-voltage condition. Switching noise
coming from Port 0 can trigger the LVD flag.
Voltage detection does not work in STOP mode. It must be disabled during STOP mode in
order to reduce current. This register is described in Table 47 on page 96.
PS024406-0106
P R E L I M I N A R Y
Reset/Stop-Mode Recovery Status
ZLP12840 OTP MCU
Product Specification
96
Table 47. Low-Voltage Detection Register (LVD)
Bit
7
6
5
4
3
Reserved
Field
2
1
0
High Battery Low Battery
Voltage
Detect
Detect
Detect Enable
Reset
1
1
1
1
1
0
0
0
R/W
R
R
R
R
R
R
R
R/W
Address
Bank D: 0Ch; Linear: D0Ch
Bit
Position R/W Value Description
[7:3]
—
—
Reserved—Reads 11111b. Writes have no effect.
[2]
R
0
1
HVD clear.
High voltage detected. VCC>VHVD
[1]
R
0
1
LVD clear.
Low voltage detected. VCC>VLVD
[0]
R/W
0
1
Voltage detection disabled.
Voltage detection enabled.
HALT Mode
This instruction turns off the internal CPU clock, but not the XTAL oscillation. The
counter/timers, UART, and interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain
active. The devices are recovered by interrupts, either externally or internally generated.
An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt
service routine, the program continues from the instruction after HALT mode.
To enter HALT mode, first flush the instruction pipeline to avoid suspending execution in
mid-instruction. Execute a NOP (Op Code = ÚÚ¸) immediately before the appropriate
sleep instruction, as follows:
ÚÚ
éÚ
ÒÑÐ
ØßÔÌ
å ½´»¿® ¬¸» °·°»´·²»
å »²¬»® ØßÔÌ ³±¼»
Power consumption during HALT mode can be reduced by first setting SMR[0]=1 to
enable the divide-by-16 clock prescaler.
PS024406-0106
P R E L I M I N A R Y
HALT Mode
ZLP12840 OTP MCU
Product Specification
97
STOP Mode
This instruction turns off the internal clock and external crystal oscillation, reducing the
MCU supply current to a very low level. For STOP mode current specifications, see DC
Characteristics on page 126.
To enter STOP mode, first flush the instruction pipeline to avoid suspending execution in
mid-instruction. Execute a NOP (Op Code = ÚÚ¸) immediately before the appropriate
sleep instruction, as follows:
ÚÚ
êÚ
ÒÑÐ
ÍÌÑÐ
å ½´»¿® ¬¸» °·°»´·²»
å »²¬»® ÍÌÑÐ ³±¼»
STOP mode is terminated only by a reset, such as WDT time-out, POR, or one of the Stopmode recovery (SMR) events described in the following sections. This condition causes
the processor to restart the application program at address ðððݸ.
Unlike a normal POR or WDT reset, a Stop-mode recovery reset does not reset the contents of some registers and bits. Register bits not reset by a Stop-mode recovery are highlighted in grey in the register tables. Register bit SMR[7] is set to 1 by a Stop-mode
recovery.
Fast Stop Mode Recovery
SMR[5] can be cleared to 0 before entering STOP mode to bypass the default TPOR reset
timer upon stop-mode recovery. See Power-On Reset Timer on page 94. If SMR[5]=0, the
stop-mode recovery source must be kept active for at least 10 input clock periods (TpC).
Note:
SMR[5] must be set to 1 if using a crystal or resonator clock source. The TPOR delay
allows the clock source to stabilize before executing instructions.
Stop Mode Recovery Interrupt
Software can set register bit SMR4[4] = 1 to enable routing of stop-mode recovery events
to IRQ1 and to Port 3, pin 3. In this configuration, if an IRQ1 interrupt occurs, register bit
P3[3] = 0 indicates that a stop-mode recovery event is occurring.
PS024406-0106
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
98
Stop Mode Recovery Event Sources
Any Port 2 or 3 input pin can be configured to generate a sop-mode recovery event, either
individually or in a variety of logical combinations. The PartName provides the following
registers for stop-mode recovery source configuration and status:
•
SMR Register—Selects one Port 3, pin 1–3 pin state or one of three Port 2 pin logical
combinations to generate an event when a defined 0 or 1 level occurs.
•
SMR1 Register—Configure one or more Port 2 input pins (0–7)to latch the latest read
or write value and generate an event when the pin state changes.
•
SMR2 Register—Selects one of seven Port 2 and 3 pin logical combinations to generate an event when a defined 0 or 1 level occurs.
•
SMR3 Register—Configure one or more Port 3 input pins (0–3) to latch the latest read
or write value and generate an event when the pin state changes.
•
SMR4 Register—Enables routing of SMR events to IRQ1. Indicates whether port data
has been latched for SMR1 or SMR3 event monitoring, and whether the latch was on
a port read or write.
A stop-mode recovery event occurs if any of the sources defined in the SMR, SMR1,
SMR2, and SMR3 registers is active.
SMR Register Events
The SMR register function is similar to the standard stop-mode recovery feature used in
previous Z8® CPU-compatible parts. Register bits SMR[4:2] are set to select one of six
event modes, as shown in Figure 35 on page 99. The output of the corresponding logic is
compared to the state of SMR[6]; when they are the same, a stop-mode recovery event is
generated.
If SMR[4:2]=000, no event source is selected by SMR. The state SMR[4:2]=001 is
reserved and selects no event in this device.
The logic configured by the SMR register ignores any port pins that are configured as an
output, or that are selected as source pins in registers SMR1 or SMR3.
The SMR register is summarized in Table 48 on page 100.
PS024406-0106
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
99
ÍÓÎÅìæîà ã ððð
ÊÝÝ
ÍÓÎÅìæîà ã ðïð
Ðíï
ÍÓÎÅìæîà ã ðïï
̸» ÍÓÎ ®»¹·-¬»® ´±¹·½ ·¹²±®»- ¿²§ °·² ½±²º·¹«®»¼
¿- ¿² ±«¬°«¬ ·² ¬¸» ÐîÓ ±® ÐíÓ ®»¹·-¬»®- ±®
¿- ¿ -±«®½» ·² ¬¸» ÍÓÎï ±® ÍÓÎí ®»¹·-¬»®-ò
Ðíî
ÍÓÎÅìæîà ã ïðð
Ðíí
ÍÓÎÅìæîà ã ïðï
ÐíÓÅïà ÑÎ
ÍÓÎìÅìÃ
Ðîé
ð
̱ ×ÎÏï
ß²¼ ÐðÅíÃ
ï
ÍÓÅìæîà ã ïïð
Ðîð
Ðîí
ÍÓÎ
ÍÓÎï
ÍÓÅìæîà ã ïïï
ÍÓÎî
ÍÓÎí
Ðîð
̱ ÎÛÍÛÌ ¿²¼ ÉÜÌ
Ý·®½«·¬®§ øß½¬·ª» Ô±©÷
Ðîé
ÍÓÎÅêÃ
Figure 35. SMR Register-Controlled Event Sources
PS024406-0106
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
100
[
Table 48. Stop-Mode Recovery Register (SMR)
Bit
7
6
5
Field
Stop
Flag
Stop-Mode
Recovery Level
Stop
Delay
Reset
0
0
1
0
0
R/W
R
W
W
W
W
Address
Bit
Position
3
2
1
0
Reserved
SCLK/TCLK
Divide-by-16
0
0
0
W
W
W
Stop-Mode Recovery
Source
Bank F: 0Bh; Linear: F0Bh
Value Description
[7]
0
1
Stop Flag—Indicates whether last startup was power-on Reset or Stop-mode recovery.
A write to this bit has no effect.
Power-On Reset.
Stop-Mode Recovery.
0
1
Stop-Mode Recovery Level—Selects whether an SMR[4:2]-selected SMR is initiated
by a Low or High level at the XOR-gate input (see Figure 35 on page 99).
Low.
High.
0
1
Stop Delay—Controls the reset delay after recovery. Must be 1 if using a crystal or
resonator clock source.
Off.
On.
[6]
[5]
[4:2]
000
001
010
011
100
101
110
111
[1]
4
Stop-Mode Recovery Source—Specifies a stop mode recovery wake-up source at the
XOR gate input (see Figure 35 on page 99). This value is not changed by a stop-mode
recovery. The following equations ignore any Port pin configured as output or selected
in SMR1 or SMR3.
No SMR register source selected.
Reserved.
P31.
P32.
P33.
P27.
Port 2 NOR 0–3.
Port 2 NOR 0–7.
—
Reserved—Reads are undefined; must write 0.
0
1
SCLK/TCLK Divide-by-16 Select—Controls a divide-by-16 prescaler of the internal
SCLK/TCLK signal (see Internal Clock Signals (SCLK and TCLK) on page 92). A
power-on reset or stop-mode recovery clears this bit to 0.
Off.
On.
[0]
PS024406-0106
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
101
SMR1 Register Events
The SMR1 register can be used to configure one or more Port 2 pins to be to be compared
to a written or sampled reference value and generate a stop-mode recovery event when the
pin state differs from the reference value.
To configure a Port 2 pin as an SMR1 event source, make sure it is configured as an input
in the P2M register, then set the corresponding SMR1 register bit. By default, a stop-mode
recovery event occurs when the pin’s state is zero.
After a Port 2 pin is configured as an SMR1 source, any subsequent read from or write to
the P2 register latches the read or written value for reference. A stop-mode recovery event
occurs when the pin’s state differs from the last reference value latched. The SMR1 source
logic is illustrated in Figure 36 on page 102.
The program can read register bits SMR4[1:0] to determine whether the Port 2 pins trigger
a stop-mode recovery on a change from the last read value (SMR4[1:0]=01), or on a
change from the last written value (SMR4[1:0]=10). Software can clear SMR4[1:0] to 00
to restore the default behavior (configured pins trigger when their state is 0).
The SMR1 register is summarized in Table 49 on page 103.
After the following example code is executed, a 1 on P2 0 will wake the part from Stop
mode.
ÔÜ ÐîÓô ýûÚÚ
ÔÜ ÍÓÎïô ýûðï
ÔÜ Ðîô ýûðð
åÍ»¬ ᮬ î ¬± ·²°«¬-ò
åÍ»´»½¬ Ðî𠺱® ÍÓÎïò
åÉ®·¬» ð𸠬± ᮬ îô -± ¬¸» Ðîð ®»º»®»²½»
媿´«» ·- ðô ¿²¼ ¿ ï ±² Ðîð ©¿µ»- ¬¸» °¿®¬ò
ÒÑÐ
ÍÌÑÐ
After the following example code is executed when the value of P2 is 00h, a 1 on P20 will
wake the part from Stop mode:
ÔÜ ÐîÓô ýûÚÚ
ÔÜ ÍÓÎïô ýûðï
ÔÜ Îêô Ðî
åÍ»¬ °±®¬- ¬± ·²°«¬-ò
åÍ»´»½¬ Ðî𠺱® ÍÓÎïò
å׺ ¿ ð ·- ®»¿¼ º®±³ ᮬ îô ¬¸» Ðîð ®»º»®»²½»
媿´«» ·- ðô -± ¿ ï ±² Ðîð ©¿µ»- ¬¸» °¿®¬ò
ÒÑÐ
ÍÌÑÐ
PS024406-0106
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
102
Individual Port 2 Pin SMR Logic, n = 0-7
Bit P2M[n]
To SMR1
Bit SMR1[n]
Port 2, Pin n
Bit P2[n]
D
Q
Port 2 Read/Write
P33
IRQ1
P3M[1] OR
SMR4[4]
P20 Logic
0
1
P21 Logic
Register P3, bit 3
P22 Logic
P23 Logic
P24 Logic
P25 Logic
P26 Logic
P27 Logic
SMR1
SMR
SMR2
SMR3
To RESET and WDT
Circuitry (Active Low)
Figure 36. SMR1 Register-Controlled Event Sources
PS024406-0106
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
103
Table 49. Stop-Mode Recovery Register 1 (SMR1)
Bit
7
6
5
4
3
2
1
0
Field
P27 Stop
Select
P26 Stop
Select
P25 Stop
Select
P24 Stop
Select
P23 Stop
Select
P22 Stop
Select
P21 Stop
Select
P20 Stop
Select
Reset
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Address
Bit
Position
Bank F: 0Ch; Linear: F0Ch
Value Description
[7]
0
1
P27 not selected.
P27 selected as an SMR source.
[6]
0
1
P26 not selected.
P26 selected as an SMR source.
[5]
0
1
P25 not selected.
P25 selected as an SMR source.
[4]
0
1
P24 not selected.
P24 selected as an SMR source.
[3]
0
1
P23 not selected.
P23 selected as an SMR source.
[2]
0
1
P22 not selected.
P22 selected as an SMR source.
[1]
0
1
P21 not selected.
P21 selected as an SMR source.
[0]
0
1
P20 not selected.
P20 selected as an SMR source.
Note:
PS024406-0106
This register is not reset after a stop-mode recovery.
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
104
SMR2 Register Events
The SMR2 register function is similar to the standard stop-mode recovery feature used in
previous Z8® CPU-compatible parts. Register bits SMR2[4:2] are set to select one of
seven event modes, as shown in Figure 37. The output of the corresponding logic is compared to the state of SMR2[6]; when they are the same, a stop-mode recovery event is generated. If SMR2[4:2]=000, no event source is selected by SMR2.
The logic configured by the SMR2 register ignores any port pins that are configured as an
output, or that are selected as source pins in registers SMR1 or SMR3.
The SMR2 register is summarized in Table 50 on page 105.
ÍÓÎîÅìæîà ã ððð
ÊÝÝ
ÍÓÎîÅìæîà ã ððï
Ðîð
Ðîí
ÍÓÎîÅìæîà ã ðïð
Ðîð
̸» ÍÓÎî ®»¹·-¬»® ´±¹·½ ·¹²±®»- ¿²§ °·² ½±²º·¹«®»¼
¿- ¿² ±«¬°«¬ ·² ¬¸» ÐîÓ ±® ÐíÓ ®»¹·-¬»®- ±®
¿- ¿ -±«®½» ·² ¬¸» ÍÓÎï ±® ÍÓÎí ®»¹·-¬»®-ò
Ðîé
ÍÓÎîÅìæîà ã ðïï
Ðíï
Ðíî
Ðíí
ÍÓÎîÅìæîà ã ïðð
Ðíí
Ðíï
Ðíî
Ðíí
Ðíï
Ðíî
Ðíí
Ððð
Ððé
Ðíï
Ðíî
Ðíí
Ððð
Ððé
ÐíÓÅïà ÑÎ
ÍÓÎìÅìÃ
ÍÓÎîÅìæîà ã ïðï
ð
ï
ÍÓÎîÅìæîà ã ïïð
ÍÓÎ
ÍÓÎï
ÍÓÎî
Ðíï
Ðíî
Ðíí
Ðîð
Ðîï
Ðîî
̱ ×ÎÏï
ß²¼ ÐðÅíÃ
ÍÓÎîÅìæîà ã ïïï
ÍÓÎí
̱ ÎÛÍÛÌ ¿²¼ ÉÜÌ
Ý·®½«·¬®§ øß½¬·ª» Ô±©÷
ÍÓÎîÅêÃ
Figure 37. SMR2 Register-Controlled Event Sources
PS024406-0106
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
105
Table 50. Stop-Mode Recovery Register 2 (SMR2)
Bit
7
6
5
Reserved
Stop-Mode Recovery
Level 2
Reserved
Reset
X
0
R/W
—
W
Field
Address
4
3
2
1
0
Stop-Mode Recovery
Source
Reserved
X
0
0
0
X
—
W
W
W
X
—
Bank F: 0Dh; Linear: F0Dh
Bit
Position
Value Description
[7]
—
Reserved—Read is undefined; write must be 0.
0
1
Stop-Mode Recovery Level 2
Selects whether an SMR2[4:2]-selected SMR is initiated by a Low or High level at the
XOR-gate input (see Figure 37 on page 104).
Low.
High.
—
Reserved—Read is undefined; write must be 0.
[6]
[5]
[4:2]
000
001
010
011
100
101
110
111
[1:0]
—
Note:
Stop-Mode Recovery Source
Specifies a stop mode recovery wake-up source at the XOR gate input (see Figure 37 on
page 104). Additional sources can be selected by SMR, SMR1, and SMR3 registers. If
more than one source is selected, any selected source event causes a stop mode
recovery. The following equations ignore any Port pin that is selected in register SMR1 or
configured as an output.
No SMR2 register source selected.
NAND of P23:P20.
NAND of P27:P20.
NOR of P33:P31.
NAND of P33:P31.
NOR of P33:P31, P00, P07.
NAND of P33:P31, P00, P07.
NAND of P33:P31, P22:P20.
Reserved—Read is undefined; write must be 00b.
This register is not reset after a stop-mode recovery.
SMR3 Register Events
The SMR3 register can be used to configure one or more of Port 3, pins 0–3 to be compared to a written or sampled reference value and generate a stop-mode recovery event
when the pin state differs from the reference value.
PS024406-0106
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
106
To configure a Port 3 input pin as an SMR3 event source set the corresponding SMR3 register bit. By default, a stop-mode recovery event occurs when the pin’s state is zero.
After a Port 3 pin is configured as an SMR3 source, any subsequent read from or write to
the P2 register latches the read or written value for reference. A stop-mode recovery event
occurs when the pin’s state differs from the last reference value latched. The SMR3 source
logic is illustrated in Figure 38 on page 107.
The program can read register bits SMR4[3:2] to determine whether the Port 3 pins trigger
a stop-mode recovery on a change from the last read value (SMR4[3:2]=01), or on a
change from the last written value (SMR4[3:2]=10). Software can clear SMR4[3:2] to 00
to restore the default behavior (configured pins trigger when their state is 0).
The SMR3 register is summarized in Table 48 on page 100.
After the following example code is executed, a 1 on P30 will wake the part from Stop
mode.
ÔÜ ÍÓÎíô ýûðï
ÔÜ Ðíô ýûðð
åÍ»´»½¬ Ðí𠺮±³ ÍÓÎíò
åÉ®·¬» ð𸠬± ᮬ íô -± ¬¸» Ðíð ®»º»®»²½»
媿´«» ·- ðô ¿²¼ ¿ ï ±² Ðíð ©¿µ»- ¬¸» °¿®¬ò
ÒÑÐ
ÍÌÑÐ
After the following example code is executed when the value of P3 is 00h, a 1 on P30 will
wake the part from Stop mode.
ÔÜ ÍÓÎíô ýûðï
ÔÜ Îêô Ðí
åÍ»´»½¬ Ðí𠺱® ÍÓÎíò
å׺ ¿ ð ·- ®»¿¼ º®±³ ᮬ íô ¬¸» Ðíð ®»º»®»²½»
媿´«» ·- ðô -± ¿ ï ±² Ðíð ©¿µ»- ¬¸» °¿®¬ò
ÒÑÐ
ÍÌÑÐ
PS024406-0106
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
107
ײ¼·ª·¼«¿´ ᮬ í з² ÍÓÎ Ô±¹·½ô n ã ðóí
̱ ÍÓÎí
Þ·¬ ÍÓÎíÅnÃ
ᮬ íô з² n
Þ·¬ ÐíÅnÃ
Ü
Ï
ᮬ í λ¿¼ñÉ®·¬»
Ðíí
Ðíð Ô±¹·½
ÐíÓÅïà ÑÎ
ÍÓÎìÅìÃ
ð
̱ ×ÎÏï
ß²¼ ÐðÅíÃ
ï
Ðíï Ô±¹·½
Ðíî Ô±¹·½
Ðíí Ô±¹·½
ÍÓÎ
ÍÓÎï
ÍÓÎî
ÍÓÎí
̱ ÎÛÍÛÌ ¿²¼ ÉÜÌ
Ý·®½«·¬®§ øß½¬·ª» Ô±©÷
Figure 38. SMR3 Register-Controlled Event Sources
PS024406-0106
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
108
Table 51. Stop-Mode Recovery Register 3 (SMR3)
Bit
7
6
5
4
—
Field
3
2
1
0
P33 SMR
Select
P32 SMR
Select
P31 SMR
Select
P30 SMR
Select
Reset
X
X
X
X
0
0
0
0
R/W
—
—
—
—
W
W
W
W
Address
Bit
Position
Bank F: 0Eh; Linear: F0Eh
Value Description
[7:4]
—
Reserved—Reads undefined; writes have no effect.
[3]
0
1
P33 not selected.
P33 SMR source selected.
[2]
0
1
P32 not selected.
P32 SMR source selected.
[1]
0
1
P31 not selected.
P31 SMR source selected.
[0]
0
1
P30 not selected.
P30 SMR source selected.
Note:
PS024406-0106
This register is not reset after a stop-mode recovery.
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
109
Stop-Mode Recovery Register 4
The Stop-Mode Recovery Register 4 (SMR4) Register enables the SMR interrupt source
and indicates the reference value status for registers SMR1 and SMR3.
Table 52. Stop-Mode Recovery Register 4 (SMR4)
Bit
7
6
5
Reserved
Field
4
SMR IRQ Enable
3
2
Port 3 SMR Status
1
0
Port 2 SMR Status
Reset
X
X
X
0
0
0
0
0
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
Address
Bit
Position
Bank F: 0Ah; Linear: F0Ah
Value Description
[7:5]
—
Reserved—Reads are undefined; must write 000b.
0
1
SMR IRQ Enable
If P3M[1]=0, SMR events do not generate an interrupt.
SMR events generate an interrupt on IRQ1.
00
01
10
11
Port 3 SMR Status
No Read or Write of the P3 register occurs.
P3 Read occurs; used as SMR3 reference.
P3 Write occurs; used as SMR3 reference.
Reserved.
00
01
10
11
Port 2 SMR Status
No Read or Write of the P2 register occurs.
P2 Read occurs; use P2 Read as SMR1 reference.
P2 Write occurs; use P2 Write as SMR1 reference.
Reserved.
[4]
[3:2]
[1:0]
Note:
PS024406-0106
This register is not reset after a stop-mode recovery.
P R E L I M I N A R Y
STOP Mode
ZLP12840 OTP MCU
Product Specification
110
Watch-Dog Timer
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets the Z8 LXM
CPU if it reaches its terminal count. The WDT must initially be enabled by executing the
WDT instruction. On subsequent executions of the WDT instruction, the WDT is
refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT instruction
affects the Zero (Z), Sign (S), and Overflow (V) flags.
The POR clock source is the internal RC-oscillator. Bits 0 and 1 of the WDT register control a tap circuit that determines the minimum time-out period. Bit 2 determines whether
the WDT is active during HALT, and bit 3 determines WDT activity during STOP mode.
Bits 4 through 7 are reserved (see Table 53). This register is accessible only during the
first 60 processor cycles (120 XTAL clocks) from the execution of the first instruction
after power-on Reset, watch-dog timer Reset, or a Stop-mode recovery (see STOP Mode
on page 97). After this point, the register cannot be modified by any means (intentional or
otherwise). The WDTMR register cannot be read. The register is located in Bank F of the
Expanded Register Group at address location ðÚ¸. It is organized as shown in Table 53.
This register is not reset after a stop-mode recovery.
Note:
Table 53. Watch-Dog Timer Mode Register (WDTMR)
Bit
7
6
5
4
—
Field
3
2
WDT During STOP WDT During HALT
Mode
Mode
1
0
Time-Out Select
Reset
X
X
X
X
1
1
0
1
R/W
X
X
X
X
W
W
W
W
Address
Bit
Position
[7:4]
Bank F: 0Fh; Linear: F0Fh
Value Description
—
Reserved—Reads are undefined; must write 0000.
WDT During STOP Mode—Determines whether or not the WDT is active during
[3]
0
1
STOP mode.
Off.
WDT active during STOP mode.
WDT During HALT Mode—Determines whether or not the WDT is active during
[2]
HALT mode. See Figure 34.
0
1
PS024406-0106
Off.
WDT active during HALT mode.
P R E L I M I N A R Y
Watch-Dog Timer
ZLP12840 OTP MCU
Product Specification
111
Bit
Position
Value Description
[1:0]
00
01
10
11
PS024406-0106
Time-Out Select—Selects the WDT time period.
5 ms minimum.
10 ms minimum.
20 ms minimum.
80 ms minimum.
P R E L I M I N A R Y
Watch-Dog Timer
ZLP12840 OTP MCU
Product Specification
112
Z8 LXM CPU Programming Summary
The following pages provide a summary of information useful for programming the Z8
LXM CPU included in this device. For details about the CPU and its instruction set, see
the Z8 LXM CPU Core User Manual (UM0183).
Addressing Notation
Table 54 summarizes Z8 LXM CPU addressing modes and symbolic notation. The text
variable n represents a decimal number; aa represents a hexadecimal address; and LABEL
represents a label defined elsewhere in the assembly source.
In reference notation only, lowercase is used to distinguish 4-bit addressed working registers (r1, r2) from 8-bit addressed registers (R1, R2). The numerals 1 and 2, respectively,
indicate whether the register is used for destination or source addressing.
.
Table 54. Symbolic Notation for Operands
Assembly
Symbol Operand Description
cc
–
Condition Code
cc represents a condition code mnemonic. See Condition Codes on page 116.
IM
ýn
Immediate Data
IM represents an Immediate Data value, prefixed by # in assembly language. The
immediate value follows the instruction opcode in program memory. n = 0 to 255.
r1
r2
Rn
Working Register
r1 or r2 represents the name, Rn, of a working register, where n = 0, 1, 2,..., 15. The
equivalent 12-bit address is {RP[3:0], RP[7:4], n}.
rr1
rr2
RRn
Working Register Pair
rr1 or rr2 represents the name, Rn, of a working register pair, where
n = 0, 2, 4,..., 14. The equivalent 12-bit address is {RP[3:0], RP[7:4], n}.
R1
R2
%aa
Register
R1 or R2 represents an 8-bit register address. For addresses 00h–DFh or
F0h–FFh, the equivalent 12-bit address is {RP[3:0], %aa}. For addresses
E0h–EFh (escaped mode), the equivalent 12-bit address is
{RP[3:0], RP[7:4], %aa[3:0]}.
RR1
RR2
%aa
Register Pair (8-bit Address)
RR1 or RR2 represents the 8-bit address of a register pair. For addresses 00h–DFh
or F0h–FFh, the equivalent 12-bit address is {RP[3:0], %aa}. For addresses
E0h–EFh (escaped mode), the equivalent 12-bit address is
{RP[3:0], RP[7:4], %aa[3:0]}.
PS024406-0106
P R E L I M I N A R Y
Z8 LXM CPU Programming Summary
ZLP12840 OTP MCU
Product Specification
113
Table 54. Symbolic Notation for Operands (Continued)
Assembly
Symbol Operand Description
Irr1
Irr2
@Rn
Indirect Working Register
Ir1 or Ir2 represents the name a working register, Rn, where n = 0, 1, 2,..., 15.
@ indicates Indirect Working Register addressing using an 8-bit effective address
contained in the specified working register. The accessed register’s equivalent 12-bit
address is {RP[3:0], 8-bit effective address}.
Irr1
Irr2
@RRn
Indirect Working Register Pair
Irr1 or Irr2 represents the name a working register pair, RRn, where n = 0, 2, 4,..., 14.
@ indicates Indirect Working Register addressing using an effective address in the
specified working register pair. Depending on the instruction, the effective address is in
the register file (12-bit address) or program/constant memory (16-bit address).
IR1
IR2
@%aa
Indirect Register
IR1 or IR2 represents the 8-bit address of a register.
@ indicates Indirect Register addressing using an 8-bit effective address contained
in the specified register. The accessed register’s equivalent 12-bit address is
{RP[3:0], 8-bit effective address}.
IRR1
@%aa
Indirect Register Pair
IRR1 represents the 8-bit address of a register.
@ indicates Indirect Register addressing with a 16-bit effective address (in program
memory) contained in the specified register pair.
X(r1)
X(r2)
%aa(Rn)
Indexed (X) Addressing
X represents the 8-bit base address to which the offset is added.
r1 or r2 represents the name, Rn, of a working register containing the 8-bit signed
offset. The 8-bit effective address is the sum of X and the contents of working
register Rn. The accessed register’s equivalent 12-bit address is
{RP[3:0], 8-bit effective address}.
DA
LABEL
Direct Address (JP, CALL)
In a JP or CALL operand, DA is a 16-bit program memory address in the range of
ððððØ to ÚÚÚÚØ. DA replaces the contents of the Program Counter to cause
execution to continue at a new location in program memory. In assembly source, the
address is typically represented as a label.
RA
LABEL
Relative Address (JR, DJNZ)
RA is a signed 8-bit program memory offset in the range +127 to –128, relative to the
address of the next instruction in program memory. In a JR or DJNZ operation, RA is
added to the program counter to cause execution to continue at a new location in
program memory. In assembly source, the jump address is typically represented as
an absolute label, and the assembler calculates RA.
PS024406-0106
P R E L I M I N A R Y
Addressing Notation
ZLP12840 OTP MCU
Product Specification
114
Table 55 contains additional symbols that are used throughout the instruction set summary.
Table 55. Additional Symbols
Symbol
Definition
dst
Destination Operand
src
Source Operand
@
Indirect Address Prefix
C
Carry Flag
SP
Stack Pointer Value
PC
Program Counter
FLAGS
Flags Register
RP
Register Pointer
#
Immediate Operand Prefix
b
Binary Number Suffix
%
Hexadecimal Number Prefix
h
Hexadecimal Number Suffix
Assignment of a value. For example,
dst
dst + src
indicates the result is stored in the destination.
Exchange of two values
~
PS024406-0106
One’s complement unary operator
P R E L I M I N A R Y
Addressing Notation
ZLP12840 OTP MCU
Product Specification
115
Flags Register
The Flags Register informs the user of the current status of the Z8 CPU. It contains six bits
of status information. See Table 56.
Table 56. Flags Register (FLAGS)
Bit
7
6
5
4
3
2
1
0
Field
C
Z
S
O
D
H
F1
F2
Reset
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Bit
Position
Bank Independent: FCh; Linear 0FCh
Value Description
[7]
0
1
Carry Flag (C)
Set when the result of an arithmetic operation generates a carry out of or a borrow into
the high-order bit (bit 7) of the result. Also used in rotate and shift instructions.
Flag Clear
Flag Set
0
1
Zero Flag (Z)
Set when the result of an arithmetic operation is 0.
Flag Clear
Flag Set
0
1
Sign Flag (S)
Stores the value of the most significant bit following an arithmetic, logical, rotate, or
shift instruction.
Flag Clear
Flag Set
0
1
Overflow Flag (O)
Set when the result of an arithmetic operation is greater than 127.
Flag Clear
Flag Set
0
1
Decimal Adjust Flag (D)
Used for binary-coded decimal (BCD) arithmetic.
Flag Clear
Flag Set
0
1
Half Carry Flag (H)
Set when a carry out of or borrow into bit 3 of an arithmetic operation occurs.
Flag Clear
Flag Set
[6]
[5]
[4]
[3]
[2]
PS024406-0106
P R E L I M I N A R Y
Flags Register
ZLP12840 OTP MCU
Product Specification
116
Bit
Position
Value Description
[1]
0
1
User Flag 1 (F1)
Available to software for use as a general-purpose bit.
Bit Clear
Bit Set
0
1
User Flag 2 (F2)
Available to software for use as a general-purpose bit.
Bit Clear
Bit Set
[0]
Condition Codes
The C, Z, S and V flags control the operation of the conditional jump (JP cc and JR cc)
instructions. Sixteen frequently useful functions of the flag settings are encoded in a 4-bit
field called the condition code (cc). Table 57 summarizes the condition codes. Some
binary condition codes can be created using more than one assembly code mnemonic. The
result of the flag test operation determines if the conditional jump executes.
Table 57. Condition Codes
Binary
Hex
Assembly
Mnemonic
Definition
Flag Test Operation
0000
0
F
Always False
–
0001
1
LT
Less Than
(S XOR V) = 1
0010
2
LE
Less Than or Equal
(Z OR (S XOR V)) = 1
0011
3
ULE
Unsigned Less Than or Equal
(C OR Z) = 1
0100
4
OV
Overflow
V=1
0101
5
Ml
Minus
S=1
0110
6
Z
Zero
Z=1
0110
6
EQ
Equal
Z=1
0111
7
C
Carry
C=1
0111
7
ULT
Unsigned Less Than
C=1
1000
8
T (or blank) Always True
–
1001
9
GE
Greater Than or Equal
(S XOR V) = 0
1010
A
GT
Greater Than
(Z OR (S XOR V)) = 0
1011
B
UGT
Unsigned Greater Than
(C = 0 AND Z = 0)
PS024406-0106
P R E L I M I N A R Y
Condition Codes
ZLP12840 OTP MCU
Product Specification
117
Table 57. Condition Codes (Continued)
Binary
Hex
Assembly
Mnemonic
Definition
Flag Test Operation
1100
C
NOV
No Overflow
V=0
1101
D
PL
Plus
S=0
1110
E
NZ
Non-Zero
Z=0
1110
E
NE
Not Equal
Z=0
1111
F
NC
No Carry
C=0
1111
F
UGE
Unsigned Greater Than or
Equal
C=0
Z8 LXM CPU Instruction Summary
Table 58 summarizes the Z8 LXM CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
Table 58. Z8 LXM CPU Instruction Summary
Address
Mode
Assembly
Mnemonic
Symbolic Operation
ADC dst, src
dst
Flag States:
dst + src + C
* = State Depends on Result;
PS024406-0106
OpFlags
code(s)
(Hex) C Z S V D H
dst
src
r
r
12
r
Ir
R
Cycles
Fetch
Execute
6
5
13
6
5
R
14
10
5
R
IR
15
10
5
R
IM
16
10
5
IR
IM
17
10
5
* * * * 0 *
– = No Change; X = Undefined;
P R E L I M I N A R Y
0 = Cleared; 1 = Set
Z8 LXM CPU Instruction Summary
ZLP12840 OTP MCU
Product Specification
118
Table 58. Z8 LXM CPU Instruction Summary (Continued)
Address
Mode
Assembly
Mnemonic
Symbolic Operation
ADD dst, src
dst
AND dst, src
dst
CALL dst
dst AND src
SP
SP -2
@SP
PC
PC
dst
CCF
C
CLR dst
dst
COM dst
dst
CP dst, src
Flag States:
dst + src
~dst
dst – src – C
* = State Depends on Result;
PS024406-0106
dst
src
r
r
02
r
Ir
R
Cycles
Fetch
Execute
6
5
03
6
5
R
04
10
5
R
IR
05
10
5
R
IM
06
10
5
IR
IM
07
10
5
r
r
52
6
5
r
Ir
53
6
5
R
R
54
10
5
R
IR
55
10
5
R
IM
56
10
5
IR
IM
57
10
5
20
0
20
0
IRR
D4
DA
D6
~C
00h
OpFlags
code(s)
(Hex) C Z S V D H
* * * * 0 *
– * * 0 – –
– – – – – –
EF
* – – – – –
6
5
R
B0
– – – – – –
6
5
IR
B1
6
5
R
60
6
5
IR
61
6
5
6
5
– * * 0 – –
r
r
A2
* * * * – –
r
Ir
A3
6
5
R
R
A4
10
5
R
IR
A5
10
5
R
IM
A6
10
5
IR
IM
A7
10
5
– = No Change; X = Undefined;
P R E L I M I N A R Y
0 = Cleared; 1 = Set
Z8 LXM CPU Instruction Summary
ZLP12840 OTP MCU
Product Specification
119
Table 58. Z8 LXM CPU Instruction Summary (Continued)
Address
Mode
Assembly
Mnemonic
Symbolic Operation
DA dst
dst
DEC dst
dst
DECW dst
dst
DA(dst)
dst – 1
dst – 1
DI
Disable Interrupts
IRQCTL[7]
0
DJNZ dst, RA
dst
dst – 1
if dst 0
PC
PC + X
dst
src
OpFlags
code(s)
(Hex) C Z S V D H
R
40
IR
41
R
00
IR
01
RR
80
IR
81
r
* * * X – –
– * * * – –
– * * * – –
8F
– – – – – –
0A–FA
– – – – – –
Cycles
Fetch
Execute
8
5
8
5
6
5
6
5
10
5
10
5
6
1
NZ/Z
12/10
5
EI
Enable Interrupts
IRQCTL[7]
1
9F
– – – – – –
6
1
HALT
Halt Mode
7F
– – – – – –
7
0
INC dst
dst
R
20
– * * * – –
6
5
IR
21
6
5
r
0E–FE
6
5
RR
A0
10
5
IR
A1
10
5
INCW dst
dst
dst + 1
dst + 1
IRET
FLAGS
@SP
SP
SP + 1
PC
@SP
SP
SP + 2
IRQCTL[7]
1
JP dst
PC
JP cc, dst
JR dst
Flag States:
dst
* * * * * *
16
0
DA
8D
– – – – – –
12
0
IRR
30
8
0
DA
PC
RA
* = State Depends on Result;
PS024406-0106
BF
if cc is true
PC
dst
PC + X
– * * * – –
0D–FD – – – – – –
8B
– – – – – –
– = No Change; X = Undefined;
P R E L I M I N A R Y
T/F
12/10
0
12
0
0 = Cleared; 1 = Set
Z8 LXM CPU Instruction Summary
ZLP12840 OTP MCU
Product Specification
120
Table 58. Z8 LXM CPU Instruction Summary (Continued)
Address
Mode
Assembly
Mnemonic
JR cc, dst
LD dst, src
dst
if cc is true
PC
PC + X
RA
dst
LDC dst, src
dst
LDCI dst, src
LDX dst, src
NOP
src
src
dst
src
r
r+1
rr
rr + 1
dst
LDXI dst, src
Flag States:
Symbolic Operation
src
dst
src
r
r+1
rr
rr + 1
No operation
* = State Depends on Result;
PS024406-0106
src
OpFlags
code(s)
(Hex) C Z S V D H
0B–FB – – – – – –
Cycles
Fetch
Execute
T/F
12/10
0
r
IM
0C–FC – – – – – –
6
5
r
R
08–F8
6
5
R
r
09–F9
6
5
r
X(r)
C7
10
5
X(r)
r
D7
10
5
r
Ir
E3
6
5
R
R
E4
10
5
R
IR
E5
10
5
R
IM
E6
10
5
IR
IM
E7
10
5
Ir
r
F3
6
5
IR
R
F5
10
5
r
Irr
C2
12
0
Irr
r
D2
12
0
Ir
Irr
C3
18
0
Irr
Ir
D3
18
0
r
Irr
82
12
0
Irr
r
92
12
0
Ir
Irr
83
18
0
Irr
Ir
93
18
0
6
0
FF
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– = No Change; X = Undefined;
P R E L I M I N A R Y
0 = Cleared; 1 = Set
Z8 LXM CPU Instruction Summary
ZLP12840 OTP MCU
Product Specification
121
Table 58. Z8 LXM CPU Instruction Summary (Continued)
Address
Mode
Assembly
Mnemonic
Symbolic Operation
OR dst, src
dst
POP dst
dst OR src
dst
SP
PUSH src
@SP
SP + 1
SP
SP – 1
@SP
src
RCF
C
RET
PC
SP
D7 D6 D5 D4 D3 D2 D1 D0
dst
RLC dst
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
RR dst
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
RRC dst
D7 D6 D5 D4 D3 D2 D1 D0
dst
* = State Depends on Result;
PS024406-0106
src
r
r
42
r
Ir
R
C
Cycles
Fetch
Execute
6
5
43
6
5
R
44
10
5
R
IR
45
10
5
R
IM
46
10
5
IR
IM
47
10
5
10
5
10
5
10
1
12
1
R
50
IR
51
R
70
IR
71
– * * 0 – –
– – – – – –
– – – – – –
CF
0 – – – – –
6
5
AF
– – – – – –
14
0
R
90
* * * * – –
6
5
IR
91
6
5
R
10
6
5
IR
11
6
5
R
E0
6
5
IR
E1
6
5
R
C0
6
5
IR
C1
6
5
@SP
SP + 2
C
Flag States:
dst
0
RL dst
OpFlags
code(s)
(Hex) C Z S V D H
* * * * – –
* * * * – –
* * * * – –
– = No Change; X = Undefined;
P R E L I M I N A R Y
0 = Cleared; 1 = Set
Z8 LXM CPU Instruction Summary
ZLP12840 OTP MCU
Product Specification
122
Table 58. Z8 LXM CPU Instruction Summary (Continued)
Address
Mode
Assembly
Mnemonic
Symbolic Operation
SBC dst, src
dst
SCF
dst – src – C
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
SRP src
RP
STOP
Stop Mode
SUB dst, src
dst
SWAP dst
Flag States:
r
r
32
r
Ir
R
C
dst – src
dst[3:0]
* = State Depends on Result;
Cycles
Fetch
Execute
6
5
33
6
5
R
34
10
5
R
IR
35
10
5
R
IM
36
10
5
IR
IM
37
10
5
* * * * 1 *
DF
1 – – – – –
6
5
R
D0
* * * 0 – –
6
5
IR
D1
6
5
IM
(NOT dst) AND src
PS024406-0106
src
src
dst[7:4]
TCM dst, src
dst
1
SRA dst
OpFlags
code(s)
(Hex) C Z S V D H
31
– – – – – –
6
1
6F
– – – – – –
6
0
* * * * 1 *
6
5
r
r
22
r
Ir
23
6
5
R
R
24
10
5
R
IR
25
10
5
R
IM
26
10
5
IR
IM
27
10
5
8
5
8
5
6
5
R
F0
IR
F1
– * * X – –
r
r
62
– * * 0 – –
r
Ir
63
6
5
R
R
64
10
5
R
IR
65
10
5
R
IM
66
10
5
IR
IM
67
10
5
– = No Change; X = Undefined;
P R E L I M I N A R Y
0 = Cleared; 1 = Set
Z8 LXM CPU Instruction Summary
ZLP12840 OTP MCU
Product Specification
123
Table 58. Z8 LXM CPU Instruction Summary (Continued)
Address
Mode
Assembly
Mnemonic
Symbolic Operation
TM dst, src
dst AND src
dst
src
r
r
72
r
Ir
R
Flag States:
dst
dst XOR src
* = State Depends on Result;
PS024406-0106
Cycles
Fetch
Execute
6
5
73
6
5
R
74
10
5
R
IR
75
10
5
R
IM
76
10
5
IR
IM
77
10
5
WDT
XOR dst, src
OpFlags
code(s)
(Hex) C Z S V D H
– * * 0 – –
5F
– – – – – –
6
0
– * * 0 – –
6
5
r
r
B2
r
Ir
B3
6
5
R
R
B4
10
5
R
IR
B5
10
5
R
IM
B6
10
5
IR
IM
B7
10
5
– = No Change; X = Undefined;
P R E L I M I N A R Y
0 = Cleared; 1 = Set
Z8 LXM CPU Instruction Summary
ZLP12840 OTP MCU
Product Specification
124
Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than those listed in Table 59 may cause permanent damage to the device.
These ratings are stress ratings only. Functional operation of the device at any condition
outside those indicated in the operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. For improved reliability, unused inputs should be tied to one of the supply voltages (VDD or VSS ).
Table 59. Absolute Maximum Ratings
Parameter
Min.
Max.
Units
0
+70
C
Storage temperature
–65
+150
C
Voltage on any pin with respect to VSS*
–0.3
+5.5
V
Voltage on VDD pin with respect to VSS
–0.3
+3.6
V
Maximum current on input and/or inactive output pin
–5
+5
µA
Maximum output current from active output pin
–25
+25
mA
75
mA
Ambient temperature under bias
Maximum current into VDD or out of VSS
*Note: This voltage applies to all pins except VDD, P32, and P33.
PS024406-0106
P R E L I M I N A R Y
Electrical Characteristics
ZLP12840 OTP MCU
Product Specification
125
Standard Test Conditions
The characteristics listed in this product specification apply for standard test conditions as
noted. All voltages are referenced to Ground. Positive current flows into the referenced
pin (see Figure 39).
From Output
Under Test
I
150 pF
Figure 39. Test Load Diagram
Capacitance
Table 60 lists the capacitances.
Table 60. Capacitance
Parameter
Maximum
Input capacitance
12 pF
Output capacitance
12 pF
I/O capacitance
12 pF
Note: TA = 25° C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND.
PS024406-0106
P R E L I M I N A R Y
Standard Test Conditions
ZLP12840 OTP MCU
Product Specification
126
DC Characteristics
Table 61 describes the direct current characteristics of the ZLP12840 OTP MCU.
Table 61. DC Characteristics
TA = 0º C to +70º C
Symbol
Parameter
VCC
Supply Voltage1
VCH
Clock Input High
Voltage
VCL
VCC
Min
Typ
Max
Units Conditions
2.0
3.6
V
See Note 5
2.0–3.6
0.8 VCC
VCC+0.3
V
Driven by External
Clock Generator
Clock Input Low
Voltage
2.0–3.6
VSS–0.3
0.4
V
Driven by External
Clock Generator
VIH
Input High Voltage
2.0–3.6
0.7 VCC
VCC+0.3
V
VIL
Input Low Voltage
2.0–3.6
VSS–0.3
0.2 VCC
V
VOH1
Output High Voltage
2.0–3.6
VCC–0.4
V
IOH = –0.5 mA
VOH2
Output High Voltage
(P36, P37, P00,
P01)
2.0–3.6
VCC–0.8
V
IOH = –7 mA
VOL1
Output Low Voltage
2.0–3.6
0.4
V
IOL = 4.0 mA
VOL2
Output Low Voltage
(P00, P01, P36,
P37)
2.0–3.6
0.8
V
IOL = 10 mA
VOFFSET Comparator Input
Offset Voltage
2.0–3.6
25
mV
VREF
Comparator
Reference Voltage
2.0–3.6
0
VDD
–1.75
V
IIL
Input Leakage
2.0–3.6
–1
1
IIL1
Input Leakage IR
Amp (P31)
2.0–3.6
–2.5
–10
A
µA
VIN = 0 V, VCC; pullups disabled.
VIN = 0 V, IR amp
enabled.
Notes:
1. ZiLOG recommends adding a filter capacitor (minimum 0.1 F), physically close to VDD and VSS if operating
voltage fluctuations are anticipated, such as those resulting from driving an infrared LED.
2. All outputs unloaded, inputs at rail.
3. CL1 = CL2 = 100 pF.
4. Oscillator stopped.
5. Oscillator stops when V CC falls below VBO limit.
PS024406-0106
P R E L I M I N A R Y
DC Characteristics
ZLP12840 OTP MCU
Product Specification
127
Table 61. DC Characteristics (Continued)
TA = 0º C to +70º C
Symbol
Parameter
IOL
Output Leakage
ICC
ICC1
ICC2
Supply
Current2,3
Current2,3
Standby
(HALT mode)
Current4
Standby
(STOP mode)
VCC
Min
2.0–3.6
–1
Typ
Max
Units Conditions
1
mA
V IN = 0 V, VCC
2.0
1
3
mA
at 8.0 MHz
3.6
5
10
mA
at 8.0 MHz
2.0
0.5
1.6
mA
3.6
0.8
2.0
mA
VIN = 0 V, VCC at
8.0 MHz
2.0
1.6
8
µA
3.6
1.8
10
µA
2.0
5
20
µA
3.6
VIN = 0 V, VCC WDT
is not running
VIN = 0 V, VCC WDT
is running
8
30
µA
ILV
Current5
Standby
(Low Voltage)
1.2
6
A
Measured at 1.3 V
VBO
VCC Low Voltage
Protection
1.9
2.0
V
8 MHz maximum
external clock
frequency
VLVD
VCC Low Voltage
Detection
2.4
V
VHVD
VCC High Voltage
Detection
2.7
V
TONIRAMP Wake-up time from
disabled mode
IDET
IR amp current for
signal detection
2.0–3.6
2.0–3.6
10
20
µs
100
µA
IR amp enabled
Notes:
1. ZiLOG recommends adding a filter capacitor (minimum 0.1 F), physically close to VDD and VSS if operating
voltage fluctuations are anticipated, such as those resulting from driving an infrared LED.
2. All outputs unloaded, inputs at rail.
3. CL1 = CL2 = 100 pF.
4. Oscillator stopped.
5. Oscillator stops when V CC falls below VBO limit.
PS024406-0106
P R E L I M I N A R Y
DC Characteristics
ZLP12840 OTP MCU
Product Specification
128
AC Characteristics
Figure 40 and Table 62 describe the Alternating Current (AC) characteristics.
1
3
Clock
2
7
2
3
7
TIN
4
5
6
IRQN
8
9
Clock
Setup
11
Stop-Mode
Recovery Source
10
Figure 40. AC Timing Diagram
PS024406-0106
P R E L I M I N A R Y
AC Characteristics
ZLP12840 OTP MCU
Product Specification
129
Table 62. AC Characteristics
TA = 0º C to +70º C
8.0 MHz
No
Symbol
Parameter
VCC
Min.
Max.
Units
1
TPC
Input Clock Period1
2.0–3.6
121
DC
ns
2
TRC,TFC
Clock Input Rise and
Fall Times1
2.0–3.6
25
ns
3
TWC
Input Clock Width1
2.0–3.6
37
ns
4
TWTIN L
Timer Input
Low Width1
2.0
100
ns
3.6
70
ns
5
TWTIN H
Timer Input High
Width1
2.0–3.6
3TPC
6
TPTIN
Timer Input Period1
2.0–3.6
8TPC
7
TRTIN,TFTIN
Timer Input Rise and
Fall Timers1
2.0–3.6
8
TWIL
Interrupt Request
Low Time1,2
2.0
100
ns
3.6
70
ns
9
TWIH
Interrupt Request Input 2.0–3.6
High Time1,2
10
TWSM
Stop-Mode Recovery
Width Spec
2.0–3.6
100
WDTMR
(Bits 1:0)
ns
5TPC
123
ns
10 TPC4
11
TOST
Oscillator
Start-Up Time4
2.0–3.6
12
TWDT
Watch-Dog Timer
Delay Time
2.0–3.6
5
ms
0, 0
2.0–3.6
10
ms
0, 1
2.0–3.6
20
ms
1, 0
2.0–3.6
80
ms
1, 1
5TPC
Notes:
1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request through Port 3 (P33:P31).
3. SMR – bit 5 = 1.
4. SMR – bit 5 = 0.
PS024406-0106
P R E L I M I N A R Y
AC Characteristics
ZLP12840 OTP MCU
Product Specification
130
Table 62. AC Characteristics (Continued)
TA = 0º C to +70º C
8.0 MHz
No
Symbol
Parameter
VCC
Min.
Max.
Units
13
TPOR
Power-On Reset
2.0–3.6
2.5
10
ms
14
fMAX
Maximum frequency of
input signal for IR
amplifier
500
kHz
15
fMIN
Minimum frequency of
input signal for IR
amplifier
0
kHz
WDTMR
(Bits 1:0)
Notes:
1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request through Port 3 (P33:P31).
3. SMR – bit 5 = 1.
4. SMR – bit 5 = 0.
PS024406-0106
P R E L I M I N A R Y
AC Characteristics
ZLP12840 OTP MCU
Product Specification
131
Packaging
Figure 41 illustrates the 28-pin SSOP (shrink small outline package) for the ZLP12840
device.
Ü
îè
Ý
ïë
ÍÇÓÞÑÔ
Ø
Û
ï
ïì
ÜÛÌß×Ô ß
Ó×ÔÔ×ÓÛÌÛÎ
ÒÑÓ
ÓßÈ
Ó×Ò
ÒÑÓ
ÓßÈ
ß
ïòéí
ïòèê
ïòçç
ðòðêè
ðòðéí
ðòðéè
ßï
ðòðë
ðòïí
ðòîï
ðòððî
ðòððë
ðòððè
ßî
ïòêè
ïòéí
ïòéè
ðòðêê
ðòðêè
ðòðéð
Þ
ðòîë
ðòíè
ðòðïð
Ý
ðòðç
ðòîð
ðòððì
ðòððê
ðòððè
Ü
ïðòðé
ïðòîð
ïðòíí
ðòíçé
ðòìðî
ðòìðé
Û
ëòîð
ëòíð
ëòíè
ðòîðë
ðòîðç
ðòîïî
»
ßî
»
×ÒÝØ
Ó×Ò
ðòêë ÌÇÐ
ðòðïë
ðòðîëê ÌÇÐ
Ø
éòêë
éòèð
éòçð
ðòíðï
ðòíðé
ðòíïï
Ô
ðòêí
ðòéë
ðòçë
ðòðîë
ðòðíð
ðòðíé
ß
Þ
ÍÛßÌ×ÒÙ ÐÔßÒÛ
Ô
ÝÑÒÌÎÑÔÔ×ÒÙ Ü×ÓÛÒÍ×ÑÒÍæ ÓÓ
ÔÛßÜÍ ßÎÛ ÝÑÐÔßÒßÎ É×ÌØ×Ò òððì ×ÒÝØÛÍò
ðóè
ÜÛÌß×Ô ùßù
Figure 41. 28-Pin SSOP Package Diagram
PS024406-0106
P R E L I M I N A R Y
Packaging
ZLP12840 OTP MCU
Product Specification
132
Figure 42 illustrates the 28-pin SOIC (small outline integrated circuit) package for the
ZLP12840 device.
Figure 42. 28-Pin SOIC Package Diagram
PS024406-0106
P R E L I M I N A R Y
Packaging
ZLP12840 OTP MCU
Product Specification
133
Figure 43 illustrates the 28-pin PDIP (plastic dual inline package) for the ZLP12840
device.
Figure 43. 28-Pin PDIP Package Diagram
PS024406-0106
P R E L I M I N A R Y
Packaging
ZLP12840 OTP MCU
Product Specification
134
Figure 44 illustrates the 20-pin SSOP (shrink small outline package) for the ZLP12840
device.
Figure 44. 20-Pin SSOP Package Diagram
PS024406-0106
P R E L I M I N A R Y
Packaging
ZLP12840 OTP MCU
Product Specification
135
Figure 45 illustrates the 20-pin SOIC (small outline integrated circuit) package for the
ZLP12840 device.
Figure 45. 20-Pin SOIC Package Diagram
PS024406-0106
P R E L I M I N A R Y
Packaging
ZLP12840 OTP MCU
Product Specification
136
Figure 46 illustrates the 20-pin PDIP (plastic dual inline package) for the ZLP12840
device.
Figure 46. 20-Pin PDIP Package Diagram
PS024406-0106
P R E L I M I N A R Y
Packaging
ZLP12840 OTP MCU
Product Specification
137
Ordering Information
Table 63 provides a product specification index code and a brief description of each part.
Each of the parts listed in Table 63 is shown in a lead-free package.
The use of lead-free packaging adheres to a socially responsible environmental standard.
See the Part Number Description on page 138 for a description of a part number’s unique
identifying attributes.
Table 63. ZLP12840 OTP MCU Part Numbers Description
PSI #
Description
PSI #
Description
Lead-Free Environmental Flow
ZLP12840H2828G
28-pin SSOP 128K OTP
ZLP12840H2896G
28-pin SSOP 96K OTP
ZLP12840S2828G
28-Pin SOIC 128K OTP
ZLP12840S2896G
28-Pin SOIC 96K OTP
ZLP12840P2828G
28-Pin PDIP 128K OTP
ZLP12840P2896G
28-Pin PDIP 96K OTP
ZLP12840H2028G
20-Pin SSOP 128K OTP
ZLP12840H2096G
20-Pin SSOP 96K OTP
ZLP12840S2028G
20-pin SOIC 128K OTP
ZLP12840S2096G
20-pin SOIC 96K OTP
ZLP12840P2028G
20-pin PDIP 128K OTP
ZLP12840P2096G
20-pin PDIP 96K OTP
ZLP12840H2864G
28-pin SSOP 64K OTP
ZLP12840H2832G
28-pin SSOP 32K OTP
ZLP12840S2864G
28-Pin SOIC 64K OTP
ZLP12840S2832G
28-Pin SOIC 32K OTP
ZLP12840P2864G
28-Pin PDIP 64K OTP
ZLP12840P2832G
28-Pin PDIP 32K OTP
ZLP12840H2064G
20-Pin SSOP 64K OTP
ZLP12840H2032G
20-Pin SSOP 32K OTP
ZLP12840S2064G
20-pin SOIC 64K OTP
ZLP12840S2032G
20-pin SOIC 32K OTP
ZLP12840P2064G
20-pin PDIP 64K OTP
ZLP12840P2032G
20-pin PDIP 32K OTP
Crimzon™ 128K Emulator
ZLP128ICE01ZEM
Crimzon™ In-Circuit Emulator
Navigate your browser to ZiLOG’s website to order the ZLP12840 microcontroller. Or,
contact your local ZiLOG Sales Office. ZiLOG provides additional assistance on its Customer Service page, and is also here to help with Technical Support issues. For ZILOG’s
valuable development tools and downloadable software, visit the ZiLOG website.
PS024406-0106
P R E L I M I N A R Y
Ordering Information
ZLP12840 OTP MCU
Product Specification
138
Part Number Description
ZiLOG part numbers consist of a number of components, as shown in Figure 47. The
example part number ZLP12840H2828G is a Crimzon™ One-Time Programmable (OTP)
product in a 28-pin SSOP package, with 128 KB of OTP and built with lead-free solder.
ZLP12840H2828G
Environmental Flow
G = Lead Free
Memory Size
28 = 128KB OTP
96 = 96KB OTP
64 = 64KB OTP
32 = 32KB OTP
Number of Pins in Package
20 = 20 Pins
28 = 28 Pins
Package Type
H = SSOP
S = SOIC
P = PDIP
Product Number: 12840
Product Line: Crimzon™ OTP
ZiLOG Product Prefix
Figure 47. Part Number Example
PS024406-0106
P R E L I M I N A R Y
Part Number Description
ZLP12840 OTP MCU
Product Specification
139
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows
about this product at this time, but additional features or nonconformance with some
aspects of the document might be found, either by ZiLOG or its customers in the course of
further application and characterization work. In addition, ZiLOG cautions that delivery
might be uncertain at times due to start-up yield issues.
ZiLOG, Inc.
532 Race Street
San Jose, CA 95126-3432
Telephone: (408) 558-8500
FAX: 408 558-8300
www.ZiLOG.com
PS024406-0106
P R E L I M I N A R Y
Precharacterization Product
ZLP12840 OTP MCU
Product Specification
140
Customer Feedback Form
Customer Support
If you experience any problems while operating this product, please check the ZiLOG Knowledge Base:
http://kb.zilog.com/kb/oKBmain.asp
If you cannot find an answer or have further questions, please see the ZiLOG Technical Support web page:
http://support.zilog.com
PS024406-0106
P R E L I M I N A R Y
Customer Feedback Form
ZLP12840 OTP MCU
Product Specification
141
Document Information
Document Number Description
The Document Control Number that appears in the footer on each page of this document
contains unique identifying attributes, as indicated in the following example:
PS024406-0106
Year Published
Month Published
Revision Number
Unique Document Number
Product Specification Prefix
Figure 48. Document Number Example
Change Log
PS024406-0106
Rev
Date
Purpose
01
03/05
Original issue
02
09/05
Updates prior to publication
03
09/05
Implement review comments
04
11/05
Minor changes to pages 30, 50, 54, 60, 65, 72, 74, 80-81, 88, 90, 9596, 101, 106, 125-126, 129, and 136-137.
05
12/05
Updated Clock and Input/Output Ports section
06
01/06
Removed the trademark symbol (TM) from LXM
P R E L I M I N A R Y
Document Information
ZLP12840 OTP MCU
Product Specification
142
Index
Numerics
interrupt 84
MCU 4
reset and watch-dog timer 94
UART 44
brown-out, voltage 95
12-bit address map 35
16-bit counter/timer circuits 66
20-pin
package pins 5, 7
PDIP package 136
SOIC package 135
SSOP package 134
28-pin
package pins 8, 9, 10
PDIP package 133
SOIC package 132
SSOP package 131
8-bit counter/timer circuits 61
C
A
absolute maximum ratings 124
AC characteristics 128, 129
AC timing 128
active low notation 3
address
12-bit linear 35
notation 112
amplifier, infrared 42
AND caution 75
architecture
MPU 1
UART 43
asynchronous data 45
B
baud rate generator
description 50
example 52
interrupt 50
Baud Rate Generator Constant register (BCNST) 55
block diagram
counter/timer 57
PS024406-0106
capacitance 125
caution
open-drain output 11
stopping timer 62
timer count 61
timer modes 77
timer registers 67
UART transmit 46
changes, document 141
characteristics
AC 128, 129
DC 126
electrical 124
clock 91
internal signals 92
CMOS gate, caution 11
comparator
inputs 19
outputs 19
condition codes 116
conditions, test 125
connection, power 3
constant memory 28, 29
constant, baud rate 55
counter/timer
block diagram 57
capture flowchart 63
input circuit 59
output configuration 18
crystal 91
crystal oscillator pins (XTAL1, XTAL2) 92
P R E L I M I N A R Y
Index
ZLP12840 OTP MCU
Product Specification
143
D
functions, I/O port pins 11
data format, UART 44, 45
data handling, UART 49
DC characteristics 126
demodulation
changing mode 77
flowchart 63, 64
timer 62, 67
demodulation mode flowchart 65
device
architecture 1
block diagram 4
features 1
part numbers 137
diagram, package 131, 132, 133, 134, 135, 136
divisor, baud rate 55
document
changes 141
information 141
number format 141
E
electrical characteristics 124
error handling, UART 49
example
BCNST register 52
register pointer 33
F
fast recovery, stop mode 97
features, device 1
feedback form 140
flags register 115
floating CMOS gate, caution 11
flowchart
demodulation mode 63, 64, 65
timer transmit 60
UART receive 50
form, feedback 140
format, UART data 44, 45
functional block diagram 4
PS024406-0106
H
h suffix 61
HALT mode 96
handshaking, UART 48
I
I/O port pin functions 11
infrared learning amplifier 42
input
comparator 19
counter/timer 59
timers 58
instruction set summary 117
instruction symbols 114
internal clock 92
interrupt
baud rate generator 50
block diagram 84
description 83
mask register 90
priority register 87
request register 86, 88
source 85
stop-mode recovery 97
type 85
UART 48
UART receive 47, 48, 50
UART transmit 46, 48
vector 85
Interrupt Mask Register (IMR) 90
Interrupt Priority Register (IPR) 87
Interrupt Request Register (IRQ) 86, 88
L
LDE and LDEI instructions removed 34
LDX, LDXI instruction addresses 35
leakage, caution 11
learning amplifier, infrared 42
linear address 33
P R E L I M I N A R Y
Index
ZLP12840 OTP MCU
Product Specification
144
load, test 125
Low-Voltage Detection Register (LVD) 96
M
map
program/constant memory 29
register 12-bit 35
register 8-bit 31
register file summary 39
maximum ratings 124
MCU
block diagram 4
features 1
part numbers 137
memory
address, linear 33
program/constant 28
program/constant map 29
register 12-bit map 35
register file map 31
register file summary 39
modulo-N mode 62, 67
MPU architecture 1
N
notation
addressing 112
operand 112
O
open-drain output caution 11
operand symbols 112
operation, UART 44
OR caution 75
ordering information 137
oscillator 91
OTP memory 28
output
comparator 19
timer/counter 69
timer/counter circuit 70
PS024406-0106
timer/counter configuration 18
overline, in text 3
overrun, UART 49
P
package diagram 131, 132, 133, 134, 135, 136
package information 131
parity, UART data 45
part number format 137, 138
pin description 5
pin function
port 0 12
port 2 13
port 3 14
port 3 summary 17
ping-pong mode 68, 69
pins
20-pin package 5, 7
28-pin package 8, 9, 10
polled UART receive 47
polled UART transmit 45
port 0
configuration 13
pin function 12
Port 0 Mode Register (P01M) 21
Port 0 Register (P0) 22
port 2
configuration 14
pin function 13
Port 2 Mode Register (P2M) 23
Port 2 Register (P2) 24
port 3
configuration 15
counter/timer output 18
pin function 14
pin function 17
Port 3 Mode Register (P3M) 25
Port 3 Register (P3) 26
Port Configuration Register (PCON) 20
port pin functions 11
power connection 3
power management 93
power-on reset timer 94
P R E L I M I N A R Y
Index
ZLP12840 OTP MCU
Product Specification
145
precharacterization 139
program memory
description 28
map 29
Program Memory Paging Register (PMPR) 36
programming summary 112
pull-up, disabled 11
R
ratings, maximum 124
register
BCNST 55
CTR1 77
CTR3 81
HI16 72
HI8 71
IMR 90
IPR 87
IRQ 86, 88
LO16 72
LO8 71
LVD 96
P0 22
P01M 21
P2 24
P2M 23
P3 26
P3M 25
PCON 20
PMPR 36
RP 37
SMR 100
SMR1 103
SMR2 105
SMR3 108
SMR4 109
SPL 38
UCTL 54
URDATA 52
USER 38
UST 53
UTDATA 52
WDTMR 110
PS024406-0106
register file
12-bit address 35
address summary 39
description 29
memory map 31
register pointer
detail 32
example 33
Register Pointer Register (RP) 37
Register Pointer register (RP) 37
reset
block diagram 94
delay bypass 97
features 93
POR timer 94
status 95
timer terminal count 75
S
SCLK signal 92
single-pass mode 62, 67
source
interrupt 85
stop-mode recovery 98, 99, 102, 104, 107
stack 30
Stack Pointer Register (SPL) 38
standard test conditions 125
standby, brown-out 95
status
reset 95
UART 53
stop bit, UART 49
stop mode
fast recovery 97
stop-mode
description 97
recovery events 98, 101, 104, 105
recovery interrupt 97
recovery source 98, 99, 102, 104, 107
recovery status 95
Stop-Mode Recovery Register (SMR) 100
Stop-Mode Recovery Register 1 (SMR1) 103
Stop-Mode Recovery Register 2 (SMR2) 105
P R E L I M I N A R Y
Index
ZLP12840 OTP MCU
Product Specification
146
Stop-Mode Recovery Register 3 (SMR3) 108
Stop-Mode Recovery Register 4 (SMR4) 109
suffix, h 61
symbols
address 112
instruction 114
operand 112
T
T16_OUT signal
modulo-N mode 67
single-pass mode 67
T8_OUT signal
modulo-N mode 62
single-pass mode 62
TCLK signal 92
terminal count, reset 75
test conditions 125
test load 125
timer
block diagram 57
changing mode 77
description 57
input circuit 58, 59
output circuit 70
output configuration 18
output description 69
reset 94
starting count caution 61
stopping caution 62
T16 demodulation 67
T16 transmit 66
T16_OUT signal 67
T8 demodulation 62
T8 transmit 59
T8_OUT signal 62
transmit flowchart 60
transmit versus demodulation mode 77
Timer 16 Capture High Register (HI16) 72
Timer 16 Capture Low Register (L016) 72
Timer 16 Control register (CTR2) 80
Timer 16 High Hold register (TC16H) 73
Timer 16 Low Hold Register (TC16L) 73
PS024406-0106
Timer 8 and Timer 16 Common Functions Register
(CTR1) 77
Timer 8 Capture High Register (HI8) 71
Timer 8 Capture Low Register (L08) 71
Timer 8 Control Register (CTR0) 75
Timer 8 High Hold Register (TC8H) 74
Timer 8 Low Hold Register (TC8L) 74
Timer 8/Timer 16 Control Register (CTR3) 81
timing, AC 128
transmit caution, UART 46
transmit mode
caution 77
flowchart 60
timer 59, 66
U
UART
architecture 43
baud rate generator 50
block diagram 44
data and error handling 49
data format 44, 45
description 43
interrupts 48
operation 44
overrun error 49
polled receive 47
polled transmit 45
receive interrupt 47, 48, 50
stop bit 49
transmit caution 46
transmit interrupt 46, 48
UART Control Register (UCTL) 54
UART Receive/Transmit Data Register (URDATA/
UTDATA) 52
UART Status Register (UST) 53
User Data Register (USER) 38
V
vector, interrupt 85
voltage
brown-out 95
P R E L I M I N A R Y
Index
ZLP12840 OTP MCU
Product Specification
147
detection 95
detection register 96
W
watch-dog timer
description 110
diagram 94
Watch-Dog Timer Mode Register (WDTMR) 110
X
XTAL1 pin 92
XTAL2 pin 92
Z
ZLP12840 MCU
block diagram 4
features 1
part numbers 137
PS024406-0106
P R E L I M I N A R Y
Index