73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem Simplifying System Integration™ DATA SHEET JUNE 2008 DESCRIPTION FEATURES • The 73K224L is a highly integrated single-chip modem IC which provides the functions needed to construct a V.22bis compatible modem, capable of 2400 bit/s full-duplex operation over dial-up lines. The 73K224L offers excellent performance and a high level of functional integration in a single 28-pin DIP package. This device supports V.22bis, V.22, V.21, Bell 212A and Bell 103 modes of operation, allowing both synchronous and asynchronous communication. The 73K224L is designed to appear to the systems designer as a microprocessor peripheral, and will easily interface with popular single-chip microprocessors (80C51 typical) for control of modem functions through its 8-bit multiplexed address/data bus or via an optional serial control bus. An ALE control line simplifies address demultiplexing. Data communications normally occur through a separate serial port. The 73K224L is pin and software compatible with the 73K212L and 73K222L singlechip modem ICs, allowing system upgrades with a single component change. • • • • • • • • • The 73K224L operates from a single +5V supply for low power consumption. • • The 73K224L is ideal for use in either free-standing or integral system modem products where full-duplex • (continued) • One-chip multi-mode V.22bis/V.22/V.21 and Bell 212A/103 compatible modem data pump FSK (300 bit/s), DPSK (600, 1200 bit/s), or QAM (2400 bit/s) encoding Pin and software compatible with other TERIDIAN Semiconductor Corporation K-Series 1-chip modems Interfaces directly with standard microcontrollers (80C51 typical) Parallel microcontroller bus for modem control and status monitoring functions Selectable asynch/synch with internal buffer/debuffer and scrambler/descrambler functions All synchronous and asynchronous operating modes (internal, external, slave) Adaptive equalization for optimum performance over all lines Programmable transmit attenuation (16 dB, 1 dB steps), selectable receive boost (+18 dB) Call progress, carrier, answer tone, unscrambled mark, S1, and signal quality monitors DTMF, answer and guard tone generators Test modes available: ALB, DL, RDL, Mark, Space, Alternating bit, S1 pattern CMOS technology for low power consumption (typically 100 mW @ 5V) with power-down mode (15 mW @ 5V) TTL and CMOS compatible inputs and outputs BLOCK DIAGRAM DTMF, ANSWER, GUARD & CALLING TONE GENERATOR FSK MODULATOR 8-BIT P BUS BUFFER SCRAMBLER DIBIT/ QUADBIT ENCODER TXA FIR PULSE SHAPER QAM/ DPSK MODULATOR + EQUALIZER + FILTER FILTER ATTEN I/F FILTER DEBUFFER DESCRAMBLER DIBIT/ QUADBIT DECODER DIGITAL SIGNAL PROCESSOR RECEIVE FUNCTIONS A/D FIXED DEMOD TXD RXA EQUALIZER FILTER FILTER AGC GAIN BOOST SERIAL I/F RXD TONE DETECTION Page: 1 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET DESCRIPTION (continued) 2400 bit/s data communications over the 2-wire switched telephone network is desired. Its high functionality, low power consumption, and efficient packaging simplify design requirements and increase system reliability. The 73K224L is designed to be a complete V.22bis compatible modem on a chip. The complete modem requires only the addition of the phone line interface, a microcontroller for modem control and status monitoring, and RS-232 level converters for a typical system. Many functions were included to simplify implementation of typical modem designs. In addition to the basic 2400 bit/s QAM, 600/1200 bit/s DPSK and 300 bit/s FSK modulator/demodulator sections, the device also includes SYNCH/ASYNCH converters, scrambler/descrambler, call progress tone detect, DTMF tone generator capabilities and handshake pattern detectors. V.22bis, V.22, V.21 and Bell 212A/103 modes are supported (synchronous and asynchronous) and test modes are provided for diagnostics. Most functions are selectable as options and logical defaults are provided. stream. The demodulator also recovers the clock, which was encoded into the analog signal during modulation. Demodulation occurs using either a 1200 Hz carrier (answer mode or ALB originate mode) or a 2400 Hz carrier (originate mode or ALB answer mode). Adaptive equalization is also used in DPSK modes for optimum operation with varying line conditions. FSK MODULATOR/DEMODULATOR The FSK modulator produces a frequency modulated analog output signal using two discrete frequencies to represent the binary data. The Bell 103 standard frequencies of 1270 and 1070 Hz (originate mark and space) and 2225 and 2025 Hz (answer mark and space) are used when this mode is selected. V.21 mode uses 980 and 1180 Hz (originate, mark and space) or 1650 and 1850 Hz (answer, mark and space). Demodulation involves detecting the received frequencies and decoding them into the appropriate binary value. The rate converter and scrambler/descrambler are automatically bypassed in the FSK modes. PASSBAND FILTERS AND EQUALIZERS OPERATION QAM MODULATOR/DEMODULATOR The 73K224L encodes incoming data into quad-bits represented by 16 possible signal points with specific phase and amplitude levels. The baseband signal is then filtered to reduce intersymbol interference on the bandlimited telephone network. The modulator transmits this encoded data using either a 1200 Hz (originate mode) or 2400 Hz (answer mode) carrier. The demodulator, although more complex, essentially reverses this procedure while also recovering the data clock from the incoming signal. Adaptive equalization corrects for varying line conditions by automatically changing filter parameters to compensate for line characteristics. DPSK MODULATOR/DEMODULATOR The 73K224L modulates a serial bit stream into di-bit pairs that are represented by four possible phase shifts as prescribed by the Bell 212A/V.22 standards. The base-band signal is then filtered to reduce intersymbol interference on the bandlimited 2-wire PSTN line. Transmission occurs on either a 1200 Hz (originate mode) or 2400 Hz carrier (answer mode). Demodulation is the reverse of the modulation process, with the incoming analog signal eventually decoded into di-bits and converted back to a serial bit Page: 2 of 31 High and low band filters are included to shape the amplitude and phase response of the transmit and receive signals and provide compromise delay equalization and rejection of out-of-band signals. Amplitude and phase equalization are necessary to compensate for distortion of the transmission line and to reduce intersymbol interference in the bandlimited receive signal. The transmit signal filtering corresponds to a 75% square root of raised Cosine frequency response characteristic. ASYNCHRONOUS MODE The Asynchronous mode is used for communication with asynchronous terminals which may communicate at 600,1200, or 2400 bit/s +1%, -2.5% even though the modem’s output is limited to the nominal bit rate ±.01% in DPSK and QAM modes. When transmitting in this mode the serial data on the TXD input is passed through a rate converter which inserts or deletes stop bits in the serial bit stream in order to output a signal that is the nominal bit rate ±.01%. This signal is then routed to a data scrambler and into the analog modulator where quad-bit/di-bit encoding results in the output signal. Both the rate converter and scrambler can be bypassed for handshaking, and synchronous operation as selected. Received data is processed in a similar fashion except that the © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET rate converter now acts to reinsert any deleted stop bits and output data to the terminal at no greater than the bit rate plus 1%. An incoming break signal (low through two characters) will be passed through without incorrectly inserting a stop bit. The SYNC/ASYNC converter also has an extended Overspeed mode, which allows selection of an output overspeed range of either +1% or +2.3%. In the extended Overspeed mode, stop bits are output at 7/8 the normal width. Both the SYNC/ASYNC rate converter and the data descrambler are automatically bypassed in the FSK modes. SYNCHRONOUS MODE Synchronous operation is possible only in the QAM or DPSK modes. Operation is similar to that of the Asynchronous mode except that data must be synchronized to a provided clock and no variation in data transfer rate is allowable. Serial input data appearing at TXD must be valid on the rising edge of TXCLK. TXCLK is an internally derived 1200 or 2400 Hz signal in Internal mode and is connected internally to the RXCLK pin in Slave mode. Receive data at the RXD pin is clocked out on the falling edge of RXCLK. The asynch/synch converter is bypassed when Synchronous mode is selected and data is transmitted at the same rate as it is input. Page: 3 of 31 PARALLEL BUS INTERFACE Eight 8-bit registers are provided for control, option select, and status monitoring. These registers are addressed with the AD0, AD1, and AD2 multiplexed address lines (latched by ALE) and appear to a control microprocessor as seven consecutive memory locations. Six control registers are read/write memory. The detect and ID registers are read only and cannot be modified except by modem response to monitored parameters. SERIAL CONTROL MODE The serial Command mode allows access to the 73K224 control and status registers via a serial control port. In this mode the AD0, AD1, and AD2 lines provide register addresses for data passed through AD7 (DATA) pin under control of the RD and WR lines. A read operation is initiated when the RD line is taken low. The next eight cycles of EXCLK will then transfer out eight bits of the selected address location LSB first. A write takes place by shifting in eight bits of data LSB first for eight consecutive cycles of EXCLK. WR is then pulsed low and data transfer into the selected register occurs on the rising edge of WR. DTMF GENERATOR The DTMF generator controls the sending of the sixteen standard DTMF tone pairs. The tone pair sent is determined by selecting TRANSMIT DTMF (bit D4) and the 4 DTMF bits (D0-D3) of the TONE register. Transmission of DTMF tones from TXA is gated by the TRANSMIT ENABLE bit of CR0 (bit D1) as with all other analog signals. © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET PIN DESCRIPTION POWER NAME TYPE DESCRIPTION GND I System Ground. VDD I Power supply input, 5V -5% +10%. Bypass with 0.22 µF and 22 µF capacitors to GND. VREF O An internally generated reference voltage. Bypass with 0.22 µF capacitor to GND. ISET I Chip current reference. Sets bias current for op-amps. The chip current is set by connecting this pin to VDD through a 2 MΩ resistor. Iset should be bypassed to GND with a 0.22 µF capacitor. PARALLEL MICROPROCESSOR INTERFACE ALE AD0- AD7 I Address latch enable. The falling edge of ALE latches the address on AD0-AD2 and the chip select on CS. I/O Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal registers. /Tristate CS I Chip select. A low on this pin allows a read cycle or a write cycle to occur. AD0AD7 will not be driven and no registers will be written if CS (latched) is not active. CS is latched on the falling edge of ALE. CLK O Output clock. This pin is selectable under processor control to be either the crystal frequency (for use as a processor clock) or 16 x the data rate for use as a baud rate clock in QAM/DPSK modes only. The pin defaults to the crystal frequency on reset. INT O Interrupt. This open drain /weak pull-up, output signal is used to inform the processor that a detect flag has occurred. The processor must then read the detect register to determine which detect triggered the interrupt. INT will stay active until the processor reads the detect register or does a full reset. RD I Read. A low requests a read of the 73K224L internal registers. Data cannot be output unless both RD and the latched CS are active or low. RESET I Reset. An active high signal on this pin will put the chip into an inactive state. All control register bits (CR0, CR1, CR2, CR3, Tone) will be reset. The output of the CLK pin will be set to the crystal frequency. An internal pull down resistor permits power on reset using a capacitor to VDD. WR I Write. A low on this informs the 73K224L that data is available on AD0-AD7 for writing into an internal register. Data is latched on the rising edge of WR. No data is written unless both WR and the latched CS are active (low). NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes DATA and AD0, AD1 and AD2 become the address only. Page: 4 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET DTE USER INTERFACE NAME TYPE EXCLK I External Clock. This signal is used in synchronous transmission when the external timing option has been selected. In the external timing mode the rising edge of EXCLK is used to strobe synchronous transmit data available on the TXD pin. Also used for serial control interface. RXCLK O/ Tristate Receive Clock. Tri stateable. The falling edge of this clock output is coincident with the transitions in the serial received data output. The rising edge of RXCLK can be used to latch QAM or DPSK valid output data. RXCLK will be active as long as a carrier is present. RXD O/ Weak Pull-up Received Digital Data Output. Serial receive data is available on this pin. The data is always valid on the rising edge of RXCLK when in synchronous mode. RXD will output constant marks if no carrier is detected. TXCLK O/ Tristate Transmit Clock. Tri stateable. This signal is used in synchronous transmission to latch serial input data on the TXD pin. Data must be provided so that valid data is available on the rising edge of the TXCLK. The transmit clock is derived from different sources depending upon the synchronization mode selection. In Internal Mode the clock is generated internally. In External Mode TXCLK is phase locked to the EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK pin. TXCLK is always active. I Transmit Digital Data Input. Serial data for transmission is input on this pin. In synchronous modes, the data must be valid on the rising edge of the TXCLK clock. In asynchronous modes (2400/1200/600 bit/s or 300 baud) no clocking is necessary. DPSK data must be +1%, -2.5% or +2.3%, -2.5 % in extended overspeed mode. TXD DESCRIPTION ANALOG INTERFACE AND OSCILLATOR RXA I Received modulated analog signal input from the phone line. TXA O Transmit analog output to the phone line. XTL1 I XTL2 I/O These pins are for the internal crystal oscillator requiring a 11.0592 MHz parallel mode crystal. Two capacitors from these pins to ground are also required for proper crystal operation. Consult crystal manufacturer for proper values. XTL2 can also be driven from an external clock. Page: 5 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET which provides an indication of monitored modem status conditions. TR, the tone control register, controls the DTMF generator, answer and guard tones and RXD output gate used in the modem initial connect sequence. CR2 is the primary DSP control interface and CR3 controls transmit attenuation and receive gain adjustments. All registers are read/write except for DR and ID, which are read only. Register control and status bits are identified below: REGISTER DESCRIPTIONS Eight 8-bit internal registers are accessible for control and status monitoring. The registers are accessed in read or write operations by addressing the A0, A1 and A2 address lines in serial mode, or the AD0, AD1 and AD2 lines in parallel mode. The address lines are latched by ALE. Register CR0 controls the method by which data is transferred over the phone line. CR1 controls the interface between the microprocessor and the 73K224L internal state. DR is a detect register REGISTER BIT SUMMARY DATA BIT NUMBER ADDRESS REGISTER AD - A0 D7 D6 D5 D4 D3 D2 D1 D0 CONTROL REGISTER 0 CR0 000 MODULATION OPTION MODULATION TYPE 1 MODULATON TYPE 0 TRANSMIT MODE 2 TRANSMIT MODE 1 TRANSMIT MODE 0 TRANSMIT ENABLE ANSWER/ ORIGINATE CONTROL REGISTER 1 CR1 001 TRANSMIT PATTERN 1 TRANSMIT PATTERN 0 ENABLE DETECT INTERRUPT BYPASS SCRAMBLER CLK CONTROL RESET TEST MODE 1 TEST MODE 0 DETECT REGISTER DR 010 RECEIVE LEVEL PATTERN S1 DET RECEIVE DATA UNSCR. MARK DETECT CARRIER DETECT SPECIAL TONE DETECT CALL PROGRESS DETECT SIGNAL QUALITY TONE CONTROL REGISTER TR 011 RXD OUTPUT CONTOL TRANSMIT GUARD TONE TRANSMIT ANSWER TONE TRANSMIT DTMF DTMF3 DTMF2/ 4W/FDX DTMF1/ EXTENDED OVERSPEED DTMF0/ GUARD/ ANSWER CONTROL REGISTER 2 CR2 100 0 SPECIAL REGISTER ACCESS CALL INITIALIZE TRANSMIT S1 16 WAY RESET DSP TRAIN INHIBIT EQUALIZER ENABLE CONTROL REGISTER 3 CR3 101 TXDALT TRISTATE TX/RXCLK 0 RECEIVE GAIN BOOST TRANSMIT ATTEN. 3 TRANSMIT ATTEN. 2 TRANSMIT ATTEN. 1 TRANSMIT ATTEN. 0 SPECIAL REGISTER SR 101 0 TX BAUD CLOCK RX UNSCR. DATA 0 TXD SOURCE SQ SELECT 1 SQ SELECT 0 0 ID REGISTER ID 110 ID ID ID ID X X X 1 NOTE: When a register containing reserved control bits is written into, the reserved bits must be programmed as 0's. X = Undefined, mask in software Page: 6 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET REGISTER ADDRESS TABLE ADDRESS REGISTER CONTROL REGISTER 0 AD2 - AD0 CR0 000 DATA BIT NUMBER D7 D6 D5 MODULATION OPTION MODULATION TYPE 1 MODULATION TYPE 0 QAM: 0=2400 BIT/S DPSK: 0=1200 BIT/S 1=600 BIT/S FSK: 0=103 MODE 1=V.21 CONTROL REGISTER 1 CR1 001 TRANSMIT PATTERN 1 00=TX DATA 01=TX ALTERNATE 10=TX MARK 11=TX SPACE DETECT REGISTER DR 010 RECEIVE LEVEL INDICATOR S1 PATTERN DETECT TRANSMIT MODE 2 ENABLE DETECT INTERRUPT 0=DISABLE 1=ENABLE RECEIVE DATA BYPASS SCRAMBLER TR 011 RXD OUTPUT CONTROL RXD PIN 0=NORMAL 1=OPEN CONTROL REGISTER 2 CR2 100 0 TRANSMIT GUARD TONE CONTROL REGISTER 3 CR3 101 TXDALT ALTERNATE TRANSMIT DATA SOURCE SPECIAL REGISTER SR 101 0 0=OFF 1=ON SPECIAL REGISTER ACCESS CALL INITIALIZE TRISTATE TX/RXCLK UNSCR. MARKS DETECT TX BAUD CLOCK 10 110 00XX=73K212AL, 322L, 321L 01XX=73K221AL, 302L 10XX=73K222AL, 222BL 1100=73K224L 1110=73K324L 1100=73K224BL 1110=73K324BL Page: 7 of 31 ID ID TRANSMIT MODE 1 D1 TRANSMIT MODE 0 TRANSMIT ENABLE 0 CLK CONTROL TRANSMIT DTMF 0=DATA 1=TX DTMF TRANSMIT S1 RECEIVE GAIN BOOST 0 OUTPUTS UNSCR. DATA ID TEST MODE 0 00=NORMAL 01=ANALOG LOOPBACK 10=REMOTE DIGITAL LOOPBACK 11=LOCAL DIGITAL LOOPBACK ANSWER TONE DETECT CP TONE DETECT 4 BIT CODE FOR 1 OF 16 DUAL TONE COMBINATIONS 0=RX=TX 1=RX=16 WAY TRAIN INHIBIT 0=DSP INACTIVE 1=DSP ACTIVE 0=ADAPT EQ ACTIVE 1=ADAPT EQ FROZEN TRANSMIT ATTEN. 3 TRANSMIT ATTEN. 1 EQUALIZER ENABLE 0=ADAPT EQ IN INIT 1=ADAPT EQ OK TO ADAPT TRANSMIT ATTEN. 0 0000-1111, SETS TRANSMIT ATTENUATOR 16 dB RANGE DEFAULT=0100 ³ -10 dbM0 TXD SOURCE 0=TXD PIN 1=TXALT BIT ID TRANSMIT ATTEN. 2 DTMF0/ GUARD/ ANSWER/ CALLING/SCT 0=1800 Hz G.T. 2225 Hz ANS TONE GENERATED 1= 550 Hz G.T. 2100 Hz ANS TONE GENERATED & DETECTED (V.21, V.22) RESET DSP 16 WAY SIGNAL QUALITY INDICATOR 0=GOOD 1=BAD DTMF1/ EXTENDED OVERSPEED DTMF2/ 4 W/FDX 0=NO BOOST 1=18 dB BOOST RX UNSCR. DATA TEST MODE 1 0=NORMAL 1=RESET DTMF3 ANSWER/ ORIGINATE 0=ANSWER 1=ORIGINATE RESET CARRIER DETECT D0 0=DISABLE TXA OUTPUT 1=ENABLE TXA OUTPUT 0=CONDITION NOT DETECTED 1=CONDITION DETECTED 0=NORMAL 0=DSP IN DOTTING DEMOD MODE 1=S1 1=DSP IN CALL PROGRESS MODE 0=NORMAL 1=TRISTATE OUTPUTS TXBAUD CLOCK ID REGISTER TRANSMIT ANSWER TONE 0=OFF 1=ON 0=ACCESS CR3 1=ACCESS SPECIAL REGISTER D2 0=NORMAL 0=XTAL 1=BYPASS 1=16 X DATA SCRAMBLER RATE OUTPUT AT CLK PIN IN QAM/DPSK MODE ONLY 0=SIGNAL 0=NOT PRESENT OUTPUTS BELOW RECEIVED 1=PATTERN THRESHOLD DATA STREAM FOUND 1=ABOVE THRESHOLD TONE CONTROL REGISTER D3 0000=PWR DOWN 0001=INT SYNCH 0010=EXT SYNCH 0011=SLAVE SYNCH 0100=ASYCH 8 BITS/CHAR 0101=ASYCH 9 BITS/CHAR 0110=ASYCH 10 BITS/CHAR 0111=ASYCH 11 BITS/CHAR 1X00=FSK 10=QAM 00=DPSK 01=FSK TRANSMIT PATTERN 0 D4 X © 2005, 2008 TERIDIAN Semiconductor Corporation SQ SELECT1 00³10 01³10 10³10 11³10 X SQ SELECT0 -5 -6 -4 -3 0 BER BER BER BER X X Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET CONTROL REGISTER 0 CR0 000 D7 D6 D5 D4 D3 D2 D1 D0 MODUL. OPTION MODUL. TYPE 1 MODUL. TYPE 0 TRANSMIT MODE 2 TRANSMIT MODE 1 TRANSMIT MODE 0 TRANSMIT ENABLE ANSWER/ ORIGINATE BIT NO. D0 D1 NAME CONDITION Answer/ Originate 0 Selects answer mode (transmit in high band, receive in low band). 1 Selects originate mode (transmit in low band, receive in high band). 0 Disables transmit output at TXA. 1 Enables transmit output at TXA. Transmit Enable DESCRIPTION Note: Transmit Enable must be set to 1 to allow activation of Answer Tone or DTMF. D5 D4 D5, D4, D3, D2 D6,D5 Page: 8 of 31 D3 D2 0 0 0 0 Selects power down mode. All functions disabled except digital interface. 0 0 0 1 Internal synchronous mode. In this mode TXCLK is an internally derived 600,1200 or 2400 Hz signal. Serial input data appearing at TXD must be valid on the rising edge of TXCLK. Receive data is clocked out of RXD on the falling edge of RXCLK. 0 0 1 0 External synchronous mode. Operation is identical to internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 600, 1200 or 2400 Hz clock must be supplied externally. 0 0 1 1 Slave synchronous mode. Same operation as other synchronous modes. TXCLK is connected internally to the RXCLK pin in this mode. 0 1 0 0 Selects asynchronous mode - 8 bits/character (1 start bit, 6 data bits, 1 stop bit). 0 1 0 1 Selects asynchronous mode - 9 bits/character (1 start bit, 7 data bits, 1 stop bit). 0 1 1 0 Selects asynchronous mode - 10 bits/character (1 start bit, 8 data bits, 1 stop bit). 0 1 1 1 Selects asynchronous mode - 11 bits/character (1 start bit, 8 data bits, Parity and/or 1 or 2 stop bits). 1 X 0 0 Selects FSK operation. D6 D5 1 0 QAM 0 0 DPSK 0 1 FSK Transmit Mode Modulation Type © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET CONTROL REGISTER 0 (continued) CR0 000 D7 D6 D5 D4 D3 D2 D1 D0 MODUL. OPTION MODUL. TYPE 1 MODUL. TYPE 0 TRANSMIT MODE 2 TRANSMIT MODE 1 TRANSMIT MODE 0 TRANSMIT ENABLE ANSWER/ ORIGINATE BIT NO. D7 NAME CONDITION DESCRIPTION Modulation Option 0 QAM selects 2400 bit/s. DPSK selects 1200 bit/s. FSK selects 103 mode. 1 DPSK selects 600 bit/s. FSK selects V.21 mode. CONTROL REGISTER 1 CR1 001 D7 D6 D5 D4 D3 D2 D1 D0 TRANSMIT PATTERN 1 TRANSMIT PATTERN 0 ENABLE DETECT INT. BYPASS SCRAMB CLK CONTROL RESET TEST MODE 1 TEST MODE 0 BIT NO. D1, D0 D2 D3 Page: 9 of 31 NAME Test Mode Reset Clock Control CONDITION DESCRIPTION D1 D0 0 0 Selects normal operating mode. 0 1 Analog loopback mode. Loops the transmitted analog signal back to the receiver, and causes the receiver to use the same carrier frequency as the transmitter. To squelch the TXA pin, TRANSMIT ENABLE bit as well as Tone Reg bit D2 must be low. 1 0 Selects remote digital loopback. Received data is looped back to transmit data internally, and RXD is forced to a mark. Data on TXD is ignored. 1 1 Selects local digital loopback. Internally loops TXD back to RXD and continues to transmit data carrier at TXA pin. 0 Selects normal operation. 1 Resets modem to power down state. All control register bits (CR0, CR1, CR2, CR3 and Tone) are reset to zero except CR3 bit D2. The output of the clock pin will be set to the crystal frequency. 0 Selects 11.0592 MHz crystal echo output at CLK pin. 1 Selects 16 X the data rate, output at CLK pin in DPSK/QAM modes only. © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET CONTROL REGISTER 1 (continued) CR1 001 D7 D6 D5 D4 D3 D2 D1 D0 TRANSMIT PATTERN 1 TRANSMIT PATTERN 0 ENABLE DETECT INT. BYPASS SCRAMB CLK CONTROL RESET TEST MODE 1 TEST MODE 0 BIT NO. D4 NAME CONDITION Bypass Scrambler 0 Selects normal operation. DPSK and QAM data is passed through scrambler. 1 Selects Scrambler Bypass. Bypass DPSK and QAM data is routed around scrambler in the transmit path. 0 Disables interrupt at INT pin. All interrupts are normally disabled in power down mode. 1 Enables INT output. An interrupt will be generated with a change in status of DR bits D1-D4 and D6. The answer tone and call progress detect interrupts are masked when the TX enable bit is set. Carrier detect is masked when TX DTMF is activated. All interrupts will be disabled if the device is in power down mode. Enable Detect Interrupt D5 D7, D6 Transmit Pattern DESCRIPTION D7 D6 0 0 Selects normal data transmission as controlled by the state of the TXD pin. 0 1 Selects an alternating mark/space transmit pattern for modem testing and handshaking. Also used for S1 pattern generation. See CR2 bit D4. 1 0 Selects a constant mark transmit pattern. 1 1 Selects a constant space transmit pattern. DETECT REGISTER DR 010 D7 D6 D5 D4 D3 D2 D1 D0 RECEIVE LEVEL INDICATOR S1 PATTERN DETECT RECEIVE DATA UNSCR MARK. DETECT CARR. DETECT ANSWER TONE DETECT CALL PROG. DETECT SIGNAL QUALITY INDICATOR BIT NO. D0 D1 Page: 10 of 31 NAME CONDITION Signal Quality Indicator 0 Indicates normal received signal. 1 Indicates low received signal quality (above average error rate). Interacts with special register bits D2, D1. 0 No call progress tone detected. 1 Indicates presence of call progress tones. The call progress detection circuitry is activated by energy in the normal 350 to 620 Hz call progress bandwidth. Call Progress Detect DESCRIPTION © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET DETECT REGISTER (continued) DR 010 D7 D6 D5 D4 D3 D2 D1 D0 RECEIVE LEVEL INDICATOR S1 PATTERN DETECT RECEIVE DATA UNSCR. MARK DETECT CARR. DETECT ANSWER TONE DETECT CALL PROG. SIGNAL QUALITY INDICATOR BIT NO. D2 D3 NAME CONDITION Answer Tone Received 0 No answer tone detected. 1 In Call Init mode, indicates detection of 2225 Hz answer tone in Bell mode (TR bit D0=0) or 2100 Hz if in CCITT mode (TR bit D0=1). The device must be in originate mode for detection of answer tone. Both answer tones are detected in demod mode. Carrier Detect 0 No carrier detected in the receive channel. 1 Indicated carrier has been detected in the received channel. 0 No unscrambled mark. 1 Indicates detection of unscrambled marks in the received data. Should be time qualified by software. Unscrambled Mark Detect D4 D5 Receive Data D6 S1 Pattern Detect Continuously outputs the received data stream. This data is the same as that output on the RXD pin, but it is not disabled when RXD is tri-stated. Receive Level Indicator D7 DESCRIPTION 0 No S1 pattern being received. 1 S1 pattern detected. Should be time qualified by software. S1 pattern is defined as a double di-bit (001100..) unscrambled 1200 bit/s DPSK signal. Pattern must be aligned with baud clock to be detected. 0 Received signal level below threshold, (typical ≈ -25 dBm0); can use receive gain boost (+18 dB). 1 Received signal above threshold. TONE REGISTER TR 011 D7 D6 D5 D4 RXD OUTPUT CONTR. TRANSMIT GUARD TONE TRANSMIT ANSWER TONE TRANSMIT DTMF BIT NO. NAME CONDITION D6 D5 D0 Page: 11 of 31 DTMF 0/ Answer/ Guard Tone D3 DTMF 3 D2 D1 D0 DTMF 2 DTMF 1/ EXTENDED OVER- SPEED DTMF 0/ ANSWER/ GUARD DESCRIPTION D4 D0 D0 interacts with bits D6, D5, and D4 as shown. X X 1 X Transmit DTMF tones. X 1 0 0 Select Bell mode answer tone. Interacts with DR bit D2 and TR bit D5. X 1 0 1 Select CCITT mode answer tone. Interacts with DR bit D2 and TR bit D5. © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET TONE REGISTER (continued) TR 011 D7 D6 D5 D4 D3 D2 D1 D0 RXD OUTPUT CONTR. TRANSMIT GUARD TONE TRANSMIT ANSWER TONE TRANSMIT DTMF DTMF 3 DTMF 2/4 WIRE FDX DTMF 1/ EXTENDED OVER- SPEED DTMF 0/ ANSWER/ GUARD BIT NO. NAME CONDITION D6 D5 D0 D1 D2 Page: 12 of 31 DTMF 0/ Answer/ Guard Tone DTMF 1/ Extended Overspeed DTMF 2/4 WIRE FDX DESCRIPTION D4 D0 D0 interacts with bits D6, D5, and D4 as shown. 1 0 0 0 Select 1800 Hz guard tone. 1 0 0 1 Select 550 Hz guard tone. D4 D1 0 0 Asynchronous QAM or DPSK +1.0% -2.5%. (normal) 0 1 Asynchronous QAM or DPSK +2.3% -2.5%. (extended overspeed) D4 D2 0 0 Selects 2 wire duplex or half duplex 0 1 D2 selects 4 wire full duplex in the modulation mode selected. The receive path corresponds to the ANS/ORIG bit CR0 D0 in terms of high or low band selection. The transmitter is in the same band as the receiver, but does not have magnitude filtering or equalization on its signal as in the receive path. D1 interacts with D4 as shown. © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET TONE REGISTER (continued) TR 011 D7 D6 D5 D4 D3 D2 D1 D0 RXD OUTPUT CONTR. TRANSMIT GUARD TONE TRANSMIT ANSWER TONE TRANSMIT DTMF DTMF 3 DTMF 2/4 WIRE FDX DTMF 1/ EXTENDED OVER- SPEED DTMF 0/ ANSWER GUARD BIT NO. NAME CONDITION D3, D2, D1, D0 DTMF 3, 2, 1, 0 D4 = 1 DESCRIPTION Programs 1 of 16 DTMF tone pairs that will be transmitted when TX DTMF and TX enable bit (CR0, bit D1) is set. Tone encoding is shown below: KEYBOARD EQUIVALENT D4 TX DTMF (Transmit DTMF) DTMF CODE D3 D2 D1 D0 TONES LOW HIGH 1 0 0 0 1 697 1209 2 0 0 1 0 697 1336 3 0 0 1 1 697 1477 4 0 1 0 0 770 1209 5 0 1 0 1 770 1336 6 0 1 1 0 770 1477 7 0 1 1 1 852 1209 8 1 0 0 0 852 1336 9 1 0 0 1 852 1477 0 1 0 1 0 941 1336 * 1 0 1 1 941 1209 # 1 1 0 0 941 1477 A 1 1 0 1 697 1633 B 1 1 1 0 770 1633 C 1 1 1 1 852 1633 D 0 0 0 0 941 1633 0 Disable DTMF. 1 Activate DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF overrides all other transmit functions. Note: DTMF0 - DTMF2 should be set to an appropriate state after DTMF dialing to avoid unintended operation. Page: 13 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET TONE REGISTER (continued) TR 011 D7 D6 D5 D4 D3 D2 D1 D0 RXD OUTPUT CONTR. TRANSMIT GUARD TONE TRANSMIT ANSWER TONE TRANSMIT DTMF DTMF 3 DTMF 2/4 WIRE FDX DTMF 1/ EXTENDED OVER- SPEED DTMF 0/ ANSWER/ GUARD BIT NO. NAME D5 CONDITION DESCRIPTION D5 interacts with bits D4 and D0 as shown. Also interacts with DR bit D2 in originate mode. See Detect Register description. D5 D4 D0 0 0 X Disables answer tone generator. 1 0 0 In answer mode, a Bell 2225 Hz tone is transmitted continuously when the Transmit Enable bit is set. 1 0 1 Likewise, a CCITT 2100 Hz answer tone is transmitted. Transmit Answer Tone D6 D7 Transmit Guard Tone 0 Disables guard tone generator. 1 Enables guard tone generator. (See D0 for selection of guard tones.) Bit D4 must be zero. RXD Output Control 0 Enables RXD pin. Receive data will be output on RXD. 1 Disables RXD pin. The RXD pin reverts to a high impedance with internal weak pull-up resistor. CONTROL REGISTER 2 CR2 100 D7 D6 D5 D4 D3 D2 D1 D0 0 SPEC REG ACCESS CALL INIT TRANSMIT S1 16 WAY RESET DSP TRAIN INHIBIT EQUALIZER ENABLE BIT NO. D0 D1 D2 D3 Page: 14 of 31 NAME CONDITION Equalizer Enable 0 The adaptive equalizer is in its initialized state. 1 The adaptive equalizer is enabled. This bit is used in handshakes to control when the equalizer should calculate its coefficients. Train Inhibit 0 The adaptive equalizer is active. 1 The adaptive equalizer coefficients are frozen. 0 The DSP is inactive and all variables are initialized. 1 The DSP is running based on the mode set by other control bits 0 The receiver and transmitter are using the same decision plane (based on the Modulator Control Mode). 1 The receiver, independent of the transmitter, is forced into a 16 point decision plane. Used for QAM handshaking. RESET DSP 16 Way DESCRIPTION © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET CONTROL REGISTER 2 (continued) CR2 100 D7 D6 D5 D4 D3 D2 D1 D0 0 SPEC REG ACCESS CALL INIT TRANSMIT S1 16WAY RESET DSP TRAIN INHIBIT EQUALIZER ENABLE BIT NO. D4 NAME Transmit S1 CONDITION 0 1 D5 Call Init 0 1 D6 Special Register Access 0 1 D7 Not used at this time 0 DESCRIPTION The transmitter when placed in alternating mark/space mode transmits 0101...... scrambled or not dependent on the bypass scrambler bit. When this bit is 1 and only when the transmitter is placed in alternating mark/space mode by CR1 bits D7, D6, and in DPSK or QAM, an unscrambled repetitive double dibit pattern of 00 and 11 at 1200 bit/s (S1) is sent. DEMOD mode: The DSP is setup to do demodulation and pattern detection based on the various mode bits. Both answer tones are detected in demod mode concurrently (wide band detection); TR-D0 is ignored. CALL INIT mode: The DSP decodes unscrambled mark, answer tone and call progress tones. Normal CR3 access. Setting this bit and addressing CR3 allows access to the SPECIAL REGISTER. See the SPECIAL REGISTER for details. Only write zero to this bit. CONTROL REGISTER 3 CR3 101 D7 TXDALT D6 TRISTATE TX/RXCLK BIT NO. NAME D3, D2, D1,D0 Transmit Attenuator D4 Receive Gain Boost D5 0 D4 RECEIVE BOOST ENABLE CONDITION D3 D2 0 0 1 1 D1 D0 0 0 1 1 D6 D7 Page: 15 of 31 TRISTATE TXCLK/RXCLK TXDALT D2 TRANSMIT ATTEN. 2 D1 TRANSMIT ATTEN. 1 D0 TRANSMIT ATTEN. 0 DESCRIPTION 0 Sets the attenuation level of the transmitted signal in 1dB steps. The default (D3-D0=0100) is for a transmit level of – 10 dBm0 on the line with the recommended hybrid transmit gain. The total range is 16 dB. 18 dB receive front end boost is not used. Boost is in the path. This boost does not change reference levels. It is used to extend dynamic range by compensating for internally generated noise when receiving weak signals. The receive level detect signal and knowledge of the hybrid and transmit attenuator setting will determine when boost should be enabled. Only write zero to this bit. 0 TXCLK and RXCLK are driven. 1 TXCLK and RXCLK are tri-stated. 0 1 Not used at this time D5 D3 TRANSMIT ATTEN. 3 Spec. Reg. Bit D3=1 Alternate TX data source. See Special Register. © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET SPECIAL REGISTER SR 101 D7 D6 D5 D4 D3 D2 D1 D0 0 TXBAUD CLOCK RXUNDSCR DATA 0 TXD SOURCE SIGNAL QUALITY LEVEL SELECT1 SIGNAL QUALITY LEVEL SELECT0 0 BIT NO. NAME DESCRIPTION D7, D4, D0 NOT USED AT THIS TIME. Only write ZEROs to these bits. D6 TXBAUD CLK TXBAUD clock is the transmit baud-synchronous clock that can be used to synchronize the input of arbitrary quad/di-bit patterns. The rising edge of TXBAUD signals the latching of a baud-worth of data internally. Synchronous data to be entered via the TXDALT bit, CR3 bit D7, should have data transitions that start 1/2 bit period delayed from the TXBAUD clock edges. D5 RXUNDSCR DATA This bit outputs the data received before going to the descrambler. This is useful for sending special unscrambled patterns that can be used for signaling. D3 TXD SOURCE This bit selects the transmit data source; either the TXD pin if ZERO or the TXDALT if this bit is a ONE. The TRANSMIT PATTERN bits D7 and D6 in CR1 override either of these sources. SIGNAL QUALITY LEVEL SELECT The signal quality indicator is a logical ZERO when the signal received is acceptable for low error rate reception. It is determined by the value of the Mean Squared Error (MSE) calculated in the decision process when compared to a given threshold. This threshold can be set to four levels of error rate. The SQI bit will be low for good or average connections. As the error rate crosses the threshold setting, the SQI bit will toggle at a 1.66 ms rate. Toggling will continue until the error rate indicates that the data pump has lost convergence and a retrain is required. At that point the SQI bit will be a ONE constantly. The SQI bit and threshold selection are valid for QAM and DPSK only and indicates typical error rate. D2 D1 THRESHOLD VALUE 0 0 0 D2, D1 UNITS 10 -5 BER (default) 1 10 -6 BER 1 0 10 -4 BER 1 1 10 -3 BER NOTE: This register is "mapped" and is accessed by setting CR2 bit D6 to a ONE and addressing CR3. This register provides functions to the 73K224L user that are not necessary in normal communications. Bits D7-D4 are read only, while D3-D0 are read/write. To return to normal CR3 access, CR2 bit D6 must be returned to a ZERO. Page: 16 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET ID REGISTER ID 110 D7 D6 D5 D4 D3 D2 D1 D0 ID 3 ID 2 ID 1 ID 0 X X X 1 BIT NO. NAME D7, D6, D5, D4 Device Identification Signature D3-D1 D0 Page: 17 of 31 CONDITION D7 D6 DESCRIPTION D5 D4 Indicates Device: 0 0 X X 73K212AL, 73K321L or 73K322L 0 1 X X 73K221AL or 73K302L 1 0 X X 73K222AL, 73K222BL 1 1 0 0 73K224L 1 1 1 0 73K324L 1 1 0 0 73K224BL 1 1 1 0 73K324BL Not Used Undefined Version 1 Mask in software Indicates industrial temperature version © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETER RATING VDD Supply Voltage 7V Storage Temperature -65 to 150°C Soldering Temperature (10 sec.) 260°C Applied Voltage -0.3 to VDD+0.3V Note: All inputs and outputs are protected from static charge using built-in, industry standard protection devices and all outputs are short-circuit protected. RECOMMENDED OPERATING CONDITIONS PARAMETER CONDITION MIN NOM MAX UNIT 4.5 5 5.5 V VDD Supply voltage External Components (Refer to Application section for placement.) VREF Bypass capacitor (VREF to GND) Bias setting resistor (Placed between VDD and ISET pins) ISET Bypass capacitor (ISET pin to GND) 0.22 µF VDD Bypass capacitor 1 (VDD to GND) 0.22 µF VDD Bypass capacitor 2 (VDD to GND) 22 µF XTL1 Load Capacitance Depends on crystal requirements 18 39 pF XTL2 Load Capacitance Depends on crystal requirements 18 27 pF -0.01 +0.01 % -40 85 °C Clock Variation (11.0592 MHz) Crystal or external clock 0.22 1.8 TA, Operating Free-Air Temperature Page: 18 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation µF 2 2.2 MΩ Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET DC ELECTRICAL CHARACTERISTICS (TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.) PARAMETER CONDITION IDD, Supply Current CLK = 11.0592 MHz ISET Resistor = 2 MΩ IDD1, Active IDD2, Idle MIN NOM MAX UNIT 18 25 mA 3 5 mA 0.8 V 2.0 VDD V 3.0 VDD V 100 µA Operating with crystal oscillator, < 5 pF capacitive load on CLK pin Digital Inputs VIL, Input Low Voltage VIH, Input High Voltage All Inputs except Reset XTL1, XTL2 Reset, XTL1, XTL2 IIH, Input High Current VI = VDD IIL, Input Low Current VI = 0V Reset Pull-down Current Reset = VDD -200 µA 2 50 µA 2.4 VDD V 0.4 V -50 µA Digital Outputs VOH, Output High Voltage IO = IOH Min IOUT = -0.4 mA VOL, Output Low Voltage IO = IOUT = 1.6 mA RXD Tri-State Pull-up Current. RXD = GND -2 Capacitance CLK Maximum permitted load 25 pF Input Capacitance All digital inputs 10 pF Page: 19 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET ELECTRICAL SPECIFICATIONS (continued) DYNAMIC CHARACTERISTICS AND TIMING (TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.) PARAMETER CONDITION MIN NOM MAX UNIT QAM/DPSK Modulator Carrier Suppression Measured at TXA 35 Output Amplitude TX scrambled marks ATT = 0100 (default) -11.5 Output Freq. Error CLK = 11.0592 MHz -0.31 Transmit Level ATT = 0100 (Default) Transmit Dotting Pattern -11.5 TXA Output Distortion All products through BPF Output Bias Distortion at RXD Dotting Pattern measured at RXD Receive Level -20 dBm, SNR 20 dB Output Jitter at RXD Sum of Bias Distortion and Output Jitter dB -10.0 -9 dBm0 +0.20 % -9 dBm0 -45 dB -10 +10 % Integrated for 5 seconds -15 +15 % Integrated for 5 seconds -17 +17 % -9 dBm0 -40 dB -0.03 +0.25 % FSK Modulator/Demodulator -10.0 Answer Tone Generator (2100 or 2225 Hz) Output Amplitude ATT = 0100 (Default Level) Not in V.21 Output Distortion Distortion products in receive band DTMF Generator -11.5 -10 Not in V.21 Freq. Accuracy Output Amplitude Low Band, ATT = 0100, DPSK Mode -10 -8 dBm0 Output Amplitude High Band, ATT = 0100, DPSK Mode -8 -6 dBm0 Twist High-Band to Low-Band, DPSK Mode 1.0 3.0 dB Receiver Dynamic Range Refer to Performance Curves -43 -3.0 dBm0 Call Progress Detector In Call Init mode -34 0 dBm0 -40 dBm0 Detect Level 460 Hz test signal 2.0 Reject Level Delay Time -70 dBm0 to -30 dBm0 STEP 25 ms Hold Time -30 dBm0 to -70 dBm0 STEP 25 ms NOTE: Parameters expressed in dBm0 refer to the following definition: 0 dB loss in the Transmit path from TXA to the line. 2 dB gain in the Receive path from the line to RXA. Refer to the Basic Box Modem diagram in the Applications section for the DAA design. Page: 20 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET DYNAMIC CHARACTERISTICS AND TIMING (continued) PARAMETER CONDITION Carrier Detect All Modes Hysteresis All Modes FSK DPSK QAM Hold Time NOM MAX UNIT -43 dBm0 Receive Gain = On for lower input level measurements Threshold Delay Time MIN FSK DPSK QAM Answer Tone Detectors 25 37 ms 70 dBm0 to -40 dBm0 25 37 ms -70 dBm0 to -6 dBm0 7 17 ms -70 dBm0 to -40 dBm0 7 17 ms -70 dBm0 to -6 dBm0 25 37 ms -70 dBm0 to -40 dBm0 25 37 ms -6 dBm0 to -70 dBm0 25 37 ms -40 dBm0 to -70 dBm0 15 30 ms -6 dBm0 to -70 dBm0 20 29 ms -40 dBm0 to -70 dBm0 14 21 ms -6 dBm0 to -70 dBm0 25 32 ms -40 dBm0 to -70 dBm0 18 28 ms -48 -43 dBm0 6 50 ms 6 50 ms DPSK Mode Call Init Mode, 2100 or 2225 Hz Hold Time Pattern Detectors 2 70 dBm0 to -6 dBm0 Detect Level Detect Time -48 DPSK Mode S1 Pattern Delay Time Hold Time For signals from -6 to -40 dBm0, -6 to -40 dBm0, Demod Mode 10 55 ms 10 45 ms 10 45 ms 10 45 ms Unscrambled Mark Delay Time Hold Time For signals from -6 to –40 call Init Mode Receive Level Indicator Detect On Valid after Carrier Detect -22 DPSK Mode 1 -28 dBm0 4 7 ms 200 300 Ω Output Smoothing Filter Output Impedance TXA pin Output load TXA pin; FSK Single Maximum Transmitted Energy Page: 21 of 31 10 KΩ Tone out for THD = -50 dB in 0.3 to 3.4 kHz range 50 pF 4 kHz, Guard Tones off -35 dBm0 10 kHz, Guard Tones off -55 dBm0 12 kHz, Guard Tones off -65 dBm0 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET DYNAMIC CHARACTERISTICS AND TIMING (continued) PARAMETER CONDITION MIN NOM MAX UNIT Scrambled data at 2400 bit/s in opposite band -14 dBm Sinusoids out of band -9 dBm -21 -6 dBm0 -0.15 +0.15 dB 300 Ω 1.5 mVrms Anti Alias Low Pass Filter Out of Band Signal Energy (Defines Hybrid Trans- Hybrid loss requirements) Level at RXA pin with receive Boost Enabled Transmit Attenuator Range of Transmit Level Default ATT=0100 (-10 dBm0) 1111-0000 Step Accuracy Output Impedance 200 Clock Noise TXA pin; 153.6 kHz Carrier Offset Capture Range Originate or Answer ±5 Hz Recovered Clock Capture Range % of frequency (originate or answer) -0.02 +0.02 % Guard Tone Generator Tone Accuracy Tone Level (Below QAM/DPSK Output) Harmonic Distortion (700 to 2900 Hz) Page: 22 of 31 550 Hz +1.2 1800 Hz -0.8 % 550 Hz -4.5 -3.0 -1.5 dB 1800 Hz -7.5 -6.1 -4.5 dB 550 Hz -50 dB 1800 Hz -50 dB © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET DYNAMIC CHARACTERISTICS AND TIMING (continued) Timing (Refer to Timing Diagrams) PARAMETER CONDITION MIN NOM MAX UNIT Parallel Mode TAL CS/Addr. setup before ALE Low 30 ns TLA CS/Addr. hold after ALE Low 6 ns TLC ALE Low to RD/WR Low 40 ns TCL RD/WR Control to ALE High 10 ns TRD Data out from RD Low TLL ALE width TRDF Data float after RD High TRW RD width 70 ns TWW WR width 70 ns TDW Data setup before WR High 70 ns TWD Data hold after WR High 20 ns TRCK Clock High after RD Low 250 TAR Address setup before RD Low TRA Address hold after RD Low TRD RD to Data valid 300 ns TRDF Data float after RD High 40 ns TCKDR Read Data out after Falling Edge of EXCLK 300 ns TWW WR width 350 ns TAW Address setup before WR Low 50 ns TWA Address hold after Rising Edge of WR 50 ns TCKDW Write Data hold after Falling Edge of EXCLK 200 ns TCKW WR High after Falling Edge of EXCLK 330 TDCK Data setup before Falling Edge of EXCLK 50 ns T1, T2 Minimum Period 500 ns 90 25 ns ns 40 ns Serial Mode T1 ns 0 ns 350 ns T1 + T2 ns NOTE: T1 and T2 are the low/high periods, respectively, of EXCLK in serial mode. NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When using non-8031 compatible processors, care must be taken to prevent this from occurring when designing the interface logic. Page: 23 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET TIMING DIAGRAMS BUS TIMING DIAGRAM (PARALLEL CONTROL MODE) TLL ALE TLC TRW TCL RD TLC TWW WR TLA TRD TRDF TWD TAL TDW ADDRESS AD0-AD7 READ DATA ADDRESS WRITE DATA CS READ TIMING DIAGRAM (SERIAL CONTROL MODE ) T1 T2 EXCLK TRCLK RD TAR TRA A0-A2 ADDRESS TRD D0 DATA TRDF TCKDR D1 D2 D3 D4 D5 D6 D7 WRITE TIMING DIAGRAM (SERIAL CONTROL MODE) T2 EXCLK T1 TWW WR TCKW TAW TWA A0-A2 ADDRESS TCKDW TDCK DATA Page: 24 of 31 D0 D1 D2 D3 D4 D5 © 2005, 2008 TERIDIAN Semiconductor Corporation D6 D7 Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET K-Series devices are available with two control interface versions: one for a parallel multiplexed address/data interface, and one for a serial interface. The parallel version is intended for use with 8039/48 or 8031/51 microcontrollers from Intel or many other manufacturers. The serial interface can be used with other microcontrollers or in applications where only a limited number of port lines are available or the application does not lend itself to a multiplexed address/data interface. The parallel versions may also be used in the serial mode, as explained in the data sheet pin description. APPLICATIONS INFORMATION GENERAL CONSIDERATIONS Figures 1 and 2 show basic circuit diagrams for K-Series modem integrated circuits. K-Series products are designed to be used in conjunction with a control processor, a UART or RS-232 serial data interface, and a DAA phone line interface to function as a typical intelligent modem. The K-Series ICs interface directly with Intel 8048 and 80C51 microprocessors for control and status monitoring purposes. Two typical DAA arrangements are shown: one for a split ±5 or ±12V design and one for a single 5V design. These diagrams are for reference only and do not represent production-ready modem designs. C14 C13 39 pF 18 pF Y1 11.0592 MHZ +5V N/C RS232 LEVEL CONVERTERS CA CB CC CD CF RTS CTS DSR DTR DCD XTL2 R10 2.2M XTL1 INT DB TXD RXD EXCLK RXCLK TXCLK U5, U6 MC145406 CLK XTL1 XTL2 INT P0.0-7 P1.2 P1.3 RD WR RD WR P1.5 ALE P3.1 ALE CS P1.6 P3.2 + C9 0.1 µF VDD C8 22 µF C1 390 pF ISET 80C51 P1.0 P1.1 P3.0 P1.7 RESET BA BB DA DD In most applications the controller will monitor the serial data for commands from the DTE and the received data for break signals from the far end modem. In this way, commands to the modem are sent over the same line as the transmitted data. In other applications the RS-232 interface handshake lines are used for modem control. GND VREF C10 0.1 µF R5 37.4K C11 0.1 µF R4 20K - RXA LM 1458 C6 0.1 µF K-SERIES LOW U1A FAMILY R7 43.2K TXA C7 R6 0.1 µF 20K RESET TXA +5V C12 1 µF R4 5.1K C2 300 pF RXA POWER + C3 1000 pF R3 3.6K V+ T1 MIDCOM 671-8005 R1 - LM 1458 U1B + V– T 475 1% C5 0.47 µF 250V C4 0.033 µF D3, D4 4.7V ZENER U2 4N35 VR1 MOV V250L20 D1 IN4004 +5V R8 22K K1 D2 IN914 R R9 10K Q1 +5 2N2222A 22K FIGURE 1: Basic Box Modem with Dual-Supply Hybrid Page: 25 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET DIRECT ACCESS ARRANGEMENT (DAA) before sending it to the other leg of the transformer. Each op-amp then supplies half the drive signal to the transformer. The receive amplifier (U1C) picks off its signal at the junction of the impedance matching resistor and the transformer. Because the bottom leg of the transformer is being driven in one direction by U1A and the resistor is driven in the opposite direction at the same time by U1B, the junction of the transformer and resistor remains relatively constant and the receive signal is unaffected. The telephone line interfaces show two examples of how the “hybrid” may be implemented. The split supply design (Figure 1) is a typical two op-amp hybrid. The receive op-amp serves two purposes. It supplies gain to amplify the receive signal to the proper level for the modem’s detectors and demodulator, and it removes the transmitted signal from the receive signal present at the transformer. This is done by supplying a portion of the transmitted signal to the non-inverting input of the receive op-amp at the same amplitude as the signal appearing at the transformer, making the transmit signal common mode. DESIGN CONSIDERATIONS TERIDIAN Semiconductor's 1-chip modem products include all basic modem functions. This makes these devices adaptable for use in a variety of applications, and as easy to control as conventional digital bus peripherals. Unlike digital logic circuitry, modem designs must properly contend with precise frequency tolerances and very low level analog signals, to ensure acceptable performance. Using good analog circuit design practices will generally result in a sound design. Following are additional recommendations, which should be taken into consideration when starting new designs. The single-supply hybrid is more complex than the dual-supply version described above, but its use eliminates the need for a second power supply. This circuit (Figure 2) uses a bridged drive to allow undistorted signals to be sent with a single 5 volt supply. Because DTMF tones utilize a higher amplitude than data, these signals will clip if a singleended drive approach is used. The bridged driver uses an extra op-amp (U1A) to invert the signal coming from the gain setting op-amp (U1B) C1 390 pF R4 37.4K 1% C3 0.1 µF 8 * U1C - RXA + C4 0.0047 µF R1 20K 1% 9 Note: Op-amp U1 must be rated for single 5V operation. R10 & R11 values depend 10 R2 20K 1% R5 3.3K +5V 5 6 R3 475 1% 4 + - 7 11 T1 MIDCOM 671-8005 * U1B C6 0.1 µF R7 20K 1% T C2 0.033 µF C5 750 pF U2 4N35 TXA R9 20K 1% 3 - * U1A R13 22K VR1 MOV V250L20 D1 IN4004 D2 3.3V ZENERS R8 20K 1% 2 +5V C10 0.47 µF 250V R6 22.1K R12 22K D3 1 + +5V +5V K1 VOLTAGE REFERENCE D4 IN914 R10* R R11* C7 0.1 µF + R14 10K C8 10 µF Q1 2N2222A HOOK RING FIGURE 2: Single 5V Hybrid Version Page: 26 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET CRYSTAL OSCILLATOR MODEM PERFORMANCE CHARACTERISTICS The K-Series crystal oscillator requires a parallel mode (antiresonant) crystal, which operates at 11.0592 MHz. It is important that this frequency be maintained to within ±0.01% accuracy. The curves presented here define modem IC performance under a variety of line conditions while inducing disturbances that are typical of those encountered during data transmission on public service telephone lines. Test data was taken using an AEA Electronics’ “Autotest I” modem test set and line simulator, operating under computer control. All tests were run fullduplex, using a Hayes SmartModem™ 2400 as the reference modem. A 511 pseudo-random-bit pattern was used for each data point. Noise was C-message weighted and all signal-to-noise (S/N) ratios reflect total power measurements similar to the CCITT V.56 measurement specification. The individual tests are defined as follows. In order for a parallel mode crystal to operate correctly and to specification, it must have a load capacitor connected to the junction of each of the crystal and internal inverter connections, terminated to ground. The values of these capacitors depend primarily on the crystal’s characteristics, and to a lesser degree on the internal inverter circuit. The values used affect the accuracy and start up characteristics of the oscillator. LAYOUT CONSIDERATIONS Good analog/digital design rules must be used to control system noise in order to obtain highest performance in modem designs. The more digital circuitry present on the PC board, the more this attention to noise control is needed. The modem should be treated as a high impedance analog device. A 22 µF electrolytic capacitor in parallel with a 0.22 µF ceramic capacitor between VDD and GND is recommended. Liberal use of ground planes and larger traces on power and ground are also highly favored. The ISET resistor and capacitor should be mounted near the ISET pin, away from digital signals. High speed digital circuits tend to generate a significant amount of EMI (Electro-Magnetic Interference), which must be minimized in order to meet regulatory agency limitations. To accomplish this, high speed digital devices should be locally bypassed, and the telephone line interface and K-Series device should be located close to each other near the area of the board where the phone line connection is accessed. To avoid problems, power supply and ground traces should be routed separately to the analog and digital functions on the board, and digital signals should not be routed near low level or high impedance analog traces. The analog and digital grounds should only connect at one point near the KSeries device ground pin to avoid ground loops. The K-Series modem IC’s should have both high frequency and low frequency bypassing as close to the package as possible. Page: 27 of 31 BER vs. S/N This test measures the ability of the modem to operate over noisy lines with a minimum of datatransfer errors. Since some noise is generated in the best of dial-up lines, the modem must operate with the lowest S/N ratio possible. Better modem performance is indicated by test curves that are closest to the BER axis. A narrow spread between curves representing the four line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a modem will exhibit better BER-performance test curves receiving in the low band than in the high band. BER vs. Receive Level This test measures the dynamic range of the modem. Because signal levels vary widely over dial-up lines, the widest possible dynamic range is desirable. The minimum Bell specification calls for 36 dB of dynamic range. S/N ratios are held constant at the indicated values while the receive level is lowered from a very high to very low signal levels. The width of the “bowl” of these curves, taken at the BER point, is the measure of dynamic range. © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET 73K224L BER vs S/N-DPSK LOW BAND 73K224L BER vs S/N-DPSK HIGH BAND 10-2 10-2 LOW BAND RECEIVE -30 dBm DPSK OPERATION 1200 BIT/S HIGH BAND RECEIVE -30 dBm DPSK OPERATION 1200 BIT/S 10-3 10-3 BIT ERROR RATE BIT ERROR RATE C1, 3002, FLAT 10-4 10-4 C1, C2, FLAT 10-5 10-5 C2 10-6 10-6 4 6 8 10 12 14 16 4 6 SIGNAL TO NOISE (dB) 8 12 10 14 16 SIGNAL TO NOISE (dB) 73K224L BER vs S/N-QAM-LOW BAND 73K224L BER vs S/N-QAM-HIGH BAND 10-2 10-2 HIGH BAND RECEIVE -30 dBm QAM OPERATION 2400 BIT/S LOW BAND RECEIVE -30 dBm QUAM OPERATION 2400 BIT/S C1 10-3 10-3 C1 BIT ERROR RATE BIT ERROR RATE FLAT FLAT 10-4 C2 10-4 3002 C2 10-5 10-5 10-6 10-6 8 10 12 14 16 18 20 8 SIGNAL TO NOISE (dB) Page: 28 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation 10 12 14 16 18 20 SIGNAL TO NOISE (dB) Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET 73K224L BER vs CARRIER OFFSET 10-2 HIGH BAND RECEIVE -30 dBm QAM OPERATION 2400 BIT/S BIT ERROR RATE 10-3 10-4 3002 17 dB S/N C2 17 dB S/N 10-5 10-6 -12 -8 -4 0 4 8 12 CARRIER OFFSET (Hz) Page: 29 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET MECHANICAL SPECIFICATIONS 28-Pin DIP 28-Pin PLCC 0.495 (12.573) 0.075 (1.905) 0.485 (12.319) PIN NO. 1 IDENT. 0.065 (1.651) 0.165 (4.191) 0.180 (4.572) 0.495 (12.573) 0.456 (11.650) 0.485 (12.319) 0.450 (11.430) 0.050 (1.270) 0.045 (1.140) 0.016 (0.406) 0.020 (0.508) 0.020 (0.508) 0.390 (9.906) 0.430 (10.922) 0.456 (11.650) 0.450 (11.430) Page: 30 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET PACKAGE PIN DESIGNATIONS (Top View) AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 1 RXA 2 VREF XTL1 4 CLK GND AD0 XTL2 CAUTION: Use handling procedures necessary for a static sensitive component. 28 27 26 RESET ISET 5 25 6 24 7 23 8 22 RXCLK RXD 9 21 TXD 10 20 11 19 CS EXCLK TXCLK INT TXA RD VDD WR ALE 12 13 14 15 16 17 18 28-Pin PLCC 73K224L-28IH ORDERING INFORMATION PART DESCRIPTION ORDER NO. PACKAGE MARK 73K224L 28-Pin Plastic Lead-Free Chip Carrier 73K224L-28IH/F 73K224L-28IH 73K224L 28-Pin Plastic Lead-Free Tape / Reel 73K224L-28IHR/F 73K224L-28IH No responsibility is assumed by TERIDIAN Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TERIDIAN Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. TERIDIAN Semiconductor Corporation, 6440 Oak Canyon Rd., Irvine, CA 92618-5201, (714) 508-8800, FAX: (714) 508-8877, http://www.teridiansemi.com Protected by the following Patents (4,777,453) (4,789,995) (4,847,868) (4,866,739) © 2005, 2008 TERIDIAN Semiconductor Corporation Page: 31 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation 06/20/08 - rev. 7.1 Rev 7.1