FAST CMOS OCTAL REGISTERED TRANSCEIVERS IDT29FCT52AT/BT/CT/DT IDT29FCT2052AT/BT/CT IDT29FCT53AT/BT/CT Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages • Features for 29FCT52/29FCT53T: – A, B, C and D speed grades – High drive outputs (-15mA IOH, 64mA IOL) – Power off disable outputs permit “live insertion” • Features for 29FCT2052T: – A, B and C speed grades – Resistor outputs (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.) – Reduced system switching noise The IDT29FCT52AT/BT/CT/DT and IDT29FCT53AT/BT/ CT are 8-bit registered transceivers built using an advanced dual metal CMOS technology. Two 8-bit back-to-back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-state output enable signals are provided for each register. Both A outputs and B outputs are guaranteed to sink 64mA. The IDT29FCT52AT/BT/CT/DT and IDT29FCT2052AT/BT/ CT are non-inverting options of the IDT29FCT53AT/BT/CT. The IDT29FCT2052AT/BT/CT has balanced drive outputs with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. The IDT29FCT2052T part is a plug-in replacement for IDT29FCT52T part. FUNCTIONAL BLOCK DIAGRAM(1) CPA CEA OEB D 0 CE CP Q0 B0 A1 A2 D1 D2 Q1 Q2 B1 B2 A3 A4 D3 Q3 A Reg. D4 Q4 B3 B4 A5 D5 D6 Q5 Q6 B5 D7 Q7 Q0 D0 Q1 Q2 D1 D2 A0 A6 A7 B6 B7 Q3 D3 B Reg. Q4 D4 Q5 Q6 D5 D6 Q 7 CE CP D7 OEA CPB CEB NOTE: 1. IDT29FCT52T/IDT29FCT2052T function is shown. IDT29FCT53T is the inverting option. 2629 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1995 Integrated Device Technology, Inc. 6.1 JUNE 1995 DSC-4224/5 1 IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES B5 B6 B7 NC Vcc A7 A6 PIN CONFIGURATIONS INDEX 1 24 2 23 3 22 4 5 6 7 8 9 P24-1 D24-1 SO24-2 SO24-7* SO24-8* & E24-1 21 20 19 18 17 16 10 15 11 14 12 13 Vcc A7 A6 A5 A4 A3 A2 A1 A0 OEA CPB CEB 4 B4 B3 B2 NC B1 B0 OEB 3 5 2 28 27 26 1 6 25 24 7 23 L28-1 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 CPA CEA GND NC CEB CPB OEA B7 B6 B5 B4 B3 B2 B1 B0 OEB CPA CEA GND 2629 drw 02 A5 A4 A3 NC A2 A1 A0 2629 drw 03 LCC TOP VIEW DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW * For 29FCT52/29FCT2052AT/BT/CT only PIN DESCRIPTION Name I/O Description A0-7 I/O Eight bidirectional lines carrying the A Register inputs or B Register outputs. B0-7 I/O Eight bidirectional lines carrying the B Register inputs or A Register outputs. CPA I Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. CEA I OEB Clock Enable for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal transitions. I CPB I Output Enable for the A Register. When OEB is LOW, the A Register outputs are enabled onto the B0-7 lines. When OEB is HIGH, the B0-7 outputs are in the high-impedance state. Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal. CEB I OEA I Clock Enable for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal transitions. Output Enable for the B Register. When OEA is LOW, the B Register outputs are enabled onto the A0-7 lines. OEA is HIGH, the A0-7 outputs are in the high-impedance state. When 2629 tbl 01 6.1 2 IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS REGISTER FUNCTION TABLE(1) MILITARY AND COMMERCIAL TEMPERATURE RANGES OUTPUT CONTROL(1) (Applies to A or B Register) D X L H Inputs CP X ↑ ↑ CE H L L Internal Internal Q NC L H Function Hold Data Load Data ABSOLUTE MAXIMUM RATINGS(1) Military –0.5 to +7.0 Unit V –0.5 to VCC +0.5 V –55 to +125 °C –65 to +135 °C –65 to +150 °C 0.5 W I OUT –60 to +120 mA –60 to +120 Q 52/2052 H X L L L H 53 Function Z Z Disable Outputs L H Enable Outputs H L 2629 tbl 03 CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Rating Commercial VTERM(2) Terminal Voltage –0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage –0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature –55 to +125 Under Bias TSTG Storage –55 to +125 Temperature PT Power Dissipation 0.5 DC Output Current OE NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 2629 tbl 02 NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care NC = No Change ↑ = LOW-to-HIGH Transition Y-Outputs Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V Typ. 6 VOUT = 0V 8 Max. Unit 10 pF 12 NOTE: 1. This parameter is measured at characterization but not tested. pF 2640 lnk 05 2529 lnk 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. 6.1 3 IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10% Symbol VIH Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level Min. 2.0 Typ.(2) — Max. — Unit V VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V II H Input HIGH Current(4) VCC = Max. VI = 2.7V — — ±1 µA II L Input LOW Current (4) VI = 0.5V — — ±1 I OZH High Impedance Output Current I OZL (3-State Output pins) (4) II Input HIGH Current(4) VIK Clamp Diode Voltage VH Input Hysteresis I CC Quiescent Power Supply Current VO = 2.7V — — ±1 VO = 0.5V — — ±1 VCC = Max., VI = VCC (Max.) — — ±1 µA VCC = Min., IIN = –18mA — –0.7 –1.2 V — — 200 — mV — 0.01 1 mA VCC = Max. VCC = Max., VIN = GND or VCC µA 2629 tbl 06 OUTPUT DRIVE CHARACTERISTICS FOR 29FCT52T/29FCT53T VOL Output LOW Voltage I OS Short Circuit Current Test Conditions(1) VCC = Min. I OH = –6mA MIL. VIN = VIH or V IL I OH = –8mA COM'L. I OH = –12mA MIL. I OH = –15mA COM'L. VCC = Min. I OL = 48mA MIL. VIN = VIH or V IL I OL = 64mA COM'L. (3) VCC = Max., VO = GND I OFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or V O ≤ 4.5V Symbol VOH Parameter Output HIGH Voltage Min. 2.4 Typ.(2) 3.3 Max. — Unit V 2.0 3.0 — V — 0.3 0.55 V –60 –120 –225 mA — — ±1 µA 2629 tbl 07 OUTPUT DRIVE CHARACTERISTICS FOR 29FCT2052T Symbol I ODL Parameter Output LOW Current Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) Min. 16 Typ.(2) 48 Max. — Unit mA I ODH Output HIGH Current VCC = 5V, VIN = VIH or V IL, VOUT = 1.5V (3) –16 –48 — mA VOH Output HIGH Voltage 2.4 3.3 — V VOL Output LOW Voltage VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or V IL — 0.3 0.50 V I OH = –12mA MIL. I OH = –15mA COM'L. I OL = 12mA NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is ±5µA at TA = –55°C. 5. This parameter is guaranteed but not tested. 6.1 2629 tbl 08 4 IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD IC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) Total Power Supply Current (6) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OEA or OEB = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OEA or OEB = GND One Bit Toggling at fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OEA or OEB = GND Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle Min. — Typ.(2) 0.5 Max. 2.0 Unit mA — 0.15 0.25 mA/ MHz FCT2xxxT — 0.06 0.12 VIN = VCC FCTxxxT VIN = GND FCT2xxxT — 1.5 3.5 — 0.6 2.2 VIN = 3.4V — 2.0 5.5 1.1 4.2 VIN = VCC FCTxxxT VIN = GND FCTxxxT VIN = GND FCT2xxxT VIN = VCC FCTxxxT VIN = GND FCT2xxxT — 3.8 7.3 (5) — 1.5 4.0 (5) VIN = 3.4V — 6.0 16.3 (5) — 3.8 13.0 (5) FCTxxxT VIN = GND FCT2xxxT NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 6.1 mA 2629 tbl 09 5 IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE 29FCT52AT/53AT 29FCT52BT/53BT 29FCT2052AT Com'l. Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tW Parameter Propagation Delay CPA, CPB to An, Bn Output Enable Time OEA or OEB to An, Bn Output Disable Time OEA or OEB to An, Bn Set-up Time, HIGH or LOW An, Bn to CPA, CPB Hold Time, HIGH or LOW An, Bn to CPA, CPB Set-up Time, HIGH or LOW CEA, CEB to CPA, CPB Hold Time, HIGH or LOW CEA, CEB to CPA, CPB Clock Pulse Width HIGH or LOW(3) Condition(1) Min.(2) CL = 50pF RL = 500Ω 29FCT2052BT Mil. Max. Min.(2) 2.0 10.0 1.5 Com'l. Max. Min.(2) 2.0 11.0 10.5 1.5 1.5 10.0 2.5 Mil. Max. Min. (2) Max. Unit 2.0 7.5 2.0 8.0 ns 13.0 1.5 8.0 1.5 8.5 ns 1.5 10.0 1.5 7.5 1.5 8.0 ns — 2.5 — 2.5 — 2.5 — ns 2.0 — 2.0 — 1.5 — 1.5 — ns 3.0 — 3.0 — 3.0 — 3.0 — ns 2.0 — 2.0 — 2.0 — 2.0 — ns 3.0 — 3.0 — 3.0 — 3.0 — ns 2629 tbl 10 29FCT52CT/53CT 29FCT2052CT Com'l. Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tW Parameter Propagation Delay CPA, CPB to An, Bn Output Enable Time OEA or OEB to An, Bn Output Disable Time OEA or OEB to An, Bn Set-up Time, HIGH or LOW An, Bn to CPA, CPB Hold Time, HIGH or LOW An, Bn to CPA, CPB Set-up Time, HIGH or LOW CEA, CEB to CPA, CPB Hold Time, HIGH or LOW CEA, CEB to CPA, CPB Clock Pulse Width HIGH or LOW(3) Condition(1) Min.(2) CL = 50pF RL = 500Ω 29FCT52DT Mil. Max. Min.(2) 2.0 6.3 1.5 Com'l. Max. Min.(2) 2.0 7.3 7.0 1.5 1.5 6.5 2.5 Mil. Max. Min. (2) Max. Unit 2.0 4.5 — — ns 8.0 1.5 5.6 — — ns 1.5 7.5 1.5 4.3 — — ns — 2.5 — 1.5 — — — ns 1.5 — 1.5 — 1.0 — — — ns 3.0 — 3.0 — 2.0 — — — ns 2.0 — 2.0 — 1.0 — — — ns 3.0 — 3.0 — 3.0 — — — ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 2629 tbl 11 6.1 6 IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS SWITCH POSITION V CC 7.0V V OUT Pulse Generator Open Drain Disable Low Closed Open All Other Tests 2629 lnk 12 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. D.U.T. 50pF RT Switch Enable Low 500Ω VIN Test 500Ω CL 2629 drw 03 SET-UP, HOLD AND RELEASE TIMES DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH 2629 drw 05 2629 drw 04 PROPAGATION DELAY ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL DISABLE 3V 1.5V CONTROL INPUT OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED 2629 drw 06 SWITCH OPEN 3.5V 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH 0V tPLZ tPZL 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V 2629 drw 07 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 6.1 7 IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION XX 29FCT X Temp. Range Family XX XX X Device Type Package Process Blank B Commercial MIL-STD-883, Class B P D E L SO PY Q Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC Shrink Small Outline Package Quarter-size Small Outline Package 52AT 53AT 52BT 53BT 52CT 53CT 52DT Non-inverting Octal Registered Transceiver Inverting Octal Registered Transceiver Blank 20 High Drive Balanced Drive 54 74 –55°C to +125°C 0°C to +70°C 2629 drw 08 6.1 8