74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS014C – AUGUST 1987 – REVISED APRIL 1996 D D D D D D, N, OR PW PACKAGE (TOP VIEW) Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N) 1A 1Y 2Y GND GND 3Y 4Y 4B 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1B 2A 2B VCC VCC 3A 3B 4A description This device contains four independent 2-input AND gates. It performs the Boolean function Y + A • B or Y + A ) B in positive logic. The 74AC11008 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H H L X L X L L logic symbol† 1A 1B 2A 2B 3A 3B 4A 4B 1 & 16 2 1Y 15 3 14 2Y 11 6 10 3Y 9 7 8 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS014C – AUGUST 1987 – REVISED APRIL 1996 logic diagram (positive logic) 1A 1B 2A 2B 3A 3B 4A 4B 1 16 15 14 11 10 9 8 2 3 6 7 1Y 2Y 3Y 4Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . . 1.3 W N package . . . . . . . . . . . . . . . . . . . . 1.1 W PW package . . . . . . . . . . . . . . . . . . . 0.5 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS014C – AUGUST 1987 – REVISED APRIL 1996 recommended operating conditions VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V MIN NOM MAX 3 5 5.5 0.9 VI VO Input voltage 0 Output voltage 0 IOH High-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature V 3.85 Low-level input voltage Low-level output current V 2.1 3.15 VIL IOL UNIT VCC = 4.5 V VCC = 5.5 V 1.35 V 1.65 VCC VCC VCC = 3 V VCC = 4.5 V V V –4 –24 VCC = 5.5 V VCC = 3 V –24 VCC = 4.5 V VCC = 5.5 V 24 mA 12 mA 24 0 10 ns/V –40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –50 µA VOH 3V 2.9 2.9 4.5 V 4.4 4.4 5.4 5.4 3V 2.58 2.48 4.5 V 3.94 3.8 IOH = –24 24 mA A 5.5 V 4.94 IOH = –75 mA† 5.5 V IOL = 12 mA IOL = 24 mA II ICC MIN 5.5 V IOH = –4 mA IOL = 50 µA VOL TA = 25°C MIN TYP MAX MAX UNIT V 4.8 3.85 3V 0.1 0.1 4.5 V 0.1 0.1 5.5 V 0.1 0.1 3V 0.36 0.44 4.5 V 0.36 0.44 5.5 V 0.36 0.44 V IOL = 75 mA† 5.5 V VI = VCC or GND VI = VCC or GND, 5.5 V ±0.1 ±1 µA 5.5 V 4 40 µA IO = 0 Ci VI = VCC or GND 5V 3.5 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.65 pF 3 74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS014C – AUGUST 1987 – REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B Y MIN TA = 25°C TYP MAX MIN MAX 1.5 6.3 9 1.5 10.2 1.5 5.6 7.8 1.5 8.6 UNIT ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B Y MIN TA = 25°C TYP MAX MIN MAX 1.5 4.3 6.2 1.5 6.9 1.5 5.6 5.9 1.5 6.5 UNIT ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate CL = 50 pF, TYP f = 1 MHz 29 UNIT pF PARAMETER MEASUREMENT INFORMATION Input (see Note B) From Output Under Test CL = 50 pF (see Note A) VCC 50% VCC 50% VCC 0V tPLH tPHL 500 Ω Output 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS LOAD CIRCUIT NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74AC11008D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11008DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11008DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11008DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11008DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11008DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11008N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 74AC11008NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 74AC11008PWLE OBSOLETE TSSOP PW 16 74AC11008PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11008PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11008PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 74AC11008DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 74AC11008PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74AC11008DR SOIC D 16 2500 333.2 345.9 28.6 74AC11008PWR TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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