74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description Pin Assignments (Top View) The 74LVC1G125 is a single non-inverting buffer/bus driver with a 3-state output. The output enters a high impedance OE 1 A 2 5 Vcc 4 Y state when a HIGH-level is applied to the output enable (OE) pin. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V GND 3 NEW PRODUCT allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power SOT25 / SOT353 down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device (Top View) is powered down. OE 1 6 Vcc A 2 5 NC GND 3 4 Y Features • Wide Supply Voltage Range from 1.65 to 5.5V • ± 24mA Output Drive at 3.3V • CMOS low power consumption • IOFF Supports Partial-Power-Down Mode Operation • Inputs accept up to 5.5V • ESD Protection Tested per JESD 22 DFN1410 (Note 2) Applications Exceeds 200-V Machine Model (A115-A) Exceeds 2000-V Human Body Model (A114-A) • Latch-Up Exceeds 100mA per JESD 78, Class II LatchUp Exceeds 100mA per JESD 78, Class II • Range of Package Options • Direct Interface with TTL Levels • SOT25, SOT353, and DFN1410: Assembled with “Green” Molding Compound (no Br, Sb) • Lead Free Finish/ RoHS Compliant (Note 1) Notes: • • • • • Voltage Level Shifting Bus Driver / Repeater Power Down Signal Isolation General Purpose Logic Wide array of products such as. o PCs, networking, notebooks, netbooks, PDAs o Computer peripherals, hard drives, CD/DVD ROM o TV, DVD, DVR, set top box o Cell Phones, Personal Navigation / GPS o MP3 players ,Cameras, Video Recorders 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at http://www.diodes.com/products/lead_free.html. 2. Pin 2 and pin 5 of the DFN1410 package are internally connected. 74LVC1G125 Document number: DS32202 Rev. 2 - 2 1 of 14 www.diodes.com October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Pin Descriptions Pin Name OE Output Enable A Data Input GND Y NEW PRODUCT Description Ground Data Output Vcc Supply Voltage NC No Connection Logic Diagram OE 1 2 A 4 Y Function Table Inputs Output OE L A Y H H L L L H X Z 74LVC1G125 Document number: DS32202 Rev. 2 - 2 2 of 14 www.diodes.com October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Absolute Maximum Ratings (Note 3) Symbol Rating Unit 2 200 KV V Supply Voltage Range -0.5 to 6.5 V VI Input Voltage Range -0.5 to 6.5 V Vo Voltage applied to output in high impedance or IOFF state -0.5 to 6.5 V Vo Voltage applied to output in high or low state -0.3 to VCC +0.5 V IIK Input Clamp Current VI<0 -50 mA IOK Output Clamp Current -50 mA IO Continuous output current ±50 mA Continuous current through Vdd or GND ±100 mA Operating Junction Temperature -40 to 150 °C Storage Temperature -65 to 150 °C ESD HBM ESD MM NEW PRODUCT VCC TJ TSTG Notes: Description Human Body Model ESD Protection Machine Model ESD Protection 3. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device operation should be within recommend values. 74LVC1G125 Document number: DS32202 Rev. 2 - 2 3 of 14 www.diodes.com October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Recommended Operating Conditions (Note 4) Symbol VCC Operating Voltage Parameter Operating Data retention only VCC = 1.65V to 1.95V High-level Input Voltage NEW PRODUCT VIH VCC = 2.3V to 2.7V VCC = 3V to 3.6V VCC = 4.5V to 5.5V Min 1.65 1.5 Low-level input voltage Unit V V 0.65 X VCC 1.7 V 2 0.7 X VCC VCC = 1.65V to 1.95V VIL Max 5.5 0.35 X VCC VCC = 2.3V to 2.7V 0.7 VCC = 3V to 3.6V 0.8 VCC = 4.5V to 5.5V V 0.3 X VCC VI Input Voltage 0 5.5 V VO Output Voltage 0 VCC V IOH Low-level output current IOL Δt/ΔV TA Notes: High-level output current VCC = 1.65V -4 VCC = 2.3V -8 VCC = 3V -16 -24 VCC = 4.5V -32 VCC = 1.65V 4 VCC = 2.3V 8 VCC = 3V 16 24 VCC = 4.5V 32 VCC = 1.8V ± 0.15V, 2.5V ± 0.2V Input transition rise or fall VCC = 3.3V ± 0.3V rate VCC = 5V ± 0.5V Operating free-air temperature mA mA 20 10 ns/V 5 -40 85 ºC 4. Unused inputs should be held at Vcc or Ground. 74LVC1G125 Document number: DS32202 Rev. 2 - 2 4 of 14 www.diodes.com October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Electrical Characteristics (All typical values are at Vcc = 3.3V, TA = 25°C) Over recommended free-air temperature range (unless otherwise noted) Symbol Parameter Test Conditions Vcc Min 1.65V to 5.5V VCC – 0.1 IOH = -4mA 1.65V 1.2 IOH = -8mA 2.3V 1.9 IOH = -100μA NEW PRODUCT VOH High Level Output Voltage IOH = -16mA 3V IOH = -24mA VOL High-level Input Voltage 0.1 IOL = 4mA 1.65V 0.45 IOL = 8mA 2.3V 0.3 VI or VO = 5.5V IOZ ICC Supply Current VI = 5.5V of GND IO=0 Ci θJA θJC 2.3 1.65V to 5.5V Input Current Power Down Leakage Current Z State Leakage Current ΔICC V IOL = 100μA IOL = 16mA VI = 5.5V or GND 3.8 V 0.4 3V 0.55 4.5V 0.55 0 to 5.5V ±5 μA 0 ± 10 μA 3.6V ± 10 μA 1.65V to 5.5V 10 μA 3V to 5.5V 500 μA VO =0 to 5.5V One input at VCC – Additional Supply Current 0.6 V Other inputs at VCC or GND Input Capacitance Vi = VCC – or GND SOT25 Thermal Resistance SOT353 Junction-to-Ambient DFN1410 SOT25 Thermal Resistance SOT353 Junction-to-Case DFN1410 Unit 2.4 4.5V IOL = 32mA IOFF Max IOH = -32mA IOL = 24mA II Typ. 3.3 (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) 4 204 371 430 52 143 190 pF C/W o C/W o C/W o C/W o C/W o C/W o Notes: 5. Test condition for SOT25, SOT353, and DFN1410: Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. 74LVC1G125 Document number: DS32202 Rev. 2 - 2 5 of 14 www.diodes.com October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Switching Characteristics Over recommended free-air temperature range, CL = 15pF (see Figure 1) Vcc = 1.8 V Vcc = 2.5 V From TO ± 0.15V ± 0.2V Parameter (Input) (OUTPUT) Min Max Min Max A NEW PRODUCT tpd Y 1.9 6.9 0.7 4.6 Vcc = 3.3 V ± 0.3V Min Max Vcc = 5 V ± 0.5V Min Max 0.6 0.5 3.7 Over recommended free-air temperature range, CL = 30 or 50pF as noted (see Figure 2) Vcc = 1.8 V Vcc = 2.5 V Vcc = 3.3 V From TO ± 0.15V ± 0.2V ± 0.3V Parameter (Input) (OUTPUT) Min Max Min Max Min Max 3.4 Vcc = 5 V ± 0.5V Min Max Unit ns Unit tpd A Y 2.8 9.0 1.2 5.5 1.0 4.5 1.0 4.0 ns ten OE Y 2.8 10.1 1.5 6.6 1.0 5.3 1.0 5.0 ns tdis OE Y 1.3 9.2 1.0 5.5 1.0 5.5 1.0 4.2 ns Operating Characteristics TA = 25 ºC Vcc = 1.8 V Test Conditions TYP Parameter Cpd Power dissipation capacitance Outputs enabled Vcc = 2.5 V Vcc = 3.3 V Vcc = 5 V TYP TYP TYP 19 19 21 19 f = 10 MHz Outputs disabled 74LVC1G125 Document number: DS32202 Rev. 2 - 2 Unit pF 2 6 of 14 www.diodes.com 2 3 4 October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Parameter Measurement Information RL From Output Under Test C NEW PRODUCT VLOAD Open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL L (see Note A) Inputs Vcc 1.8V±0.15V 2.5V±0.2V 3.3V±0.3V 5V±0.5V S1 VI VCC VCC 3V VCC tr/tf ≤2ns ≤2ns ≤2.5ns ≤2.5ns S1 Open Vload GND VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5V VCC/2 2 X VCC 2 X VCC 6V 2 X VCC 15pF 15pF 15pF 15pF 1MΩ 1MΩ 1MΩ 1MΩ 0.15V 0.15V 0.3V 0.3V Voltage Waveform Pulse Duration Voltage Waveform Enable and Disable Times Low and High Level Enabling Voltage Waveform Propagation Delay Times Inverting and Non Inverting Outputs Figure 1. Load Circuit and Voltage Waveforms Notes: A. Includes test lead and test apparatus capacitance. B. All pulses are supplied at pulse repetition rate ≤ 10 MHz. C. Inputs are measured separately one transition per measurement. D. tPLZ and tPHZ are the same as tdis. E. tPZL and tPZH are the same as tEN. F. tPLH and tPHL are the same as tPD. 74LVC1G125 Document number: DS32202 Rev. 2 - 2 7 of 14 www.diodes.com October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Parameter Measurement Information (Continued) RL From Output Under Test C NEW PRODUCT VLOAD Open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL L (see Note A) Inputs Vcc 1.8V±0.15V 2.5V±0.2V 3.3V±0.3V 5V±0.5V S1 VI VCC VCC 3V VCC tr/tf ≤2ns ≤2ns ≤2.5ns ≤2.5ns S1 Open Vload GND VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5V VCC/2 2 X VCC 2 X VCC 6V 2 X VCC 30pF 30pF 50pF 50pF 1KΩ 500Ω 500Ω 500Ω 0.15V 0.15V 0.3V 0.3V Voltage Waveform Pulse Duration Voltage Waveform Enable and Disable Times Low and High Level Enabling Voltage Waveform Propagation Delay Times Inverting and Non Inverting Outputs Figure 2. Load Circuit and Voltage Waveforms Notes: A. Includes test lead and test apparatus capacitance. B. All pulses are supplied at pulse repetition rate ≤ 10 MHz. C. Inputs are measured separately one transition per measurement. D. tPLZ and tPHZ are the same as tdis. E. tPZL and tPZH are the same as tEN0 F. tPLH and tPHL are the same as tPD. 74LVC1G125 Document number: DS32202 Rev. 2 - 2 8 of 14 www.diodes.com October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Ordering Information NEW PRODUCT 74LVC1G 125 XXX - 7 Logic Device Function Package 74 : Logic Prefix LVC : 1.65 to 5.5V Family 1G : One gate 125 : 3-State Buffer OE-Low W5 : SOT25 SE : SOT353 FZ4 : DFN1410 Device 74LVC1G125W5-7 74LVC1G125SE-7 74LVC1G125FZ4-7 Notes: Package Code W5 SE FZ4 Packaging (Note 6) SOT25 SOT353 DFN1410 Packing 7 : Tape & Reel 7” Tape and Reel Quantity Part Number Suffix 3000/Tape & Reel -7 3000/Tape & Reel -7 5000/Tape & Reel -7 6. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. 74LVC1G125 Document number: DS32202 Rev. 2 - 2 9 of 14 www.diodes.com October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Marking Information (1) SOT25 and SOT353 (Top View) 4 7 5 XX : Identification code Y : Year 0~9 W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week X : A~Z : Internal code NEW PRODUCT XX Y W X 1 2 3 Part Number 74LVC1G125W5 74LVC1G125SE Package SOT25 SOT353 Identification Code UY UY (2) DFN1410 (Top View) XX YWX Part Number 74LVC1G125FZ4 74LVC1G125 Document number: DS32202 Rev. 2 - 2 XX : Identification Code Y : Year : 0~9 W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week X : A~Z : Internal code Package DFN1410 10 of 14 www.diodes.com Identification Code UY October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Package Outline Dimensions (All Dimensions in mm) NEW PRODUCT (1) Package Type: SOT25 (2) Package Type: SOT353 6x-0.42 CL 0.10/0.30 C L 0.40/0.45 0.65Bsc. 0.25/0.40 C L 1.8/2.2 74LVC1G125 Document number: DS32202 Rev. 2 - 2 0.1/0.22 Detail"A" 0.9/1.0 0/0.1 1.10Max. Gauge Plane Land Pattern Recommendation (unit:mm) Top View 0.25 PIN 1 0°/8 ° C L 6x-0.60 2x-0.65 1.15/1.35 2.0/2.2 C L 1.9 1.3 "A" 11 of 14 www.diodes.com October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Package Outline Dimensions (Continued) Side View 1.35/1.45 0.550 6x-0.25 2X- NEW PRODUCT C 6x-0.35 Seating Plane 0.25 A 0.08 C 0.13Typ. 0.40Max. 0.10 C 6x- 0/0.05 (3) Package Type: DFN1410 A 0.50Typ. 2X- (Pin #1 ID) C0. 1x4 5¢X 0.075¡ Ó 0.030 6x-0.25/0.35 0.95/1.05 B 4x-0.50Typ. Land Pattern Recommendation (mm) Top View 0.25 B 0.10(4x) 6x-0.15/0.25 0.10 C A B Bottom View 74LVC1G125 Document number: DS32202 Rev. 2 - 2 12 of 14 www.diodes.com October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Taping Orientation (Note 7) NEW PRODUCT For DFN1410 Notes: 7. The taping orientation of the other package type can be found on our website at http://www.diodes.com/datasheets/ap02007.pdf 74LVC1G125 Document number: DS32202 Rev. 2 - 2 13 of 14 www.diodes.com October 2010 © Diodes Incorporated 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). NEW PRODUCT Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. 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