74LVC2G125 Dual bus buffer/line driver; 3-state Rev. 11 — 9 September 2010 Product data sheet 1. General description The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V ±24 mA output drive (VCC = 3.0 V) CMOS low-power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G125DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G125DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm 74LVC2G125GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm 74LVC2G125GF −40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1 × 0.5 mm 74LVC2G125GD −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm 74LVC2G125GM −40 °C to +125 °C XQFN8U plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm SOT902-1 74LVC2G125GN −40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.2 × 1.0 × 0.35 mm SOT1116 74LVC2G125GS −40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1.0 × 0.35 mm SOT1203 SOT1089 4. Marking Table 2. Marking codes Type number Marking code[1] 74LVC2G125DP V25 74LVC2G125DC V25 74LVC2G125GT V25 74LVC2G125GF VM 74LVC2G125GD V25 74LVC2G125GM V25 74LVC2G125GN VM 74LVC2G125GS VM [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 2 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state 5. Functional diagram 74LVC2G125 1A 74LVC2G125 1Y 1 EN1 1OE 2A 2Y 2 2OE EN2 001aae009 mna941 Fig 1. Logic symbol Fig 2. IEC logic symbol 6. Pinning information 6.1 Pinning 74LVC2G125 1OE 1 8 VCC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 74LVC2G125 1OE 1 8 VCC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 001aab739 Transparent top view 001aab738 Fig 3. Pin configuration SOT505-2 and SOT765-1 74LVC2G125 Product data sheet Fig 4. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 3 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state 74LVC2G125 74LVC2G125 1 8 VCC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 1 1Y 2A 8 2OE 7 1OE 2 6 1A 3 5 2Y GND 4 1OE VCC terminal 1 index area 001aai243 Transparent top view Transparent top view Fig 5. 001aae010 Pin configuration SOT996-2 Fig 6. Pin configuration SOT902-1 6.2 Pin description Table 3. Symbol Pin description Pin Description SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 SOT902-1 1OE, 2OE 1, 7 7, 1 output enable input (active LOW) 1A, 2A 2, 5 6, 3 data input GND 4 4 ground (0 V) 1Y, 2Y 6, 3 2, 5 data output VCC 8 8 supply voltage 7. Functional description Table 4. Function table[1] Control Input Output nOE nA nY L L L L H H H X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 4 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current [1] output voltage VO VI < 0 V Min Max Unit −0.5 +6.5 V −50 - mA −0.5 +6.5 V - ±50 mA Enable mode [1] −0.5 VCC + 0.5 V Disable mode [1] −0.5 +6.5 V [1][2] −0.5 +6.5 V - ±50 mA VO > VCC or VO < 0 V Power-down mode IO output current VO = 0 V to VCC ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C - 300 mW total power dissipation Ptot Tamb = −40 °C to +125 °C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Min Max Unit 1.65 5.5 V 0 5.5 V VCC = 1.65 V to 5.5 V; Enable mode 0 VCC V VCC = 1.65 V to 5.5 V; Disable mode 0 5.5 V VCC = 0 V; Power-down mode 0 5.5 V Tamb ambient temperature −40 +125 °C Δt/ΔV input transition rise and VCC = 1.65 V to 2.7 V fall rate VCC = 2.7 V to 5.5 V - 20 ns/V - 10 ns/V 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 5 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Typ[1] Max Conditions Min Unit VCC = 1.65 V to 1.95 V 0.65VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7VCC - - V VCC = 1.65 V to 1.95 V - - 0.35VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC V IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.3 V Tamb = −40 °C to +85 °C VIH VIL VOL VOH HIGH-level input voltage LOW-level input voltage LOW-level output voltage VI = VIH or VIL IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V IO = 32 mA; VCC = 4.5 V - - 0.55 V HIGH-level output voltage VI = VIH or VIL IO = −100 μA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V IO = −4 mA; VCC = 1.65 V 1.2 - - V IO = −8 mA; VCC = 2.3 V 1.9 - - V IO = −12 mA; VCC = 2.7 V 2.2 - - V IO = −24 mA; VCC = 3.0 V 2.3 - - V IO = −32 mA; VCC = 4.5 V 3.8 - - V II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - ±0.1 ±5 μA IOZ OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V - ±0.1 ±10 μA IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±10 μA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 10 μA ΔICC additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 μA CI input capacitance - 2 - pF 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 6 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit VCC = 1.65 V to 1.95 V 0.65VCC - - V Tamb = −40 °C to +125 °C HIGH-level input voltage VIH LOW-level input voltage VIL LOW-level output voltage VOL VOH VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7VCC - - V VCC = 1.65 V to 1.95 V - - 0.35VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC V VI = VIH or VIL IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V VCC − 0.1 - - V IO = −4 mA; VCC = 1.65 V 0.95 - - V IO = −8 mA; VCC = 2.3 V 1.7 - - V IO = −12 mA; VCC = 2.7 V 1.9 - - V IO = −24 mA; VCC = 3.0 V 2.0 - - V HIGH-level output voltage VI = VIH or VIL IO = −100 μA; VCC = 1.65 V to 5.5 V IO = −32 mA; VCC = 4.5 V 3.4 - - V II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - ±20 μA IOZ OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V - - ±20 μA IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - ±20 μA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 40 μA ΔICC additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 5 mA [1] Typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 7 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 9. Symbol Parameter −40 °C to +85 °C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 1.0 3.7 9.1 1.0 11.4 ns VCC = 2.3 V to 2.7 V 0.5 2.5 4.8 0.5 6.0 ns VCC = 2.7 V 1.0 2.7 4.8 1.0 6.0 ns VCC = 3.0 V to 3.6 V 0.5 2.3 4.3 0.5 5.5 ns VCC = 4.5 V to 5.5 V 0.5 1.9 3.7 0.5 4.6 ns 1.5 4.3 9.9 1.5 12.4 ns propagation delay nA to nY; see Figure 7 tpd enable time ten nOE to nY; see Figure 8 [2] [3] VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 1.0 2.8 5.6 1.0 7.0 ns VCC = 2.7 V 1.5 3.3 5.7 1.5 7.1 ns VCC = 3.0 V to 3.6 V 0.5 2.4 4.7 0.5 5.9 ns 0.5 2.0 3.8 0.5 4.8 ns VCC = 1.65 V to 1.95 V 1.0 3.5 11.6 1.0 14.1 ns VCC = 2.3 V to 2.7 V 0.5 1.8 5.8 0.5 7.6 ns VCC = 2.7 V 1.0 2.7 4.8 1.0 6.2 ns VCC = 3.0 V to 3.6 V 1.0 2.7 4.6 1.0 5.9 ns VCC = 4.5 V to 5.5 V 0.5 1.8 3.4 0.5 4.6 ns output enabled - 18 - - - pF output disabled - 5 - - - pF VCC = 4.5 V to 5.5 V disable time tdis power dissipation capacitance CPD nOE to nY; see Figure 8 per buffer; VI = GND to VCC [1] Typical values are measured at nominal VCC and at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL. [3] ten is the same as tPZH and tPZL. [4] tdis is the same as tPLZ and tPHZ. [5] −40 °C to +125 °C Unit Typ[1] [4] [5] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 8 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state 12. Waveforms VI VM nA input GND tPHL tPLH VOH VM nY output VOL mna230 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Propagation delay input (nA) to output (nY) VI nOE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled mna362 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 9. 3-state output enable and disable times Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 1.95 V 0.5VCC 0.5VCC VOL + 0.15 V VOH − 0.15 V 2.3 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH − 0.15 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 4.5 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 9 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 10. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 9. Table 10. Test circuit for measuring switching times Test data Supply voltage Input VCC VI tr, tf Load CL RL VEXT tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open GND 2VCC 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open GND 2VCC 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND 6V 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND 6V 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open GND 2VCC 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 10 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Fig 10. Package outline SOT505-2 (TSSOP8) 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 11 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA MO-187 EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 11. Package outline SOT765-1 (VSSOP8) 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 12 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 12. Package outline SOT833-1 (XSON8) 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 13 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area A D A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 terminal 1 index area 8 L1 X 0 0.5 scale Dimensions Unit mm max nom min 1 mm A(1) 0.5 A1 b D E e L e1 L1 0.04 0.20 1.40 1.05 0.35 0.40 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.27 0.32 0.12 1.30 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1089 sot1089_po References IEC JEDEC JEITA European projection Issue date 10-04-09 10-04-12 MO-252 Fig 13. Package outline SOT1089 (XSON8) 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 14 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm B D SOT996-2 A A E A1 detail X terminal 1 index area e1 v w b e L1 1 4 8 5 C C A B C M M y y1 C L2 L X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 L2 v w y y1 mm 0.5 0.05 0.00 0.35 0.15 2.1 1.9 3.1 2.9 0.5 1.5 0.5 0.3 0.15 0.05 0.6 0.4 0.1 0.05 0.05 0.1 REFERENCES OUTLINE VERSION IEC SOT996-2 --- JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 14. Package outline SOT996-2 (XSON8U) 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 15 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm B D SOT902-1 A terminal 1 index area A E A1 detail X L1 e e C ∅v M C A B ∅w M C L 4 y1 C y 5 3 metal area not for soldering e1 b 2 6 e1 7 1 terminal 1 index area 8 X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 v w y y1 mm 0.5 0.05 0.00 0.25 0.15 1.65 1.55 1.65 1.55 0.55 0.5 0.35 0.25 0.15 0.05 0.1 0.05 0.05 0.05 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT902-1 --- MO-255 --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 15. Package outline SOT902-1 (XQFN8U) 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 16 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm 1 2 SOT1116 b 4 3 (4×)(2) L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95 L L1 0.35 0.40 0.30 0.35 0.27 0.32 0.3 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1116_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1116 Fig 16. Package outline SOT1116 (XSON8) 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 17 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 2 1 3 (4×)(2) 4 L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1203_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1203 Fig 17. Package outline SOT1203 (XSON8) 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 18 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2G125 v.11 20100909 Product data sheet - 74LVC2G125 v.10 Modifications: • • • Added type number 74LVC2G125GF (SOT1089/XSON8 package) Added type number 74LVC2G125GN (SOT1116/XSON8 package). Added type number 74LVC2G125GS (SOT1203 / XSON8 package). 74LVC2G125 v.10 20080611 Product data sheet - 74LVC2G125 v.9 74LVC2G125 v.9 20080226 Product data sheet - 74LVC2G125 v.8 74LVC2G125 v.8 20070907 Product data sheet - 74LVC2G125 v.7 74LVC2G125 v.7 20060523 Product data sheet - 74LVC2G125 v.6 74LVC2G125 v.6 20051223 Product data sheet - 74LVC2G125 v.5 74LVC2G125 v.5 20050201 Product specification - 74LVC2G125 v.4 74LVC2G125 v.4 20040922 Product specification - 74LVC2G125 v.3 74LVC2G125 v.3 20040109 Product specification - 74LVC2G125 v.2 74LVC2G125 v.2 20030901 Product specification - 74LVC2G125 v.1 74LVC2G125 v.1 20030310 Product specification - - 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 19 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVC2G125 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 20 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC2G125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 9 September 2010 © NXP B.V. 2010. All rights reserved. 21 of 22 74LVC2G125 NXP Semiconductors Dual bus buffer/line driver; 3-state 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 9 September 2010 Document identifier: 74LVC2G125