74LVC3GU04 Triple inverter Rev. 07 — 11 November 2009 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. 2. Features n n n n n n n n n n Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: u JESD8-7 (1.65 V to 1.95 V) u JESD8-5 (2.3 V to 2.7 V) u JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: u HBM JESD22-A114F exceeds 2000 V u MM JESD22-A115-A exceeds 200 V ±24 mA output drive at VCC = 3.0 V CMOS low power consumption Latch-up performance exceeds 250 mA Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC3GU04DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC3GU04DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74LVC3GU04 NXP Semiconductors Triple inverter Table 1. Ordering information …continued Type number Package Temperature range Name Description Version 74LVC3GU04GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1 74LVC3GU04GD −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 × 2 × 0.5 mm SOT996-2 XQFN8U SOT902-1 74LVC3GU04GM −40 °C to +125 °C plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm 4. Marking Table 2. Marking codes Type number Marking code[1] 74LVC3GU04DP VU04 74LVC3GU04DC VU4 74LVC3GU04GT VU4 74LVC3GU04GD VU4 74LVC3GU04GM VU4 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 1 2A 2Y 3A 3Y 1 001aah794 001aah793 Fig 1. Logic symbol Fig 2. VCC IEC logic symbol VCC 100 Ω Y A mna636 Fig 3. Logic diagram (one gate) 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 2 of 17 74LVC3GU04 NXP Semiconductors Triple inverter 6. Pinning information 6.1 Pinning 74LVC3GU04 1A 1 8 VCC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y 74LVC3GU04 1A 1 8 VCC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y 001aac021 Transparent top view mnb120 Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT833-1 (XSON8) 74LVC3GU04 74LVC3GU04 1 8 VCC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y 1 3A 2Y 7 1A 2 6 3Y 3 5 2A GND 001aal098 001aag056 Transparent top view Transparent top view Fig 6. 8 1Y 4 1A VCC terminal 1 index area Pin configuration SOT996-2 (XSON8U) Fig 7. Pin configuration SOT902-1 (XQFN8U) 6.2 Pin description Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1, SOT833-1 and SOT996-2 SOT902-1 1A, 2A, 3A 1, 3, 6 7, 5, 2 data input GND 4 4 ground (0 V) 1Y, 2Y, 3Y 7, 5, 2 1, 3, 6 data output VCC 8 8 supply voltage 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 3 of 17 74LVC3GU04 NXP Semiconductors Triple inverter 7. Functional description Table 4. Function table[1] Input nA Output nY L H H L [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Min Max Unit −0.5 +6.5 V input voltage [1] −0.5 +6.5 V VO output voltage [1] −0.5 VCC + 0.5 V IIK input clamping current VI < 0 V −50 - mA IOK output clamping current VO > VCC or VO < 0 V - ±50 mA IO output current VO = 0 V to VCC - ±50 mA ICC supply current - 100 mA IGND ground current −100 - mA Ptot total power dissipation - 250 mW Tstg storage temperature −65 +150 °C VI Conditions Active mode Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 packages: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K. For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter Min Max Unit VCC supply voltage Conditions 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 5.5 V Tamb ambient temperature −40 +125 °C ∆t/∆V input transition rise and fall rate VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 5.5 V - 10 ns/V 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 4 of 17 74LVC3GU04 NXP Semiconductors Triple inverter 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit V Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VCC = 1.65 V to 5.5 V 0.75 × VCC - - VIL LOW-level input voltage VCC = 1.65 V to 5.5 V - - 0.25 × VCC V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V IO = −4 mA; VCC = 1.65 V 1.2 - - V IO = −8 mA; VCC = 2.3 V 1.9 - - V IO = −12 mA; VCC = 2.7 V 2.2 - - V IO = −24 mA; VCC = 3.0 V 2.3 - - V IO = −32 mA; VCC = 4.5 V 3.8 - - V IO = 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V IO = 32 mA; VCC = 4.5 V - - 0.55 V VOL LOW-level output voltage VI = VIH or VIL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - ±0.1 ±5 µA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 10 µA CI input capacitance - 5 - pF Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 1.65 V to 5.5 V 0.8 × VCC - - V VIL LOW-level input voltage VCC = 1.65 V to 5.5 V - - 0.2 × VCC V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V IO = −4 mA; VCC = 1.65 V 0.95 - - V IO = −8 mA; VCC = 2.3 V 1.7 - - V IO = −12 mA; VCC = 2.7 V 1.9 - - V IO = −24 mA; VCC = 3.0 V 2.0 - - V IO = −32 mA; VCC = 4.5 V 3.4 - - V 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 5 of 17 74LVC3GU04 NXP Semiconductors Triple inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Min Typ[1] Max Unit IO = 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V Symbol Parameter Conditions VOL LOW-level output voltage VI = VIH or VIL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - ±20 µA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 40 µA [1] All typical values are measured at Tamb = 25 °C. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter −40 °C to +85 °C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 0.5 2.3 5.0 0.5 6.3 ns VCC = 2.3 V to 2.7 V 0.3 1.8 4.0 0.3 4.0 ns VCC = 2.7 V 0.3 2.6 4.5 0.3 5.6 ns VCC = 3.0 V to 3.6 V 0.3 2.3 3.7 0.3 4.5 ns VCC = 4.5 V to 5.5 V 0.3 1.7 3.0 0.3 3.8 ns - 7 - - - pF propagation delay nA to nY; see Figure 8 tpd power dissipation capacitance CPD −40 °C to +125 °C Unit Typ[1] VI = GND to VCC; VCC = 3.3 V [2] [3] [1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 6 of 17 74LVC3GU04 NXP Semiconductors Triple inverter 12. Waveforms VI VM nA input VM GND t PHL t PLH VOH VM nY output VOL VM mna344 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 9. The input (nA) to output (nY) propagation delays Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 × VCC 0.5 × VCC 2.3 V to 2.7 V 0.5 × VCC 0.5 × VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 × VCC 0.5 × VCC 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 7 of 17 74LVC3GU04 NXP Semiconductors Triple inverter VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 10. Load circuitry for measuring switching times Test data Supply voltage Input Load VCC VI tr = t f CL RL tPLH, tPHL 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open 74LVC3GU04_7 Product data sheet VEXT © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 8 of 17 74LVC3GU04 NXP Semiconductors Triple inverter 13. Additional characteristics mnb108 160 gfs (mA/V) 120 Rbias = 560 kΩ 80 VCC 0.47 µF input output 40 100 µF VI (f = 1 kHz) A IO 0 GND 0 1 2 3 4 5 6 VCC (V) mna050 Tamb = 25 °C. ∆I O g fs = --------∆V I Fig 10. Test set-up for measuring forward transconductance Fig 11. Typical forward transconductance as a function of supply voltage 14. Application information R2 R1 VCC 1 µF R2 R1 U04 U04 C1 ZL C2 out mna053 mna052 ZL > 10 kΩ C1 = 47 pF R1 ≥ 3 kΩ C2 = 22 pF R2 ≤ 1 MΩ R1 = 1 MΩ to 10 MΩ Open loop gain: Gol = 20 R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC = 2 mA at VCC = 3.3 V and f = 10 MHz). G ol Voltage gain: G v = – --------------------------------------R1 1 + ------- ( 1 + G ol ) R2 Vo(p-p) = VCC − 1.5 V centered at 0.5 × VCC Unity gain bandwidth product is 5 MHz. Fig 12. Linear amplifier application Fig 13. Crystal oscillator application Remark: All values given are typical values unless otherwise specified. 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 9 of 17 74LVC3GU04 NXP Semiconductors Triple inverter 15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Fig 14. Package outline SOT505-2 (TSSOP8) 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 10 of 17 74LVC3GU04 NXP Semiconductors Triple inverter VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA MO-187 EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 15. Package outline SOT765-1 (VSSOP8) 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 11 of 17 74LVC3GU04 NXP Semiconductors Triple inverter XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 16. Package outline SOT833-1 (XSON8) 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 12 of 17 74LVC3GU04 NXP Semiconductors Triple inverter XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm B D SOT996-2 A A E A1 detail X terminal 1 index area e1 L1 v w b e 1 4 8 5 C C A B C M M y y1 C L2 L X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 L2 v w y y1 mm 0.5 0.05 0.00 0.35 0.15 2.1 1.9 3.1 2.9 0.5 1.5 0.5 0.3 0.15 0.05 0.6 0.4 0.1 0.05 0.05 0.1 REFERENCES OUTLINE VERSION IEC SOT996-2 --- JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 17. Package outline SOT996-2 (XSON8U) 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 13 of 17 74LVC3GU04 NXP Semiconductors Triple inverter XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm B D SOT902-1 A terminal 1 index area E A A1 detail X L1 e e C ∅v M C A B ∅w M C L 4 y1 C y 5 3 metal area not for soldering e1 b 6 2 e1 7 1 terminal 1 index area 8 X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 v w y y1 mm 0.5 0.05 0.00 0.25 0.15 1.65 1.55 1.65 1.55 0.55 0.5 0.35 0.25 0.15 0.05 0.1 0.05 0.05 0.05 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT902-1 --- MO-255 --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 18. Package outline SOT902-1 (XQFN8U) 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 14 of 17 74LVC3GU04 NXP Semiconductors Triple inverter 16. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 17. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC3GU04_7 20091111 Product data sheet - 74LVC3GU04_6 Modifications: • Added type number 74LVC3GU04GD (XSON8U package) 74LVC3GU04_6 20080304 Product data sheet - 74LVC3GU04_5 74LVC3GU04_5 20071005 Product data sheet - 74LVC3GU04_4 74LVC3GU04_4 20070315 Product data sheet - 74LVC3GU04_3 74LVC3GU04_3 20050201 Product data sheet - 74LVC3GU04_2 74LVC3GU04_2 20041027 Product data sheet - 74LVC3GU04_1 74LVC3GU04_1 20040512 Product data sheet - - 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 15 of 17 74LVC3GU04 NXP Semiconductors Triple inverter 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC3GU04_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 11 November 2009 16 of 17 74LVC3GU04 NXP Semiconductors Triple inverter 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional characteristics . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 11 November 2009 Document identifier: 74LVC3GU04_7