INTEGRATED CIRCUITS 74LVC86 Quad 2-input EXCLUSIVE-OR gate Product specification Supersedes data of February 1996 IC24 Data Handbook 1997 Mar 18 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LVC86 FEATURES DESCRIPTION • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels The 74LVC86 is a high-performance, low-power, low-voltage Si-gate CMOS device that is pin and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC86 provides the 2-input EXCLUSIVE-OR function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER tPHL tPLH Propagation delay nA, nB to nY CI Input capacitance CPD CONDITIONS TYPICAL UNIT 3.7 ns 5.0 pF 55 pF CL = 15 pF; VCC = 3.3 V Power dissipation capacitance per gate VCC = 3.3 V, VI = GND to VCC1 NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL PACKAGES –40°C to +85°C 74LVC86 N 74LVC86 N SOT27-1 14-Pin Plastic SO –40°C to +85°C 74LVC86 D 74LVC86 D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +85°C 74LVC86 DB 74LVC86 DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC86 PW 74LVC86PW DH SOT402-1 PIN CONFIGURATION LOGIC SYMBOL (IEEE/IEC) 1 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A 7 8 3Y GND =1 3 2 4 =1 6 5 9 =1 8 10 12 SV00481 =1 11 13 PIN DESCRIPTION PIN NUMBER SYMBOL SV00479 FUNCTION 1, 4, 9, 12 1A – 4A Data inputs 2, 5, 10, 13 1B – 4B Data inputs 3, 6, 8, 11 1Y – 4Y Data outputs 7 GND Ground (0 V) 14 VCC Positive supply voltage 1997 Mar 18 2 853–1946 17864 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LVC86 LOGIC SYMBOL FUNCTION TABLE INPUTS 1 1A 2 1B 1Y 3 4 2A 5 2B 2Y 6 9 3A 10 3B 3Y 8 12 4A 13 4B 4Y 11 nA OUTPUTS nB nY L L L L H H H L H H H L NOTES: H = HIGH voltage level L = LOW voltage level SV00480 LOGIC DIAGRAM (ONE GATE) A Y B SV00478 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS LIMITS MIN MAX UNIT VCC DC supply voltage (for max. speed performance) 2.7 3.6 V VCC DC supply voltage (for low-voltage applications) 1.2 3.6 V DC input voltage range 0 5.5 V VI/O VI DC input voltage range for I/Os 0 VCC V VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V Tamb tr, tf Operating free-air temperature range VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V Input rise and fall times ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). PARAMETER SYMBOL VCC CONDITIONS DC supply voltage IIK DC input diode current VI t 0 VI DC input voltage Note 2 VI/O DC input voltage range for I/Os IOK DC output diode current VO uVCC or VO t 0 VOUT DC output voltage Note 2 IOUT DC output source or sink current VO = 0 to VCC IGND, ICC Tstg PTOT DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K RATING UNIT –0.5 to +6.5 V –50 mA –0.5 to +5.5 V –0.5 to VCC +0.5 V "50 mA –0.5 to VCC +0.5 V "50 mA "100 mA –60 to +150 °C 500 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1997 Mar 18 3 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LVC86 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C TYP1 MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 MAX V VCC = 1.2V GND VCC = 2.7 to 3.6V HIGH level output voltage 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*1.0 VCC LOW level output voltage 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND 0.20 VCC = 3.0V; VI = VIH or VIL; IO = 24mA II V 0.55 Input leakage current 6V; VI = 5 5V or GND VCC = 3 3.6V; 5.5V IIHZ/IILZ Input current for common I/O pins VCC = 3.6V; VI = VCC or GND IOZ 3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND ICC Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 ∆ICC V V VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL UNIT Not for I/O pins "0 1 "0.1 "5 µA "0.1 "15 µA 0.1 "10 µA 0.1 20 µA 5 500 µA NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC CHARACTERISTICS GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500; Tamb = –40C to +85C LIMITS SYMBOL PARAMETER tPHL/ tPLH Propagation delay nA, nB to nY VCC = 3.3V ±0.3V WAVEFORM Figures 1, 2 VCC = 2.7V VCC = 1.2V MIN TYP1 MAX MIN TYP1 MAX TYP 1.5 4.0 6.5 1.5 4.5 7.0 20 UNIT ns NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25°C. AC WAVEFORMS TEST CIRCUIT VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. S1 VCC VI nA, nB INPUT VM PULSE GENERATOR GND t PHL VI 2 < VCC Open GND 500Ω VO D.U.T. t PLH RT 50pF CL 500Ω VOH nY OUTPUT VM Test VOL SV00477 Figure 1. Input (nA, nB) to output (nY) propagation delays S1 VCC VI tPLH/tPHL Open t 2.7V VCC tPLZ/tPZL 2 < VCC 2.7V – 3.6V 2.7V tPHZ/tPZH GND SY00003 Figure 2. Load circuitry for switching times. 1997 Mar 18 4 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LVC86 DIP14: plastic dual in-line package; 14 leads (300 mil) 1997 Mar 18 5 SOT27-1 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LVC86 SO14: plastic small outline package; 14 leads; body width 3.9 mm 1997 Mar 18 6 SOT108-1 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LVC86 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm 1997 Mar 18 7 SOT337-1 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LVC86 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm 1997 Mar 18 8 SOT402-1 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LVC86 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1997 Mar 18 9