78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
DATA SHEET
JULY 2005
DESCRIPTION
FEATURES
•
The 78P2344JAT is a low-power, 4-port
DS3/E3/STS1 Line Interface Unit (LIU) with
integrated Jitter Attenuator (JAT). It includes all the
required clock recovery and transmitter pulse
shaping functions for applications using 75-ohm
coaxial cable at distances up to 1350 feet. These
applications include DSLAMs, T1,3/E1,3 digital
multiplexers, SONET Add/Drop multiplexers, PDH
equipment, DS3 to Fiber optic and microwave
modems and ATM WAN access for routers and
switches.
•
•
•
•
•
•
•
The receiver recovers clock and data from a B3ZS
or HDB3 coded AMI signal. It can compensate for
over 12dB of cable and 6dB of flat loss. The
transmitter generates a signal that meets the
standard pulse shape requirements.
The
78P2344JAT includes optional B3ZS/HDB3 ENDEC
with a receive line code violation detector, loop-back
modes, Loss of Signal detector, clock polarity
selection, and the ability to receive a DSX3 monitor
signal.
•
•
•
•
•
STANDARDS
•
•
•
•
•
•
Telcordia GR-499-CORE and GR-253-CORE
ITU-T G.823, G.824, G.775, and G.703
ETSI TBR-24, ETS 300 686, ETS 300 687, and
ETS EN 300 689
ANSI T1.102-1993, T1.231-1997, T1.404-1994,
and T1.105.03b
Transmit and receive interfaces for E3, DS3 and
STS-1 applications
Designed for use with 75 ohm coaxial cable
lengths up to 1350 ft
Receives DS3-high and DSX3 monitor signals
Local and Remote loopbacks
Selectable B3ZS/HDB3 ENDEC with line code
violation detector
Standards-based LOS detector
Optional serial-port based mode selection and
channel status monitoring
Adaptive digital clock recovery (uses line-rate
reference clock input)
Receive output clock maintains nominal line-rate
frequency at all times
Fully integrated Jitter Attenuation function
provided for all line rates (no external VCXO
required)
Jitter Attenuator configurable for transmit or
receive path
Transmit line fault monitor
Requires no external current-setting resistor or
loop filter components
Single 3.3V supply operation
Available in 100-pin Exposed Pad JEDEC LQFP
BLOCK DIAGRAM
Controls
Flags
LBO E3 DS3
RLBK
Transmit
Monitor
TXEN
TPOS
B3ZS /
HDB3
Encoder
TNEG
TCLK
RNEG
RCLK
LOUTP
Pulse
Shaper
Jitter
Attenuator
RPOS
TXNW
LOUTN
Attenuator
ENDEC
B3ZS /
HDB3
Decoder
Data
Detector
AGC
Adaptive
Equalizer
LINP
LINN
MON
TCLKP
RCLKP
Power
Distribution
Signal
Detector
Clock
Recovery
LOS
LLBKA
LLBKB
PDTX PDRX
CKREF
Signals from
Adjacent Port
Each Channel
CS
SCK
SDI
Control
Registers
Master
Bias
Generator
CKREF
SDO
Page 1 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
FUNCTIONAL DESCRIPTION
The 78P2344JAT contains all the necessary
transmit and receive circuitry for connection
between E3, DS3, or STS-1 line interfaces and
digital Framer/Mapper ICs.
The jitter tolerance of 78P2344JAT meets the
requirements of ITU-T G.823 for E3 rates; the
requirements of ITU-T G.824 and Telcordia GR-499
(Cat I and II) for DS3 rates; and the requirements of
Telcordia GR-253 for STS1 rates.
OPERATING RATE
With the Jitter Attenuator disabled, the jitter transfer
function meets the requirements of GR-499 for
Category II DS3 interfaces.
The Master Control Register (MSCR) determines
which mode the device operates in according to the
table below. The MSL0 pin is also provided for
mode selection in applications without a serial
control interface. Upon power-up or reset, the state
of the MSL0 pin is sensed and mapped into the DS3
and E3 register bits representing the appropriate
mode of operation. After power-up/reset, the state of
the MSL0 pin is ignored.
Standard
E3
DS3
STS-1
STS-1
MSL0 pin
DS3 bit
E3 bit
L
H
Z
Z
0
1
0
1
1
0
0
1
RECEIVER OPERATION
RECEIVER MONITOR MODE
When in monitor mode, 20dB of flat gain is applied
to the incoming signal before it is fed to the receive
equalizer. This mode is controlled by the MON bit in
the Mode Control Register.
SIGNAL DETECT
The receiver input is either transformer-coupled or
capacitor-coupled to the line signal. In applications
where the highest performance and isolation are
required, a 1:1 transformer is used in the receive
path. In applications where isolation is provided
elsewhere in the circuit, capacitor coupling can be
used. The receiver input should be line terminated
externally with a termination resistor.
The AMI signal first enters an AGC, which has a
selectable gain range setting. In normal operation,
the AGC can compensate for signals with up to 6dB
of flat loss. When Receiver Monitor Mode is
enabled, the AGC can compensate for a DSX3
monitor signal with 16 to 20 dB of flat loss. The
signal then enters a high performance adaptive
equalizer. The equalizer is designed to overcome
inter-symbol interference caused by long cable
lengths. Because the equalizer is adaptive, the
circuit will work with all square-shaped signals such
as DS3-high or 34.368 Mbit/s E3. The variable gain
differential amplifier automatically controls the gain
to maintain a constant voltage level output
regardless of the input voltage level.
Page 2 of 37
When the Jitter Attenuator is enabled, the
78P2344JAT meets the requirements of GR-499
and GR-253 for all categories of DS3/STS1
equipment and the ETSI TBR-24 requirements for
E3 rates.
To check conformance with other
standards,
please
refer
to
the
JITTER
ATTENUATOR TRANSFER FUNCTION section for
more detailed info.
When the received signal is below a minimum
threshold, the corresponding LOS signal (bit) is
asserted. A time delay is provided before this output
is active so that transient interruptions do not cause
false indications. The LOS signal can also be used
to trigger an interrupt on the INTRx pin when serial
interface control is not available. This is controlled
by setting the RXER bit in the Interrupt Control
Register (INTC).
Note: In DS3 or STS-1 mode, when LBO is not
enabled, the transmitters have to be properly
terminated to ensure reliable LOS detection. If a
transmitter is not terminated, the resultant 2x signal
is large enough to couple to the neighboring
receivers through the ESD diodes, causing false
Signal Detect indication.
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
LOCAL LOOPBACK AND REDUNDANCY MUX
Each receiver has a 4-input MUX as shown in the
adjacent figure. In multiport applications where
redundant channels are required, the receiver MUX
can be configured to provide the necessary
multiplexing functions. This allows the user to use
one port as a redundant monitor for the other port.
The tables below show the register settings for
selecting the desired receiver input source.
LLBKA
(Port 1)
LLBKB
(Port 1)
0
0
1
1
0
1
0
1
Receiver #1 Input
Source
Transmitter
#1
LOUTP1, LOUTN1
00
01
10
LINP1, LINN1
11
LLBKA,B(1)
Transmitter
#2
LOUTP2, LOUTN2
00
01
LINP2, LINN2
LINP1/LINN1
LOUTP1/LOUTN1
LINP2/LINN2
LOUTP2/LOUTN2
10
11
LLBKB
(Port 2)
0
0
1
1
0
1
0
1
Receiver #2 Input
Source
Transmitter
#3
00
LINP3, LINN3
01
10
11
LINP2/LINN2
LOUTP2/LOUTN2
LINP1/LINN1
LOUTP1/LOUTN1
LLBKB
(Port 3)
0
0
1
1
0
1
0
1
LLBKA
(Port 4)
LLBKB
(Port 4)
0
0
1
1
0
1
0
1
Receiver #3 Input
Source
LINP3/LINN3
LOUTP3/LOUTN3
LINP4/LINN4
LOUTP4/LOUTN4
Receiver #4 Input
Source
LINP4/LINN4
LOUTP4/LOUTN4
LINP3/LINN3
LOUTP3/LOUTN3
Note: The LLBKA and LLBKB bits are located in the
Mode Control Register (MDCR).
The Register
Control bit, REGEN, should be enabled when using
the register settings to avoid conflict with external
loopback setting pins.
Page 3 of 37
Receiver
#3
LLBKA,B(3)
Transmitter
#4
LOUTP4, LOUTN4
LLBKA
(Port 3)
Receiver
#2
LLBKA,B(2)
LOUTP3, LOUTN3
LLBKA
(Port 2)
Receiver
#1
00
LINP4, LINN4
01
10
11
Receiver
#4
LLBKA,B(4)
When serial interface control is not available, the
respective LPBKx pin for each of the channels can
also be used to activate local loopback mode as
shown below. Note that redundant channel modes
can only be activated using the serial interface.
LPBKx
pin
L
Z
H
Loopback Mode
Normal Operation
Same as LLBKA,B = ‘00’
Remote (Digital) Loopback
Same as RLBK = ‘1’
Local (Analog) Loopback
Same as LLBKA,B = ‘01’
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
B3ZS/HDB3 ENDEC WITH LINE CODE VIOLATION
DETECT
The 78P2344JAT includes a selectable B3ZS/HDB3
Encoder/Decoder (ENDEC). The ENDEC function
can be enabled or disabled through pin selection or
register setting as shown below.
ENDECB
bit/pin
RPOSx
RNEGx
0/L
NRZ data
Receive Line Code
Violation Indicator
1/H
Positive AMI
Negative AMI
When the ENDEC is enabled, the decoder
generates a composite NRZ logic data stream
following the B3ZS (for DS3/STS-1) or HDB3 (for E3)
substitution codes via the RPOSx pins:
The decoder also detects Receive Line Code
Violations (RLCV) and outputs a pulse via the
RNEG pin. Three different classes of line code
violations are detected.
1) Too many zeros:
More than two (three)
consecutive zeros in B3ZS (HDB3) mode.
2) Not enough zeros between bipolar pulse (B)
and bipolar violation pulse (V): (B,V) for B3ZS.
(B,V) or (B,0,V) for HDB3.
3) Code violation: Even number of bipolar pulses
(B) detected between bipolar violation pulses
(V).
When the ENDEC is disabled, the 78P2344JAT
outputs a dual rail data stream via the RPOSx and
RNEGx pins. In this mode, the Framer/Mapper
providing the ENDEC function typically detects Line
Code Violations.
On the transmit side, when the ENDEC is enabled,
NRZ input data is encoded to Positive and Negative
AMI logic data following the B3ZS (for DS3/STS-1)
or HDB3 (for E3) substitution codes. The NRZ data
is input to the TPOS pin as shown below:
ENDECB
bit/pin
TPOSx
TNEGx
0/L
NRZ data
‘Don’t Care’
1/H
Positive AMI
Negative AMI
TRANSMITTER OPERATION
Transmitters 1-4 are enabled by their corresponding
TXEN bit. When enabled, each transmitter accepts
logic level clock and data signals and generates
current pulses on the LOUTPx and LOUTNx pins.
When properly connected to a 1:2CT center-tapped
transformer, a standards compliant AMI pulse is
generated which can drive a 75Ω coaxial cable.
When the recommended transformer is used and
when DS3 mode is selected, the transmitted pulse
shape at the end of the 75Ω terminated cable of 0 to
450 feet will fit the DS3 template found in ANSI
T1.102-1993 and Telcordia GR-499-CORE. For
STS-1 applications, the transmitted pulse for a short
cable meets the requirements of Telcordia GR-253CORE. For E3 applications, the transmitted pulse
for a short cable meets the requirements of ITU-T
G.703.
In either DS3 and STS-1 modes, the LBOx pin or
LBO bit should be set high for short cable (< 225 ft),
and should be set low for long cable (> 225 ft). The
LBO settings are ignored in E3 mode.
RCLK/TCLK POLARITY REVERSAL
To simplify the interface with various framer circuitry,
TCLK polarity can be internally inverted by setting
the TCLKP bit, and RCLK polarity can be inverted
by setting the RCLKP bit. Both bits are located in
the Master Control Register (MSCR).
REMOTE (DIGITAL) LOOPBACK
When the Register Control bit, REGEN, is disabled
and the LPBKx pin is floating; or when the Register
Control bit, REGEN, is enabled and the RLBK bit is
set, RCLKx, RNEGx, and RPOSx outputs are
internally looped back to the TCLKx, TNEGx, and
TPOSx inputs respectively.
Page 4 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
LINE BUILD-OUT
The Line Build-Out (LBO) function controls the
transmit amplitude and pulse shape in DS3 and
STS-1 modes. The selection of LBO depends on
the amount of cable the transmitter is connected to.
When less than 225 ft of cable is used, the
corresponding LBOx pin or LBO bit should be high.
When 225ft or more cable is used the corresponding
LBO setting (LBOx pin or LBO bit) should be low.
LBO can be controlled either from pins or from
register settings, depending on the status of the
Register Control bit, REGEN.
The Jitter Attenuator can be configured
independently for each channel by writing to the
Jitter Attenuator Control Register (JACR) as follows:
JAEN
bit
JASL
bit
0
X
Jitter Attenuator disabled
1
0
Jitter Attenuator configured
to be in the receive path
1
1
Jitter Attenuator configured
to be in the transmit path
Jitter Attenuator Mode
TRANSMIT ENABLE
The TXEN bit in the Mode Control Register controls
the transmitter output.
When logic zero, the
transmitter output is disabled. This feature is used to
disable ports as well as to multiplex two or more
transceivers to one port. The transmitter of any port
can also be disabled by floating the respective LBOx
pin, in which case it will also power-down the entire
transmitter.
See section on the Power-Down
Function for more info.
TRANSMIT MONITOR
The transmit monitor function detects activity on the
transmitter output at the LOUTPx and LOUTNx pins.
When there is a transmitter fault, in the case of an
open or short on the chip, the transformer, or the
circuit board, the transmit signal amplitude will be
altered. The transmit monitor detects the amplitude
of the driven signal. The TXNW signal (bit) goes
high when the amplitude of the transmit signal is
outside a valid amplitude range. When the signal
amplitude is either too high or too low for longer than
a specified duration, the TXNW bit goes high (See
Transmit Monitor Specifications, pg.28). The TXNW
signal can be also used to trigger an interrupt on the
INTRx pin when serial interface control is not
available.
MSL1 pin
Jitter Attenuation function is provided on-chip. The
Jitter Attenuator can be configured to be in the
transmit or the receive path. When configured in the
transmit path, the input clock at TCLK pin is passed
through a very low bandwidth digital PLL. The
corresponding transmit data is buffered into a FIFO
and clocked out using the de-jittered output clock of
the PLL. When configured in the receive path, the
recovered clock is passed through the low
bandwidth digital PLL, and the corresponding
receive data is buffered into the FIFO and clocked
out using the de-jittered clock.
Jitter Attenuator Mode
L
Jitter Attenuator in receive path
H
Jitter Attenuator in transmit path
Z
Jitter Attenuator disabled
PLL Bandwidth
A PLL response with effectively one pole below 27
Hz is adequate to meet the ETSI TBR24 E3
standards. A PLL response with one pole below 40
Hz is adequate to meet the GR-499 (Cat I) DS3
standards. One of two bandwidths can be selected
via register settings.
The PLL bandwidth is
proportional to the data rate as follows:
Line Rate
JITTER ATTENUATOR
Page 5 of 37
When serial interface control is not available, the
MSL1 pin is provided for global Jitter Attenuator
mode selection. Upon power-up or reset, the state
of the MSL1 pin is sensed and mapped into the
JAEN and JASL register bits for all channels,
representing the appropriate mode of operation.
After power-up or reset, the state of the MSL1 pin is
ignored. The state of the MSL1 pin, and the
corresponding Jitter Attenuator configuration is
shown below.
JABW bit
PLL Bandwidth (Hz)
0
*13
1
188
0
*17
1
245
0
20
1
*283
E3
DS3
STS1
* The default state of the JABW bit depends on
which line-rate is selected through the MSL0 pin. If
E3 or DS3 mode is selected, the default state is ‘0’.
If STS1 mode is selected, the default state is ‘1’.
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
Elastic Store Depth
SERIAL CONTROL INTERFACE
To optimize the trade-off between data latency and
clock wander tolerance, the FIFO elastic store depth
can be selected through the serial port by writing to
the Jitter Attenuator Control Register (JACR) as
follows:
The serial port controlled register allows a generic
controller to interface with the 78P2344JAT. It is
used for mode settings, diagnostics and test, and
the retrieval of status and performance information.
ESP[1:0]
bits
Elastic Store Depth
00
Pass-Through mode
01
16 UI
10
32 UI
11
64 UI (default)
The Elastic Store Depth selects the nominal FIFO
read pointer address. The total or maximum elastic
store depth is set to be twice as deep as the nominal
pointer address. The circular buffer length is always
twice as long as the nominal pointer address.
POWER-DOWN FUNCTION
Power-down control is provided to allow the
transceivers to be shut off individually. Transmit and
receive power-down can be set independently via
the PDTX and PDRX bits in the Mode Control
Register. Floating the respective LBOx pin can also
set PDTX for each channel. The Serial Control
Interface and Configuration Registers are not
affected by power-down.
INTERNAL POWER-ON RESET
The 78P2344JAT includes on-chip Power-On Reset
(POR) function to ensure the serial-port registers are
initialized to known default states upon power-up.
Roughly 50us after Vcc reaches 2.4V at power up,
reset is released. This reset signal also sets all state
machines within the LIU to nominal operational
states. The internal reset signal is also brought out
to the PORB pin. This pin is a multi-function pin that
allows for the following:
1) Override the internal POR signal by driving in an
external active-low reset signal;
2) Monitor the state of the internal POR signal (for
test and debug only);
3) Add external capacitor to delay the release of
the internal power-on reset signal to allow the
MSL0 pin to stabilize prior to release of reset
(approximately 8µs per nF added).
The internal resistance of the PORB pin is
approximately 5kΩ.
Page 6 of 37
The serial interface consists of four pins: Chip Select
(CS), Serial Clock (SCK), Serial Data In (SDI), and
Serial Data Out (SDO). The CS pin initiates the
read and write operations. It can also be used to
select a particular device allowing SCK, SDI and
SDO to be bussed together. SCK is the clock input
that times the data on SDI and SDO. Data on SDI is
latched in on the rising-edge of SCK, and data on
SDO is clocked out using the falling edge of SCK.
SDI is used to insert mode, address, and register
data into the chip. Address and Data information
are input least significant bit (LSB) first.
SDO is a tristate capable output. It is used to output
register data during a read operation. SDO output is
normally high impedance, and is enabled only
during the duration when register data is being
clocked out.
Read data is clocked out least
significant bit (LSB) first.
If SDI coming out of the micro-controller chip is also
tristate capable, SDI and SDO can be connected
together to simplify connections.
The maximum clock frequency for register access is
20MHz.
Note: To allow equipment to power up in a known
state, some register defaults are set by their
corresponding pin control at power-up.
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION
REGISTER ADDRESSING
Address Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Port Address
Assignment
PA[3]
PA[2]
Bit 1
Bit 0
Read/
Write
Sub-Address
PA[1]
PA[0]
SA[2]
SA[1]
SA[0]
R/W*
REGISTER TABLE
a) PA[3:0] = 0 : Global Registers
Sub
Addr
0
1
Reg.
Name
MSCR
(R/W)
INTC
(R/W)
Description
Master Control
Interrupt Control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
REGEN
<0>
INPOL
<0>
DS3
<X>
E3
<X>
ENDECB
<0>
RCLKP
<0>
--
--
--
--
TCLKP
<0>
JAER
<0>
RXER
<1>
SRST
<0>
TXER
<1>
--
Bit 0
2
RSVD
Reserved
--
--
--
--
--
--
--
--
3
RSVD
Reserved
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
4
RSVD
Reserved
--
--
--
--
--
--
--
--
5
RSVD
Reserved
--
--
--
--
--
--
--
--
6
RSVD
Reserved
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
7
RSVD
Reserved
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
b) PA[3:0] = 1-4 : Port-Specific Registers
Sub
Addr
0
1
Reg.
Name
MDCR
(R/W)
STAT
(R/O)
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mode Control
PDTX
<0>
LLBKA
<0>
--
RLBK
<0>
MON
<0>
TXEN
<1>
FERR
LBO
<1>
--
LLBKB
<0>
Status Monitor
PDRX
<0>
--
LOS
TXNW
--
SGLO
2
RSVD
Reserved
<1>
<1>
<0>
<1>
<0>
<1>
<0>
<0>
3
JACR
(R/W)
Jitter Attenuator
Control
JAEN
<X>
JASL
<X>
JLBK
<0>
<0>
ESP[1]
<1>
ESP[0]
<1>
<0>
JABW
<X>
4
RSVD
Reserved
--
--
--
--
--
--
--
--
5
RSVD
Reserved
<0>
--
--
<0>
<0>
<0>
<0>
<0>
6
RSVD
Reserved
--
--
--
--
--
--
--
--
7
RSVD
Reserved
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
Note: Shaded registers in Register Table are reserved for Teridian internal use only. Accessing reserved or
undefined registers may cause undesirable operation.
Page 7 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
LEGEND
TYPE
R/O
DESCRIPTION
TYPE
Read only
R/W
DESCRIPTION
Read or Write
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
BIT
7
NAME
REGEN
TYPE
R/W
DFLT
VALUE
0
6
DS3
R/W
X
5
E3
R/W
X
4
3
ENDECB
RCLKP
R/W
R/W
DESCRIPTION
Register Control Enable:
0 : Pin selection overrides register settings
1 : Device is controlled via register set.
NOTE: Pin 15 (ENDECB) must be tied low when REGEN is enabled.
Line Speed Selection:
Selects the line speed of all channels as well as the input clock frequency
at the CKREF pin.
[DS3 E3] = 00 : STS-1 (51.840MHz)
01 : E3 (34.368MHz)
10 : DS3 (44.736MHz)
11 : STS-1 (51.840MHz)
NOTE: The default values of these register bits depend on the state of
the MSL0 pin upon power-up or reset.
0
Encoder/Decoder Disable:
0 : selects NRZ digital data interface
1 : selects AMI digital data interface
NOTE: Relevant only when the REGEN bit is set. Otherwise, ENDECB
pin selection prevails.
0
RCLK Polarity Selection:
0 : Receive Data clocked out on the falling-edge of RCLK
1 : Receive Data clocked out on the rising-edge of RCLK
2
TCLKP
R/W
0
TCLK Polarity Selection:
0 : Transmit Data clocked in on the rising-edge of TCLK
1 : Transmit Data clocked in on the falling-edge of TCLK
1
RSVD
R/O
--
Reserved
0
Register Soft-Reset:
When this bit is set, all registers are reset to their default values. Also
resets Jitter Attenuator to “centered” states. This register bit is selfclearing.
0
SRST
Page 8 of 37
R/W
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS 0-1: INTERRUPT CONTROL REGISTER
This register selects the events that would cause the respective interrupt pin (INTRx) for each of the ports to be
activated. User may set as many bits as required.
BIT
NAME
TYPE
DFLT
VALUE
7
INPOL
R/W
0
Interrupt Pin Polarity Selection:
0 : Interrupt output is active-low
1 : Interrupt output is active-high
6:3
RSVD
R/O
--
Reserved
2
JAER
R/W
0
Jitter Attenuator Error Event:
When set, JAT FIFO overflow or underflow (as indicated by the FERR bit)
will cause an interrupt to be flagged.
1
RXER
R/W
1
Receiver Error Event:
When set, loss of receive signal (as indicated by the LOS bit) will cause
an interrupt to be flagged.
0
TXER
R/W
1
Transmitter Error Event:
When set, transmitter fault (as indicated by the TXNW bit) will cause an
interrupt to be flagged.
Page 9 of 37
DESCRIPTION
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
PORT-SPECIFIC REGISTERS
For PA[3:0] = N = 1-4 only. Accessing a register with port address greater than 4 constitutes an invalid
command, and the read/write operation will be ignored.
ADDRESS N-0: MODE CONTROL REGISTER
BIT
7
6
NAME
PDTX
PDRX
TYPE
R/W
R/W
DFLT
VALUE
DESCRIPTION
0
Transmitter Power-Down:
0 : Normal Operation
1 : Power-Down
NOTE: Relevant only when the REGEN bit is set. Otherwise, LBOx pin
selection prevails.
0
Receiver Power-Down:
0 : Normal Operation
1 : Power-Down
Transmitter Line Build-Out (DS3 and STS-1 only):
5
LBO
R/W
1
4
LLBKA
R/W
0
3
LLBKB
R/W
0
2
1
0
RLBK
MON
TXEN
Page 10 of 37
R/W
R/W
R/W
0 : ≥ 225ft of cable attached to the cross-connect
1 : < 225ft of cable attached to the cross-connect
NOTE: Relevant only when the REGEN bit is set. Otherwise, LBOx pin
selection prevails.
Local (Analog) Loopback Mode Selection:
[LLBKA : LLBKB] = 00 : Normal operation
01 : Local (Analog) Loopback
10 : Adjacent receiver input (see page 3)
11 : Adjacent transmitter loopback (see page 3)
NOTE: Relevant only when the REGEN bit is set. Otherwise, LPBKx pin
selection prevails.
0
Remote (Digital) Loopback Enable:
0 : Normal Operation
1 : Loops RCLK, RPOS, and RNEG back onto TCLK, TPOS, and TNEG
NOTE: Relevant only when the REGEN bit is set. Otherwise, LPBKx pin
selection prevails.
0
Monitor Mode Enable:
Used for reception of split-off signals that are flat attenuated by at least
16dB but no more than 20dB.
0 : Disable
1 : Enable
1
Transmitter Output Enable:
0 : Transmit driver is disabled. Output is tri-stated.
1 : Normal Operation
NOTE: Relevant only when the REGEN bit is set. Otherwise, LBOx pin
selection prevails.
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS N-1: STATUS MONITOR REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7
FERR
R/O
X
Jitter Attenuator FIFO Error Flag:
This bit is set whenever a FIFO overflow or underflow occurred. It is
reset after a read operation to this register.
0 : Proper Operation
1 : FIFO Overflow/Underflow
6:4
RSVD
R/O
X
Reserved
X
Loss-of-Signal Indication:
0 : Signal Detector detecting a valid receive input signal
1 : Standards-based Loss-of-Signal indication
NOTE: RPOSx and RNEGx are forced low when LOS=’1’. RCLK will
continue to output a line rate clock
3
LOS
R/O
2
TXNW
R/O
X
Transmitter Not-Working Indication:
0 : Transmitter OK
1 : Transmitter not working
1
RSVD
R/O
X
Reserved
0
SGLO
R/O
X
Signal Low Indication:
0 : Receive signal level OK
1 : Receive signal level too low / Loss of signal
Page 11 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS N-3: JITTER ATTENUATOR CONTROL REGISTER
BIT
7
6
5
NAME
JAEN
JASL
JLBK
TYPE
R/W
R/W
R/W
DFLT
VALUE
DESCRIPTION
X
Jitter Attenuator Enable:
0 : Disables jitter attenuation function
1 : Enables jitter attenuation function
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset.
X
Jitter Attenuation Selection:
0 : Jitter Attenuator on the receive path
1 : Jitter Attenuator on the transmit path
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset.
0
Jitter Attenuator Local Loopback Enable:
0 : Normal Operation
1 : TCLKx, TPOSx, TNEGx connected to JAT input and
RCLKx, RPOSx, RNEGx connected to JAT output
NOTE: If both RLBK and JLBK bits are set, RLBK mode takes priority.
4
RSVD
R/W
0
Reserved. Must be set to zero.
3:2
ESP
[1:0]
R/W
11
FIFO Elastic Store Pointer Selection:
ESP[1:0] = 00 : Pass-through
01 : 8 UI
10 : 16 UI
11 : 32 UI (default)
1
RSVD
R/W
0
Reserved. Must be set to zero.
X
Jitter Attenuator Bandwidth Selection:
0 : Low bandwidth
1 : High bandwidth
(see JAT Bandwidth Selection Table on page 5)
NOTE: The default values of these register bits depend on the state of
the MSL0 pin upon power-up or reset. If the state of the MSL0 pin
selects E3 or DS3 mode, the default value of JABW is ‘0’. If the state of
the MSL0 pin selects STS1 mode, the default value of JABW is ‘1’.
0
JABW
Page 12 of 37
R/W
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION
LEGEND
TYPE
DESCRIPTION
TYPE
DESCRIPTION
A
Analog Pin
CIT
CMOS 3-State Input
CI
CMOS Digital Input
CO
CMOS Digital Output
CIU
CMOS Digital Input w/ Pull-up
COZ
CMOS Tristate Digital Output
CID
CMOS Digital Input w/ Pull-down
S
Supply
CIS
CMOS Schmitt Trigger Input
G
Ground
TRANSMITTER PINS
NAME
PIN
TYPE
DESCRIPTION
Transmit Positive Data/Transmit NRZ:
23, 31
TPOSx
39, 47
CI
When ENDECB =’1’, a logic one on this pin generates a positive AMI
pulse on the coax. This pin should not be high at the same time that
corresponding TNEGx is high.
When ENDECB =’0’, data on this pin is encoded and converted into
positive and negative AMI pulses.
Transmit Negative Data:
24, 32
TNEGx
40, 48
CI
When ENDECB =’1’, a logic one on this pin generates a negative AMI
pulse on the coax. This pin should not be high at the same time that
corresponding TPOSx is high.
When ENDECB =’0’, this pin is ignored.
25, 33
TCLKx
41, 49
Transmitter Clock Input:
CIS
This signal is used to latch the respective TPOSx and TNEGx signals
into the 78P2344JAT.
98, 92
LOUTPx
Line Out:
85, 79
A
LOUTNx
99, 93
Differential AMI Outputs. Requires a 1:2CT center-tapped
transformer and a shunt termination resistor. See APPLICATION
INFORMATION section for more info.
86, 80
Page 13 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION (continued)
RECEIVER PINS
NAME
PIN
TYPE
DESCRIPTION
Reference Clock Input:
CKREF
57
CIS
This clock should be from a clean source (± 20 ppm) and match the
selected line-rate frequency as follows:
E3 : 34.368 MHz
DS3: 44.736 MHz
STS-1: 51.840 MHz
Receive Clock:
27, 35
RCLKx
43, 51
CO
Recovered receive clock output.
NOTE: During LOS conditions, RCLKx will continue to output a line
rate clock
Receive Negative Data:
28, 36
RNEGx
44, 52
CO
When ENDECB =’1’, this pin indicates reception of a negative AMI pulse
on the coax.
When ENDECB =’0’, this pin outputs a one when a Receive Line
Code Violation (RLCV) is detected.
NOTE: During LOS conditions, RNEGx output is squelched
Receive Positive Data/NRZ Data:
29, 37
RPOSx
45, 53
CO
When ENDECB =’1’, this pin indicates reception of a positive AMI
pulse on the coax cable.
When ENDECB =’0’, it outputs decoded NRZ data.
NOTE: During LOS conditions, RPOSx output is squelched
96, 90
LINPx
Line In:
83, 77
A
LINNx
Page 14 of 37
95, 89
Differential AMI Inputs. Should be 1:1 transformer-coupled and
terminated with a shunt resistor. See APPLICATION INFORMATION
section for more info.
82, 76
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION (continued)
CONTROL AND STATUS PINS
NAME
MSL0
MSL1
PIN
19
20
TYPE
DESCRIPTION
CIT
Data-Rate Mode Selection:
Low = E3 mode
High = DS3 mode
Float = STS-1 mode
NOTE: Pin state is latched-in on rising-edge of PORB signal. Pin
state is ignored after reset.
CIT
Jitter Attenuator Mode Selection:
Low = JAT in Receive path
High = JAT in Transmit path
Float = JAT is bypassed
NOTE: Pin state is latched-in on rising-edge of PORB signal. Pin
state is ignored after reset.
Chip Reset (active-low):
PORB
14
A
Forces hardware reset on device. See description on Internal Poweron Reset for complete use of this pin.
ENDEC Enable (active-low):
ENDECB
15
CID
Set high to disable internal ENDEC function. See description on
B3ZS/HDB3 ENDEC with Line Code Violation Detect for complete
use of this pin.
NOTE: Relevant only when the REGEN bit is ‘0’. Pin must be held
low when the REGEN bit is set.
5, 6
LBOx
7, 8
10, 11
LPBKx
12, 13
64, 63
INTRx
Page 15 of 37
62, 61
CIT
Line Build-Out:
Low = Used with 225ft or more of cable.
High = Used with less than 225ft of cable.
Float = Disable and power down transmitter. [TXEN=0; PDTX=1]
NOTE: LBO control relevant only when the REGEN bit is ‘0’. Pin
state sampled approximately once every 0.5ms.
CIT
Loopback Enable:
Low = Normal Operation
High = Local Loopback. Transmitter looped back to Receiver
Float = Remote Loopback. Receiver looped back to Transmitter
NOTE: Relevant only when the REGEN bit is ‘0’. Pin state sampled
approximately once every 0.5ms.
CO
Interrupt Flag:
This pin is normally high when the INPOL bit is ‘0’ (default), and
normally low when the INPOL bit is ‘1’. When an interrupt event
occurs (as defined in the Interrupt Control Register description), the
respective INTRx pin will change state.
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION (continued)
SERIAL-PORT PINS
NAME
PIN
TYPE
DESCRIPTION
Chip Select:
CS
65
CI
SCK
66
CIS
High during write and read operations. Low disables the serial port.
While CS is low, SDO remains in high impedance state, and SDI and
SCK activities are ignored.
Serial Clock:
Controls the timing of SDI and SDO.
Serial Data Input:
Inputs mode and address information. Also inputs register data during
a Write operation. Both address and data are input least significant bit
first.
SDI
68
CI
SDO
67
COZ
Serial Data Output:
Outputs register information during a Read operation. Data is output
least significant bit first.
POWER AND GROUND PINS
It is recommended that all supply pins be connected to a single power supply plane and all ground pins be
connected to a single ground plane.
NAME
PINS
TYPE
VCC
1, 2, 3, 4, 17, 59,
72, 73, 74, 75
S
Analog Power Supply
GND
18, 60, 78, 81, 84,
87, 91, 94, 97, 100
S
Analog Ground
VCCD
16, 22, 30, 38, 46,
54, 55, 58
S
Digital Power Supply
GNDD
9, 21, 26, 34, 42,
50, 56, 69
S
Digital Ground
Page 16 of 37
DESCRIPTION
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation beyond these limits may permanently damage the device.
PARAMETER
RATING
Supply Voltage (VCC/VCCD)
-0.5 to 4.0 VDC
Storage Temperature
-65 to 150 °C
Junction Temperature
-40 to 125 °C
Pin Voltage (LOUTPx, LOUTNx)
VCC + 1.5 VDC
Pin Voltage (all other pins)
-0.3 to (VCC+0.6) VDC
Pin Current
±100 mA
RECOMMENDED OPERATING CONDITIONS
Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges.
PARAMETER
RATING
DC Voltage Supply (VCC/VCCD)
3.0 to 3.6 V
Ambient Operating Temperature
-40 to 85°C
DC CHARACTERISTICS:
PARAMETER
Supply Current
All channels enabled; LBO=0
Receive-only Supply Current
All channels PDTX = 1
SYMBOL
JAT Enabled:
JAT Disabled:
DS3/E3 mode
Iddr
JAT Enabled:
JAT Disabled:
DS3/E3 mode
Iddt
Supply Current per Port
JAT Enabled:
JAT Disabled:
DS3/E3 mode
(including transmitter current
through transformer)
Iddx
Power-Down Current
Iddq
Page 17 of 37
MIN
DS3/E3 mode
Idd
Transmit-only Supply Current
All channels PDRX = 1;
LBO=0
CONDITIONS
JAT Enabled:
JAT Disabled:
PDTX = 1, PDRX = 1
2005 Teridian Semiconductor Corporation
NOM
MAX
UNIT
350
330
380
355
mA
155
130
170
142
mA
260
225
mA
82
76
mA
11
15
mA
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
ANALOG PINS CHARACTERISTICS:
The following table is provided for informative purpose only. Not tested in production.
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
Ground reference
1.9
2.25
2.6
V
LINPx and LINNx
Common-Mode Bias Voltage
Vblin
LINPx and LINNx Differential
Input Impedance
Rilin
10
kΩ
PORB Input Impedance
Ripor
5
kΩ
DIGITAL I/O CHARACTERISTICS:
Pins of type CI, CIU, CID:
PARAMETER
SYMBOL
CONDITIONS
MIN
Input Voltage Low
Vil
Input Voltage High
Vih
2.0
Input Current
Iil, Iih
-1
Pull-up Resistance
Rpu
Type CIU only
32
Pull-down Resistance
Rpd
Type CID only
32
Input Capacitance
Cin
NOM
MAX
UNIT
0.8
V
V
1
µA
56
84
kΩ
56
84
kΩ
8
pF
Pins of type CIS:
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
Low-to-High Threshold
Vt+
1.3
1.7
V
High-to-Low Threshold
Vt-
0.8
1.2
V
Iil, Iih
-1
1
µA
Input Current
Input Capacitance
Page 18 of 37
Cin
2005 Teridian Semiconductor Corporation
8
pF
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
Pins of type CIT:
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
0.8
V
Input Voltage Low
Vtil
Input Voltage High
Vtih
2.0
V
Minimum impedance to be
considered as “float” state
Rtiz
30
kΩ
Pins of type CO and COZ:
PARAMETER
SYMBOL
CONDITIONS
Output Voltage Low
Vol
Iol = 8mA
Output Voltage High
Voh
Ioh = -8mA
Output Transition Time
Tt
MIN
NOM
MAX
UNIT
0.4
V
2.4
V
CL = 20pF; (20-80%)
6
ns
Pin Capacitance
Cout
8
pF
Effective Source Impedance
Rsrc
30
Ω
Tristate Output Leakage
Current
Page 19 of 37
Iz
Type COZ only
-1
2005 Teridian Semiconductor Corporation
1
µA
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
SERIAL-PORT TIMING CHARACTERISTICS:
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
CS or SDI to SCK setup time
tsu
4
ns
CS or SDI to SCK hold time
th
4
ns
SCK to SDO propagation
delay
tprop
5
SCK Frequency
SCK
SEN
12
ns
20
MHz
tsu
th
SCK
tsu th
SDI
X
1
SA0
tprop
SA1
SDO
SA2
PA0
PA1
PA2
PA3
X or Z
Z
D0
D1
D2
D3
D4
D5
D6
D7
Z
Read Operation
SEN
tsu
th
SCK
tsu th
SDI
X
0
SDO
SA0
SA1
SA2
PA0
PA1
PA2
PA3
D0
D1
D2
D3
D4
D5
D6
D7
X
Z
Write Operation
Page 20 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
TRANSMIT TIMING CHARACTERISTICS:
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
Clock Duty Cycle
TTC/TTCF
40
60
%
Setup Time
TTDxS
2.5
ns
Hold Time
TTDxH
2.5
ns
TIMING DIAGRAM: Transmitter Waveforms (E3/DS3/STS-1)
TTCF
TTC
TCLK
TCLKP=LOW
TCLK
TCLKP=HIGH
TTDPH
TTDPS
TPOS
TTDNH
TTDNS
TNEG
Page 21 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
RECEIVE TIMING CHARACTERISTICS:
PARAMETER
SYMBOL
MAX
UNIT
40
60
%
-20
+20
ppm
TRC/TRCF
40
60
%
TPROP
-0.3
3
ns
CKREF Duty Cycle
--
CKREF Frequency Stability
--
RCLK Duty Cycle
Data Propagation Delay
Receive Loss of Signal
Assert Timing
Receive Loss of Signal
De-assert Timing
Note 1:
--
--
CONDITIONS
w.r.t. line-rate
frequency
MIN
NOM
E3 mode
10
140
255
UI
DS3 mode
100
150
250
UI
STS1 mode
2.3
3
100
µS
E3 mode
10
130
255
UI
DS3 mode
100
130
250
UI
STS1 mode, see
Note 1
2.3
3
250
µS
At least a 100µS of software delay must be added after STS-1 LOS de-assertion to be compliant with
the ANSI T1.231 requirement of 100 to 250µS.
TIMING DIAGRAM: Receive Waveforms (E3/DS3/STS-1)
RECEIVE LINE
INPUT (REF)
(LINP,LINN)
TRCF
TRC
RCLK
RCLKP=LOW
RCLK
RCLKP=HIGH
TPROP
RPOS
TPROP
RNEG
Page 22 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
E3 – TRANSMITTER SPECIFICATIONS
PARAMETER
CONDITION (see timing diagram)
MIN
TYP
MAX
UNIT
Transmitter Amplitude
Measured at 0ft of terminated
75ohm cable
900
1000
1100
mVpk
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive and
negative pulses measured at pulse
centers
0.95
1.05
Transmitter Pulsewidth Mismatch
Ratio of widths of positive and
negative pulses measured at pulse
half amplitude
0.95
1.05
Transmitter Pulsewidth
Measured at 0ft of terminated
75ohm cable
12.1
14.8
17
ns
DS3 – TRANSMITTER SPECIFICATIONS
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Transmitter Amplitude
Measured at 0ft of terminated
75ohm cable with LBO pin held
high (enabled).
700
800
850
mVpk
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive
and negative pulses measured at
pulse peaks.
0.9
1.1
Transmitter Power
at 22.368 MHz
All ones pattern, 3kHz bandwidth
-1.8
+5.7
dBm
-20
dBm
Harmonic Power
at 44.736 MHz
All ones pattern
Power below fundamental at
22.368MHz
STS-1 – TRANSMITTER SPECIFICATIONS
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Transmitter Amplitude
Measured at 0ft of terminated
75ohm cable with LBO pin held
high (enabled).
700
825
950
mVpk
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive and
negative pulses measured at pulse
peaks.
0.9
1.1
Transmitter Power
PRBS15 pattern band-limited to
207.36MHz.
-2.7
+4.7
Page 23 of 37
2005 Teridian Semiconductor Corporation
dBm
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
E3 TRANSMIT PULSE TEMPLATE
17 ns
0.2
0.1
1.0
8.65 ns
0.1
0.2
14.55 ns
0.5
12.1 ns
24.5 ns
0.1
0.1
0
0.1
0.1
0.2
29.1 ns
Page 24 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
DS3 TRANSMIT PULSE TEMPLATE
1.2
1
Normalized Amplitude
0.8
0.6
0.4
0.2
0
-0.2
-1
-0.5
0
0.5
1
1.5
Time, Unit Intervals
Time axis range (UI)
Normalized amplitude equation
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.36
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
0.36 < T < 1.4
0.08+0.407 e-1.84(T-0.36)
LOWER CURVE
-0.85 < T < -0.36
-0.03
-0.36 < T < 0.36
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
0.36 < T < 1.4
-0.03
Page 25 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
STS-1 TRANSMIT PULSE TEMPLATE
1.2
1
Normalized Amplitude
0.8
0.6
0.4
0.2
0
-0.2
-1
-0.5
0
0.5
1
1.5
Time, Unit Intervals
STS-1 (Transmit template specs)
Time axis range (T)
Normalized amplitude equation (A)
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.26
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
0.26 < T < 1.4
0.1+0.61 e-2.4(T-0.26)
LOWER CURVE
-0.85 < T < -0.38
-0.03
-0.38 < T < 0.36
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
0.36 < T < 1.4
-0.03
Page 26 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
TRANSMITTER OUTPUT JITTER
The transmit jitter specification ensures compliance with ITU-T G.823 and G.824, Telcordia GR-499 CORE(I)
and GR-253-CORE, and ANSI T1.102-1993 for all supported rates. Transmit output jitter is guaranteed only if a
clean SONET quality transmit clock source is used.
Jitter
Detector
Measured Jitter
Amplitude
20dB/decade
Transmitter
Output
f1
PARAMETER
Transmitter Output Jitter
CONDITION
f2
MIN
NOM
MAX
UNIT
10 Hz to 800 kHz
0.15
UIpp
10 kHz to 800 kHz
0.08
UIpp
Note: Filters defined by standards are used for all testing
Page 27 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
TRANSMIT MONITOR SPECIFICATIONS
The transmit monitor function looks at the signals on the LOUTPx and LOUTNx pins and checks for the
existence of a valid signal. The monitor detects the peak of the transmitted signal at the LOUTPx and LOUTNx
pins and checks that it is between VUNDER and VOVER at all times. If the peak level is within the voltage threshold
window, the TXNW signal is low. If the peak level falls outside of the threshold limits for more than
approximately 25 bit times, the TXNW signal goes high.
VTPOS - VTNEG
VOVER
VPEAK
VUNDER
Time
PARAMETER
VUNDER
VOVER
Page 28 of 37
CONDITION
MIN
TYP
MAX
UNIT
DS3/STS-1 mode with LBOx=1
450
mVpk
E3 mode;
DS3/STS-1 mode with LBOx=0
550
mVpk
DS3/STS-1 mode with LBOx=1
1050
mVpk
E3 mode;
DS3/STS-1 mode with LBOx=0
1480
mVpk
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
DS3/STS-1 -- RECEIVER SPECIFICATIONS (Transformer-coupled)
PARAMETER
Peak Differential Input
Amplitude, LINPx and LINNx
(see Note 1)
Flat-loss Tolerance
Receive Clock Jitter
Interfering Tone Tolerance
(see Note 5)
CONDITION
MIN
MON=0;
Signal at DSX is 360-850 mVpk.
(see Note 2)
MON=1
(see Note 3)
MON=0; DS3-HIGH
(see Note 4)
MON=0.
All valid cable lengths.
DS3 mode with 10 Hz – 400 kHz
a) Normal receive mode
b) Remote loopback mode
Maximum ratio of Interference Power
to Signal Power for BER < 10-8
a) With 0ft cable from DSX
b) With 450ft cable from DSX
TYP
MAX
UNIT
90
850
mVpk
25
80
mVpk
90
1200
mVpk
0
6
dB
0.1
0.06
UIpp
UIpp
-9
-10
dB
dB
Note 1:
Signal source should meet DS3 template of ANSI-T102.1993 Figure 4 and STS-1 template of ANSIT102.1993 Figure 5. Loss characteristics of the WE728A or RG59B cable should be better than Figure
C2 of ANSI-T102.1993.
Note 2:
Min spec corresponds to minimum DSX amplitude, 5.5dB of cable loss (450ft) and 6dB of flat
attenuation. Error-free receiver performance is guaranteed for up to 600ft of cable from DSX crossconnect. Typical part can handle up to 900ft.
Note 3:
Min spec corresponds to amplitude of 425mVpk at DSX, 5.5dB of cable loss (450ft) and 20dB of flat
attenuation. In monitor mode, interfering tone performance is not guaranteed.
Note 4:
In this mode, no noise, jitter, or interfering tone impairments should be added for guaranteed receiver
performance.
Note 5:
Interfering signal is a non-synchronous sinusoidal tone of 22.368MHz for DS3 or 25.92MHz for STS-1.
15
Data is a PRBS15 (2 -1) pattern.
Page 29 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
E3 – RECEIVER SPECIFICATIONS (Transformer-coupled)
PARAMETER
CONDITION
MON=0
(See Note 1)
Peak Differential Input
Amplitude, LINPx and LINNx MON=1
(See Note 2)
Flat-loss Tolerance
Receive Clock Jitter
Interfering Tone Tolerance
(see Note 3)
MON=0.
All valid cable lengths.
With 100Hz-800kHz filter:
a) Normal receive mode
b) Remote loopback mode
Maximum ratio of Interference Power
to Signal Power for BER < 10-8
a) With 0ft cable
b) With 900ft cable
MIN
TYP
MAX
UNIT
120
1200
mVpk
25
100
mVpk
0
6
dB
0.1
0.06
UIpp
UIpp
-9
-10
dB
dB
Note 1:
Min spec corresponds to signal amplitude of 950mVpk at source, 12dB of cable loss (1100ft) and 6dB
of flat attenuation. Error-free receiver performance is guaranteed for all cable less than 1100ft. Typical
part can handle up to 1350ft.
Note 2:
Min spec corresponds to signal amplitude of 1000mVpk at source, 12dB of cable loss (1100ft) and
20dB of flat attenuation. In monitor mode, interfering tone performance is not guaranteed.
Note 3:
Interfering signal is a non-synchronous E3 signal of the specified power level below the desired E3
23
signal. Both data and interfering signals are PRBS23 (2 -1) pattern.
Page 30 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER JITTER TOLERANCE
The 78P2344JAT receive jitter tolerance exceeds all specifications as shown on the graph below.
PARAMETER
CONDITION
MIN
Receiver High Frequency Jitter
Tolerance
> 60 kHz
0.75
NOM
MAX
UNIT
UIpp
Jitter Tolerance: 78P234x vs. Standards
Jitter Tolerance (UIp-p)
10
4
10
3
10
2
10
1
10
10
10
JAT enabled
0
-1
-2
10
Page 31 of 37
78P234x
GR-499- CORE(I) [DS3]
GR-499- CORE(II) [DS3]
GR-253- CORE(II) [STS1]
ITU-T G.823 [E3]
ITU-T G.824 [DS3]
1
10
2
10
3
4
10
10
Jitter Frequency (Hz)
5
2005 Teridian Semiconductor Corporation
10
6
10
7
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER JITTER TRANSFER FUNCTION
The receiver clock recovery loop characteristics are such that the receiver has the following transfer function.
When the Jitter Attenuator (JAT) is enabled in the receive or transmit path, the receiver or transmitter will
exhibit a jitter transfer as shown in the graph and table below. Jitter Attenuator operation is guaranteed through
digital scan testing. The actual jitter transfer is guaranteed by logic design and is not tested during production
testing.
PARAMETER
CONDITION
Receiver Jitter transfer function
Below Fc
At –3dB point
JABW= 0, E3 mode (default)
JABW= 1, E3 mode
Receiver Jitter Bandwidth, Fc
Jitter transfer function roll-off
10
MIN
0.1
17
245
JABW= 0, STS1 mode
JABW= 1, STS1 mode (default)
20
283
JAEN= 0, JAT disabled
55
After Fc
dB
Hz
kHz
dB per
decade
20
40kHz
59.6kHz
1kHz
9
49
3)
DS
I(
tI
)
Ca
S1
99
ST
-4
I(
tI
GR
Ca
53
-2
GR
GR
53
-2
GR
3)
DS
)
S3
(D
I(
tI
Ca
t
Ca
-10
UNIT
13
188
27Hz
0
MAX
JABW= 0, DS3 mode (default)
JABW= 1, DS3 mode
40Hz
Jitter Transfer (dB)
NOM
ETSI TBR 24 (E3)
-20
E3 JAT
STS1 JAT
JAT Disabled
-30
DS3 JAT
-40
-50
10
100
1k
10k
100k
1M
Jitter Frequency
Page 32 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
APPLICATION INFORMATION
EXTERNAL COMPONENTS:
COMPONENT
PIN(S)
LINPx
LINNx
LOUTPx
LOUTNx
Receiver Termination Resistor
Transmitter Termination Resistor
VALUE
UNITS
TOLERANCE
84.5
Ω
1%
402
Ω
1%
VALUE
UNITS
TOLERANCE
TRANSFORMER SPECIFICATIONS:
COMPONENT
Turns Ratio for the Receiver
1:1
Turns Ratio for the Transmitter (center-tapped)
1:2CT
Suggested Manufacturer: Pulse, Tamura, Halo
THERMAL INFORMATION
PACKAGE
CONDITIONS
Standard 100-pin JEDEC LQFP (78P2344JAT-IGT)
No forced air;
4-layer JEDEC test board
Θja ( ûC/W)
46
No forced air;
Exposed Pad 100-pin JEDEC LQFP (78P2344JAT-IEL)
4-layer JEDEC test board;
24.8
Die attach pad soldered to PCB
SCHEMATICS
For schematics, recommended transformer part numbers, etc. please check Teridian Semiconductor's website or
contact your local sales representative for the latest application note(s) and/or demo board manuals.
Page 33 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
MECHANICAL SPECIFICATIONS
(Top View)
15.7 (0.618)
16.3 (0.641)
+
15.7 (0.618)
16.3 (0.641)
PIN No. 1
Indicator
13.8 (0.543) SQ
14.2 (0.559)
0.60 (0.024) TYP.
0.18( 0.007)
0.27 (0.011)
0.50 TYP.
(0.0197)
1.40 (0.055)
1.60 (0.063)
0.00(0)
0.20 (0.008)
78P2344JAT-IGT Mechanical Specification
100-pin TQFP (JEDEC LQFP)
Page 34 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
MECHANICAL SPECIFICATIONS
(Bottom View)
16.000 +/- 0.200
14.000 +/- 0.100
12.000 REF.
100
16.000 +/- 0.200
10.000 MAX.
14.000 +/- 0.100
1
MAX. EXPOSED
PAD AREA
10.000 MAX.
13.950 +/- 0.100
MAX. 1.600
1.400 +/- 0.050
0.220 +/- 0.050
0.500
0.100 +/- 0.050
0.600 +/- 0.150
78P2344JAT-IEL Mechanical Specification
100-pin Exposed Pad LQFP (JEDEC LQFP)
Page 35 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
PACKAGE INFORMATION
Pin-Out
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
GND
LOUTN1
LOUTP1
GND
LINP1
LINN1
GND
LOUTN2
LOUTP2
GND
LINP2
LINN2
N/C
GND
LOUTN3
LOUTP3
GND
LINP3
LINN3
GND
LOUTN4
LOUTP4
GND
LINP4
LINN4
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
78P2344JAT
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VCC
VCC
VCC
VCC
N/C
N/C
GNDD
SDI
SDO
SCK
CS
INTR1
INTR2
INTR3
INTR4
GND
VCC
VCCD
CKREF
GNDD
VCCD
VCCD
RPOS4
RNEG4
RCLK4
GNDD
RCLK1
RNEG1
RPOS1
VCCD
TPOS2
TNEG2
TCLK2
GNDD
RCLK2
RNEG2
RPOS2
VCCD
TPOS3
TNEG3
TCLK3
GNDD
RCLK3
RNEG3
RPOS3
VCCD
TPOS4
TNEG4
TCLK4
GNDD
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
VCC
VCC
VCC
LBO1
LBO2
LBO3
LBO4
GNDD
LPBK1
LPBK2
LPBK3
LPBK4
PORB
ENDECB
VCCD
VCC
GND
MSL0
MSL1
GNDD
VCCD
TPOS1
TNEG1
TCLK1
100-pin TQFP (JEDEC LQFP)
ORDERING INFORMATION
PART DESCRIPTION
ORDER NUMBER
PACKAGE MARK
78P2344JAT-IGT
xxxxxxxxxxP7
100-pin JEDEC LQFP
78P2344JAT-IGT /A07
100-pin JEDEC LQFP,
No Jitter Attenuator
78P2344-IGT /A07
78P2344JAT-IGT
xxxxxxxxxxP7
100-pin JEDEC LQFP w/ Exposed Solder Pad
78P2344JAT-IEL /A07
78P2344JAT-IEL
xxxxxxxxxxP7
100-pin JEDEC LQFP w/ Exposed Solder Pad,
No Jitter Attenuator
78P2344-IEL /A07
78P2344JAT-IEL
xxxxxxxxxxP7
Tape & Reel option
Lead-free option
Page 36 of 37
append ‘R’
append ‘/F’
2005 Teridian Semiconductor Corporation
n/a
78Pxxxxxxx-xxx
xxxxxxxxxxP7F
Rev 2.2
78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REVISION HISTORY
Revision Date:
February 9, 2004
Revision Description:
Final Datasheet Release (Revision.2.1)
•
Contact Teridian Semiconductor for list of changes from earlier datasheet revisions
Revision 2.2 Changes
July 29, 2005
•
Changed company name and logo from TDK to Teridian
•
Changed Package Marking for non-JAT 78P2344 ordering option
This product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to
warranty, patent infringement and limitation of liability. Teridian Semiconductor Corporation (TSC) reserves the right to make changes in
specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders.
TSC assumes no liability for applications assistance.
Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridiansemiconductor.com
Page 37 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2