PCMCIA Flash Memory Card FLG Series PCMCIA Flash Memory Card 256KILOBYTE through 5 MEGABYTE (Intel based) General Description Features WEDC’s FLG Series Flash memory cards offer low/medium density linear Flash solid state storage solutions for code and data storage, high performance disk emulation and execute in • Low cost Low/Medium Density Linear Flash Card • Supports 5V systems with 12V VPP. place (XIP) applications in mobile PC and dedicated (embedded) equipment. • Based on Intel CMOS Components FLG series cards conform to PCMCIA international standard. • Fast Read Performance - 150ns Maximum Access Time The card’s control logic provides the system interface and controls the internal Flash memories. Card can be read/written in byte-wide or word-wide mode which allows for flexible integration into various systems. Combined with • x8/ x16 Data Interface • Quick-Pulse Programming Algorithm - typical 10µs Byte-Program file management software, such as Flash Translation Layer (FTL), FLG Flash cards provide removable high-performance disk emulation. • 100,000 Erase/Program Cycles • PC Card Standard Type I Form Factor The FLG series cards contain separate 2kB EEPROM memory for Card Information Structure (CIS) which can be used for easy identification of card characteristics. The WEDC FLG series is based on Intel 28F010 or 28F020 Flash memories. Note: Standard options include attribute memory. Cards without attribute memory are available. Cards are also available with or without a hardware write protect switch. Architecture Overview WEDC’s FLG series is designed to support from 2 to 20, 1Mb or 2MB components, providing a wide range of density options. Cards are based on the 28F010 (1Mb) or 28F020 components which work with 5V Vcc / 12V Vpp applications. Device codes are B4h and BDh respectively. Systems should be able to recognize both codes. Cards utilizing the1Mb components provide densities ranging from 256KB to 2.5MB in 256KB increments, cards utilizing 2Mb components provide densities ranging from 512KB to 5MB in 512KB increments. In support of the PC Card 95 standard for word wide access devices are paired. Write, read and erase operations can be performed as either a word or byte wide operation . By multiplexing A0, CE1# and CE2#, 8-bit hosts can access all data on data lines DQ0 - DQ7. The FLG series cards conform to the PC Card Standard (PCMCIA) and JEIDA, providing electrical and physical compatibility. The PC Card form factor offers an industry standard pinout and mechanical outline, allowing density upgrades without system design changes. WEDC’s standard cards are shipped with WEDC’s Logo. Cards are also available with blank housings (no Logo). The blank housings are available in both a recessed (for label) and flat housing. Please contact WEDC sales representative for further information on Custom artwork. August 2000 Rev. 3 - ECO #13132 1 PC Card Products PCMCIA Flash Memory Card FLG Series Block Diagram Vcc Vpp2 Vpp1 Device Pair 9 Device 19 Device 18 CSH9 CSL9 Array Address Bus A1-A17(18) ADDRESS BUFFER ADDRESS BUS A1-A21(22) Control Address Bus Vcc CSH9 CSH0 Device Pair 1 CSL9 Device 2 Device 3 CSL0 CSH1 CSL1 C9 High C0 Control Logic PCMCIA Interface C9 Low C0 Ctrl Att enable WE# OE# CE2# CE1# REG# A0 WP Device Pair 0 Device 1 Device 0 CSH0 Vcc Attrib. Mem CIS EEPROM 2kB CSL0 WR# DATA BUS Q8-Q15 RD# DATA BUS Q0-Q7 Q0-Q7 control I/O buffer Vcc DATA BUS D8-D15 DATA BUS D0-D7 SUPPORTED COMPONENTS (max 20 X): 28F010 - max 2.5MB 28F020 - max 5MB Device type Manuf ID Device ID CD1# CD2# GND 28F010 89H B4H 28F020 89H BDH WAIT# BVD1 Vcc BVD2 Vcc VS1 open VS2 open August 2000 Rev. 3 - ECO #13132 2 PC Card Products PCMCIA Flash Memory Card FLG Series Pinout Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal name GND DQ3 DQ4 DQ5 DQ6 DQ7 CE1# A10 OE# A11 A9 A8 A13 A14 WE# RDY/BSY# Vcc Vpp1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 WP GND I/O Function Ground Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 Card enable 1 Address bit 10 Output enable Address bit 11 Address bit 9 Address bit 8 Address bit 13 Address bit 14 Write Enable Ready/Busy Supply Voltage Prog. Voltage Address bit 16 Address bit 15 Address bit 12 Address bit 7 Address bit 6 Address bit 5 Address bit 4 Address bit 3 Address bit 2 Address bit 1 Address bit 0 Data bit 0 Data bit 1 Data bit 2 Write Potect Ground I/O I/O I/O I/O I/O I I I I I I I I I O I I I I I I I I I I I I/O I/O I/O O Active Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 LOW LOW LOW N.C. HIGH Signal name GND CD1# DQ11 DQ12 DQ13 DQ14 DQ15 CE2# VS1 RFU RFU A17 A18 A19 A20 A21 Vcc Vpp2 A22 A23 A24 A25 VS2 RST Wait# RFU REG# BVD2 BVD1 DQ8 DQ9 DQ10 CD2# GND I/O O I/O I/O I/O I/O I I O I I I I I I I I I O I O I O O I/O I/O O O Function Ground Card Detect 1 Data bit 11 Data bit 12 Data bit 13 Data bit 14 Data bit 15 Card Enable 2 Voltage Sense 1 Reserved Reserved Address bit 17 Address bit 18 Address bit 19 Address bit 20 Address bit 21 Supply Voltage Prog. Voltage Address bit 22 Address bit 23 Address bit 24 Address bit 25 Voltage Sense 2 Card Reset Extended Bus cycle Reserved Attrib Mem Select Bat. Volt. Detect 2 Bat. Volt. Detect 1 Data bit 8 Data bit 9 Data bit 10 Card Detect 2 Ground Active LOW LOW N.C. 256KB(2) 512KB(2) 1MB(2) 2MB(2) 4MB(2,3) 8MB(2,3) N.C. N.C. N.C. N.C. N.C. LOW(1) (1) (1) LOW Notes: 1. Wait#, BVD1 and BVD2 are driven high for compatibility 2. Shows density for which specified address bit is MSB. Higher order address bits are no connects (i.e. 4MB A21 is MSB A22 - A25 are NC). 3. For the 3MB card the memory will wrap at the 4MB boundary, for the 5MB card the memory will wrap at the 8MB boundary. Mechanical Interconnect area 1.0mm ± 0.05 (0.039”) 1.6mm ± 0.05 (0.063”) 3.0mm MIN 10.0mm MIN (0.400”) Substrate area 85.6mm ± 0.20 (3.370”) 1.0mm ± 0.05 (0.039”) 10.0mm MIN (0.400”) August 2000 Rev. 3 - ECO #13132 54.0mm ± 0.10 (2.126”) 3.3mm ± T1 (0.130”) T1=0.10mm interconnect area T1=0.20mm substrate area 3 PC Card Products PCMCIA Flash Memory Card FLG Series Card Signal Description Symbol Type A0 - A25 INPUT DQ0 - DQ15 INPUT/OUTPUT CE1#, CE2# INPUT OE# INPUT WE# RDY/BSY# INPUT N.C. CD1#, CD2# OUTPUT WP OUTPUT VPP1 VPP2 VCC GND REG# INPUT RST N.C. WAIT# OUTPUT BVD1, BVD2 OUTPUT VS1, VS2 OUTPUT Name and Function ADDRESS INPUTS: A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is not used in word access mode. The memory will wrap at the card density boundary (see PINOUT, note 3). The system should not try to access memory beyond the card density. A25 is the most significant bit. A23 – A25 are not connected. DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the bidirectional databus. DQ0 – DQ7 constitute the lower (even) byte and DQ8 – DQ15 the upper (odd) byte. DQ15 is the MSB. CARD ENABLE 1 AND 2: CE1# enables even byte accesses, CE2# enables odd byte accesses. Multiplexing A0, CE1# and CE2# allows 8-bit hosts to access all data on DQ0 - DQ7. OUTPUT ENABLE: Active low signal gating read data from the memory card. WRITE ENABLE: Active low signal gating write data to the memory card. READY/BUSY OUTPUT: Indicates status of internally timed erase or program algorithms. This signal is not connected. CARD DETECT 1 and 2: Provide card insertion detection. These signals are internally connected to ground on the card. The host shall monitor these signals to detect card insertion (pulled-up on host side). WRITE PROTECT: Write protect reflects the status of the Write Protect switch on the memory card. WP set to high = write protected, providing internal hardware write lockout to the Flash array. If card does not include optional write protect switch, this signal will be pulled low internally indicating write protect = "off". PROGRAM/ERASE POWER SUPPLY: Provides programming voltages 12.0V for lower byte (D0 – D7) memory components. PROGRAM/ERASE POWER SUPPLY: Provides programming voltages 12.0V for upper byte (D8 – D15) memory components. CARD POWER SUPPLY: (5.0V). CARD GROUND ATTRIBUTE MEMORY SELECT : Active low signal, enables access to Attribute Memory Plane, occupied by Card Information Structure and Card Registers. RESET: Active high signal for placing cards in Power-on default state. This signal is not connected. WAIT: This signal is pulled high internally for compatibility. No wait states are generated. BATTERY VOLTAGE DETECT: These signals are pulled high to maintain SRAM card compatibility. VOLTAGE SENSE: Notifies the host socket of the card's VCC requirements. VS1 and VS2 are open to indicate a 5V card. RESERVED FOR FUTURE USE NO INTERNAL CONNECTION TO CARD: pin may be driven or left floating RFU N.C. Functional Truth Table READ function Function Mode Standby Mode Byte Access (8 bits) Word Access (16 bits) Odd-Byte Only Access WRITE function* Standby Mode Byte Access (8 bits) Word Access (16 bits) Odd-Byte Only Access /CE2 /CE1 H H H L H L L L L H H H H L L H L L L H A0 X L H X X /OE X L L L L /WE X H H H H X L H X X X H H H H X L L L L Common Memory Attribute Memory /REG D15-D8 D7-D0 High-Z High-Z X High-Z Even-Byte H High-Z Odd-Byte H Odd-Byte Even-Byte H High-Z Odd-Byte H /REG D15-D8 D7-D0 High-Z High-Z X High-Z Even-Byte L High-Z Not Valid L L Not Valid Even-Byte High-Z L Not Valid X H H H H X X X Even-Byte X Odd-Byte Odd-Byte Even-Byte Odd-Byte X X L L L L X X X X X X Even-Byte X Even-Byte X * Require proper programming voltages (Vpp1, Vpp2). Program or Erase with an invalid Vpp should not be attempted. August 2000 Rev. 3 - ECO #13132 4 PC Card Products PCMCIA Flash Memory Card FLG Series Absolute Maximum Ratings (1) Operating Temperature TA (ambient) Commercial Industrial Storage Temperature Commercial Industrial Voltage on any pin relative to VSS VCC supply Voltage relative to VSS Note: (1) Stress greater than those listed under “Absolute Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 0°C to +60 °C -40°C to +85 °C -30°C to +80 °C -40°C to +85 °C -0.5V to VCC+0.5V -0.5V to +7.0V DC Characteristics (1) Symbol Parameter Density ICCR VCC Read Current All ICCW VCC Program Current All IPPW VPP Program Current All ICCE VCC Erase Current All IPPE VPP Erase Current Notes (3) Typ Max Units Test Conditions 10 30 mA 1.0 10 mA 8.0 30 mA 5.0 15 mA 10 30 mA VCC = VCCmax tcycle = 150ns,CMOS levels Programming in Progress Vpp = 12V Vpp=VppH Programming in Progress Erasure in Progress Vpp = 12V ICCS VCC Standby Current (CMOS) All 256KB 512KB 1MB 2MB 3MB 4MB 5MB 100 Vpp=VppH Erasure in Progress VCC = VCCmax Control Signals = VCC CMOS levels µA CMOS Test Conditions: VCC = 5V ± 5%, VIL = VSS ± 0.2V, VIH = VCC ± 0.2V Notes: 1. All currents are RMS values unless otherwise specified. ICCR, ICCW and ICCE are based on Byte wide operations. For 16 bit operation values are double. 2. Control Signals: CE1#, CE2#, OE#, WE#, REG#. 3. Typical: VCC = 5V, T = +25ºC. Symbol Parameter Notes Min Max Units Test Conditions ILI Input Leakage Current 1 ±1.0 µA VCC = VCCMAX Vin =VCC or VSS VCC = VCCMAX Vout =VCC or VSS ILO Output Leakage Current 1 ±10 µA V IL Input Low Voltage 1 0 0.8 V V IH Input High Voltage 1 0.7VCC VCC+0.5 V V OL Output Low Voltage 1 0.4 V IOL = 3.2mA V OH Output High Voltage 1 VCC-0.4 VCC V IOH = -2.0mA V LKO VCC Erase/Program Lock Voltage 1 2.5 V Notes: 1. Values are the same for byte and word wide modes for all card densities. 2. Exceptions: Leakage currents on CE1#, CE2#, OE#, REG# and WE# will be < 500 µA when VIN = GND due to internal pull-up resistors. August 2000 Rev. 3 - ECO #13132 5 PC Card Products PCMCIA Flash Memory Card FLG Series AC Characteristics Read Timing Parameters 150ns 200ns SYMBOL (PCMCIA) tC(R) Parameter Min Max Min Max Unit Read Cycle Time 150 ta(A) Address Access Time 150 200 ns ta(CE) Card Enable Access Time 150 200 ns ta(OE) Output Enable Access Time 75 100 ns tsu(A) Address Setup Time 20 20 ns tsu(CE) Card Enable Setup Time 0 0 ns th(A) Address Hold Time 20 20 ns th(CE) Card Enable Hold Time 20 20 ns tv(A) 0 0 ns tdis(CE) Output Hold from Address Change Output Disable Time from CE# 60 60 ns tdis(OE) Output Disable Time from OE# 60 60 ns ten(CE) Output Enable Time from CE# 5 5 ns ten(OE) Output Enable Time from OE# 5 5 ns 200 ns Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications. Read Timing Diagram tc(R ) ta (A ) th (A ) A [2 5::0], /R E G tv(A ) ta(C E ) tsu(C E ) /C E 1, /C E 2 NOTE 1 NOTE 1 tsu(A ) ta(O E ) th(C E ) tdis(C E ) /O E tdis(O E ) ten(O E ) D [1 5::0] D A TA V A LID Note: Signal may be high or low in this area. August 2000 Rev. 3 - ECO #13132 6 PC Card Products PCMCIA Flash Memory Card FLG Series Write Timing Parameters SYMBOL (PCMCIA) 150ns Parameter Min Max 200ns Min Max Unit tCW Write Cycle Time 150 200 ns tw(WE) Write Pulse Width 80 120 ns tsu(A) Address Setup Time 20 20 ns tsu(A-WEH) tsu(CEWEH) tsu(D-WEH) Address Setup Time for WE# 100 100 ns Card Enable Setup Time for WE# 100 100 ns Data Setup Time for WE# 50 50 ns th(D) Data Hold Time 20 20 ns trec(WE) Write Recover Time 20 20 ns tdis(WE) Output Disable Time from WE# 60 60 ns tdis(OE) Output Disable Time from OE# 60 60 ns ten(WE) Output Enable Time from WE# 5 5 ns ten(OE) Output Enable Time from OE# 5 5 ns tsu(OE-WE) Output Enable Setup from WE# 10 10 ns th(OE-WE) Output Enable Hold from WE# 10 10 ns tsu(CE) Card Enable Setup Time from OE# 0 0 ns th(CE) Card Enable Hold Time 20 20 ns Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications. Write Timing Diagram tc (W ) A [ 2 5 :: 0 ], / R E G ts u ( A - W E H ) tre c (W E ) ts u ( C E - W E H ) th (C E ) ts u (C E ) /C E 1 , /C E 2 NOTE 1 NO TE 1 /O E tw (W E ) ts u ( A ) th (O E -W E ) /W E th ( D ) ts u (O E -W E ) D [ 1 5 : :0 ] ( D in ) ts u (D -W E H ) NO TE 2 D A T A IN P U T t d is ( W E ) t d is ( O E ) te n (O E ) te n (W E ) D [ 1 5 ::0 ] ( D o u t ) NO TE 2 Notes: 1. Signal may be high or low in this area. 2. When the data I/O pins are in the output state, no signals shall be applied to the data pins (D15 - D0) by the host system. August 2000 Rev. 3 - ECO #13132 7 PC Card Products PCMCIA Flash Memory Card FLG Series Data Write and Erase Performance VCC = 5V ± 5%, Vpp1 = Vpp2=12.0V, TA = 25ºC Parameter Chip Program Time Chip Erase Time Notes 28F010 1,2,4 28F020 1,2,4 28F010 1,3,4 28F020 1,3,4 Min Typ(1) 2 4 1 2 Max 12.5 25 10 30 Units sec sec Notes: 1. Typical: Nominal voltages and TA = 25ºC. 2. Minimum byte programming time excluding system overhead is 16 µs (10µs program + 6µs write recovery), while maximum is 400µs/byte (16 µs x 25 loops allowed by algorithm). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. 3. Excludes 00H Programming prior to Erasure. 4. Excludes System-Level Overhead. August 2000 Rev. 3 - ECO #13132 8 PC Card Products PCMCIA Flash Memory Card FLG Series CIS Information for FLG Series Cards Address 00H 02H 04H 12H 14H 16H 18H 1AH 1CH 1EH 20H 22H 24H 26H 28H 2AH Value 01H 03H 53H 52H 0CH 05H 0DH 06H 2DH 0EH 4DH FFH 18H 02H 89H B4H BDH 17H 03H 42H 01H FFH 1EH 06H 02H 11H 01H 01H 01H 01H 2CH 2EH 30H 32H 34H 36H 38H 3AH 3CH 3EH 40H 42H 44H 20H 04H F6H 01H 00H 00H 15H 47H 05H 00H 45H 44H 49H 46H 48H 37H 50H 06H 08H 0AH 0CH 0EH 10H Description CISTPL_DEVICE TPL_LINK FLASH = 150ns (device writable) FLASH = 200ns (device writable) CARD SIZE: 256KB 512KB 1MB 2MB 3MB 4MB 5MB END OF DEVICE CISTPL_JEDEC_C TPL_LINK INTEL - ID INTEL 28F010 - ID INTEL 28F020 - ID CISTPL_DEVICE_A TPL_LINK EEPROM - 200ns Device Size = 2KBytes END OF TUPLE CISTPL_DEVICEGEO TPL_LINK DGTPL_BUS DGTPL_EBS DGTPL_RBS DGTPL_WBS DGTPL_PART FLASH DEVICE NON-INTERLEAVED CISTPL_MANFID TPL_LINK(04H) TPLMID_MANF: LSB EDI TPLMID_MANF: MSB EDI LSB: Number Not Assigned MSB: Number Not Assigned August 2000 Rev. 3 - ECO #13132 Address 4AH 4CH 4EH Value 32H 35H 36H 31H 32H 30H 30H Description 2 5 6 5 1 2 0 0 31H 30H 30H 32H 30H 30H 33H 30H 30H 34H 30H 30H 35H 1 0 0 2 0 0 3 0 0 4 0 0 5 46H 4CH 47H 30H 32H 30H 36H 2DH 2DH 2DH 31H 35H 20H 00H 43H 4FH 50H 59H 52H 49H 47H 48H 54H F L G 0 2 0 6 1 5 SPACE END TEXT C O P Y R I G H T 35H 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H CISTPL_VERS1 TPL_LINK TPLLV1_MAJOR TPLLV1_MINOR E D I 7 P 9 PC Card Products PCMCIA Flash Memory Card FLG Series CIS Information for FLG Series Cards -(Cont.) Address 7AH 7CH 7EH 80H 82H 84H 86H 88H 8AH 8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 9EH A0H A2H A4H A6H A8H AAH ACH AEH B0H B2H B4H B6H B8H BAH BCH BEH C0H C2H C4H C6H C8H CAH DCH Value 20H 45H 4CH 45H 43H 54H 52H 4FH 4EH 49H 43H 20H 44H 45H 53H 49H 47H 4EH 53H 20H 49H 4EH 43H 4FH 52H 50H 4FH 52H 41H 54H 45H 44H 20H 00H 31H 39H 39H 37H 00H FFH FFH 00H August 2000 Rev. 3 - ECO #13132 Description SPACE E L E C T R O N I C SPACE D E S I G N S SPACE I N C O R P O R A T E D SPACE END TEXT 1 9 9 7 END TEXT END OF LIST CISTPL_END INVALID ADDRESS 10 PC Card Products PCMCIA Flash Memory Card FLG Series PRODUCT MARKING WED 7P001FLG0200C15 C995 9915 EDI Date code Lot code / trace number Part number Company Name Note: Some products are currently marked with our pre-merger company name/acronym (EDI). During our transition period, some products will also be marked with our new company name/acronym (WED). Starting October 2000 all PCMCIA products will be marked only with the WED prefix. PART NUMBERING 7 P 001 FLG02 00 C 15 Card access time 15 25 150ns 250ns Temperature range C Commercial 0°C to +70°C I Industrial -40°C to +85°C Packaging option 00 Standard, type 1 Card family and version - See Card Family and Version Info. for details (next page) Card capacity 001 1MB PC card P R Standard PCMCIA Ruggedized PCMCIA Card technology 7 8 August 2000 Rev. 3 - ECO #13132 FLASH SRAM 11 PC Card Products PCMCIA Flash Memory Card FLG Series Card Family and Version Information FLG 01-FLG04 FLG01 FLG02 FLG03 FLG04 Based on 28F010 No Attribute Memory, no Write Protect With Attribute Memory, no Write Protect No Attribute Memory, with Write Protect With Attribute Memory, with Write Protect Example P/N 7P XXX FLG 02 SS T ZZ FLG 05-FLG08 FLG05 FLG06 FLG07 FLG08 Based on 28F020 No Attribute Memory, no Write Protect With Attribute Memory, no Write Protect No Attribute Memory, with Write Protect With Attribute Memory, with Write Protect Example P/N 7P XXX FLG 06 SS T ZZ Ordering Information 7P XXX FLGYY SS T ZZ where XXX: 256 1) 512 001 002 003 2) 004 2) 005 2) 256KB 512KB 1MB 2MB 3MB 4MB 5MB 1) 2) available only with 28F010 available only with 28F020 FLGYY: Card Version (See Card Family and Version Information) SS: 00 01 02 WEDC Silkscreen Blank Housing, Type I Blank Housing, Type I Recessed T: C I** Commercial Industrial ZZ: 15 20 150ns 200ns Note: Options with intermediate memory capacities, without attribute memory and with hardware write protect switch are available. ** Denotes advanced information. August 2000 Rev. 3 - ECO #13132 12 PC Card Products PCMCIA Flash Memory Card FLG Series Revision History: Rev Level Description Date rev 0 initial release March 6, 1998 rev 1 Logo change May 27, 1999 rev 2 Added Page 11 May 31, 2000 Changed Page Header rev 3 Corrected Timing Errors August 1, 2000 on pg. 6 & 7 White Electronic Designs Corporation One Research Drive, Westborough, MA 01581, USA tel: (508) 366 5151 fax: (508) 836 4850 www.whiteedc.com August 2000 Rev. 3 - ECO #13132 13 PC Card Products