INTEGRATED CIRCUITS DATA SHEET SAA7185 Digital Video Encoder (DENC2) Preliminary specification Supersedes data of 1995 Jun 15 File under Integrated Circuits, IC02 1996 Jul 08 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 FEATURES • CMOS 5 V device • Digital PAL/NTSC encoder • System pixel frequency 13.5 MHz • Accepts MPEG decoded data • 8-bit wide MPEG port GENERAL DESCRIPTION • Input data format Cb, Y, Cr etc. (CCIR 656) The SAA7185 encodes digital YUV video data to an NTSC, PAL CVBS or S-Video signal. • 16-bit wide YUV input port • I2C-bus control or alternatively MPU parallel control port • Programmable horizontal sync output phase The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data. It includes a sync/clock generator and on-chip Digital-to-Analog Converters (DACs). • OSD overlay with Look-Up Tables (LUTs) 8 × 3 bytes The circuit is compatible to the DIG-TV2 chip family. • Encoder can be master or slave • Programmable horizontal and vertical input synchronization phase • Colour bar generator • Line 21 Closed Caption encoder • Cross-colour reduction • DACs operating at 27 MHz with 10-bit resolution • Controlled rise/fall times of output syncs and blanking • Down-mode of DACs • CVBS and S-Video output simultaneously • PLCC68 package. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDA analog supply voltage 4.75 5.0 5.25 V VDDD digital supply voltage 4.5 5.0 5.5 V IDDA analog supply current − 50 55 mA IDDD digital supply current − 140 170 mA Vi input signal voltage levels Vo(p-p) analog output signal voltages Y, C and CVBS without load − (peak-to-peak value) 2 − V RL load resistance 80 − − Ω ILE LF integral linearity error − − ±2 LSB DLE LF differential linearity error − − ±1 LSB Tamb operating ambient temperature 0 − +70 °C 1996 Jul 08 TTL compatible 2 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7185WP DESCRIPTION PLCC68 VERSION plastic leaded chip carrier; 68 leads SOT188-2 BLOCK DIAGRAM KEY SEL_ED 18 MP7 to MP0 VP0 to VP7 OSD0 to OSD2 31 VDDD1 to VDDD3 RTCI 32 to 34 VDDA1 to VrefH VDDA4 II 47 55 48,50, 54,56 53 A 51 17,37,67 43 20 to 27 8 DATA MANAGER 9 to 16 8 OUTPUT INTERFACE ENCODER 8 8 D 49 8 internal control bus RCM1 RCM2 8 clock timing signals VSSA 46 VrefL 8 1,8,19 28,35, 42,62 63 to 66 2 to 5 CONTROL INTERFACE 68 61 59 60 SAA7185 8 SYNC CLK 58 57 41 RESET XTALI 40 38 39 36 6 7 MBE733 DP0 to DP7 CS/SA SEL_MPU A0/SDA RW/SCL DTACK XTALO andbook, full pagewidth VSSD1 to VSSD7 Fig.1 Block diagram. 1996 Jul 08 3 LLC CDIR Cref RCV2 RCV1 Y CHROMA 52 29 30 CVBS Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 PINNING SYMBOL PIN DESCRIPTION VSSD1 1 DP4 2 digital ground 1 DP5 3 DP6 4 DP7 5 RCV1 6 Raster Control 1 for Video port. Depending on the synchronization mode, this pin receives/provides a VS/FS/FSEQ signal. RCV2 7 Raster Control 2 for Video port. Depending on the synchronization mode, this pin receives/provides an HS/HREF/CBL signal. VSSD2 8 digital ground 2 VP0 9 VP1 10 Upper 4 bits of the Data Port. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the parallel MPU interface. If it is LOW, they are the UV lines of the Video Port. VP2 11 VP3 12 VP4 13 VP5 14 VP6 15 VP7 16 VDDD1 17 digital supply voltage 1 SEL_ED 18 Select Encoder Data. Selects data either from MPEG port or from video port as encoder input. VSSD3 19 digital ground 3 MP7 20 MP6 21 MP5 22 MP4 23 MP3 24 MP2 25 MP1 26 MP0 27 VSSD4 28 digital ground 4 RCM1 29 Raster Control 1 for MPEG port. This pin provides a VS/FS/FSEQ signal. RCM2 30 Raster Control 2 for MPEG port. This pin provides an HS pulse for the MPEG decoder. KEY 31 Key signal for OSD. It is active HIGH. OSD0 32 OSD1 33 OSD2 34 VSSD5 35 digital ground 5 CDIR 36 Clock direction. If the CDIR input is HIGH, the circuit receives a clock signal, otherwise LLC and CREF are generated by the internal crystal oscillator. VDDD2 37 digital supply voltage 2 1996 Jul 08 Video Port. This is an input for CCIR 656 compatible, multiplexed video data. If the 16-bit DIG-TV2 format is used, this is the Y data. MPEG Port. It is an input for CCIR 656 style multiplexed YUV data. On-Screen Display data. This is the index for the internal OSD look-up table. 4 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 SYMBOL PIN DESCRIPTION LLC 38 Line-Locked Clock. This is the 27 MHz master clock for the encoder. The direction is set by the CDIR pin. Cref 39 Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals. XTALO 40 Crystal oscillator output (to crystal). XTALI 41 Crystal oscillator input (from crystal). If the oscillator is not used, this pin should br connected to ground. VSSD6 42 digital ground 6 RTCI 43 Real Time Control Input. If the clock is provided by an SAA7151B, RTCI should be connected to the RTCO pin of the decoder to improve the signal quality. AP 44 Test pin. Connect to digital ground for normal operation. SP 45 Test pin. Connect to digital ground for normal operation. VrefL 46 Lower reference voltage input for the DACs. VrefH 47 Upper reference voltage input for the DACs. VDDA1 48 Analog positive supply voltage 1 for the DACs and output amplifiers. CHROMA 49 Analog output of the chrominance signal. VDDA2 50 Analog supply voltage 2 for the DACs and output amplifiers. Y 51 Analog output of the luminance signal. VSSA 52 Analog ground for the DACs and output amplifiers. CVBS 53 Analog output of the CVBS signal. VDDA3 54 Analog supply voltage 3 for the DACs and output amplifiers. II 55 Current input for the output amplifiers, connect via a 15 kΩ resistor to VDDA. VDDA4 56 Analog supply voltage 4 for the DACs and output amplifiers. RESET 57 Reset input, active LOW. After reset is applied, all outputs are in 3-state input mode. The I2C-bus receiver waits for the start condition. DTACK 58 Data acknowledge output of the parallel MPU interface, active LOW, otherwise high impedance. RW/SCL 59 If pin 68 (SEL_MPU) is HIGH, this is the read/write signal of the parallel MPU interface, otherwise it is the I2C-bus serial clock input. A0/SDA 60 If pin 68 (SEL_MPU) is HIGH, this is the address signal of the parallel MPU interface, otherwise it is the I2C-bus serial data input/output. CS/SA 61 If pin 68 (SEL_MPU) is HIGH, this is the chip select signal of the parallel MPU interface, otherwise it is the I2C-bus slave address select pin. LOW: slave address = 88H, HIGH = 8CH. VSSD7 62 digital ground 7 DP0 63 DP1 64 DP2 65 DP3 66 VDDD3 67 digital supply voltage 3 SEL_MPU 68 Select MPU interface input. If it is HIGH, the parallel MPU interface is active, otherwise the I2C-bus interface will be used. 1996 Jul 08 Lower 4 bits of the Data Port. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the parallel MPU interface. If it is LOW, they are the UV lines of the Video Port. 5 Philips Semiconductors Preliminary specification 44 AP VrefL 46 45 SP VrefH 47 48 VDDA1 49 CHROMA 50 VDDA2 51 Y 52 VSSA SAA7185 53 CVBS 54 VDDA3 55 II 56 VDDA4 57 RESET 58 DTACK 60 A0/SDA handbook, full pagewidth 59 RW/SCL Digital Video Encoder (DENC2) CS/SA 61 43 RTCI VSSD7 62 42 VSSD6 DP0 63 41 XTALI DP1 64 40 XTALO DP2 65 39 DP3 66 38 LLC VDDD3 67 Cref 37 VDDD2 SEL_MPU 68 36 CDIR SAA7185 VSSD1 1 35 VSSD5 DP4 2 34 OSD2 DP5 3 33 OSD1 DP6 4 32 OSD0 DP7 5 31 KEY Fig.2 Pin configuration. 1996 Jul 08 6 MP1 26 MP2 25 MP3 24 MP4 23 MP5 22 MP6 21 MP7 20 27 MP0 VSSD3 19 9 SEL_ED 18 VP0 VDDD1 17 28 VSSD4 VP7 16 8 VP6 15 VSSD2 VP5 14 29 RCM1 VP4 13 7 VP3 12 RCV2 VP2 11 30 RCM2 VP1 10 RCV1 6 MBE732 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 A number of possibilities are provided for setting of different video parameters such as: FUNCTIONAL DESCRIPTION The digital MPEG-compatible Video Encoder (DENC2) encodes digital luminance and chrominance into analog CVBS and simultaneously S-Video (Y/C) signals. NTSC-M and PAL B/G standards also sub-standards are supported. black and blanking level control colour subcarrier frequency black variable burst amplitude etc. The basic encoder function consists of subcarrier generation and colour modulation also insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements RS-170-A and CCIR 624. During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to input mode. A reset forces the control interfaces to abort any running bus transfer and to set Register 3AH to contents 13H, Register 61H to contents 0X010101b, and Register 6CH to contents 00H. All other control registers are not influenced by a reset. For ease of analog post filtering the signals are twice oversampled with respect to pixel clock before digital-to-analog conversion. Data manager In the Data manager, real time arbitration on the data stream to be encoded is performed. For total filter transfer characteristics see Figs 3, 4, 5 and 6. The DACs are realized with full 10-bit resolution. The encoder provides three 8-bit wide data ports, that serve different applications. Depending on hardware conditions (signals on pins SEL_ED, KEY, OSD2 to OSD0, MP7 to to MP0, VP7 to VP0 and DP7 to DP0) and different software programming either data from the MP port, from the VP port, or from the OSD port are selected to be encoded to CVBS and Y/C signals. The MPEG Port (MP) and the Video Port (VP) accept 8 lines multiplexed Cb-Y-Cr data. The Video Port (VP) is also able to handle DIG-TV2 family compatible 16-bit YUV signals. In this event, the Data Port (DP) is used for the U/V components. Optionally, the OSD colour look-up tables located in this block, can be read out in a pre-defined sequence (8 steps per active video line), achieving e.g. a colour bar test pattern generator without need for an external data source. The colour bar function is only under software control. The Data Port can handle the data of an 8-bit wide microprocessor interface, alternatively. The 8-bit multiplexed Cb-Y-Cr formats are CCIR 656 (D1 format) compatible, but the SAV, EAV etc. codes are not decoded. Encoder A crystal-stable master clock (LLC) of 27 MHz, which is twice the CCIR line-locked pixel clock of 13.5 MHz, needs to be supplied externally. Optionally, a crystal oscillator input/output pair of pins and an on-chip clock driver is provided. Additionally, a DMSD2 compatible clock interface, using Cref (input or output) and RTC (see “data sheet SAA7151B” ) is available. VIDEO PATH The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y/C signals. Luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). After having been inserted a fixed synchronization level, in accordance with standard composite synchronization schemes, a variable blanking level, programmable also in a certain range, is inserted. The DENC2 synthesizes all necessary internal signals, colour subcarrier frequency, and synchronization signals, from that clock. DENC2 is always timing master for the MPEG Port (MP), but it can additionally be configured as master or slave for the Video Port (VP). In order to enable easy analog post filtering, luminance is interpolated from 13.5 MHz data rate to 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. For transfer characteristic of the luminance interpolation filter see Figs 5 and 6. The IC also contains Closed Caption and Extended Data Services Encoding (Line 21); it also supports OSD via KEY and three-bit overlay techniques by a 24 × 8 LUT. The IC can be programmed via I2C-bus or 8-bit MPU interface, but only one interface configuration can be active at a time; if the 16-bit Video Port mode (VP and DP) is being used, only the I2C-bus interface can be selected. 1996 Jul 08 7 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 MHz data rate to 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y/C output. For transfer characteristics of the chrominance interpolation filter see Figs 3 and 4. The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitudes at the input of the DAC for CVBS is reduced by 15⁄16 with respect to Y and C DACs to make maximum use of conversion ranges. Outputs of all DACs can be set together via software control to minimum output voltage for either purpose. Synchronization The amplitude of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. The synchronization of the DENC2 is able to operate in two modes; slave mode and master mode. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour related to the video signal on VP (and DP, if used) can be influenced by programming the polarity and on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. The numeric ratio between Y and C outputs is in accordance with set standards. CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of Closed Caption or Extended Data Service, delivered by the control interface, can be encoded (Line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. If the horizontal phase is not be influenced by RCV1, a horizontal pulse needs to be supplied at the RCV2 pin. Timing and trigger behaviour can also be influenced for RCV2. The actual line number where data is to be encoded in, can be modified in a certain range. If there are missing pulses at RCV1 and/or RCV2, the time base of DENC2 runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (such with wrong phase) must occur. Data clock frequency is in accordance with definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 Ω. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. It is also possible to encode Closed Caption Data for 50 Hz field frequencies at 32 times horizontal line frequency. In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the IC can output: Output Interface • A Vertical Sync signal (VS) with 3 or 2.5 lines duration, or In the output interface encoded Y and C signals are converted from digital-to-analog in 10-bit resolution both Y and C signals are combined to a 10-bit CVBS signal, also; in front of the summation point, the luminance signal can optionally be fed through a further filter stage, suppressing components in the range of subcarrier frequency. Thus, a type of Cross Colour reduction is provided, which is useful in a standard TV set with CVBS input. • An ODD/EVEN signal which is LOW in odd fields, or • A field sequence signal (FSEQ) which is HIGH in the first of 4 respectively 8 fields. On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up e.g. a composite blanking signal. Slopes of synchronization pulses are not affected with any Cross Colour reduction active. The phase of the pulses output on RCV1 or RCV2 are referenced to the VP port, polarity of both signals is selectable. Three different filter characteristics or bypass are available, see Fig.5. 1996 Jul 08 8 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 The DENC2 is always the timing master for the source at the MP input. The IC provides two signals for synchronizing this source: Input levels and formats DENC2 expects digital YUV data with levels (digital codes) in accordance with CCIR 601. On the RCM1 port the same signals as on RCV1 (as output) are available; on RCM2 the IC provides a horizontal pulse with programmable start and stop phase. Deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. The length of a field also start and end of its active part can be programmed. The active part of a field always starts at the beginning of a line. The MPEG port accepts only 8-bit multiplexed CCIR 656 compatible data. If the I2C-bus interface is used, the VP port can handle both formats, 8-bit multiplexed Cb-Y-Cr data on the VP lines, or the 16-bit DTV2 format with the Y signal on the VP lines and the UV signal on the DP port. Control interface DENC2 contains two control interfaces: an I2C-bus slave transceiver and 8-bit parallel microprocessor interface. The interfaces cannot be used simultaneously. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. I2C-bus The interface is a standard slave transceiver, supporting 7-bit slave addresses and 100 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one readable status byte. Two I2C-bus slave addresses can be selected (pin SEL_MPU must be LOW): 88H: LOW at pin 61 8CH: HIGH at pin 61. The parallel interface is defined by: D7 to D0 data bus CS active-LOW chip select signal RW read/not write signal, LOW for a write cycle DTACK 680xx style data acknowledge (handshake), active-LOW A0 register select, LOW selects address, HIGH selects data. The parallel interface uses two registers, one auto-incremental containing the current address of a control register (equals subaddress with I2C-bus control), one containing actual data. The currently addressed register is mapped to the corresponding control register. The status byte can be read optionally via a read access to the address register, no other read access is provided. 1996 Jul 08 9 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) Table 1 CCIR signal component levels SIGNAL Y IRE DIGITAL LEVEL 0 16 50 126 100 235 bottom peak 16 colourless 128 top peak 240 Cb bottom peak 16 colourless 128 top peak 240 Cr Table 2 SAA7185 straight binary straight binary straight binary 8-bit multiplexed format (similar to CCIR 656) TIME Sample 0 1 2 2 4 5 6 7 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Luminance pixel number 0 1 Colour pixel number Table 3 CODE 2 3 0 2 16-bit multiplexed format (DTV2 format) TIME Sample Y line Sample UV line Luminance pixel number Colour pixel number 1996 Jul 08 0 1 2 3 4 5 6 7 Y0 Y1 Y2 Y3 Cb0 Cr0 Cb2 Cr2 0 1 2 3 0 10 2 1996 Jul 08 3A 42 43 44 Input port control OSD LUT Y0 OSD LUT U0 OSD LUT V0 5B 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B Gain U MSB, black level Gain V MSB, blanking level Null Cross-colour select Standard control Burst amplitude Subcarrier 0 Subcarrier 1 Subcarrier 2 Subcarrier 3 Line 21 odd 0 Line 21 odd 1 Line 21 even 0 Line 21 even 1 Encoder control, CC line 5A Chrominance phase 5C 59 OSD LUT V7 Gain V 58 OSD LUT U7 Gain U 57 OSD LUT Y7 ↓ 39 ↓ 00 Null Null SUB ADDRESS 11 MODIN1 L21E17 L21E07 L21O17 MODIN0 L21E16 L21E06 L21O16 L21O06 FSC30 FSC22 FSC14 FSC06 BSTA6 DOWN CCRS0 0 0 0 GAINV6 GAINU6 CHPS6 OSDV76 OSDU76 OSDY76 OSDV06 OSDU06 OSDY06 0 0 0 D6 0 L21E15 L21E05 L21O15 L21O05 FSC29 FSC21 FSC13 FSC05 BSTA5 INPI1 0 0 BLNNL5 BLCKL5 GAINV5 GAINU5 CHPS5 OSDV75 OSDU75 OSDY75 OSDV05 OSDU05 OSDY05 0 0 0 D5 SCCLN4 L21E14 L21E04 L21O14 L21O04 FSC28 FSC20 FSC12 FSC04 BSTA4 YGS 0 0 BLNNL4 BLCKL4 GAINV4 GAINU4 CHPS4 OSDV74 OSDU74 OSDY74 OSDV04 OSDU04 OSDY04 V656 0 0 D4 ↓ ↓ SCCLN3 L21E13 L21E03 L21O13 L21O03 FSC27 FSC19 FSC11 FSC03 BSTA3 RTCE 0 0 BLNNL3 BLCKL3 GAINV3 GAINU3 CHPS3 OSDV73 OSDU73 OSDY73 OSDV03 OSDU03 OSDY03 VY2C 0 0 D3 DATA BYTE (note 1) SCCLN2 L21E12 L21E02 L21O12 L21O02 FSC26 FSC18 FSC10 FSC02 BSTA2 SCBW 0 0 BLNNL2 BLCKL2 GAINV2 GAINU2 CHPS2 OSDV72 OSDU72 OSDY72 OSDV02 OSDU02 OSDY02 VUV2C 0 0 D2 SCCLN1 L21E11 L21E01 L21O11 L21O01 FSC25 FSC17 FSC09 FSC01 BSTA1 PAL 0 0 BLNNL1 BLCKL1 GAINV1 GAINU1 CHPS1 OSDV71 OSDU71 OSDY71 OSDV01 OSDU01 OSDY01 MY2C 0 0 D1 SCCLN0 L21E10 L21E00 L21O10 L21O00 FSC24 FSC16 FSC08 FSC00 BSTA0 FISE 0 0 BLNNL0 BLCKL0 GAINV0 GAINU0 CHPS0 OSDV70 OSDU70 OSDY70 OSDV00 OSDU00 OSDY00 MUV2C 0 0 D0 Digital Video Encoder (DENC2) L21O07 FSC31 FSC23 FSC15 FSC07 SQP 0 CCRS1 0 GAINV8 GAINU8 GAINV7 GAINU7 CHPS7 OSDV77 OSDU77 OSDY77 OSDV07 OSDU07 OSDY07 CBENB 0 0 D7 Slave Receiver (Slave Address 88H or 8CH) REGISTER FUNCTION Table 4 Bit allocation map Philips Semiconductors Preliminary specification SAA7185 1996 Jul 08 74 75 76 77 78 79 Null Null Null Begin RCV2 output End RCV2 output MSBs RCV2 output 12 0 LAL7 FAL7 FLEN7 0 ERCV7 BRCV7 0 0 0 0 EMRQ7 BMRQ7 PHRES1 0 HTRIG7 0 SRCV11 D7 0 LAL6 FAL6 FLEN6 ERCV10 ERCV6 BRCV6 0 0 0 EMRQ10 EMRQ6 BMRQ6 PHRES0 0 HTRIG6 0 SRCV10 D6 D5 LAL8 LAL5 FAL5 FLEN5 ERCV09 ERCV5 BRCV5 0 0 0 EMRQ09 EMRQ5 BMRQ5 SBLBN 0 HTRIG5 0 TRCV2 1. All bits labelled ‘0’ are reserved. They must be programmed with logic 0. Note 7D 73 MSBs MP request 7C 72 End MP request MSBs field control 71 Begin MP request Last active line 70 fsc reset mode, Vertical trigger 7B 6F Horizontal trigger First active line 6E Horizontal trigger 7A 6D Field length 6C RCM, CC mode SUB ADDRESS RCV port control REGISTER FUNCTION FAL8 LAL4 FAL4 FLEN4 ERCV08 ERCV4 BRCV4 0 0 0 EMRQ08 EMRQ4 BMRQ4 VTRIG4 0 HTRIG4 0 ORCV1 D4 0 LAL3 FAL3 FLEN3 0 ERCV3 BRCV3 0 0 0 0 EMRQ3 BMRQ3 VTRIG3 0 HTRIG3 SRCM11 PRCV1 D3 DATA BYTE (note 1) 0 LAL2 FAL2 FLEN2 BRCV10 ERCV2 BRCV2 0 0 0 BMRQ10 EMRQ2 BMRQ2 VTRIG2 HTRIG10 HTRIG2 SRCM10 CBLF D2 FLEN9 LAL1 FAL1 FLEN1 BRCV09 ERCV1 BRCV1 0 0 0 BMRQ09 EMRQ1 BMRQ1 VTRIG1 HTRIG09 HTRIG1 CCEN1 ORCV2 D1 FLEN8 LAL0 FAL0 FLEN0 BRCV08 ERCV0 BRCV0 0 0 0 BMRQ08 EMRQ0 BMRQ0 VTRIG0 HTRIG08 HTRIG0 CCEN0 PRCV2 D0 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 I2C-bus format I2C-bus address; see Table 6 Table 5 S SLAVE ADDRESS Table 6 ACK SUBADDRESS ACK DATA 0 ACK -------- DATA n ACK P Explanation of Table 5 PART DESCRIPTION S START condition Slave address 1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1) ACK acknowledge, generated by the slave Subaddress (note 2) subaddress byte DATA data byte -------- continued data bytes and ACKs P STOP condition Notes 1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. Slave Receiver Table 7 Subaddress 3A DATA BYTE MUV2C MY2C VUV2C VY2C V656 CBENB 1996 Jul 08 LOGIC LEVEL DESCRIPTION 0 Cb/Cr data at MP are two’s complement. 1 Cb/Cr data at MP are straight binary. Default after reset. 0 Y data at MP are two’s complement. 1 Y data at MP are straight binary. Default after reset. 0 Cb/Cr data input to VP or DP are two’s complement. Default after reset. 1 Cb/Cr data input to VP or DP are straight binary. 0 Y data input to VP are two’s complement. Default after reset. 1 Y data input to VP are straight binary. 0 Selects YUV 422 format on VP (8 lines Y) and DP (8 lines multiplexed Cb/Cr). 1 Selects CCIR 656 compatible format on VP (8 lines Cb, Y, Cr). Default after reset. 0 Data from input ports are encoded. Default after reset. 1 Colour bar with programmable colours (entries of OSD_LUTs) is encoded. The LUTs are read in upward order from index 0 to index 7. 13 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) Table 8 SAA7185 Subaddress 42 to 59 DATA BYTE (note 1) COLOUR INDEX (note 2) White Yellow Cyan OSDY OSDU OSDV 107 (6BH) 0 (00H) 0 (00H) 107 (6BH) 0 (00H) 0 (00H) 82 (52H) 144 (90H) 18 (12H) 34 (22H) 172 (ACH) 14 (0Eh) 42 (2AH) 38 (26H) 144 (90H) 03 (03H) 29 (1DH) 172 (ACH) Green 17 (11H) 182 (B6H) 162 (A2H) 240 (F0H) 200 (C8H) 185 (B9H) Magenta 234 (EAH) 74 (4AH) 94 (5EH) 212 (D4H) 56 (38H) 71 (47H) 209 (D1H) 218 (DAH) 112 (70H) 193 (C1H) 227 (E3H) 84 (54H) 169 (A9H) 112 (70H) 238 (EEH) 163 (A3H) 84 (54H) 242 (F2H) 144 (90H) 0 (00H) 0 (00H) 144 (90H) 0 (00H) 0 (00H) Red Blue Black 0 1 2 3 4 5 6 7 Notes 1. Contents of OSD Look-up tables. All 8 entries are 8-bits. Data representation is in accordance with CCIR 601 (Y, Cb, Cr), but two’s complement, e.g. for a 100⁄100 (upper number) or 100⁄75 (lower number) colour bar. 2. For normal colour bar with CBENB = logic 1. Table 9 Subaddress 5A DATA BYTE CHPS DESCRIPTION Phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in steps of 360/256 degrees. Table 10 Subaddress 5B and 5D DATA BYTE GAINU DESCRIPTION CONDITIONS variable gain for Cb signal; white-to-black = 92.5 input representation GAINU = 0 accordance with CCIR 601 GAINU = 118 (76H) white-to-black = 100 output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal IRE(2) GAINU = 0 output subcarrier of U contribution = 0 GAINU = 125 (7DH) output subcarrier of U contribution = nominal Notes 1. GAINU = −2.17 × nominal to +2.16 × nominal. 2. GAINU = −2.05 × nominal to +2.04 × nominal. 1996 Jul 08 REMARKS IRE(1) 14 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 Table 11 Subaddress 5C and 5E DATA BYTE GAINV DESCRIPTION CONDITIONS variable gain for Cr signal; white-to-black = 92.5 IRE(1) input representation GAINV = 0 accordance with CCIR 601 GAINV = 165 (A5H) white-to-black = 100 REMARKS output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal IRE(2) GAINV = 0 output subcarrier of V contribution = 0 GAINV = 175 (AFH) output subcarrier of V contribution = nominal Notes 1. GAINV = −1.55 × nominal to +1.55 × nominal. 2. GAINV = −1.46 × nominal to +1.46 × nominal. Table 12 Subaddress 5D DATA BYTE BLCKL DESCRIPTION CONDITIONS variable black level; input white-to-sync = 140 IRE(1) representation accordance BLCKL = 0 with CCIR 601 BLCKL = 63 (3FH) REMARKS output black level = 24 IRE output black level = 49 IRE white-to-sync = 143 IRE(2) BLCKL = 0 output black level = 24 IRE BLCKL = 63 (3FH) output black level = 50 IRE Notes 1. Output black level/IRE = BLCKL × 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal. 2. Output black level/IRE = BLCKL × 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal. Table 13 Subaddress 5E DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS REMARKS white-to-sync = 140 IRE(1) BLNNL = 0 output blanking level = 17 IRE BLNNL = 63 (3FH) output blanking level = 42 IRE white-to-sync = 143 IRE(2) BLNNL = 0 output blanking level = 17 IRE BLNNL = 63 (3FH) output blanking level = 43 IRE Notes 1. Output black level/IRE = BLNNL × 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal. 2. Output black level/IRE = BLNNL × 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal. 1996 Jul 08 15 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 Table 14 Subaddress 60 (CCRS; select cross colour reduction filter in luminance) DATA BYTE FUNCTION CCRS1 CCRS0 0 0 no cross colour reduction (for overall transfer characteristic of luminance see Fig.5) 0 1 cross colour reduction #1 active (for overall transfer characteristic see Fig.5) 1 0 cross colour reduction #2 active (for overall transfer characteristic see Fig.5) 1 1 cross colour reduction #3 active (for overall transfer characteristic see Fig.5) Table 15 Subaddress 61 DATA BYTE FISE PAL SCBW RTCE YGS INPI DOWN 1996 Jul 08 LOGIC LEVEL DESCRIPTION 0 864 total pixel clocks per line 1 858 total pixel clocks per line; default after reset 0 NTSC encoding (non-alternating V component); default after reset 1 PAL encoding (alternating V component) 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4); default after reset 0 no real time control of generated subcarrier frequency; default after reset 1 real time control of generated subcarrier frequency through SAA7151B (timing see Fig.9) 0 luminance gain for white − black 100 IRE 1 luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black; default after reset 0 PAL switch phase is nominal; default after reset 1 PAL switch phase is inverted compared to nominal 0 DACs in normal operational mode (not defined after reset, program after all zero-bits are set to zero) 1 DACs forced to lowest output voltage (not defined after reset, program after all zero-bits are set to zero) 16 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 Table 16 Subaddress 62 DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation accordance with CCIR 601 CONDITIONS REMARKS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding BSTA = 0 to 1.25 × nominal(1) white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 1.76 × nominal(2) white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.20 × nominal(3) white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 1.67 × nominal(4) SQP subcarrier real time logic 0 control from SAA7151B digital colour decoder logic 1 not supported in current version, do not use Notes 1. Recommended value: BSTA = 102 (66H). 2. Recommended value: BSTA = 72 (48H). 3. Recommended value: BSTA = 106 (6AH). 4. Recommended value: BSTA = 75 (4BH). Table 17 Subaddress 63 to 66 (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION CONDITIONS FSC0 to FSC3 ffsc = subcarrier frequency f fsc 32 FSC = round -------- × 2 (in multiples of line f llc frequency); fllc = clock frequency (in see note 1 multiples of line frequency) REMARKS FSC3 = most significant byte FSC0 = least significant byte Notes 1. Examples: a) NTSC-M: ffsc = 227.5 MHz, fllc = 1716 MHz → FSC = 569408543 (21F07C1FH). b) PAL-B/G: ffsc = 283.7516 MHz, fllc = 1728 MHz → FSC = 705268427 (2A098ACBH). 1996 Jul 08 17 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 Table 18 Subaddress 67 to 6A DATA BYTE(1) DESCRIPTION L21O0 first byte of captioning data, odd field L21O1 second byte of captioning data, odd field L21E0 first byte of extended data, even field L21E1 second byte of extended data, even field Note 1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format. Table 19 Subaddress 6B DATA BYTE DESCRIPTION SCCLN selects the actual line, where closed caption or extended data are encoded; see note 1 MODIN defines video data of MP port or VP(DP) port to be encoded; see Table 20 Note 1. Line = (SCCLN + 4) for M systems; line = (SCCLN + 1) for other systems. Table 20 Logic levels and function of MODIN DATA BYTE FUNCTION MODIN1 MODIN0 0 0 unconditionally from MP port 0 1 from MP port, if pin SEL_ED = HIGH; otherwise from VP port 1 0 unconditionally from VP port 1 1 from VP port, if pin SEL_ED = HIGH; otherwise from MP port 1996 Jul 08 18 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 Table 21 Subaddress 6C DATA BYTE LOGIC LEVEL PRCV2 ORCV2 CBLF DESCRIPTION 0 polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively; default after reset 1 polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively 0 pin RCV2 is switched to input; default after reset 1 pin RCV2 is switched to output 0 if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference Pulse that is HIGH during active portion of line, also during vertical blanking Interval); default after reset 1 if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1); default after reset if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) also as an internal blanking signal PRCV1 0 polarity of RCV1 as output is active HIGH, rising edge is taken when input, respectively; default after reset 1 polarity of RCV1 as output is active LOW, falling edge is taken when input, respectively ORCV1 0 pin RCV1 is switched to input; default after reset 1 pin RCV1 is switched to output TRCV2 0 horizontal synchronization is taken from RCV1 port; default after reset 1 horizontal synchronization is taken from RCV2 port − defines signal type on pin RCV1; see Table 22 SRCV1 Table 22 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT AS INPUT 0 VS VS Vertical Sync each field; default after reset 0 1 FS FS Frame Sync (odd/even) 1 0 FSEQ FSEQ 1 1 − − SRCV11 SRCV10 0 FUNCTION Field Sequence, vertical sync every fourth field (FISE = 1) or eighth field (FISE = 0) not applicable Table 23 Subaddress 6D DATA BYTE DESCRIPTION CCEN enables individual line 21 encoding; see Table 24 SRCM defines signal type on pin RCM1; see Table 25 1996 Jul 08 19 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 Table 24 Logic levels and function of CCEN DATA BYTE FUNCTION CCEN1 CCEN0 0 0 line 21 encoding OFF 0 1 enables encoding in field 1 (odd) 1 0 enables encoding in field 2 (even) 1 1 enables encoding in both fields Table 25 Logic levels and function of SRCM DATA BYTE AS OUTPUT FUNCTION SRCM1 SRCM0 0 0 VS Vertical Sync each field 0 1 FS Frame Sync (odd/even) 1 0 FSEQ 1 1 − Field Sequence, vertical sync every fourth field (FISE = 1) or eighth field (FISE = 0) not applicable Table 26 Subaddress 6E to 6F DATA BYTE HTRIG DESCRIPTION sets the Horizontal Trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed increasing HTRIG decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = 032H Table 27 Subaddress 70 DATA BYTE VTRIG LOGIC LEVEL − DESCRIPTION sets the Vertical TRIGger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines variation range of VTRIG = 0 to 31 (1FH) SBLBN PHRES 0 vertical blanking is defined by programming of FAL and LAL 1 vertical blanking is forced automatically at least during field synchronization and equalization pulses; note 1 − selects the phase reset mode of the colour subcarrier generator; see Table 28 Note 1. If cross-colour reduction is programmed, it is active between FAL and LAL in both events. 1996 Jul 08 20 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 Table 28 Logic levels and function of PHRES DATA BYTE FUNCTION PHRES1 PHRES0 0 0 no reset 0 1 reset every two lines 1 0 reset every eight fields 1 1 reset every four fields Table 29 Subaddress 71 to 73 DATA BYTE BMRQ DESCRIPTION beginning of MP ReQuest signal (RCM2) values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at BMRQ = 0F9H (115H) EMRQ end of MP ReQuest signal (RCM2) values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at EMRQ = 686H (690H) Table 30 Subaddress 77 to 79 DATA BYTE BRCV DESCRIPTION beginning of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at BRCV = 0F9H (115H) ERCV end of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at ERCV = 686H (690H) Table 31 Subaddress 7A to 7D DATA BYTE FLEN DESCRIPTION Length of a Field = FLEN + 1, measured in half lines valid range is limited to 524 to 1022 (FISE = 1) respectively 624 to 1022 (FISE = 0), FLEN should be even FAL First Active Line after vertical blanking interval = FAL + 1, measured in lines LAL Last Active Line before vertical blanking interval = LAL + 1, measured in lines FAL = 0 coincides with the first field synchronization pulse LAL = 0 coincides with the first field synchronization pulse SUBADDRESSES In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up. 1996 Jul 08 21 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 Slave Transmitter Table 32 Slave Transmitter (slave address 89H or 8DH) REGISTER FUNCTION DATA BYTE SUBADDRESS − Status byte D7 D6 D5 VER2 VER1 VER0 D4 D3 CCRDE CCRDO D2 D1 D0 FSQ2 FSQ1 FSQ0 Table 33 No subaddress DATA BYTE DESCRIPTION VER Version identification of the device. It will be changed with all versions of the IC that have different programming models. Current Version is 000 binary. CCRDE Closed caption bytes of the even field have been encoded. The bit is reset after information has been written to the subaddresses 69 and 6A. It is set immediately after the data have been encoded. CCRDO Closed caption bytes of the odd field have been encoded. The bit is reset after information has been written to the subaddresses 67 and 68. It is set immediately after the data have been encoded. FSQ State of the internal field sequence counter. Bit 0 (FSQ0) gives the odd/even information; odd = LOW, even = HIGH. 1996 Jul 08 22 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 MBE737 handbook, full 6 pagewidth Gv (dB) 0 −6 −12 −18 −24 (1) (2) −30 −36 −42 −48 −54 0 2 4 6 8 10 (1) SCBW = 1. (2) SCBW = 0. Fig.3 Chrominance transfer characteristic 1. MBE735 handbook, halfpage 2 Gv (dB) 0 (1) (2) −2 −4 −6 0 0.4 0.8 1.2 f (MHz) 1.6 (1) SCBW = 1. (2) SCBW = 0. Fig.4 Chrominance transfer characteristic 2. 1996 Jul 08 23 12 f (MHz) 14 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 MBE738 6 Gv full pagewidth handbook, (dB) (4) 0 (2) (3) −6 −12 −18 −24 (1) −30 −36 −42 −48 −54 0 (1) (2) (3) (4) 2 4 6 8 10 CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0. Fig.5 Luminance transfer characteristic 1. MBE736 handbook, halfpage 1 Gv (dB) 0 −1 −2 −3 −4 −5 0 2 4 f (MHz) 6 CCRS1 = 0; CCRS0 = 0. Fig.6 Luminance transfer characteristic 2 1996 Jul 08 24 12 f (MHz) 14 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 CHARACTERISTICS VDDD = 4.5 to 5.5 V; Tamb = 0 to 70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Supply VDDD digital supply voltage 4.5 5.5 V VDDA analog supply voltage 4.75 5.25 V IDDD digital supply current note 1 − 170 mA IDDA analog supply current note 1 − 55 mA V Inputs VIL LOW level input voltage (except LLC, SDA, SCL, AP, SP and XTALI) −0.5 +0.8 VIH HIGH level input voltage (except LLC, SDA, SCL, AP, SP and XTALI) 2.0 VDDD + 0.5 V HIGH level input voltage (LLC) 2.4 VDDD + 0.5 V VLI input leakage current − 1 µA CI input capacitance clocks operating − 10 pF data available − 8 pF I/Os at high impedance − 8 pF V Outputs VOL LOW level output voltage (except SDA and XTALO) note 2 0 0.6 VOH HIGH level output voltage (except LLC, SDA, DTACK and XTALO) note 2 2.4 VDDD + 0.5 V HIGH level output voltage (LLC) note 2 2.6 VDDD + 0.5 V I2C-bus; SDA and SCL VIL LOW level input voltage −0.5 +1.5 VIH HIGH level input voltage 3.0 VDDD + 0.5 V II input current VI = LOW or HIGH −10 +10 µA VOL LOW level output voltage (SDA) IOL = 3 mA − 0.4 V IO output current during acknowledge 3 − mA V Clock timing (LLC) TLLC cycle time note 3 34 41 ns δ duty factor tHIGH/TLLC note 4 40 60 % tr rise time note 3 − 5 ns tf fall time note 3 − 6 ns 1996 Jul 08 25 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SYMBOL SAA7185 PARAMETER CONDITIONS MIN. MAX. UNIT Input timing tSU;CREF input data set-up time (Cref) 6 − ns tHD;CREF input data hold time (Cref) 3 − ns tSU input data set-up time (any other except SEL_MPU, CDIR, RW/SCL, A0/SDA, CS/SA, RESET, AP and SP) 6 − ns tHD input data hold time (any other except SEL_MPU, CDIR, RW/SCL, A0/SDA, CS/SA, RESET, AP and SP) 3 − ns Crystal oscillator fn nominal frequency (usually 27 MHz) 3rd harmonic − 30 MHz ∆f/fn permissible deviation of nominal frequency note 5 −50 +50 10−6 CRYSTAL SPECIFICATION Tamb operating ambient temperature 0 70 °C CL load capacitance 8 − pF RS series resistance − 80 Ω C1 motional capacitance (typical) 1.5 −20% 1.5 +20% fF C0 parallel capacitance (typical) 3.5 −20% 3.5 +20% pF MPU interface timing tAS address set-up time tAH address hold time tRWS read/write set-up time tRWH read/write hold time note 6 note 6 9 − ns 0 − ns 9 − ns 0 − ns tDD data bus floating from CS (read) notes 7, 8 and 9; n = 9 − 400 ns tDF data valid from CS (read) notes 7 and 8; n = 5 − 255 ns tDS data bus set-up time (write) note 6 9 − ns tDH data bus hold time (write) note 6 9 − ns tACS acknowledge delay from CS notes 7 and 8; n = 11 − 475 ns tCSD CS HIGH from acknowledge 0 − ns tDAT DTACK floating from CS HIGH − 330 ns 7.5 40 pF notes 7 and 8; n = 7 Data and reference signal output timing CL output load capacitance tOH output hold time tOD output delay time 1996 Jul 08 Cref in output mode 26 4 − ns − 25 ns Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SYMBOL SAA7185 PARAMETER CONDITIONS MIN. MAX. UNIT CHROMA, Y and CVBS outputs Vo(p-p) output signal voltage (peak-to-peak value) 1.9 2.1 V RI internal serial resistance note 10 18 35 Ω RL output load resistance 80 − Ω B output signal bandwidth of DACs 10 − MHz ILE LF integral linearity error of DACs −3 dB − ±2 LSB DLE LF differential linearity error of DACs − ±1 LSB Notes 1. At maximum supply voltage with highly active input signals. 2. The levels have to be measured with load circuits of 1.2 kΩ to 3.0 V (standard TTL load) and CL = 25 pF. 3. The data is for both input and output direction. 4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 6. The value is calculated via equation t = t SU + t HD 7. The value depends on the clock frequency. The numbers given are calculated with fLLC = 27 MHz. 8. The values given are calculated via equation t dmax = t OD + n × t LLC + t LLC + t SU 9. The falling edge of DTACK will always occur1 × LLC after data is valid. 10. For full digital range, without load, VDDA = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V. 1996 Jul 08 27 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) handbook, full pagewidth SAA7185 TLLC tHIGH 2.6 V 1.5 V 0.6 V LLC clock output tHD; DAT tf tr TLLC tHIGH 2.4 V 1.5 V 0.8 V LLC clock input tSU; DAT tHD; DAT tf tr 2.0 V input data valid valid not valid 0.8 V td tHD; DAT 2.4 V output data valid valid not valid 0.6 V MBE742 Fig.7 Clock data timing. handbook, full pagewidth LLC CREF VP(n) Y(0) Y(1) Y(2) Y(3) Y(4) DP(n) Cb(0) Cr(0) Cb(2) Cr(2) Cb(4) RCV2 MBE739 The data demultiplexing phase is coupled to the internal horizontal phase. The Cref signal applies only for the 16 lines digital TV format, because these signals are only valid in 13.5 MHz. The phase of the RCV2 signal is programmed to 0F8h (115H for 50 Hz) in this example in output mode (BRCV2). Fig.8 Digital TV timing. 1996 Jul 08 28 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) handbook, full pagewidth H/L transition count start 128 HPLL increment 13 SAA7185 4 bits reserved 0 5 bits reserved 21 sequence bit (1) reserved (2) 0 RTCI not used in DENC2 valid invalid sample sample 8/LLC MBE743 (1) Sequence bit: PAL = logic 0 then (R − Y) line normal; PAL = logic 1 then (R − Y) line inverted. NTSC = logic 0 then no change. (2) Reserved bits: 236 with 50 Hz systems; 233 with 60 Hz systems. Fig.9 RTCI timing. handbook, full pagewidth A0 tAS tAH tRWS tRWH CSN RWN D(7 to 0) tDF tDD DTACK tACS tCSD Fig.10 MPU interface timing (READ cycle). 1996 Jul 08 29 tDAT MBE740 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 handbook, full pagewidth A0 tAS tAH tRWS tRWH CSN RWN D(7 to 0) tDF tDS DTACK tACS tCSD tDAT Fig.11 MPU interface timing (WRITE cycle). 1996 Jul 08 30 MBE741 1996 Jul 08 VDDD1 17 XTAL0 40 41 10 pF XTAL1 3rd harmonic (3) 10 pF X1 27.0 MHz 0.1 µF 0.1 µF 0.1 µF 67 31 VSSD VSSD VSSD 56 55 47 35 Ω (1) 49 VSSA VrefL VSSD1 to VSSD7 VSSA 52 DAC1 48 VDDA1 35 Ω (1) 53 50 VDDA2 VSSA VSSA 35 Ω (1) 51 54 VDDA3 0.1 µF 0.1 µF 0.1 µF DAC2 DAC3 II VrefH 15 kΩ 46 0.1 µF 0.1 µF 1, 8, 19, 28, 35, 42, 62 VDDA4 VSSA VSSA + 5 V analog Fig.12 Application environment of the DENC2. SAA7185 37 VDDD2 VDDD3 + 5 V digital VSSA Y CVBS 1.23 V (p-p)(2) VSSA 1.0 V (p-p) (2) VSSA CHROMA 0.62 V (p-p) (2) MBE734 75 Ω 12 Ω 75 Ω 20 Ω 75 Ω 20 Ω Digital Video Encoder (DENC2) (1) Typical value. (2) For 100/100 colour bar. (3) Philips 12NC ordering code: 4312 065 02341. digital inputs and outputs 1 nF 10 µH handbook, full pagewidth VSSD Philips Semiconductors Preliminary specification SAA7185 APPLICATION INFORMATION Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 PACKAGE OUTLINE PLCC68: plastic leaded chip carrier; 68 leads SOT188-2 eD eE y X 60 A 44 43 Z E 61 bp b1 w M 68 1 HE E pin 1 index A e A4 A1 (A 3) β 9 k1 27 Lp k detail X 10 26 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT A A1 min. A3 A4 max. bp b1 mm 4.57 4.19 0.51 0.25 3.30 0.53 0.33 0.81 0.66 0.180 inches 0.020 0.01 0.165 D (1) E (1) e eD eE HD HE k 24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07 k1 max. Lp v w y 0.51 1.44 1.02 0.18 0.18 0.10 Z D(1) Z E (1) max. max. 2.16 β 2.16 45 o 0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950 Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT188-2 112E10 MO-047AC 1996 Jul 08 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-03-11 32 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 SOLDERING Wave soldering Introduction Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream corners. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 1996 Jul 08 33 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Jul 08 34 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 NOTES 1996 Jul 08 35 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 708 296 8556 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 615 800, Fax. +358 615 80920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 52 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. +30 1 4894 339/911, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 648 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 83749, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 São Paulo, SÃO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com/ps/ (1) SAA7185_2 June 26, 1996 11:51 am © Philips Electronics N.V. 1996 SCA50 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 657021/1200/02/pp36 Date of release: 1996 Jul 08 Document order number: 9397 750 00943