INTEL 8XL196NP

8XL196NP COMMERCIAL
CHMOS 16-BIT MICROCONTROLLER
n 14 MHz Operation at 2.7–3.3 Volts
n 4 External Interrupt Pins and NMI Pin
n Chip-select Unit
— 6 Chip Select Pins
— Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each
Chip Select
— Programmable Wait States (0, 1, 2,
or 3) for Each Chip Select
— Programmable Bus Width (8- or 16bit) for Each Chip Select
— Programmable Address Range for
Each Chip Select
n 2 Flexible 16-bit Timer/Counters with
Quadrature Counting Capability
n 2.0µs 16 × 16 Unsigned Multiplication
n 3.4µs 32/16 Unsigned Division
n 3 Pulse-width Modulator (PWM) Outputs
with High Drive Capability
n 100-pin SQFP or 100-pin QFP Package
n 1 Mbyte of Linear Address Space
n Optional 4 Kbytes of ROM
n 1000 Bytes of Register RAM
n Register-register Architecture
n 32 I/O Port Pins
n 16 Prioritized Interrupt Sources
n Full-duplex Serial Port with Dedicated
Baud-rate Generator
n Peripheral Transaction Server
n Complete System Development
Support
n High-speed CHMOS Technology
n Event Processor Array (EPA) with 4 Highspeed Capture/Compare Channels
The 8XL196NP is a member of Intel’s 16-bit MCS® 96 microcontroller family. The device features 1 Mbyte of
linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch
between multiplexed and demultiplexed operation. When operating at 14 MHz in demultiplexed mode, the
8XL196NP can access a 200 ns memory device with zero wait states. The 8XL196NP is available without
ROM (80L196NP) or with 4 Kbytes of ROM (83L196NP).
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such
products. Information contained herein supersedes previously published specifications on these devices from Intel.
Order Number: 272824-001
© INTEL CORPORATION, 1996
March 1996
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
16
CPU
1000
Byte
Register
File
24 Bytes
CPU SFRs
RALU
Interrupt
Controller
Peripheral
Transaction
Server
Microcode
Engine
4K Bytes
ROM (optional)
Memory Controller
with
Chip Select
Chip Select
CS5:0#
Control
Signals
Queue
8
A19:16/
EPORT3:0
16
A15:0
Timer 1
Timer 2
Event
Processor
Array
Serial
Port
Port 1
Port 2
Port 1/
EPA3:0,
Timer 1,
Timer 2
Port 2/
Hold Control,
SIO,
EXTINT1:0
Pulse
Width
Modulator
Baud
Rate
Gen
Port
3
AD15:0
Port
4
Port 3/
Port 4/
EXTINT3:2 PWM2:0
A2351-01
Figure 1. 8XL196NP Block Diagram
2
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
1.0 NOMENCLATURE OVERVIEW
X
XX
8
X
X
XXXXX
XX
De
ct
ed
ly
or
s
on
pti
n
tio
yO
ma
mi
Fa
or
em
Inf
-m
pe
eS
du
ss
am
ce
gr
vic
o
Pr
o
Pr
o
Pr
atu
er
tio
ns
Op
tio
in
Op
nur
ing
ag
dB
an
re
mp
ck
Pa
Te
ns
A2815-01
Figure 2. 8XL196NP Family Nomenclature
Table 1. Description of Product Nomenclature
Parameter
Temperature and Burn-in Options
Packaging Options
Options
Description
no mark
Commercial operating temperature range (0°C to 70°C)
with Intel standard burn-in.
S
SB
QFP
SQFP
Program–memory Options
0
3
No ROM
ROM
Process Information
L
Low Voltage CHMOS
Product Family
196NP
Device Speed
no mark
14 MHz
3
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VCC
AD8
VSS
AD9
AD10
AD11
AD12
AD13
AD14
AD15
A16 / EPORT.0
A17 / EPORT.1
VCC
2.0 PINOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
S8XL196NP
View of component as
mounted on PC board
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
A18 / EPORT.2
A19 / EPORT.3
WR# / WRL#
RD#
BHE# / WRH#
ALE
INST
READY
RPD
ONCE
VSS
VCC
VSS
A8
A9
A10
A11
A12
A13
A14
A15
VSS
XTAL1
XTAL2
VSS
P2.7 / CLKOUT
NC
P2.6 / HLDA#
P2.5 / HOLD#
P1.1 / EPA1
P1.2 / EPA2
P1.3 / EPA3
P1.4 / T1CLK
P1.5 / T1DIR
VCC
P1.6 / T2CLK
VSS
P1.7 / T2DIR
P4.0 / PWM0
P4.1 / PWM1
P4.2 / PWM2
P4.3
VCC
VSS
P2.0 / TXD
P2.1 / RXD
P2.2 / EXTINT0
P2.3 / BREQ#
P2.4 / EXTINT1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AD0
NC
RESET#
NMI
EA#
A0
A1
VCC
VSS
A2
A3
A4
A5
A6
A7
VCC
VSS
NC
P3.0 / CS0#
P3.1 / CS1#
P3.2 / CS2#
P3.3 / CS3#
VSS
P3.4 / CS4#
P3.5 / CS5#
P3.6 / EXTINT2
NC
P3.7 / EXTINT3
P1.0 / EPA0
VCC
A4318-01
Figure 3. 8XL196NP 100-pin SQFP Package
4
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 2. 8XL196NP 100-pin SQFP Pin Assignment
Pin
†
Name
Pin
Name
Pin
Name
Pin
Name
1
RESET#
26
EXTINT3/P3.7
51
CLKOUT/P2.7
76
WR#/WRL#
2
NMI
27
EPA0/P1.0
52
NC†
77
EPORT.3/A19
3
EA#
28
VCC
53
VSS
78
EPORT.2/A18
4
A0
29
EPA1/P1.1
54
XTAL2
79
VSS
5
A1
30
EPA2/P1.2
55
XTAL1
80
VCC
6
VCC
31
EPA3/P1.3
56
VSS
81
EPORT.1/A17
7
VSS
32
T1CLK/P1.4
57
NC†
82
EPORT.0/A16
8
A2
33
T1DIR/P1.5
58
A15
83
AD15
9
A3
34
VCC
59
A14
84
AD14
10
A4
35
T2CLK/P1.6
60
A13
85
AD13
11
A5
36
VSS
61
A12
86
AD12
12
A6
37
T2DIR/P1.7
62
A11
87
AD11
13
A7
38
PWM0/P4.0
63
A10
88
AD10
14
VCC
39
PWM1/P4.1
64
A9
89
AD9
15
VSS
40
PWM2/P4.2
65
A8
90
VSS
16
NC†
41
P4.3
66
VSS
91
AD8
17
NC†
42
VCC
67
VCC
92
VCC
18
CS0#/P3.0
43
VSS
68
VSS
93
AD7
19
CS1#/P3.1
44
TXD/P2.0
69
ONCE
94
AD6
20
CS2#/P3.2
45
RXD/P2.1
70
RPD
95
AD5
21
CS3#/P3.3
46
EXTINT0/P2.2
71
READY
96
AD4
22
VSS
47
BREQ#/P2.3
72
INST
97
AD3
23
CS4#/P3.4
48
EXTINT1/P2.4
73
ALE
98
AD2
24
CS5#/P3.5
49
HOLD#/P2.5
74
BHE#/WRH#
99
AD1
25
EXTINT2/P3.6
50
HLDA#/P2.6
75
RD#
100
AD0
To be compatible with future versions of the Nx family, tie the no connection (NC) pins as follows:
Pin 57 = VSS, Pin 16 = VCC, Pin 17 = VSS (5 volts on this pin will enable a clock doubler on future
devices), and Pin 52 = VCC.
5
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 3. 100-pin SQFP Pin Assignment Arranged by Functional Categories
Address & Data
Name
A0
Address & Data (cont)
Pin
4
Name
AD13
Input/Output
Pin
85
Name
CS0#/P3.0
Power & Ground
Pin
18
Name
Pin
VCC
6
A1
5
AD14
84
CS1#/P3.1
19
VCC
14
A2
8
AD15
83
CS2#/P3.2
20
VCC
28
CS3#/P3.3
21
VCC
34
CS4#/P3.4
23
VCC
42
Pin
CS5#/P3.5
24
VCC
67
73
EPA0/P1.0
27
VCC
80
A3
9
A4
10
A5
11
A6
12
ALE
A7
13
BHE#/WRH#
74
EPA1/P1.1
29
VCC
92
A8
65
BREQ#
47
EPA2/P1.2
30
VSS
7
Bus Control & Status
Name
A9
64
HOLD#
49
EPA3/P1.3
31
VSS
15
A10
63
HLDA#
50
EPORT.0
82
VSS
22
A11
62
INST
72
EPORT.1
81
VSS
36
A12
61
RD#
75
EPORT.2
78
VSS
43
A13
60
READY
71
EPORT.3
77
VSS
53
A14
59
WR#/WRL#
76
P2.2
46
VSS
56
A15
58
P2.3
47
VSS
66
A16
82
P2.4
48
VSS
68
A17
81
A18
78
Processor Control
Name
CLKOUT
Pin
P2.5
49
VSS
79
51
P2.6
50
VSS
90
A19
77
EA#
3
P2.7
51
AD0
100
EXTINT0
46
P3.6
25
AD1
99
EXTINT1
48
P3.7
26
AD2
98
EXTINT2
25
P4.3
41
NC
16
AD3
97
EXTINT3
26
PWM0/P4.0
38
NC
17
AD4
96
NMI
2
PWM1/P4.1
39
NC
52
AD5
95
ONCE
69
PWM2/P4.2
40
NC
57
AD6
94
RESET#
1
RXD/P2.1
45
AD7
93
RPD
70
T1CLK/P1.4
32
AD8
91
XTAL1
55
T1DIR/P1.5
33
AD9
89
XTAL2
54
T2CLK/P1.6
35
AD10
88
T2DIR/P1.7
37
AD11
87
TXD/P2.0
44
AD12
86
6
No Connection
Name
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RESET#
NMI
EA#
A0
A1
VCC
VSS
A2
A3
A4
A5
A6
A7
VCC
VSS
NC
NC
P3.0 / CS0#
P3.1 / CS1#
P3.2 / CS2#
P3.3 / CS3#
VSS
P3.4 / CS4#
P3.5 / CS5#
P3.6 / EXTINT2
P3.7 / EXTINT3
P1.0 / EPA0
VCC
P1.1 / EPA1
P1.2 / EPA2
P1.3 / EPA3
P1.4 / T1CLK
P1.5 / T1DIR
VCC
P1.6 / T2CLK
VSS
P1.7 / T2DIR
P4.0 / PWM0
P4.1 / PWM1
P4.2 / PWM2
P4.3
VCC
VSS
P2.0 / TXD
P2.1 / RXD
P2.2 / EXTINT0
P2.3 / BREQ#
P2.4 / EXTINT1
P2.5 / HOLD#
P2.6 / HLDA#
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VCC
AD8
VSS
AD9
AD10
AD11
AD12
AD13
AD14
AD15
A16 / EPORT.0
A17 / EPORT.1
VCC
VSS
A18 / EPORT.2
A19 / EPORT.3
WR# / WRL#
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
SB8XL196NP
View of component as
mounted on PC board
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RD#
BHE# / WRH#
ALE
INST
READY
RPD
ONCE
VSS
VCC
VSS
A8
A9
A10
A11
A12
A13
A14
A15
NC
VSS
XTAL1
XTAL2
VSS
NC
P2.7 / CLKOUT
A4317-01
Figure 4. 8XL196NP 100-pin QFP Package
7
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. 8XL196NP 100-pin QFP Pin Assignment
Pin
8
Name
Pin
Name
Pin
Name
Pin
Name
1
AD0
26
EXTINT2/P3.6
51
HOLD#/P2.5
76
RD#
2
No Connection
27
No Connection
52
HLDA#/P2.6
77
WR#/WRL#
3
RESET#
28
EXTINT3/P3.7
53
No Connection
78
EPORT.3/A19
4
NMI
29
EPA0/P1.0
54
CLKOUT/P2.7
79
EPORT.2/A18
5
EA#
30
VCC
55
VSS
80
VSS
6
A0
31
EPA1/P1.1
56
XTAL2
81
VCC
7
A1
32
EPA2/P1.2
57
XTAL1
82
EPORT.1/A17
8
VCC
33
EPA3/P1.3
58
VSS
83
EPORT.0/A16
9
VSS
34
T1CLK/P1.4
59
A15
84
AD15
10
A2
35
T1DIR/P1.5
60
A14
85
AD14
11
A3
36
VCC
61
A13
86
AD13
12
A4
37
T2CLK/P1.6
62
A12
87
AD12
13
A5
38
VSS
63
A11
88
AD11
14
A6
39
T2DIR/P1.7
64
A10
89
AD10
15
A7
40
PWM0/P4.0
65
A9
90
AD9
16
VCC
41
PWM1/P4.1
66
A8
91
VSS
17
VSS
42
PWM2/P4.2
67
VSS
92
AD8
18
No Connection
43
P4.3
68
VCC
93
VCC
19
CS0#/P3.0
44
VCC
69
VSS
94
AD7
20
CS1#/P3.1
45
VSS
70
ONCE
95
AD6
21
CS2#/P3.2
46
TXD/P2.0
71
RPD
96
AD5
22
CS3#/P3.3
47
RXD/P2.1
72
READY
97
AD4
23
VSS
48
EXTINT0/P2.2
73
INST
98
AD3
24
CS4#/P3.4
49
BREQ#/P2.3
74
ALE
99
AD2
25
CS5#/P3.5
50
EXTINT1/P2.4
75
BHE#/WRH#
100
AD1
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 5. 100-pin QFP Pin Assignment Arranged by Functional Categories
Address & Data
Name
A0
Address & Data (cont)
Pin
Name
Input/Output
Pin
Name
Power & Ground
Pin
Name
Pin
6
AD13
86
CS0#/P3.0
19
VCC
8
A1
7
AD14
85
CS1#/P3.1
20
VCC
16
A2
10
AD15
84
CS2#/P3.2
21
VCC
30
A3
11
CS3#/P3.3
22
VCC
36
A4
12
Bus Control & Status
CS4#/P3.4
24
VCC
44
Pin
CS5#/P3.5
25
VCC
68
74
EPA0/P1.0
29
VCC
81
A5
13
A6
14
Name
A7
15
BHE#/WRH#
75
EPA1/P1.1
31
VCC
93
A8
66
BREQ#
49
EPA2/P1.2
32
VSS
9
A9
65
HOLD#
51
EPA3/P1.3
33
VSS
17
A10
64
HLDA#
52
EPORT.0
83
VSS
23
ALE
A11
63
INST
73
EPORT.1
82
VSS
38
A12
62
RD#
76
EPORT.2
79
VSS
45
A13
61
READY
72
EPORT.3
78
VSS
55
A14
60
WR#/WRL#
77
P2.2
48
VSS
58
A15
59
A16
83
P2.3
49
VSS
67
P2.4
50
VSS
69
Pin
P2.5
51
VSS
80
54
P2.6
52
VSS
91
Processor Control
A17
82
A18
79
Name
A19
78
EA#
5
P2.7
54
AD0
1
EXTINT0
48
P3.6
26
AD1
100
EXTINT1
50
P3.7
28
AD2
99
EXTINT2
26
P4.3
43
AD3
98
EXTINT3
28
PWM0/P4.0
40
NC
18
AD4
97
NMI
4
PWM1/P4.1
41
NC
27
AD5
96
ONCE
70
PWM2/P4.2
42
NC
53
AD6
95
RESET#
3
RXD/P2.1
47
CLKOUT
AD7
94
RPD
71
T1CLK/P1.4
34
AD8
92
XTAL1
57
T1DIR/P1.5
35
AD9
90
XTAL2
56
T2CLK/P1.6
37
AD10
89
T2DIR/P1.7
39
AD11
88
TXD/P2.0
46
AD12
87
No Connection
Name
NC
Pin
2
9
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
3.0 SIGNALS
Table 6. Signal Descriptions
Name
A15:0
Type
I/O
Description
System Address Bus
These address pins provide address bits 0–15 during the entire external memory
cycle during both multiplexed and demultiplexed bus modes.
A19:16
I/O
Address Pins 16–19
These address pins provide address bits 16–19 during the entire external memory
cycle during both multiplexed and demultiplexed bus modes, supporting extended
addressing of the 1-Mbyte address space.
NOTE: Internally, there are 24 address bits; however, only 20 external address
pins (A19:0) are implemented. The internal address space is 16 Mbytes
(000000–FFFFFFH) and the external address space is 1 Mbyte (00000–
FFFFFH). The microcontroller resets to FF2080H in internal memory or
F2080H in external memory.
A19:16 share package pins with EPORT.3:0.
AD15:0
I/O
Address/Data Lines
The function of these pins depends on the bus width and mode.
16-bit Multiplexed Bus Mode:
AD15:0 drive address bits 0–15 during the first half of the bus cycle and drive or
receive data during the second half of the bus cycle.
8-bit Multiplexed Bus Mode:
AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0 drive address
bits 0–7 during the first half of the bus cycle and drive or receive data during the
second half of the bus cycle.
16-bit Demultiplexed Mode:
AD15:0 drive or receive data during the entire bus cycle.
8-bit Demultiplexed Mode:
AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data that
is currently on the high byte of the internal bus.
ALE
O
Address Latch Enable
This active-high output signal is asserted only during external memory cycles. ALE
signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus (A19:16 and AD15:0 for a
multiplexed bus; A19:0 for a demultiplexed bus).
An external latch can use this signal to demultiplex address bits 0–15 from the
address/data bus in multiplexed mode.
10
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued)
Name
BHE#
Type
O
Description
Byte High Enable
†
During 16-bit bus cycles, this active-low output signal is asserted for word and highbyte reads and writes to external memory. BHE# indicates that valid data is being
transferred over the upper half of the system data bus. Use BHE#, in conjunction
with address bit 0 (A0 for a demultiplexed address bus, AD0 for a multiplexed
address/data bus), to determine which memory byte is being transferred over the
system bus:
BHE#
AD0 or A0
Byte(s) Accessed
0
0
1
0
1
0
both bytes
high byte only
low byte only
BHE# shares a package pin with WRH#.
†
BREQ#
O
When this pin is configured as a special-function signal (P5_MODE.5 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as BHE# or
WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
Bus Request
This active-low output signal is asserted during a hold cycle when the bus controller
has a pending external memory cycle. When the bus-hold protocol is enabled
(WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#, regardless of the
configuration selected through the port configuration registers (P2_MODE,
P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until
the bus-hold protocol is disabled (WSR.7 is cleared).
The microcontroller can assert BREQ# at the same time as or after it asserts
HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted.
BREQ# shares a package pin with P2.4.
CLKOUT
O
Clock Output
Output of the internal clock generator. The CLKOUT frequency is ½ the internal
operating frequency (f). CLKOUT has a 50% duty cycle.
CLKOUT shares a package pin with P2.7.
CS5#:0
O
Chip-select Lines 0–5
The active-low output CSx# is asserted during an external memory cycle when the
address to be accessed is in the range programmed for chip select x. If the external
memory address is outside the range assigned to the six chip selects, no chipselect output is asserted and the bus configuration defaults to the CS5# values.
Immediately following reset, CS0# is automatically assigned to the range FF2000–
FF20FFH (F2000–F20FFH if external).
CS5:0# share package pins with P3.5:0.
11
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued)
Name
EA#
Type
I
Description
External Access
This input determines whether memory accesses to special-purpose and program
memory partitions (FF2000–FF2FFFH) are directed to internal or external memory.
These accesses are directed to internal memory if EA# is held high and to external
memory if EA# is held low. For an access to any other memory location, the value
of EA# is irrelevant.
EA# is not latched and can be switched dynamically during normal operating mode.
Be sure to thoroughly consider the issues, such as different access times for
internal and external memory, before using this dynamic switching capability.
Always connect EA# to VSS when using a microcontroller that has no internal
nonvolatile memory.
EPA3:0
I/O
Event Processor Array (EPA) Capture/Compare Channels
High-speed input/output signals for the EPA capture/compare channels.
EPA3:0 share package pins with P1.3:0.
EPORT.3:0
I/O
Extended Addressing Port
This is a 4-bit, bidirectional, memory-mapped port.
EPORT.3:0 share package pins with A.19:16.
EXTINT0
EXTINT1
EXTINT2
EXTINT3
I
External Interrupts
In normal operating mode, a rising edge on EXTINTx sets the EXTINTx interrupt
pending bit. EXTINTx is sampled during phase 2 (CLKOUT high). The minimum
high time is one state time.
In standby and powerdown modes, asserting the EXTINTx signal for at least 50 ns
causes the device to resume normal operation. The interrupt does not need to be
enabled, but the pin must be configured as a special-function input. If the EXTINTx
interrupt is enabled, the CPU executes the interrupt service routine. Otherwise, the
CPU executes the instruction that immediately follows the command that invoked
the power-saving mode.
In idle mode, asserting any enabled interrupt causes the device to resume normal
operation.
EXTINT0 shares a package pin with P2.2, EXTINT1 shares a package pin with
P2.4, EXTINT2 shares a package pin with P3.6, and EXTINT3 shares a package
pin with P3.7.
HLDA#
O
Bus Hold Acknowledge
This active-low output indicates that the CPU has released the bus as the result of
an external device asserting HOLD#. When the bus-hold protocol is enabled
(WSR.7 is set), the P2.6/HLDA# pin can function only as HLDA#, regardless of the
configuration selected through the port configuration registers (P2_MODE,
P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until
the bus-hold protocol is disabled (WSR.7 is cleared).
12
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued)
Name
HOLD#
Type
I
Description
Bus Hold Request
An external device uses this active-low input signal to request control of the bus.
When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can
function only as HOLD#, regardless of the configuration selected through the port
configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change
the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is
cleared).
HOLD# shares a package pin with P2.5.
INST
O
Instruction Fetch
When high, INST indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle of an external
instruction fetch. INST is low for data accesses, including interrupt vector fetches
and chip configuration byte reads. INST is low during internal memory fetches.
NMI
I
Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI generates a nonmaskable
interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for
greater than one state time to guarantee that it is recognized.
ONCE
I
On-circuit Emulation
Holding ONCE high during the rising edge of RESET# places the device into oncircuit emulation (ONCE) mode. This mode puts all pins into a high-impedance
state, thereby isolating the device from other components in the system. The value
of ONCE is latched when the RESET# pin goes inactive. While the device is in
ONCE mode, you can debug the system using a clip-on emulator.
To exit ONCE mode, reset the device by pulling the RESET# signal low. To prevent
inadvertent entry into ONCE mode, connect the ONCE pin to VSS.
P1.7:0
I/O
Port 1
This is a standard, 8-bit, bidirectional port that shares package pins with individually
selectable special-function signals.
Port 1 shares package pins with the following signals: P1.0/EPA0, P1.1/EPA1,
P1.2/EPA2, P1.3/EPA3, P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR.
P2.7:0
I/O
Port 2
This is a standard, 8-bit, bidirectional port that shares package pins with individually
selectable special-function signals.
Port 2 shares package pins with the following signals: P2.0/TXD, P2.1/RXD,
P2.2/EXTINT0, P2.3/BREQ#, P2.4/EXTINT1, P2.5/HOLD#, P2.6/HLDA#, and
P2.7/CLKOUT.
P3.7:0
I/O
Port 3
This is a standard, 8-bit, bidirectional port that shares package pins with individually
selectable special-function signals.
Port 3 shares package pins with the following signals: P3.0/CS0#, P3.1/CS1#,
P3.2/CS2#, P3.3/CS3#, P3.4/CS4#, P3.5/CS5#, P3.6/EXTINT2, and
P3.7/EXTINT3.
13
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued)
Name
P4.3:0
Type
I/O
Description
Port 4
This ia a 4-bit bidirectional, standard I/O port with high-current drive capability.
Port 4 shares package pins with the following signals: P4.0/PWM0, P4.1/PWM1,
and P4.2/PWM2. P4.3 has a dedicated package pin.
PWM2:0
O
Pulse Width Modulator Outputs
These are PWM output pins with high-current drive capability.
PWM2:0 share package pins with P4.2:0.
RD#
O
Read
Read-signal output to external memory. RD# is asserted only during external
memory reads.
RD# shares a package pin with OE#. (While most signals that share package pins
are connected to the pin by programming their associated control registers, both of
these signals are always connected to the pin.)
READY
I
Ready Input
This active-high input can be used to insert wait states in addition to those
programmed in the chip configuration byte 0 (CCB0) and the bus control x register
(BUSCONx). CCB0 is programmed with the minimum number of wait states (0–3)
for an external fetch of CCB1, and BUSCONx is programmed with the minimum
number of wait states (0–3) for all external accesses to the address range assigned
to the chip-select x channel. If READY is low when the programmed number of wait
states is reached, additional wait states are added until READY is pulled high.
READY shares a package pin with P5.6.
RESET#
I/O
Reset
A level-sensitive reset input to and open-drain system reset output from the
microcontroller. Either a falling edge on RESET# or an internal reset turns on a pulldown transistor connected to the RESET# pin for 16 state times. In the powerdown,
standby, and idle modes, asserting RESET# causes the chip to reset and return to
normal operating mode. After a device reset, the first instruction fetch is from
FF2080H (or F2080H in external memory). For the 80L196NP, the program and
special-purpose memory locations (FF2000–FF2FFFH) reside in external memory.
For the 83L196NP, these locations can reside either in external memory or in
internal ROM.
RPD
I
Return from Powerdown
Timing pin for the return-from-powerdown circuit.
If your application uses powerdown mode, connect a capacitor between RPD and
VSS if the internal oscillator is the clock source.
The capacitor causes a delay that enables the oscillator and PLL circuitry to
stabilize before the internal CPU and peripheral clocks are enabled.
The capacitor is not required if your application uses powerdown mode and if an
external clock input is the clock source.
If your application does not use powerdown mode, leave this pin unconnected.
14
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued)
Name
RXD
Type
I/O
Description
Receive Serial Data
In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as
either an input or an open-drain output for data.
RXD shares a package pin with P2.1.
T1CLK
I
Timer 1 External Clock
External clock for timer 1. Timer 1 increments (or decrements) on both rising and
falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature
counting mode.
and
External clock for the serial I/O baud-rate generator input (program selectable).
T1CLK shares a package pin with P1.4.
T2CLK
I
Timer 2 External Clock
External clock for timer 2. Timer 2 increments (or decrements) on both rising and
falling edges of T2CLK. It is also used in conjunction with T2DIR for quadrature
counting mode.
T2CLK shares a package pin with P1.6.
T1DIR
I
Timer 1 External Direction
External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high
and decrements when it is low. Also used in conjunction with T1CLK for quadrature
counting mode.
T1DIR shares a package pin with P1.5.
T2DIR
I
Timer 2 External Direction
External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high
and decrements when it is low. It is also used in conjunction with T2CLK for
quadrature counting mode.
T2DIR shares a package pin with P1.7.
TXD
O
Transmit Serial Data
In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it
is the serial clock output.
TXD shares a package pin with P2.0.
VCC
PWR
Digital Supply Voltage
Connect each VCC pin to the digital supply voltage.
VSS
GND
Digital Circuit Ground
These pins supply ground for the digital circuitry. Connect each VSS pin to ground
through the lowest possible impedance path.
WR#
O
Write†
This active-low output indicates that an external write is occurring. This signal is
asserted only during external memory writes.
WR# shares a package pin with WRL#.
†
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as WR# or
WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
15
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued)
Name
WRH#
Type
O
Description
Write High
†
During 16-bit bus cycles, this active-low output signal is asserted for high-byte
writes and word writes to external memory. During 8-bit bus cycles, WRH# is
asserted for all write operations.
WRH# shares a package pin with BHE#.
†
WRL#
O
When this pin is configured as a special-function signal (P5_MODE.5 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as BHE# or
WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
Write Low†
During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes
and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for
all write operations.
WRL# shares a package pin with WR#.
†
XTAL1
I
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as WR# or
WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator and the internal clock generators. The internal clock
generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When
using an external clock source instead of the on-chip oscillator, connect the clock
input to XTAL1. The external clock signal must meet the VIH specification for XTAL1.
XTAL2
O
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design
uses an external clock source instead of the on-chip oscillator.
16
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
4.0 ADDRESS MAP
Table 7. 8XL196NP Address Map
Address
(Note 1)
Description
Notes
FF FFFFH
FF 3000H
External device (memory or I/O) connected to address/data bus
FF 2FFFH
FF 2000H
Internal ROM or external device (memory or I/O) connected to address/data bus
(determined by EA# pin)
FF 1FFFH
FF 0100H
External device (memory or I/O) connected to address/data bus
2
FF 00FFH
FF 0000H
Reserved for ICE
4
FE FFFFH
0F 0000H
Overlaid memory (reserved for future devices);
locations xF0000–xF00FFH are reserved for ICE
2
0E FFFFH
01 0000H
896 Kbytes of external device (memory or I/O) connected to address/data bus
2
00 FFFFH
00 3000H
External device (memory or I/O) connected to address/data bus
2
00 2FFFH
00 2000H
External device (memory or I/O) connected to address/data bus or
remapped internal ROM
2, 5, 6
00 1FFFH
00 1FE0H
Memory-mapped peripheral special-function registers (SFRs)
2, 4, 7
00 1FDFH
00 1F00H
Internal peripheral special-function registers (SFRs)
4, 7, 9
00 1EFFH
00 0400H
External device (memory or I/O) (reserved for future devices)
00 03FFH
00 0100H
Upper register file (general-purpose register RAM)
8, 9
00 00FFH
00 0018H
Lower register file (general-purpose register RAM and stack pointer)
8, 10
00 0017H
00 0000H
Lower register file (CPU SFRs)
2
2, 3
6
4, 7, 8, 10
NOTES:
1. Internally, there are 24 address bits (A23:0); however, only 20 address lines (A19:0) are bonded out.
The external address space is 1 Mbyte (00000–FFFFFH).
2. Address with indirect, indexed, or extended modes.
3. The 8XL196NP resets to internal address FF2080H (FF2080H in internal ROM or F2080H in external
memory).
4. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits.
5. These areas are mapped into internal ROM if the REMAP bit (CCB1.2) is set and EA# is at logic 1.
Otherwise, they are mapped to external memory.
6. WARNING: The contents or functions of these memory locations may change with future device revisions, in which case a program that relies on one or more of these locations may not function properly.
7. Refer to the 8XC196NP, 80C196NU Microcontroller User’s Manual.
8. Code executed in locations 000000H to 0003FFH will be forced external.
9. Address with indirect, indexed, or extended modes or through register windows.
10. Address with direct, indirect, indexed, or extended modes.
17
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature ................................. –60°C to +150°C
Supply Voltage with Respect to VSS ............. –0.5 V to +7.0 V
Power Dissipation ........................................................ 1.5 W
OPERATING CONDITIONS*
TA (Ambient Temperature Under Bias) ..............0°C to +70°C
VCC (Digital Supply Voltage) ............................ 2.7 V to 3.3 V
FXTAL1 (Input Frequency for VCC = 2.7–3.3 V)
(Note 1).............. 8 MHz to 14 MHz
NOTES:
1.
This device is static and should operate below 1 Hz, but
has been tested only down to 8 MHz.
NOTICE: This document contains information on
products in the design phase of development. The
specifications are subject to change without notice.
Do not finalize a design with this information.
Revised information will be published when the
product is available. Verify with your local Intel
sales office that you have the latest datasheet
before finalizing a design.
*WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage. These
are stress ratings only. Operation beyond the “Operating
Conditions” is not recommended and extended exposure
beyond the “Operating Conditions” may affect device reliability.
5.1 DC Characteristics
Table 8. DC Characteristics at VCC = 2.7 – 3.3 V
Typ(1)
Max
Units
Test Conditions
ICC
VCC Supply Current
28
40
mA
XTAL1 = 14MHz
VCC = 3.3V
Device in Reset
IIDLE
Idle Mode Current
14
25
mA
XTAL1 = 14MHz
VCC = 3.3 V
IPD
Powerdown Mode Current
(Note 2)
50
75
µA
VCC = 3.3V
ILI
Input Leakage Current
(all input pins except RESET)
±10
µA
VSS < VIN < VCC
VIL
Input Low Voltage (all pins)
–0.5
0.4
V
Symbol
Parameter
Min
VIH
Input High Voltage
0.2 VCC +1.3
VCC + 0.5
V
VIL1
Input Low Voltage XTAL1
–0.5
0.3 VCC
V
VIH1
Input High Voltage XTAL1
0.7 VCC
VCC + 0.5
V
NOTES:
1. Typical values are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature and with VCC = 3.0 V.
2. For temperatures below 100°C, typical is 10 µA.
3. For all pins except P4.3:0, which have higher drive capability.
4. If VOL is held above 0.45 V or VOH is held below Vcc–0.7 V, current on pins must be externally limited to
the following values: IOL and IOH maximum on all output pins is 12 mA.
5. For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which
were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3).
6. Pin capacitance is not tested. CS is based on design simulations.
18
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. DC Characteristics at VCC = 2.7 – 3.3 V(Continued)
Symbol
Parameter
Min
Typ(1)
Max
Units
Test Conditions
0.3
0.45
V
V
IOL = 200 µA
IOL = 3.2 mA
VOL
Output Low Voltage (output
configured as complementary) (Note 3,4)
VOH
Output High Voltage (output
configured as complementary) (Note 4)
VCC – 0.3
VCC – 0.7
V
V
IOH = –200 µA
IOH = –3.2 mA
VOH2
Output High Voltage on
XTAL2
VCC – 0.3
VCC – 0.7
V
V
IOH = –100 µA
IOH = –500 µA
VOL1
Output Low Voltage on P4.x
(output configured as complementary)
0.45
0.6
V
V
IOL = 8 mA
IOL = 10 mA
VOL2
Output Low Voltage in
RESET on ALE, INST, and
NMI
0.45
V
IOL = 2 µA
VOH1
Output High Voltage in
RESET (Note 5)
V
IOH = –2 µA
VOL3
Output Low Voltage in
RESET for ONCE pin
0.8
V
IOL = 30 µA
VOL4
Output Low Voltage on
XTAL2
0.3
0.45
V
V
IOL = 100 µA
IOL = 500 µA
VTH+ –VTH–
Hysteresis voltage width on
RESET# pin
CS
Pin Capacitance (any pin to
VSS) (Note 6)
RRST
RESET Pull-up Resistor
VCC – 0.7
0.3
9
V
10
pF
95
kΩ
VCC = 3.3V,
VIN = 2.0V
NOTES:
1. Typical values are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature and with VCC = 3.0 V.
2. For temperatures below 100°C, typical is 10 µA.
3. For all pins except P4.3:0, which have higher drive capability.
4. If VOL is held above 0.45 V or VOH is held below Vcc–0.7 V, current on pins must be externally limited to
the following values: IOL and IOH maximum on all output pins is 12 mA.
5. For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which
were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3).
6. Pin capacitance is not tested. CS is based on design simulations.
19
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
35
IIDLE@VCC = 3.0 V
ICC, IIDLE (mA)
30
ICC@VCC = 3.0 V
25
20
15
10
5
0
2
4
6
8
10
12
14
16
18
20
Frequency (MHz)
A4319-01
Figure 5. ICC, IIDLE versus Frequency
20
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.2 AC Characteristics — Multiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 9. AC Characteristics, Multiplexed Bus Mode
Symbol
Parameter
VCC = 2.7 V – 3.3 V
Min
Max
Units
The 8XL196NP Will Meet These Specifications
FXTAL1
Input frequency on XTAL1
8
14
MHz
TXTAL1
Period, 1/FXTAL1
71
125
ns
TXHCH
XTAL1 High to CLKOUT High/Low
20
110
ns
TCLCL
CLKOUT Cycle Time
TCHCL
CLKOUT High Period
TXTAL1 – 10
TAVRL
A15:0, CSx# Valid to RD# Low
2TXTAL1 – 30
ns
TAVWL
A15:0, CSx# Valid to WR# Low
2TXTAL1 – 15
ns
TWHSH
A19:16, CSx# Hold after WR# Rising Edge
TRHSH
A19:16, CSx# Hold after RD# Rising Edge
TCLLH
CLKOUT Low to ALE High
TLLCH
ALE Low to CLKOUT High
TLHLH
ALE Cycle Time
4TXTAL1
TLHLL
ALE High Period
TXTAL1 – 15
2TXTAL1
ns
TXTAL1 + 15
ns
0
0
–12
10
–10
15
ns
ns
ns (1)
TXTAL1 + 5
ns
TAVLL
AD15:0 Valid to ALE Low
TXTAL1 – 18
ns
TLLAX
AD15:0 Hold after ALE Low
TXTAL1 – 25
ns
TLLRL
ALE Low to RD# Low
TXTAL1 – 30
TRLCL
RD# Low to CLKOUT Low
5
TRLRH
RD# Low Period
TXTAL1 – 10
TRHLH
RD# High to ALE High
TXTAL1 – 5
TRLAZ
RD# Low to Address Float
TLLWL
ALE Low to WR# Low
TCLWL
CLKOUT Low to WR# Low
TQVWH
Data Valid before WR# High
TCHWH
CLKOUT High to WR# High
TWLWH
WR# Low Period
ns
30
ns
TXTAL1 + 20
ns (2)
ns (1)
5
TXTAL1 – 30
–18
10
TXTAL1 – 23
–10
TXTAL1 – 10
ns
ns
ns
ns (1)
10
ns
ns (1)
NOTES:
1. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.
2. Assuming back-to-back bus cycles.
3. 8-bit bus only.
21
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 9. AC Characteristics, Multiplexed Bus Mode (Continued)
Symbol
Parameter
VCC = 2.7 V – 3.3 V
Min
Max
Units
The 8XL196NP Will Meet These Specifications
TWHQX
Data Hold after WR# High
TXTAL1 – 33
TWHLH
WR# High to ALE High
TXTAL1 – 12
ns
TXTAL1 + 20
ns (2)
TWHBX
BHE#, INST Hold after WR# High
TXTAL1 – 10
ns
TWHAX
A15:8 Hold after WR# High
TXTAL1 – 30
ns (3)
TRHBX
BHE#, INST Hold after RD# High
TXTAL1 – 10
ns
TRHAX
A15:8 Hold after RD# High
TXTAL1 – 25
ns (3)
NOTES:
1. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.
2. Assuming back-to-back bus cycles.
3. 8-bit bus only.
22
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 10. AC Characteristics, Multiplexed Bus Mode
Symbol
VCC = 2.7 V – 3.3 V
Parameter
Min
Max
Units
The External Memory System Must Meet These Specifications
TAVYV
AD15:0 Valid to READY Setup
TYLYH
Non READY Time
No Upper Limit
0
TCLYX
READY Hold after CLKOUT Low
TAVDV
AD15:0 Valid to Input Data Valid
2TXTAL1 – 60
ns
ns
TXTAL1 – 20
ns (1)
3TXTAL1 – 55
ns (2)
ns (2)
TRLDV
RD# Active to Input Data Valid
TXTAL1 – 25
TSLDV
Chip-select Low, A19:16 Valid to Data Valid
4TXTAL1 – 75
TCLDV
CLKOUT Low to Input Data Valid
TXTAL1 – 50
ns
TRHDZ
End of RD# to Input Data Float
TXTAL1 – 10
ns
TRXDX
Data Hold after RD# Inactive
0
ns
NOTES:
1. Exceeding the maximum specification causes additional wait states.
2. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.
Table 11. AC Timing Symbol Definitions
Signals
Conditions
A†
Address
B
BHE#
HA
HLDA#
C
CLKOUT
L
ALE
D
Data
Q
Data Out
Y
READY
X
No Longer Valid
G
Buswidth
R
RD#
BR
BREQ#
Z
Floating
†
H
HOLD#
CSx#
H
High
W
WR#, WRH#, WRL#
L
Low
X
XTAL1
V
Valid
S
Address bus (demultiplexed mode) or Address/data bus (multiplexed mode)
23
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
TXTAL1
XTAL1
TCLCL
TCHCL
TXHCH
CLKOUT
TRLCL
TCLLH
TLLCH
TLHLH
ALE
TLHLL
TLLRL
TAVLL
TLLAX
TRLRH
TRHLH
RD#
TRHDZ
TRLDV
TRLAZ
AD15:0
(read)
Address Out
Data
TAVDV
TWHLH
TWLWH
TLLWL
WR#
TWHQX
TQVWH
AD15:0
(write)
Address Out
Data Out
Address Out
TRHBX
TWHBX
BHE#,
INST
Valid
TRHAX
TWHAX
AD15:8
Address Out
TSLDV
A19:16
CSx#
Address Out
TWHSH
TRHSH
A2844-01
Figure 6. System Bus Timing Diagram (Multiplexed Bus Mode)
24
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
TCLYX (max)
CLKOUT
TAVYV
TCLYX (min)
READY
TLHLH + 2TXTAL1
ALE
TRLRH + 2TXTAL1
RD#
AD15:0
(read)
TRLDV + 2TXTAL1
TAVDV + 2TXTAL1
Address Out
Data In
TWLWH + 2TXTAL1
WR#
TQVWH + 2TXTAL1
AD15:0
(write)
Address Out
Data Out
BHE#, INST
A19:16
Extended Address Out
CSx#
A3250-01
Figure 7. READY Timing Diagram (Multiplexed Bus Mode)
25
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.3 AC Characteristics — Demultiplexed Bus Mode
Test Coditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 12. AC Characteristics, Demultiplexed Bus Mode
Symbol
Parameter
VCC = 2.7 V – 3.3 V
Min
Max
Units
The 8XL196NP Will Meet These Specifications
FXTAL1
Input requency on XTAL1
8
14
MHz
TXTAL1
Period, 1/FXTAL1
71
125
ns
TXHCH
XTAL1 High to CLKOUT High/Low
20
110
ns
TCLCL
CLKOUT Cycle Time
TCHCL
CLKOUT High Period
TXTAL1 – 10
TAVRL
A19:0, CSx# Valid to RD# Low
2TXTAL1 – 48
TAVWL
A19:0, CSx# Valid to WR# Low
2TXTAL1 – 37
TCLLH
CLKOUT Low to ALE High
TLLCH
ALE Low to CLKOUT High
TLHLH
ALE Cycle Time
4TXTAL1
TLHLL
ALE High Period
TXTAL1 – 12
TXTAL1 + 10
TRLCH
RD# Low to CLKOUT High
–5
20
TRLRH
RD# Low Period
TRHLH
RD# High to ALE High
TXTAL1 – 5
TXTAL1 + 20
ns (2)
TWLCH
WR# Low to CLKOUT High
– 10
10
ns
2TXTAL1
ns
TXTAL1 + 15
ns
ns
– 12
10
– 15
15
TQVWH
Data Valid before WR# High
3TXTAL1 – 55
CLKOUT High to WR# High
– 15
ns
ns
ns (1)
2TXTAL1 – 10
TCHWH
ns
ns
ns
ns (1)
ns (1)
5
ns
TWLWH
WR# Low Period
2TXTAL1 – 13
ns (1)
TWHQX
Data Hold after WR# High
TXTAL1 – 25
ns
TWHLH
WR# High to ALE High
TXTAL1 – 10
TWHBX
BHE#, INST Hold after WR# High
TXTAL1 – 10
ns
TWHAX
A19:0, CSx# Hold after WR# High
0
ns
TRHBX
BHE#, INST Hold after RD# High
TXTAL1 – 10
ns
TRHAX
A19:0, CSx# Hold after RD# High
0
ns
NOTES:
1. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.
2. Assuming back-to-back bus cycles.
26
TXTAL1 + 20
ns (2)
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 13. AC Characteristics, Demultiplexed Bus Mode
Symbol
Parameter
VCC = 2.7 V – 3.3 V
Min
Max
Units
The External Memory System Must Meet These Specifications
TAVYV
A19:0, CSx# Valid to READY Setup
TYLYH
Non READY Time
3TXTAL1 – 88
No Upper Limit
ns
ns
TCLYX
READY Hold after CLKOUT Low
TXTAL1 – 30
ns (1)
TAVDV
A19:0, CSx# Valid to Input Data Valid
4TXTAL1 – 75
ns (2)
TRLDV
RD# Active to Input Data Valid
2TXTAL1 – 33
ns (2)
TCLDV
CLKOUT Low to Input Data Valid
TXTAL1 – 50
ns
TRHDZ
End of RD# to Input Data Float
TXTAL1 – 5
ns
TRXDX
Data Hold after RD# Inactive
0
ns
NOTES:
1. Exceeding the maximum specification causes additional wait states.
2. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.
27
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
TXTAL1
XTAL1
TCLCL
TCHCL
TXHCH
CLKOUT
TCLDV
TLLCH
TCLLH
TLHLH
ALE
TLHLL
TRLRH
TRHLH
TRLCH
RD#
TRHDZ
TRLDV
AD15:0
(read)
Valid
TAVDV
TCHWH
TWHLH
TWLWH
WR#
TWLCH
TQVWH
AD15:0
(write)
TWHQX
Valid
TRHBX
TWHBX
BHE#,
INST
Valid
TRHAX
A19:0
CSx#
TWHAX
Address Out
Address
A2845-01
Figure 8. System Bus Timing Diagram (Demultiplexed Bus Mode)
28
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
TCLYX (max)
CLKOUT
TAVYV
TCLYX (min)
READY
TLHLH + 2TXTAL1
ALE
TRLRH + 2TXTAL1
RD#
TRLDV + 2TXTAL1
TAVDV + 2TXTAL1
AD15:0
(read)
Data
TWLWH + 2TXTAL1
WR#
TQVWH + 2TXTAL1
AD15:0
(write)
Data Out
BHE#, INST
A19:0
Extended Address Out
CSx#
A3256-01
Figure 9. READY Timing Diagram (Demultiplexed Bus Mode)
29
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.4 HOLD#/HLDA# Timing
Table 14. HOLD#/HLDA# Timings
Symbol
VCC = 2.7 V – 3.3V
Parameter
Min
THVCH
HOLD# Setup Time (to guarantee recognition at next clock)
83
Max
Units
ns
TCLHAL
CLKOUT Low to HLDA# Low
–15
15
ns
TCLBRL
CLKOUT Low to BREQ# Low
–15
15
ns
THALAZ
HLDA# Low to Address Float
33
ns
THALBZ
HLDA# Low to BHE#, INST, RD#, WR# Weakly Driven
25
ns
TCLHAH
CLKOUT Low to HLDA# High
–25
15
ns
TCLBRH
CLKOUT Low to BREQ# High
–25
25
ns
THAHAX
HLDA# High to Address No Longer Floating
–20
ns
THAHBV
HLDA# High to BHE#, INST, RD#, WR# Valid
–20
ns
CLKOUT
THVCH
THVCH
Hold Latency
HOLD#
TCLHAL
TCLHAH
HLDA#
TCLBRL
TCLBRH
BREQ#
THALAZ
THAHAX
A19:0, AD15:0
CSx#, BHE#,
INST, RD#, WR#
WRL#, WRH#
THALBZ
THAHBV
Weakly held inactive
TCLLH
ALE
Start of strongly driven ALE
A2460-03
Figure 10. HOLD#/HLDA# Timing Diagram
30
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.5 AC Characteristics — Serial Port, Shift Register Mode
Table 15. Serial Port Timing — Shift Register Mode
Symbol
VCC = 2.7 V – 3.3V
Parameter
Min
Serial Port Clock period
(BRR ≥ x002H)
(BRR = x001H) (Note 1)
TXLXL
Units
Max
6TXTAL1
4TXTAL1
ns
ns
ns
TQVXH
Output data setup to clock high
3TXTAL1 – 30
TXHQX
Output data hold after clock high
2TXTAL1 – 90
TXHQV
Next output data valid after clock high
TDVXH
Input data setup to clock high
TXHDX
Input data hold after clock high
TXHQZ
Last clock high to output float
ns
2TXTAL1 + 50
ns
2TXTAL1 + 50
ns
0
ns
5TXTAL1+ 30
ns
NOTE:
1. The minimum baud-rate register value for receptions is x002H and the minimum baud-rate register
value for transmissions is x001H.
TXLXL
TXD
TXHQV
TXLXH
RXD
(Out)
0
1
2
Valid
4
3
TDVXH
RXD
(In)
TXHQZ
TXHQX
TQVXH
7
6
5
TXHDX
Valid
Valid
Valid
Valid
Valid
Valid
Valid
A2080-02
Figure 11. Serial Port Waveform — Shift Register Mode
31
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.6 External Clock Drive
Table 16. External Clock Drive
Symbol
Parameter
1/TXLXL
Input frequency
Min
Max
Units
8
14
MHz
TXLXL
Period (TXTAL1)
71
125
ns
TXHXX
High Time
0.35TXTAL1
0.65TXTAL1
ns
TXLXX
Low Time
0.35TXTAL1
0.65TXTAL1
ns
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
TXHXX
TXHXL
TXLXH
0.7 VCC + 0.5 V
T
0.7 VCC + 0.5 V
XLXX
0.3 VCC – 0.5 V
0.3 VCC – 0.5 V
T
XLXL
A2119-02
Figure 12. External Clock Drive Waveforms
5.7 Test Output Waveforms
2.5 V
1.6 V
1.6 V
Test Points
0.25 V
0.5 V
0.5 V
AC testing inputs are driven at 2.5 V for a logic "1" and 0.25 V for
a logic "0". Timing measurements are made at 1.6 V for a logic
"1" and 0.5 V for a logic "0".
A2740-01
Figure 13. AC Testing Output Waveforms During 3.0 Volt Testing
32
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
VLOAD + 0.15 V
VOH – 0.15 V
Timing Reference
Points
VLOAD
VLOAD – 0.15 V
VOL + 0.15 V
For timing purposes, a port pin is no longer floating when a
150 mV change from load voltage occurs and begins to float
when a 150 mV change from the loading VOH/VOL level occurs
with IOL/IOH ≤10 mA.
A2739-01
Figure 14. Float Waveforms During 3.0 Volt Testing
33
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.0 THERMAL CHARACTERISTICS
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
will change depending on operating conditions and
the application. The Intel Packaging Handbook
(order number 240800) describes Intel’s thermal
impedance test methodology.
Table 17. Thermal Characteristics
θJA
θJC
100-pin SQFP
55°C/W
14°C/W
100-pin QFP
56°C/W
16°C/W
Package Type
7.0 8XL196NP ERRATA
Change identifiers have been used on embedded
products since 1990. The change identifier is the
last character in the FPO number. The FPO number
is typically a nine character number located on the
second line of the topside package mark. The
following errata listing is applicable to the B–step
(denoted by a “B” or “C” at the end of the topside
tracking number):
1.
Any jump, conditional jump, or call instruction
located within six bytes of the top of a page,
i.e., 0FFFA–0FFFFH, may cause a jump to the
wrong page. To ensure this problem does not
occur, place at least six NOPs at the top of
each page.
8.0 DATASHEET REVISION HISTORY
This datasheet is valid for devices with an “A” at the
end of the topside tracking number. Datasheets are
changed as new device information becomes
available. Verify with your local Intel sales office that
you have the latest version before finalizing a
design or ordering devices.
34