MICROCHIP 93C46C-E/MS

93AA46A/B/C, 93LC46A/B/C,
93C46A/B/C
1K Microwire Compatible Serial EEPROM
Device Selection Table
VCC Range
ORG Pin
Word Size
Temp Ranges
Packages
93AA46A
1.8-5.5
No
8-bit
I
P, SN, ST, MS, OT, MC
93AA46B
1.8-5-5
No
16-bit
I
P, SN, ST, MS, OT, MC
93LC46A
2.5-5.5
No
8-bit
I, E
P, SN, ST, MS, OT, MC
93LC46B
2.5-5.5
No
16-bit
I, E
P, SN, ST, MS, OT, MC
93C46A
4.5-5.5
No
8-bit
I, E
P, SN, ST, MS, OT, MC
Part Number
93C46B
4.5-5.5
No
16-bit
I, E
P, SN, ST, MS, OT, MC
93AA46C
1.8-5.5
Yes
8 or 16-bit
I
P, SN, ST, MS, MC
93LC46C
2.5-5.5
Yes
8 or 16-bit
I, E
P, SN, ST, MS, MC
93C46C
4.5-5.5
Yes
8 or 16-bit
I, E
P, SN, ST, MS, MC
Features:
Description:
• Low-power CMOS technology
• ORG pin to select word size for ‘46C’ version
• 128 x 8-bit organization ‘A’ version devices
(no ORG)
• 64 x 16-bit organization ‘B’ version devices
(no ORG)
• Self-timed erase/write cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power-on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device Status signal (Ready/Busy)
• Sequential read function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Temperature ranges supported:
The Microchip Technology Inc. 93XX46A/B/C devices
are 1K bit low-voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA46C, 93LC46C or 93C46C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA46A, 93LC46A or 93C46A devices are available,
while the 93AA46B, 93LC46B and 93C46B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for low
power, nonvolatile memory applications. The entire
93XX Series is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, 8-lead 2x3
DFN and 8-lead TSSOP. Pb-free (Pure Matte Sn) finish
is also available.
- Industrial (I)
-40°C to +85°C
- Automotive (E)
-40°C to +125°C
Pin Function Table
Name
Function
CS
Chip Select
CLK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
VSS
Ground
NC
No internal connection
ORG
Memory Configuration
VCC
Power Supply
© 2005 Microchip Technology Inc.
DS21749F-page 1
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Package Types (not to scale)
ROTATED SOIC
(ex: 93LC46BX)
NC
VCC
CS
CLK
PDIP/SOIC
(P, SN)
8 ORG*
7 VSS
6 DO
5 DI
1
2
3
4
CS
CLK
DI
DO
TSSOP/MSOP
(ST, MS)
CS
CLK
DI
DO
1
2
3
4
1
2
3
4
8
7
6
5
VCC
NC
ORG*
VSS
SOT-23
(OT)
8
7
6
5
VCC
NC
ORG*
VSS
DO
1
6
VCC
VSS
2
5
CS
DI
3
4
CLK
DFN
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG*
VSS
* ORG pin is NC on A/B devices
DS21749F-page 2
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Param.
No.
Symbol
Parameter
Industrial (I):
TA = -40°C to +85°C, VCC = +1.8V TO +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V TO +5.5V
Min
Typ
Max
Units
Conditions
D1
VIH1
VIH2
High-level input voltage
2.0
0.7 VCC
—
—
VCC +1
VCC +1
V
V
VCC ≥ 2.7V
VCC < 2.7V
D2
VIL1
VIL2
Low-level input voltage
-0.3
-0.3
—
—
0.8
0.2 VCC
V
V
VCC ≥ 2.7V
VCC < 2.7V
D3
VOL1
VOL2
Low-level output voltage
—
—
—
—
0.4
0.2
V
V
IOL = 2.1 mA, VCC = 4.5V
IOL = 100 μA, VCC = 2.5V
D4
VOH1
VOH2
High-level output voltage
2.4
VCC - 0.2
—
—
—
—
V
V
IOH = -400 μA, VCC = 4.5V
IOH = -100 μA, VCC = 2.5V
D5
ILI
Input leakage current
—
—
±1
μA
VIN = VSS or VCC
D6
ILO
Output leakage current
—
—
±1
μA
VOUT = VSS or VCC
D7
CIN,
COUT
Pin capacitance
(all inputs/outputs)
—
—
7
pF
VIN/VOUT = 0V (Note 1)
TA = 25°C, FCLK = 1 MHz
D8
ICC
write
Write current
—
—
—
500
2
—
mA
μA
FCLK = 3 MHz, VCC = 5.5V
FCLK = 2 MHz, VCC = 2.5V
D9
ICC read Read current
—
—
—
—
—
100
1
500
—
mA
μA
μA
FCLK = 3 MHz, VCC = 5.5V
FCLK = 2 MHz, VCC = 3.0V
FCLK = 2 MHz, VCC = 2.5V
D10
ICCS
Standby current
—
—
—
—
1
5
μA
μA
I-Temp
E-Temp
CLK = CS = 0V
ORG = DI = VSS or VCC
(Note 2) (NOTE 3)
D11
VPOR
VCC voltage detect
—
—
1.5
3.8
—
—
V
V
(Note 1)
93AA46A/B/C, 93LC46A/B/C
93C46A/B/C
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG pin not available on ‘A’ or ‘B’ versions.
3: Ready/Busy status must be cleared from DO, see Section 3.4 "Data Out (DO)".
© 2005 Microchip Technology Inc.
DS21749F-page 3
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
TABLE 1-2:
AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Param.
No.
Symbol
Parameter
Industrial (I):
TA = -40°C to +85°C, VCC = +1.8V TO +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V TO +5.5V
Min
Max
Units
Conditions
A1
FCLK
Clock frequency
—
3
2
1
MHz
MHz
MHz
4.5V ≤ VCC < 5.5V, 93XX46C only
2.5V ≤ VCC < 5.5V
1.8V ≤ VCC < 2.5V
A2
TCKH
Clock high time
200
250
450
—
ns
ns
ns
4.5V ≤ VCC < 5.5V, 93XX46C only
2.5V ≤ VCC < 5.5V
1.8V ≤ VCC < 2.5V
A3
TCKL
Clock low time
100
200
450
—
ns
ns
ns
4.5V ≤ VCC < 5.5V, 93XX46C only
2.5V ≤ VCC < 5.5V
1.8V ≤ VCC < 2.5V
A4
TCSS
Chip Select setup time
50
100
250
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
A5
TCSH
Chip Select hold time
0
—
ns
1.8V ≤ VCC < 5.5V
A6
TCSL
Chip Select low time
250
—
ns
1.8V ≤ VCC < 5.5V
A7
TDIS
Data input setup time
50
100
250
—
ns
4.5V ≤ VCC < 5.5V, 93XX46C only
2.5V ≤ VCC < 5.5V
1.8V ≤ VCC < 2.5V
A8
TDIH
Data input hold time
50
100
250
—
ns
4.5V ≤ VCC < 5.5V, 93XX46C only
2.5V ≤ VCC < 5.5V
1.8V ≤ VCC < 2.5V
A9
TPD
Data output delay time
—
—
—
200
250
400
ns
4.5V ≤ VCC < 5.5V, CL = 100 pF
2.5V ≤ VCC < 4.5V, CL = 100 pF
1.8V ≤ VCC < 2.5V, CL = 100 pF
A10
TCZ
Data output disable time
—
—
100
200
ns
4.5V ≤ VCC < 5.5V, (Note 1)
1.8V ≤ VCC < 4.5V, (Note 1)
A11
TSV
Status valid time
—
200
300
500
ns
4.5V ≤ VCC < 5.5V, CL = 100 pF
2.5V ≤ VCC < 4.5V, CL = 100 pF
1.8V ≤ VCC < 2.5V, CL = 100 pF
A12
TWC
Program cycle time
—
6
ms
Erase/Write mode (AA and LC
versions)
A13
TWC
—
2
ms
Erase/Write mode (93C versions)
A14
TEC
—
6
ms
ERAL mode, 4.5V ≤ VCC ≤ 5.5V
A15
TWL
—
15
ms
WRAL mode, 4.5V ≤ VCC ≤ 5.5V
A16
—
1M
—
Endurance
cycles 25°C, VCC = 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which may be obtained from Microchip’s web site
at www.microchip.com.
DS21749F-page 4
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
FIGURE 1-1:
CS
SYNCHRONOUS DATA TIMING
VIH
TCSS
VIL
TCKH
TCKL
TCSH
VIH
CLK
VIL
TDIS
TDIH
VIH
DI
VIL
TPD
TPD
DO
(Read)
DO
(Program)
Note:
TCZ
VOH
TCZ
VOL
TSV
VOH
Status Valid
VOL
TSV is relative to CS.
TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
A5
A4
A3
A2
A1
A0
—
(RDY/BSY)
9
ERAL
1
00
1
0
X
X
EWDS
1
00
0
0
X
X
X
X
—
(RDY/BSY)
9
X
X
—
High-Z
9
EWEN
1
00
1
1
X
X
READ
1
10
A5
A4
A3
A2
X
X
—
High-Z
9
A1
A0
—
D15 - D0
25
WRITE
1
01
A5
A4
A3
A2
A1
A0
D15 - D0
(RDY/BSY)
25
WRAL
1
00
0
1
X
X
X
X
D15 - D0
(RDY/BSY)
25
TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
A6 A5 A4 A3 A2 A1 A0
—
(RDY/BSY)
10
ERAL
1
00
1
0
X
X
X
X
X
—
(RDY/BSY)
10
EWDS
1
00
0
0
X
X
X
X
X
—
High-Z
10
EWEN
1
00
1
1
X
X
X
X
X
—
High-Z
10
READ
1
10
A6 A5 A4 A3 A2 A1 A0
—
D7 - D0
18
WRITE
1
01
A6 A5 A4 A3 A2 A1 A0
D7 - D0
(RDY/BSY)
18
WRAL
1
00
D7 - D0
(RDY/BSY)
18
© 2005 Microchip Technology Inc.
0
1
X
X
X
X
X
DS21749F-page 5
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.0
FUNCTIONAL DESCRIPTION
When the ORG pin (93XX46C) is connected to VCC,
the (x16) organization is selected. When it is connected
to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI
pin on the rising edge of the clock (CLK). The DO pin is
normally held in a High-Z state except when reading
data from the device, or when checking the Ready/
Busy status during a programming operation. The
Ready/Busy status can be verified during an erase/
write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
2.1
Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
2.3
All modes of operation are inhibited when VCC is below
a typical voltage of 1.5V for '93AA' and '93LC' devices
or 3.8V for '93C' devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note:
Block Diagram
VCC
2.2
Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
DS21749F-page 6
VSS
Address
Decoder
Memory
Array
Address
Counter
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.
For added protection, an EWDS
command should be performed after
every write operation and an external 10
kΩ pull-down protection resistor should be
added to the CS pin.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
Note:
Data Protection
Data Register
Output
Buffer
DO
DI
ORG*
CS
CLK
Mode
Decode
Logic
Clock
Register
*ORG input is not available on A/B devices
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.4
Erase
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. CS is brought
low following the loading of the last address bit. This
falling edge of the CS pin initiates the self-timed
programming cycle, except on ‘93C’ devices where the
rising edge of CLK before the last address bit initiates
the write cycle.
FIGURE 2-1:
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
ERASE TIMING FOR 93AA AND 93LC DEVICES
TCSL
CS
Check Status
CLK
1
DI
1
1
AN
AN-1 AN-2
•••
A0
TCZ
TSV
DO
High-Z
Busy
Ready
High-Z
TWC
FIGURE 2-2:
ERASE TIMING FOR 93C DEVICES
TCSL
CS
Check Status
CLK
1
DI
1
1
AN
AN-1 AN-2
•••
A0
TCZ
TSV
DO
High-Z
Busy
Ready
High-Z
TWC
© 2005 Microchip Technology Inc.
DS21749F-page 7
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.5
Erase All (ERAL)
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL).
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
FIGURE 2-3:
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be ≥ 4.5V for proper operation of ERAL.
ERAL TIMING FOR 93AA AND 93LC DEVICES
TCSL
CS
Check Status
CLK
DI
1
0
0
1
0
x
•••
x
TCZ
TSV
DO
High-Z
Busy
Ready
High-Z
TEC
VCC must be ≥ 4.5V for proper operation of ERAL.
FIGURE 2-4:
ERAL TIMING FOR 93C DEVICES
TCSL
CS
Check Status
CLK
DI
1
0
0
1
0
x
•••
x
TCZ
TSV
DO
High-Z
Busy
Ready
High-Z
TEC
DS21749F-page 8
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.6
Erase/Write Disable and Enable
(EWDS/EWEN)
To protect against accidental data disturbance, the EWDS
instruction can be used to disable all erase/write functions
and should follow all programming operations. Execution
of a READ instruction is independent of both the EWEN and
EWDS instructions.
The 93XX46A/B/C powers up in the Erase/Write Disable
(EWDS) state. All Programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed or
Vcc is removed from the device.
FIGURE 2-5:
EWDS TIMING
TCSL
CS
CLK
1
DI
FIGURE 2-6:
0
0
0
0
•••
x
x
EWEN TIMING
TCSL
CS
CLK
2.7
0
1
DI
0
1
1
•••
x
Read
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (TPD).
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (if ORG pin is low or A-Version
devices) or 16-bit (if ORG pin is high or B-version
devices) output string.
FIGURE 2-7:
x
READ TIMING
CS
CLK
DI
DO
1
1
0
High-Z
© 2005 Microchip Technology Inc.
An
•••
A0
0
Dx
•••
D0
Dx
•••
D0
Dx
•••
D0
DS21749F-page 9
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.8
Write
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
The WRITE instruction is followed by 8 bits (if ORG is
low or A-version devices) or 16 bits (if ORG pin is high
or B-version devices) of data which are written into the
specified address. For 93AA46A/B/C and 93LC46A/B/C
devices, after the last data bit is clocked into DI, the
falling edge of CS initiates the self-timed auto-erase and
programming cycle. For 93C46A/B/C devices, the selftimed auto-erase and programming cycle is initiated by
the rising edge of CLK on the last data bit.
FIGURE 2-8:
Note:
After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/Busy status from DO.
WRITE TIMING FOR 93AA AND 93LC DEVICES
TCSL
CS
CLK
DI
1
0
1
An
•••
A0
Dx
•••
D0
TSV
High-Z
DO
Busy
TCZ
Ready
High-Z
TWC
FIGURE 2-9:
WRITE TIMING FOR 93C DEVICES
TCSL
CS
CLK
DI
1
0
1
An
•••
A0
Dx
•••
D0
TSV
DO
High-Z
Busy
TCZ
Ready
High-Z
TWC
DS21749F-page 10
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.9
Write All (WRAL)
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA46A/B/C and 93LC46A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C46A/B/C devices, the self-timed autoerase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
FIGURE 2-10:
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be ≥ 4.5V for proper operation of WRAL.
WRAL TIMING FOR 93AA AND 93LC DEVICES
TCSL
CS
CLK
DI
1
0
0
0
1
x
•••
x
Dx
•••
D0
TSV
High-Z
DO
Busy
TCZ
Ready
HIGH-Z
TWL
VCC must be ≥ 4.5V for proper operation of WRAL.
FIGURE 2-11:
WRAL TIMING FOR 93C DEVICES
TCSL
CS
CLK
DI
1
0
0
0
1
x
•••
x
Dx
•••
D0
TSV
DO
High-Z
Busy
TCZ
Ready
HIGH-Z
TWL
© 2005 Microchip Technology Inc.
DS21749F-page 11
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
3.0
PIN DESCRIPTIONS
TABLE 3-1:
PIN DESCRIPTIONS
SOIC/PDIP/
MSOP/
TSSOP/DFN
SOT-23
Rotated SOIC
CS
1
5
3
Chip Select
CLK
2
4
4
Serial Clock
DI
3
3
5
Data In
DO
4
1
6
Data Out
Vss
5
2
7
Ground
ORG/NC
6
—
8
Organization / 93XX46C
No Internal Connection / 93XX46A/B
NC
7
—
1
No Internal Connection
VCC
8
6
2
Power Supply
Name
3.1
Chip Select (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communication between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
CLK is a “don't care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become “don't care” inputs waiting for a new Start
condition to be detected.
DS21749F-page 12
Function
3.3
Data In (DI)
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4
Data Out (DO)
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (TPD after the
positive edge of CLK).
This pin also provides Ready/Busy status information
during erase and write cycles. Ready/Busy status information is available on the DO pin if CS is brought high
after being low for minimum Chip Select low time (TCSL)
and an erase or write operation has been initiated.
The Status signal is not available on DO, if CS is held
low during the entire erase or write cycle. In this case,
DO is in the High-Z mode. If status is checked after the
erase/write cycle, the data line will be high to indicate
the device is ready.
Note:
3.5
After a programming cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
Organization (ORG)
When the ORG pin is connected to VCC or Logic HI, the
(x16) memory organization is selected. When the ORG
pin is tied to VSS or Logic LO, the (x8) memory
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX46A devices are always x8 organization and
93XX46B devices are always x16 organization.
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
8-Lead MSOP (150 mil)
XXXXXXT
YWWNNN
6-Lead SOT-23
XXNN
Example:
3L46BI
5281L7
Example:
1EL7
8-Lead PDIP
Example:
XXXXXXXX
T/XXXNNN
YYWW
93LC46B
I/P e3 1L7
0528
8-Lead SOIC
Example:
XXXXXXXT
XXXXYYWW
NNN
93LC46BI
SN e3 0528
1L7
8-Lead TSSOP
Example:
XXXX
TYWW
NNN
8-Lead 2x3 DFN
XXX
YWW
NN
© 2005 Microchip Technology Inc.
L46B
I528
1L7
Example:
314
528
L7
DS21749F-page 13
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
1st Line Marking Codes
Part Number
SOT-23
TSSOP
DFN
MSOP
I Temp.
E Temp.
I Temp.
E Temp.
93AA46A
A46A
3A46AT
1BNN
—
301
—
93AA46B
A46B
3A46BT
1LNN
—
311
—
93AA46C
A46C
3A46CT
—
—
321
—
93LC46A
L46A
3L46AT
1ENN
1FNN
304
305
93LC46B
L46B
3L46BT
1PNN
1RNN
314
315
93LC46C
L46C
3L46CT
—
—
324
325
93C46A
C46A
3C46AT
1HNN
1JNN
307
308
93C46B
C46B
3C46BT
1TNN
1UNN
317
318
C46C
3C46CT
—
—
327
328
93C46C
Note:
T = Temperature grade (I, E)
NN = Alphanumeric traceability code
Legend: XX...X
T
Y
YY
WW
NNN
e3
Note:
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note:
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
DS21749F-page 14
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
n
p
MIN
INCHES
NOM
MAX
MILLIMETERS*
NOM
8
0.65 BSC
0.75
0.85
0.00
4.90 BSC
3.00 BSC
3.00 BSC
0.40
0.60
0.95 REF
0°
0.08
0.22
5°
5°
-
MIN
8
Number of Pins
Pitch
.026 BSC
A
.043
Overall Height
A2
Molded Package Thickness
.030
.033
.037
A1
.000
.006
Standoff
E
Overall Width
.193 TYP.
E1
.118 BSC
Molded Package Width
D
.118 BSC
Overall Length
L
.016
.024
.031
Foot Length
Footprint (Reference)
F
.037 REF
φ
0°
8°
Foot Angle
c
.003
.006
.009
Lead Thickness
B
.009
.012
.016
Lead Width
α
5°
15°
Mold Draft Angle Top
β
5°
15°
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.40
15°
15°
JEDEC Equivalent: MO-187
Drawing No. C04-111
© 2005 Microchip Technology Inc.
DS21749F-page 15
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
6-Lead Plastic Small Outline Transistor (OT) (SOT-23)
E
E1
B
p1
n
D
1
α
c
A
A2
φ
L
β
Units
Dimension Limits
n
p
MIN
A1
INCHES*
NOM
MAX
MILLIMETERS
NOM
6
0.95
1.90
0.90
1.18
0.90
1.10
0.00
0.08
2.60
2.80
1.50
1.63
2.80
2.95
0.35
0.45
0
5
0.09
0.15
0.35
0.43
0
5
0
5
MIN
Number of Pins
6
Pitch
.038
p1
Outside lead pitch (basic)
.075
Overall Height
A
.035
.046
.057
Molded Package Thickness
.035
.043
.051
A2
Standoff
.000
.003
.006
A1
Overall Width
E
.102
.110
.118
Molded Package Width
.059
.064
.069
E1
Overall Length
D
.110
.116
.122
Foot Length
L
.014
.018
.022
φ
Foot Angle
0
5
10
c
Lead Thickness
.004
.006
.008
Lead Width
B
.014
.017
.020
α
Mold Draft Angle Top
0
5
10
β
Mold Draft Angle Bottom
0
5
10
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
MAX
1.45
1.30
0.15
3.00
1.75
3.10
0.55
10
0.20
0.50
10
10
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
DS21749F-page 16
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
c
§
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2005 Microchip Technology Inc.
DS21749F-page 17
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21749F-page 18
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
A1
A2
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
φ
c
B
α
β
MIN
INCHES
NOM
MAX
8
.026
.033
.002
.246
.169
.114
.020
0
.004
.007
0
0
.035
.004
.251
.173
.118
.024
4
.006
.010
5
5
.043
.037
.006
.256
.177
.122
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
8
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
2.90
3.00
3.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
© 2005 Microchip Technology Inc.
DS21749F-page 19
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated
p
D
b
n
L
E
PIN 1
ID INDEX
AREA
(NOTE 2)
E2
EXPOSED
METAL
PAD
2
1
D2
BOTTOM VIEW
TOP VIEW
A
A1
A3
EXPOSED
TIE BAR
(NOTE 1)
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Contact Width
Contact Length
Units
Dimension Limits
n
p
(Note 3)
(Note 3)
A
A1
A3
D
D2
E
E2
b
L
MIN
.031
.000
.055
.047
.008
.012
INCHES
NOM
8
.020 BSC
.035
.001
.008 REF.
.079 BSC
-.118 BSC
-.010
.016
MAX
MIN
.039
.002
0.80
0.00
.064
1.39
.071
.012
.020
1.20
0.20
0.30
MILLIMETERS*
NOM
8
0.50 BSC
0.90
0.02
0.20 REF.
2.00 BSC
-3.00 BSC
-0.25
0.40
MAX
1.00
0.05
1.62
1.80
0.30
0.50
*Controlling Parameter
Notes:
1. Package may have one or more exposed tie bars at ends.
2. Pin 1 visual index feature may vary, but must be located within the hatched area.
3. Exposed pad dimensions vary with paddle size.
4. JEDEC equivalent: MO-229
Drawing No. C04-123
DS21749F-page 20
Revised 05/24/04
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
APPENDIX A:
REVISION HISTORY
Revision D
Corrections to Section 1.0, Electrical Characteristics.
Section 4.1, 6-Lead SOT-23 package to OT.
Revision E
Added DFN package.
Revision F
Added notes throughout.
© 2005 Microchip Technology Inc.
DS21749F-page 21
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
NOTES:
DS21749F-page 22
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
In addition, there is a Development Systems
Information Line which lists the latest versions of
Microchip’s development systems software products.
This line also provides information on how customers
can receive currently available upgrade kits.
The Development
numbers are:
Systems
Information
Line
1-800-755-2345 – United States and most of Canada
1-480-792-7302 – Other International Locations
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2005 Microchip Technology Inc.
DS21749F-page 23
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
Literature Number: DS21749F
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21749F-page 24
© 2005 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
X
Pinout Tape & Reel Temperature
Range
Device:
/XX
X
Package
X
Lead Finish
93AA46A: 1K 1.8V Microwire Serial EEPROM
93AA46B: 1K 1.8V Microwire Serial EEPROM
93AA46C: 1K 1.8V Microwire Serial EEPROM w/ORG
93LC46A: 1K 2.5V Microwire Serial EEPROM
93LC46B: 1K 2.5V Microwire Serial EEPROM
93LC46C: 1K 2.5V Microwire Serial EEPROM w/ORG
93C46A:
93C46B:
93C46C:
Pinout:
1K 5.0V Microwire Serial EEPROM
1K 5.0V Microwire Serial EEPROM
1K 5.0V Microwire Serial EEPROM w/ORG
Blank =
X
=
Standard pinout
Rotated pinout
Blank =
T
=
Standard packaging
Tape & Reel
Temperature Range:
I
E
=
=
-40°C to +85°C
-40°C to +125°C
Package:
MS
OT
P
SN
ST
MC
=
=
=
=
=
=
Plastic MSOP (Micro Small outline, 8-lead)
SOT-23, 6-lead (Tape & Reel only)
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
TSSOP, 8-lead
2x3 DFN, 8-lead
Lead Finish:
Blank =
G
=
Tape & Reel:
Note:
Examples:
a)
b)
c)
93AA46C-I/MS: 1K, 128x8 or 64x16 Serial
EEPROM, MSOP package, 1.8V
93AA46B-I/MS: 1K, 64x16 Serial EEPROM,
MSOP package, 1.8V
93AA46AT-I/OT: 1K, 128x8 Serial EEPROM,
SOT-23 package, tape and reel, 1.8V
d)
93AA46CT-I/MS: 1K, 128x8 or 16x16 Serial
EEPROM, MSOP package, tape and reel, 1.8V
a)
93LC46A-I/MS: 1K, 128x8 Serial EEPROM,
MSOP package, 2.5V
93LC46BT-I/OT: 1K, 64x16 Serial EEPROM,
SOT-23 package, tape and reel, 2.5V
93LC46B-I/MS: 1K, 64x16 Serial EEPROM,
MSOP package, 2.5V
b)
c)
a)
b)
c)
93C46B-I/MS: 1K, 64x16 Serial EEPROM,
MSOP package, 5.0V
93C46C-I/MS: 1K, 128x8 or 16x16 Serial
EEPROM, MSOP package, 5.0V
93C46AT-I/OT: 1K, 128x8 Serial EEPROM,
SOT-23 package, tape and reel, 5.0V
Pb-free – Matte Tin (see Note 1)
Pb-free – Matte Tin only
Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products manufactured
before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb).
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion, including conversion date codes.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences
and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of
the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
© 2005 Microchip Technology Inc.
DS21749F-page 25
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
NOTES:
DS21749F-page 26
© 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,
Smart Serial, SmartTel, Total Endurance and WiperLock are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005 Microchip Technology Inc.
DS21749F-page 27
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
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Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
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Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
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Tel: 86-10-8528-2100
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Tel: 91-11-5160-8631
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Fax: 82-2-558-5932 or
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Toronto
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Canada
Tel: 905-673-0699
Fax: 905-673-6509
04/20/05
DS21749F-page 28
© 2005 Microchip Technology Inc.