DATASHEET ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Description Features/Benefits The ICS9EX21801 provides 18 output clocks for PCIe Gen2 (100MHz) or QPI (133MHz) applications. The 9EX21801 has 4 selectable SMBus addresses, and dedicated CKPWRGD/PD# and VDDA pins for easy board design. A differential CPU clock from a CK410B+ main clock generator, such as the ICS932S421, drives the ICS9EX21801. In fanout mode, the 9EX21801 provides outputs up to 400MHz. • • • • Supports output clock frequencies up to 400 MHz 4 Selectable SMBus addresses SMBus address is independent of PLL operating mode Dedicated CKPWRGD/PD# and VDDA pins ease board design Key Specifications • • • • DIF output cycle-to-cycle jitter < 50ps DIF output-to-output skew < 150 ps PCIe Gen2 compliant phase noise QPI 133MHz compliant phase noise Funtional Block Diagram OE(17:15)# OE(14:5)#, OE_01234# 12 CLKA_IN CLKA_IN# PLL (SS Compatible) 18 DIF(17:0) CLKB_IN CLKB_IN# HIBW_BYPM_LOBW# 100M_133M# CKPWRGD/PD# SMB_A0 SMB_A1 SEL_A_B# SMBDAT SMBCLK Logic IREF IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 1 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux VDD OE7# DIF_7 DIF_7# OE8# DIF_8 DIF_8# HIBW_BYPM_LOBW# SMBCLK SMBDAT SMB_A1 SMB_A0 SEL_A_B# CKPWRGD/PD# DIF_9 DIF_9# OE9# Pin Configuration 100M_133M# Datasheet 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDD OE10# DIF_10 DIF_10# OE11# DIF_11 DIF_11# OE12# DIF_12 DIF_12# GND VDD DIF_13 DIF_13# OE13# DIF_14 DIF_14# OE14# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 9EX21801AKLF DIF_6# DIF_6 OE6# DIF_5# DIF_5 OE5# DIF_4# DIF_4 DIF_3# DIF_3 GND VDD DIF_2# DIF_2 DIF_1# DIF_1 DIF_0# DIF_0 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 OE_01234# VDD CLKB_IN# CLKB_IN GND CLKA_IN# CLKA_IN VDDA GNDA IREF DIF_17# DIF_17 DIF_16# DIF_16 OE15_17# VDD DIF_15# DIF_15 72-pin MLF Frequency/Functionality Table Power Groups Byte 0, bit 2 (100_133M# Latch) Byte 0, bit 1 FSB Byte 0, bit 0 FSA Input MHz 1 0 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 0 100.00 133.33 166.67 200.00 266.67 333.33 400.00 1 1 1 DIF_x MHz 100.00 133.33 166.67 200.00 266.67 333.33 400.00 Reserved Pin Number VDD GND 29 28 1,12,21,35,43,55 11,32,44 Notes 1 1 2 2 2 2 2 INPUTS CKPWRGD/PD# Input 1 Running 0 X OUTPUTS DIF_x Running Hi-Z PLL State ON OFF SMBus Address Selection (pins 66, 67) SMB_A1 0 0 1 1 HIBW_BYPM_LOBW# Selection (Pin 63) Voltage <0.8V 1.2<Vin<1.8V Vin > 2.0V Main PLL, Analog DIF clocks Power Down Functionality Notes:100M_133M# 1. Latch selects between 100 and 133 MHz. This is equivalent to FSC in CK410B+/CK509B FS table. 2. Writing Byte 0 bits (2:0) can select other frequencies. These frequencies are not characterized in PLL Mode State Low Mid High Description Mode Low BW Bypass High BW IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux SMB_A0 0 1 0 1 Address D4 D6 D8 DA 1463B — 01/20/10 2 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Datasheet Pin Description PIN # PIN NAME 1 VDD 2 OE10# 3 4 DIF_10 DIF_10# 5 OE11# 6 7 DIF_11 DIF_11# 8 OE12# 9 10 11 12 13 14 DIF_12 DIF_12# GND VDD DIF_13 DIF_13# 15 OE13# 16 17 DIF_14 DIF_14# 18 OE14# 19 20 21 DIF_15 DIF_15# VDD 22 OE15_17# 23 24 25 26 DIF_16 DIF_16# DIF_17 DIF_17# 27 IREF 28 29 30 31 32 33 34 35 GNDA VDDA CLKA_IN CLKA_IN# GND CLKB_IN CLKB_IN# VDD 36 OE_01234# PIN TYPE DESCRIPTION PWR Power supply, nominal 3.3V Active low input for enabling DIF pair 10. IN 1 = tri-state outputs, 0 = enable outputs OUT 0.7V differential true clock output OUT 0.7V differential complement clock output Active low input for enabling DIF pair 11. IN 1 = tri-state outputs, 0 = enable outputs OUT 0.7V differential true clock output OUT 0.7V differential complement clock output Active low input for enabling DIF pair 12. IN 1 = tri-state outputs, 0 = enable outputs OUT 0.7V differential true clock output OUT 0.7V differential complement clock output PWR Ground pin. PWR Power supply, nominal 3.3V OUT 0.7V differential true clock output OUT 0.7V differential complement clock output Active low input for enabling DIF pair 13. IN 1 = tri-state outputs, 0 = enable outputs OUT 0.7V differential true clock output OUT 0.7V differential complement clock output Active low input for enabling DIF pair 14. IN 1 = tri-state outputs, 0 = enable outputs OUT 0.7V differential true clock output OUT 0.7V differential complement clock output PWR Power supply, nominal 3.3V Active low input for enabling DIF pairs 15, 16 and 17 IN 1 = tri-state outputs, 0 = enable outputs OUT 0.7V differential true clock output OUT 0.7V differential complement clock output OUT 0.7V differential true clock output OUT 0.7V differential complement clock output This pin establishes the reference current for the differential current-mode output pairs. This pin OUT requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. PWR Ground pin for the PLL core. PWR 3.3V power for the PLL core. IN True Input for differential reference clock. IN Complement Input for differential reference clock. PWR Ground pin. IN True Input for differential reference clock. IN Complement Input for differential reference clock. PWR Power supply, nominal 3.3V Active low input for enabling DIF pairs 0, 1, 2, 3 and 4. IN 1 = tri-state outputs, 0 = enable outputs IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 3 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Datasheet Pin Description (continued) PIN # 37 38 39 40 41 42 43 44 45 46 47 48 PIN NAME DIF_0 DIF_0# DIF_1 DIF_1# DIF_2 DIF_2# VDD GND DIF_3 DIF_3# DIF_4 DIF_4# PIN TYPE OUT OUT OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT 49 OE5# IN 50 51 DIF_5 DIF_5# 52 OE6# 53 54 55 DIF_6 DIF_6# VDD 56 OE7# 57 58 DIF_7 DIF_7# 59 OE8# 60 61 DIF_8 DIF_8# 62 100M_133M# IN 63 HIBW_BYPM_LOBW# IN 64 65 66 67 SMBCLK SMBDAT SMB_A1 SMB_A0 IN I/O IN IN 68 SEL_A_B# IN 69 CKPWRGD/PD# IN 70 71 DIF_9 DIF_9# 72 OE9# OUT OUT IN OUT OUT PWR IN OUT OUT IN OUT OUT OUT OUT IN DESCRIPTION 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 5. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 6. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Active low input for enabling DIF pair 7. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 8. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Input to select operating frequency 0 = 133MHz (QPI), 1 = 100.00MHz (PCIe Gen2) Trilevel input to select High BW, Bypass Mode or Low BW. 0 = Low BW Mode, Mid= Bypass Mode, 1 = High Bandwidth Clock pin of SMBUS circuitry, 5V tolerant Data pin of SMBUS circuitry, 5V tolerant SMBus address bit 1 SMBus address bit 0 (LSB) Input to select differential input clock A or differential input clock B. 0 = Input B selected, 1 = Input A selected. Notifies the clock to sample latched inputs on the rising edge, and to power down on the falling edge. 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 9. 1 = tri-state outputs, 0 = enable outputs IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 4 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Datasheet Absolute Maximum Ratings PARAMETER 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection SYMBOL CONDITIONS MIN TYP MAX UNITS Notes VDD_A GND - 0.5 VDD + 0.5 V VDD Ts Tambient Tcase ESD prot GND - 0.5 -65 0 VDD + 0.5 150 70 115 V ° C °C °C V Human Body Model 2000 1 1 1 1 1 1 Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V Input Low Voltage Input High Current VIL I IH 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors GND - 0.3 -5 0.8 5 V uA -5 uA I IL2 VIN = 0 V; Inputs with pull-up resistors -200 uA Digital Supply Current I DD3.3D Full Active, CL = Full load; 450 mA 1 Analog Supply Current I DD3.3A Full Active, CL = Full load; 40 mA 1 I DD3.3DPD all differential pairs tri-stated 15 mA 1 I DD3.3APD all differential pairs tri-stated 20 mA 1 FiPLL FiBYPASS Lpin CIN COUT PLL Mode Bypass Mode 80 33 Logic Inputs Output pin capacitance From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 1.5 150 400 7 5 6 MHz MHz nH pF pF 1 1 1 1 1 1 ms 1 Triangular Modulation 30 33 kHz 1,3 4 12 cycles 1,2 300 us 1,2 5 5 ns ns 1 I IL1 Input Low Current Digital Powerdown Current Analog Powerdown Current Input Frequency Pin Inductance Capacitance Clk Stabilization TSTAB Allowable Spread Modulation Frequency fMOD OE# Latency t LATOE# Tdrive_PD t DRVPD Tfall Trise tF tR DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD de-assertion Fall time of OE# Rise time of OE# TYP MAX UNITS NOTES 1 Guaranteed by design and characterization, not 100% tested in production. Time from deassertion until outputs are >200 mV 3 For which spread spectrum tracking error spec will be met. 2 IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 5 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Datasheet Electrical Characteristics - Clock Input Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage DIF_IN Input Low Voltage DIF_IN Input Common Mode Voltage - DIF_IN SYMBOL VIHDIF VILDIF CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) MIN TYP MAX UNITS NOTES 600 800 1150 mV 1 VSS - 300 0 300 mV 1 VCOM Common Mode Input Voltage 300 1000 mV 1 Input Amplitude - DIF_IN VSWING Peak to Peak value 300 1450 mV 1 Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2 Input Leakage Current IIN -5 5 uA 1 Input Duty Cycle dtin VIN = VDD , VIN = GND Measurement from differential wavefrom 45 55 % 1 Input Jitter - Cycle to Cycle JDIFIn 0 125 ps 1 1 Differential Measurement Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - DIF 0.7V Current Mode Differential Pairs TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, RREF=475Ω, 10 inch transmission lines PARAMETER SYMBOL CONDITIONS MIN Current Source Output Impedance Zo1 VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. 660 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Rise Time Fall Time Rise Time Variation Fall Time Variation Vovs Vuds Vcross(abs) d-Vcross ppm tr tf d-tr d-tf Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V Measurement from differential wavefrom PLL mode Jitter, Cycle to cycle t jcyc-cyc BYPASS mode as additive jitter 1 Guaranteed by design and characterization, not 100% tested in production. Duty Cycle dt3 TYP MAX UNITS NOTES Ω 850 1 1,3 mV -150 150 1150 -300 250 175 175 45 1,3 550 140 0 700 700 125 125 mV mV ppm ps ps ps ps 1 1 1 1 1,2 1 1 1 1 55 % 1 50 50 ps ps 1,5 1,4 mV 2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK509B accuracy requirements. The 9EX21801 itself does not contribute to ppm error. 3 4 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. I OH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. Applies to Bypass Mode Only IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 6 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Datasheet Electrical Characteristics - Skew and Differential Jitter Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% Group Parameter CLK_IN, DIF[x:0] tSPO_PLL100M CLK_IN, DIF[x:0] tSPO_PLL133M CLK_IN, DIF[x:0] tPD_BYP CLK_IN, DIF [x:0] ∆tSPO_PLL Input-to-Output Skew Variation in PLL mode (over specified voltage / temperature operating ranges) CLK_IN, DIF [x:0] ∆tPD_BYP DIF[17:0] tSKEW_A19 DIF[17:0] tJPH DIF[17:0] tSSTERROR Description Input-to-Output Skew in PLL mode (1:1 only), nominal value @ 25°C, 3.3V, 100MHz Input-to-Output Skew in PLL mode (1:1 only), nominal value @ 25°C, 3.3V, 133MHz Input-to-Output Skew in Bypass mode (1:1 only), nominal value @ 25°C, 3.3V Min TYP 950 1100 Units Notes 1000 1125 ps 1,2,4,5,8 1125 1175 ps 1,2,4,5,8 ns 1,2,3,5 |250| |350| ps 1,2,4,5,6, 10 Input-to-Output Skew Variation in Bypass mode (over specified voltage / temperature operating ranges) |800| |900| ps 1,2,3,4,5, 6,10 Output-to-Output Skew across all 18 outputs (Common to Bypass and PLL mode - all outputs at same gear) 100 150 ps 1,2,3 Differential Phase Jitter (RMS Value) 2 10 ps 1,4,7 Differential Spread Spectrum Tracking Error (peak to peak) 20 80 ps 1,4,9 4 4.7 Max 5.2 NOTES: 1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 2. Measured from differential cross-point to differential cross-point 3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 4. This parameter is deterministic for a given device 5. Measured with scope averaging on to find mean value. 6. Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device. 7. This parameter is measured at the outputs of two separate ICS9EX21801 devices driven by a single CK410B+. The ICS9EX21801's must be set to high bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the affects of spread spectrum). Target ranges of consideration are agents with BW of 1-22Mhz and 11-33Mhz. 8. t is the period of the input clock 9. Differential spread spectrum tracking error is the difference in spread spectrum tracking between two ICS9EX21801 devices This parameter is measured at the outputs of two separate ICS9EX21801 devices driven by a single CK410B+ in Spread Spectrum mode. The ICS9EX21801's must be set to high bandwidth. The spread spectrum characteristics are: maximum of 0.5%, 30-33KHz modulation frequency, linear profile. 10. This parameter is an absolute value. It is not a double-sided figure. IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 7 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Datasheet Electrical Characteristics - Phase Jitter (PLL Mode) PARAMETER PLL Bandwidth PLL Bandwidth PLL Jitter Peaking PLL Jitter Peaking SYMBOL BWH BWL jPKH jPKL tjphase_LoBW Jitter, Phase tjphase_HIBW CONDITIONS* High Bandwidth Selected Low Bandwidth Selected High Bandwidth Selected Low Bandwidth Selected PCIe Gen 1 (1.5 - 22 MHz) PCIe Gen 2 (8-16 MHz, 5-16 MHz) Lo-band content (10kHz to 1.5MHz) PCIe Gen 2 (8-16 MHz, 5-16 MHz) Hi-band content (1.5MHz to Nyquist) NOTES TYP. 3 1 2.5 2 MAX 4 2 3 2.5 UNITS MHz MHz dB dB 36/42 108 ps 1,2 1.1/1.2 3 ps rms 1,2 2.0/2.1 3.1 ps rms 1,2 QPI_133MHz (4.8Gb, 12 UI) 0.24/0.25 0.5 ps rms 2, 3 QPI_133MHz (6.4Gb, 12 UI) 0.18/0.19 0.5 ps rms 2, 3 28/32 86 ps 1,2 1.2/1.5 3 ps rms 1,2 2.6/2.7 3.1 ps rms 1,2 QPI_133MHz (4.8Gb, 12 UI) 0.27/0.28 0.5 ps rms 2, 3 QPI_133MHz (6.4Gb, 12 UI) 0.2/0.21 0.5 ps rms 2, 3 PCIe Gen 1 (1.5 - 22 MHz) PCIe Gen 2 (8-16 MHz, 5-16 MHz) Lo-band content (10kHz to 1.5MHz) PCIe Gen 2 (8-16 MHz, 5-16 MHz) Hi-band content (1.5MHz to Nyquist) MIN 2 0.7 Notes on Phase Jitter: (Guaranteed by design and characterization, not tested in production) 1 See http://www.pcisig.com for complete specs. First number is Spread Spectrum Off, second is Spread Spectrum On. 2 Device driven by IDT CK410B+ (932S421CGLF) or CK509B (932S509EKLF) or equivalent Calculated from Intel Supplied Clock Jitter Tool 1.5.1. First number is Spread Spectrum Off, second is Spread Spectrum On 3 IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 8 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Datasheet General SMBus serial interface information for the ICS9EX21801A How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D4(h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D4(h)* WR WRite Controller (host) will send start bit. Controller (host) sends the write address D4 (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D5 (h) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controller (Host) T starT bit Slave Address D4(h)* WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D5(h)* RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P Not acknowledge stoP bit Note: The address is selectable among 4 values (page 2). IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 9 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Datasheet 9EX21801 SMBus Addressing SMB_A(2:0) = 000 SMB Adr: D0 (DB1200G/GS) (DB1900G/GS) SMB_A(2:0) = 001 SMB Adr: D2 (DB1200G/GS) (DB1900G/GS) SMB_A(1:0) = 00 SMB Adr: D4 OR SMB_A(2:0) = 010 SMB Adr: D4 (DB1200G/GS) (DB1900G/GS) OR SMB_A(2:0) = 011 SMB Adr: D6 (DB1200G/GS) ` (DB1900G/GS) 9EX21801 SMB_A(1:0) = 01 SMB Adr: D6 9EX21801 SMB_A(1:0) = 10 SMB Adr: D8 OR 9EX21801 SMB_A(1:0) = 11 SMB Adr: DA 9EX21801 OR SMB Adr: D2 OR (CK410B+/CK509B) SMB_A(2:0) = 100 SMB Adr: D8 (DB1200G/GS) (DB1900G/GS) SMB_A(2:0) = 101 SMB Adr: DA (DB1200G/GS) (DB1900G/GS) SMB_A(2:0) = 110 SMB Adr: DC (DB1200G/GS) (DB1900G/GS) OR SMB Adr: DC 9DB403/803 (DB400E/800E) SMB_A(2:0) = 111 SMB Adr: DE (DB1200G/GS) (DB1900G/GS) IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 10 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux SMBusTable: Output, and PLL BW Control Register Byte 0 Pin # Name Control Function Datasheet Type PLL_BW# adjust RW BYPASS# test mode / PLL RW Bit 7 4 Bit 6 Enable Enable Latch Latch SMBusTable: Output Control Register Byte 1 Pin # Name DIF_7 Bit 7 DIF_6 Bit 6 DIF_5 Bit 5 DIF_4 Bit 4 DIF_3 Bit 3 DIF_2 Bit 2 DIF_1 Bit 1 DIF_0 Bit 0 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 SMBusTable: Output Control Register Pin # Name Byte 2 DIF_15 Bit 7 DIF_14 Bit 6 DIF_13 Bit 5 DIF_12 Bit 4 DIF_11 Bit 3 DIF_10 Bit 2 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 100M_133M# FSB FSA Hi-Z Hi-Z PWD RW RW RW - RW RW 1 Output Control Output Control RESERVED Frequency Select Bit C Frequency Select Bit B Frequency Select bit A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DIF_17 DIF_16 0 00 = Low BW (1MHz) 10 = Bypass 11 = High BW (3MHz) 133MHz 100MHz See Frequency Select Table 1 1 0 Latch 0 1 Bit 1 DIF_9 Output Control RW Hi-Z Enable 1 Bit 0 DIF_8 Output Control RW Hi-Z Enable 1 Type R R R R R R R R 0 Pin Low Pin Low Pin Low Pin Low Pin Low Pin Low Pin Low Pin Low 1 Pin Hi Pin Hi Pin Hi Pin Hi Pin Hi Pin Hi Pin Hi Pin Hi PWD X X X X X X X X SMBusTable: Output Enable Readback Register Byte 3 Pin # Name Control Function 5 OE11# Input Pin Readback Bit 7 2 OE10# Input Pin Readback Bit 6 72 OE9# Input Pin Readback Bit 5 59 OE8# Input Pin Readback Bit 4 56 OE7# Input Pin Readback Bit 3 52 OE6# Input Pin Readback Bit 2 49 OE5# Input Pin Readback Bit 1 36 OE_01234# Input Pin Readback Bit 0 IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 11 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux SMBusTable: Output Enable Readback Register Pin # Name Control Function Byte 4 RESERVED Bit 7 RESERVED Bit 6 62 100M_133M# Input Pin Readback Bit 5 68 SEL_A_B# Input Pin Readback Bit 4 22 OE15_17# Input Pin Readback Bit 3 18 OE14# Input Pin Readback Bit 2 15 OE13# Input Pin Readback Bit 1 8 OE12# Input Pin Readback Bit 0 Datasheet Type 0 1 R R R R R R 133M Input B Pin Low Pin Low Pin Low Pin Low 100M Input A Pin Hi Pin Hi Pin Hi Pin Hi PWD 0 0 X X X X X X Note: For an output to be enabled, BOTH the Output Enable Bit and the OE# pin must be enabled. This means that the Output Enable Bit must be '1' and the corresponding OE# pin must be '0'. SMBusTable: Vendor & Revision ID Register Byte 5 Pin # Name Control Function RID3 Bit 7 RID2 Bit 6 REVISION ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R 0 - 1 - PWD 0 0 0 1 0 0 0 1 SMBusTable: DEVICE ID Byte 6 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R 0 1 PWD 0 0 0 1 1 0 0 0 Name Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 SMBusTable: Byte Count Register Byte 7 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Writing to this register configures how many bytes will be read back. IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Type RW RW RW RW RW RW RW RW Device ID is 18 hex 0 - 1 - PWD 0 0 0 0 0 1 1 1 1463B — 01/20/10 12 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Datasheet (Ref. ) Seating Plane (N D - 1)x e (Ref. ) A1 Index Area ND & NE Even A3 N L N Anvil Singulation 1 2 E2 OR E (N E - 1)x e E2 (Ref. ) 2 Sawn Singulation Top View e (Typ.) 2 If N D & N E are Even 1 b (Ref.) A D e ND & NE Odd Thermal Base D2 2 D2 Chamfer 4x 0.6 x 0.6 max OPTIONAL C C 0.08 THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS (mm) DIMENSIONS SYMBOL N ND NE SYMBOL A A1 A3 b e D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. 72L 72 18 18 MIN. MAX. 0.8 1.0 0 0.05 0.25 Reference 0.18 0.3 0.50 BASIC 10.00 x 10.00 5.75 6.15 5.75 6.15 0.3 0.5 Ordering Information Part / Order Number Shipping Packaging 9EX21801AKLF Tubes 9EX21801AKLFT Tape and Reel Package 72-pin MLF 72-pin MLF Temperature 0 to +70°C 0 to +70°C “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate to the datasheet revision). IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 13 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Datasheet R ev isio n H isto ry Rev. 0.1 0.2 0.3 0.4 0.5 A B Issu e Date Descrip tio n 4/29/2008 Initial Releas e 1. S M B us B y tes 11-16 are now res erv ed 2. S M B us Referenc es to 1:1 operating s et point regis ter are rem ov ed. 5/1/2008 3. Updated readbac k regis ters to m atc h new c ontrol pins 3. A dded Q P I phas e nois e s pec 4. S ignific ant c hanges to pinout to im prov e perform anc e 1. Updated/Correc ted S M B us , filled in em pty by tes 2. Updated F requenc y /F unc tionality T able 5/30/2008 3. A dded S M B us A ddres s dec oding table and graph 4. Correc ted P ower hook up table. 6/3/2008 A dded rev is ion des ignator to orderng inform ation 1. Updated front page tex t 2. Updated F unc tionality foot notes on P age 2. 3. Deleted duplic ate table on page 6. 4. Correc ted DIF 0.7V Current M ode elec tric al c harac teris itc s - rem ov ed s k ew s pec . 12/8/2008 5. Updated s k ew and Differential P aram eters T able to reflec t c har data, added P LL B W and jitterpeak ing data to this table. 6. Updated P has e J itter T able - rem ov ed F B D s pec s and added HiB W and Low B W s ec tions 7. A dded S M B us A ddres s ing T able after page 9 1. Updated P LL m ode input frequenc y range 2. Noted that M odulation frequenc y is the A llowable S pread M odulation F requenc y . A dded foonote 3. 12/17/2008 3. Correc ted P CIe G en1 M ax phas e jitter s pec to be 86 ps ins tead of 108ps . 86ps is the derated lim it when us ing ~ 160K c y c les to c alc ulate the v alue. Releas ed to final - Rev A . 1/20/2010 1. Correc ted P in Des c ription for P in 62. 0 = 133M , 1 = 100M . P ag e # - V arious V arious 12 1,2,6,7,8, 10 5,8 4 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com TM For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 [email protected] Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 14