ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet 48-pin CK505 for Intel Systems Recommended Application: 48-pin Low Cost CK505 w/fully integrated VREG and series resistors on differential outputs Output Features: • Integrated Series Resistors on differential outputs • 2 - CPU differential push-pull pairs • 4 - SRC differential push-pull pairs • 1 - CPU/SRC selectable differential push-pull pair • 1 - SRC/DOT selectable differential push-pull pair • 1- SRC/Stop_Inputs selectable differential push-pull pair • 1 - 25MHz SE1 output for Wake-on-Lan applications • 3 - PCI, 33MHz • 1 - USB, 48MHz • 1 - REF, 14.31818MHz Features/Benefits: • Supports spread spectrum modulation, default is 0.5% down spread • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Table 1: CPU Frequency Select Table 2 FSLC B0b7 0 0 0 0 1 1 1 1 1 1 FSLB B0b6 0 0 1 1 0 0 1 1 FS LA B0b5 0 1 0 1 0 1 0 1 CPU MHz SRC MHz PCI MHz REF MHz USB MHz DOT MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/-100ppm frequency accuracy on all clocks PCI0/CR#_A VDDPCI PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOT96T_LPR/SRCT0_LPR DOT96C_LPR/SRCC0_LPR GND VDD SE1 GND SRCT2_LPR/SATAT_LPR SRCC2_LPR/SATAC_LPR GNDSRC SRCT3_LPR/CR#_C SRCC3_LPR/CR#_D VDDSRC_IO SRCT4_LPR SRCC4_LPR CPU_STOP#/SRCC5_LPR specifications in the Input/Supply/Common Output Parameters Table for correct values. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 9LPRS535 Pin Configuration 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SCLK SDATA REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0_LPR CPUC0_LPR GNDCPU CPUT1_LPR_F CPUC1_LPR_F VDDCPU_IO CPUT2_ITP_LPR/SRCT8_LPR CPUC2_ITP_LPR/SRCC8_LPR VDDSRC_IO SRCT7_LPR/CR#_F SRCC7_LPR/CR#_E GNDSRC VDDSRC PCI_STOP#/SRCT5_LPR 48-SSOP/TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor 1461A—07/28/09 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet SSOP/TSSOP Pin Description PIN # PIN NAME 1 PCI0/CR#_A 2 VDDPCI 3 PCI4/SRC5_EN 4 PCI_F5/ITP_EN 5 GNDPCI TYPE DESCRIPTION 3.3V PCI clock output or CR#_A input. Default is PCI0. To configure this pin as CR#_A, the PCI output must first be disabled in Byte 2, bit 0. I/O Byte 5, bit 7: 0 = PCI0 enabled (default), 1= CR#_A enabled. Byte 5, bit 6: 0 = CR#_A controls SRC0 (default), 1= CR#_A# controls SRC2. PWR Power supply for PCI clocks, nominal 3.3V 3.3V PCI clock output / SRC5 enable strap. On powerup, the logic value on this pin determines if SRC5 or CPU_STOP#/PCI_STOP# is enabled. The latched value controls the pin function as follows I/O 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. I/O 0 =SRC8/SRC8# 1 = ITP/ITP# PWR Ground pin for the PCI outputs 6 VDD48 7 USB_48MHz/FSLA PWR Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed I/O 48MHz USB clock output. 3.3V. PWR Ground pin for the 48MHz outputs 8 GND48 9 VDD96_IO 10 DOT96T_LPR/SRCT0_LPR 11 DOT96C_LPR/SRCC0_LPR 12 GND PWR Power pin for the DOT96 clocks, nominal 1.05V to 3.3V. True clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is SRCT0. After powerup, this pin function may be changed to DOT96T via SMBus Byte 1, bit 7 as follows: OUT 0= SRC0T 1=DOT96T Complementary clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is SRC0C. After powerup, this pin function may be changed to DOT96C via SMBus Byte 1, bit 7 as follows: OUT 0= SRC0C 1=DOT96C PWR Ground pin. 13 VDD PWR Power supply, nominal 3.3V 14 SE1 OUT CK505 Singled Ended Output 1. 3.3V. 15 GND 16 SRCT2_LPR/SATAT_LPR 17 SRCC2_LPR/SATAC_LPR 18 GNDSRC 19 SRCT3_LPR/CR#_C 20 SRCC3_LPR/CR#_D 21 VDDSRC_IO PWR Ground pin. True clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor to GND OUT needed. Complementary clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor OUT to GND needed. PWR Ground pin for the SRC outputs True clock of push-pull SRC output with int. 33ohm series resistor/CR#_C input. Disable SRC3 via Byte 4, bit 7, before using as CR#_C. I/O Byte 5, bit 3: 0=SRC3 (default), 1=CR#_C. Byte 5, bit 2: 0=CR# C controls SRC0 (default), 1=CR# C controls SRC2 Complementary clock of push-pull SRC output with int. 33ohm series resistor/CR#_D input. Disable SRC3 via Byte 4, bit 7, before using as CR#_D. I/O Byte 5, bit 1: 0=SRC3 (default),1=CR#_D. Byte 5, bit 0: 0=CR#_D controls N/A (default), 1=CR#_D controls SRC4 PWR 1.05V to 3.3V from external power supply 22 SRCT4_LPR OUT True clock of push-pull SRC output with int. 33ohm series resistor. 23 SRCC4_LPR OUT Complementary clock of push-pull SRC output with int. 33ohm series resistor. 24 CPU_STOP#/SRCC5_LPR I/O Stops all CPUCLK, except those set to be free running clocks / Complementary clock of push-pull SRC pair with int. 33ohm series resistor. 1461A—07/28/09 2 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet SSOP/TSSOP Pin Description (Continued) 25 PCI_STOP#/SRCT5_LPR 26 VDDSRC 27 GNDSRC 28 29 30 31 32 33 34 35 36 37 38 I/O Stops all PCICLKs at logic 0 level, when low. Can also stop SRC clocks. Free running PCICLKs are not effected by this input. / True clock of push-pull SRC pair with int. 33ohm series resistor. PWR Supply for SRC clocks, 3.3V nominal PWR Ground pin for the SRC outputs Complementary clock of push-pull SRC output with int. 33ohm series resistor/CR#_E input. Disable SRC7 via Byte 3, bit 3 before using as CR#_E. SRCC7_LPR/CR#_E I/O Byte 6, bit 7: 0=SRC7 (default), 1=CR#_E Outputs controlled by CR#_E are not present on this device True clock of push-pull SRC output with int. 33 ohm series resistor/CR#_F input. Disable SRC7 via Byte 3, bit 3 before SRCT7_LPR/CR#_F I/O using CR#_F. Byte 6, bit 6: 0 = SRC7 (default),1 = CR#_F enabled to control SRC8. VDDSRC_IO PWR 1.05V to 3.3V from external power supply Complementary clock of low power differential CPU2_ITP/SRC pair. No Rs needed. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: CPUC2_ITP_LPR/SRCC8_LPR OUT Pin 7 latched input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2_ITP/SRC8 pair. No Rs needed. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: CPUT2_ITP_LPR/SRCT8_LPR OUT Pin 7 latched input Value 0 = SRC8 1 = ITP VDDCPU_IO PWR 1.05V to 3.3V from external power supply Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running CPUC1_LPR_F OUT during iAMT. No 50ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running during CPUT1_LPR_F OUT iAMT No 50 ohm resistor to GND needed. GNDCPU PWR Ground pin for the CPU outputs Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm CPUC0_LPR OUT resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm resistor to CPUT0_LPR OUT GND needed. 39 VDDCPU 40 CK_PWRGD/PD# 41 FSLB/TEST_MODE 42 GNDREF Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. PWR Ground pin for the REF outputs. 43 X2 OUT Crystal output, Nominally 14.318MHz 44 X1 45 VDDREF 46 REF0/FSLC/TEST_SEL 47 SDATA 48 SCLK PWR Supply for CPU clocks, 3.3V nominal IN IN Crystal input, Nominally 14.318MHz. PWR Ref, XTAL power supply, nominal 3.3V 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for I/O Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table I/O Data pin for SMBus circuitry, 3.3V tolerant. IN Clock pin of SMBus circuitry, 5V tolerant. 1461A—07/28/09 3 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet General Description ICS9LPRS535 is compliant to the Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel desktop chipsets. ICS9LPRS535 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support. Block Diagram X1 X2 REF OSC REF CPU(1:0) SRC8/ITP CPU PLL1 SS CPU SRC = SRC_MAIN SRC(7,5:3) PCI33MHz PCI(5:4,0) PLL3 Non-SS SE1 (25MHz) 25MHz SRC2/SATA FSLA CKPWRGD/PD# PCI_STOP# CPU_STOP# CR#_(A,C:D) SRC5_EN Control Logic ITP_EN FSLC/TESTSEL FSLB/TESTMODE SRC0/DOT96 SATA PLL2 Non-SS DOT96MHz 48MHz 48MHz Power Groups Pin Number VDD 33 39 30, 21 13 9 6 45 2 GND 36 36 18, 27 15 12 8 42 5 Description CPU Outputs CPU/SRC Analog SRC Outputs PLL3 25MHz DOT96 outputs USB 48 Output/Analog Xtal, REF PCI outputs 1461A—07/28/09 4 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet Absolute Maximum Ratings - DC Parameters PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Storage Temperature Input ESD protection SYMBOL VDDxxx VDDxxx_IO VIH VIL Ts ESD prot 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied, nor guaranteed. 3 Maximum input voltage is not to exceed VDD CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply 3.3V Inputs Any Input Human Body Model MIN MAX 4.6 3.8 4.6 GND - 0.5 -65 2000 150 UNITS Notes V 7 V 7 V 4,5,7 V 4,7 ° 4,7 C V 6,7 AC Electrical Characteristics - Low Power Differential Outputs PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Maximum Output Voltage Minimum Output Voltage Duty Cycle CPU[1:0] Skew CPU[2_ITP:0] Skew SRC[10:0] Skew SYMBOL tSLR tFLR tSLVAR VSWING VXABS VXABSVAR VHIGH VLOW DCYC CPUSKEW10 CPUSKEW20 SRCSKEW CONDITIONS Averaging on Averaging on Averaging on Averaging off Averaging off Averaging off Averaging off Averaging off Averaging on Differential Measurement Differential Measurement Differential Measurement MIN 2.5 2.5 MAX 4 4 20 300 300 550 140 1150 -300 45 55 100 150 3000 UNITS NOTES V/ns 2, 3 V/ns 2, 3 % 1, 10 mV 2 mV 1,4,5 mV 1,4,9 mV 1,7 mV 1,8 % 2 ps 1 ps 1 ps 1,6,11 NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Measurement taken for single ended waveform on a component test board (not in system) 2 Measurement taken from differential waveform on a component test board. (not in system) 3 Slew rate emastured through V_swing voltage range centered about differential zero 4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) Only applies to the differential rising edge (Clock rising, Clock# falling) 5 6 Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps. 7 The max voltage including overshoot. 8 The min voltage including undershoot. 9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross 10 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising 11 For PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew. Electrical Characteristics - PCICLK/PCICLK_F PARAMETER Long Accuracy SYMBOL ppm Clock period Tperiod Absolute min/max period Tabs Output High Voltage Output Low Voltage VOH VOL Output High Current I OH Output Low Current I OL Rising Edge Slew Rate Falling Edge Slew Rate Pin to Pin Skew Intential PCI to PCI delay Duty Cycle Jitter, Cycle to cycle t SLR t FLR tskew tskew dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 33.33MHz output no spread 33.33MHz output spread 33.33MHz output no spread 33.33MHz output nominal/spread IOH = -1 mA I OL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 1461A—07/28/09 5 MIN -100 29.99700 30.08421 29.49700 29.56617 2.4 -33 30 1 1 100 45 MAX UNITS NOTES 100 ppm 1,2 30.00300 ns 2 30.23459 ns 2 30.50300 ns 2 30.58421 ns 2 V 1 0.55 V 1 mA 1 -33 mA 1 mA 1 38 mA 1 4 V/ns 1 4 V/ns 1 250 ps 2 200 ps 2 55 % 2 500 ps 2 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet Electrical Characteristics - Input/Supply/Common Output DC Parameters PARAMETER Ambient Operating Temp Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Low Threshold Input- High Voltage SYMBOL Tambient VDDxxx VDDxxx_IO VIHSE VILSE VIH_FS_TEST CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply Single-ended 3.3V inputs Single-ended 3.3V inputs 3.3 V +/-5% MIN 0 3.135 0.9975 2 VSS - 0.3 2 Low Threshold Input- FSC = '1' Voltage VIH_FS_FSC 3.3 V +/-5% 0.7 1.5 V VIH_FS_FSAB 3.3 V +/-5% 0.7 VDD+0.3 V 3.3 V +/-5% VIN = VDD , VIN = GND Inputs with pull up or pull down resistors VIN = VDD , VIN = GND Single-ended outputs, IOH = -1mA Single-ended outputs, IOL = 1 mA Full Active, CL = Full load; Idd 3.3V Full Active, CL = Full load; IDD IO M1 mode, 3.3V Rail M1 Mode, IO Rail Power down mode, 3.3V Rail Power down mode, IO Rail VDD = 3.3 V VSS - 0.3 -5 0.35 5 V uA -200 200 uA Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or de-assertion of PD to 1st clock Output stop after CR deasserted Output run after CR asserted CPU output enable after PCI_STOP# de-assertion 1.5 0.4 125 50 40 10 5 0.1 15 7 5 6 6 V V mA mA mA mA mA mA MHz nH pF pF pF Low Threshold Input- FSA,FSB = '1' Voltage Low Threshold Input-Low Voltage Input Leakage Current VIL_FS IIN Input Leakage Current IINRES Output High Voltage Output Low Voltage VOHSE VOLSE Operating Supply Current IDDOP3.3 IDDOPIO iAMT Mode Current Powerdown Current Input Frequency Pin Inductance Input Capacitance IDDiAMT3.3 IDDiAMTIO IDDPD3.3 IDDPDIO Fi Lpin CIN COUT CINX Clk Stabilization TSTAB Tdrive_CR_off Tdrive_CR_on TDRCROFF TDRCRON Tdrive_CPU TDRSRC Tfall_SE Trise_SE SMBus Voltage Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time TFALL TRISE VDD VOLSMB IPULLUP Maximum SMBus Operating Frequency FSMBUS Spread Spectrum Modulation Frequency fSSMOD TRI2C TFI2C 2.4 Fall/rise time of all 3.3V control inputs from 20-80% 2.7 @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Triangular Modulation MAX UNITS Notes 70 °C 3.465 V 3.465 V 10 VDD + 0.3 V 3 0.8 V 3 VDD + 0.3 V 8 1.8 ms 400 0 ns us 10 ns 10 10 5.5 0.4 ns ns V V mA 1000 ns 300 ns 100 kHz 33 kHz 4 30 NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Signal is required to be monotonic in this region. 2 input leakage current does not include inputs with pull-up or pull-down resistors 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected. 3 4 Intentionally blank 5 Maximum VIH is not to exceed VDD 6 Human Body Model 7 Operation under these conditions is neither implied, nor guaranteed. 8 Frequency Select pins which have tri-level input 9 PCI3/CFG0 is optional 10 If present. Not all parts have this feature. 1461A—07/28/09 6 8 2 1 1 10 10 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet Electrical Characteristics - USB48MHz PARAMETER Long Accuracy Clock period Absolute min/max period CLK High Time CLK Low time Output High Voltage Output Low Voltage SYMBOL ppm Tperiod Tabs THIGH TLOW VOH VOL Output High Current I OH Output Low Current I OL Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 48.00MHz output nominal 48.00MHz output nominal I OH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V MIN -100 20.83125 20.48125 8.216563 7.816563 2.4 -29 29 1 1 45 MAX UNITS NOTES 100 ppm 2,4 20.83542 ns 2,3 21.18542 ns 2 11.15198 V 10.95198 V V 0.55 V mA -23 mA mA 27 mA 2 V/ns 1 2 V/ns 1 55 % 2 350 ps 2 Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period CLK High Time CLK Low time Output High Voltage Output Low Voltage SYMBOL ppm Tperiod Tabs THIGH TLOW VOH VOL Output High Current IOH Output Low Current IOL Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V MIN -100 69.82033 69.83400 29.97543 29.57543 2.4 MAX UNITS Notes 100 ppm 2, 4 69.86224 ns 2, 3 70.84800 ns 2 38.46654 V 38.26654 V V 0.4 V -33 -33 mA 30 38 mA 1 1 45 4 4 55 1000 V/ns V/ns % ps 1 1 2 2 NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Edge rate in system is measured from 0.8V to 2.0V. 2 Duty cycle, Peroid and Jitter are measured with respect to 1.5V 3 The average period over any 1us period of time 4 Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz Clock Jitter Specs - Low Power Differential Outputs PARAMETER CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle SYMBOL CPUJC2C SRCJC2C DOTJC2C CONDITIONS Differential Measurement Differential Measurement Differential Measurement MIN MAX 85 125 250 UNITS NOTES ps 1 ps 1,2 ps 1 NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the rece 2 Phase jitter requirement: The deisgnated Ge2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base Spec. The test is performed on a componnet test board under quiet condittions with all outputs on. Jitter analysis is performed using a standardized tool provided by the PCI SIG or equivalent. Measurement methodology is as defined by the PCI SIG. 1461A—07/28/09 7 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet Table 2: PLL3 Quick Configuration (Read Only) Pin 14 Spread B1b4 B1b3 B1b2 B1b1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MHz N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 25.000 N/A N/A N/A Comment % N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A None 25Mhz on SE1 N/A N/A N/A N/A N/A N/A Table 3: Vswing Select Table B9b2 B9b1 B9b0 Vswing 0 0 0 0.3V 0 0 1 0.4V 0 1 0 0.5V 0 1 1 0.6V 1 0 0 0.7V 1 0 1 0.8V 1 1 0 0.9V 1 1 1 1.0V Table 4: Device ID table B8b7 B8b6 B8b5 B8b4 Comment 0 1 1 0 48 SSOP/TSSOP 1461A—07/28/09 8 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet PCI_STOP# Power Management Single-ended Clocks SMBus OE Bit PCI_STOP# 1 Stoppable Running Free running Running 0 Low Running Enable Disable Low X Differential Clocks (Except CPU) Stoppable Free running Running Running CK= High Running CK# = Low CK= Pull down, CK# = Low CPU_STOP# Power Management SMBus OE Bit CPU_STOP# 1 Running Running 0 CK= High CK# = Low Running Enable Disable CPU Clocks Free running Stoppable X Low CR# 1 0 X Differential Clocks (Except CPU) CR# controlled Free running Running Running CK= Pull down, CK# = Low CK = Pull down, CK# = Low CR# Power Management SMBus OE Bit Enable Disable PD# Power Management Device State Single-ended Clocks (Except SE1) w/o Latched input w/Latched input SE1 w/B11b5 = 0 Latches Open SE1 w/B11b5 = 1 Low Power Down 25MHz Low Hi-Z Low Differential Clocks (Except CPU1) CPU1 CK= Pull down, CK# = Low CK= Pull down CK# = Low CK= Pull down, CK# = Low CK= Pull down CK# = Low M1 25MHz CK= Pull down CK# = Low Running Virtual Power Cycle to Latches Open 25MHz CK= Pull down, CK# = Low CK= Pull down, CK# = Low 1461A—07/28/09 9 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet General SMBus serial interface information for the ICS9LPRS535 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 1461A—07/28/09 10 Not acknowledge stoP bit ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet Byte 0 FS Readback and PLL Selection Register Bit 7 6 5 Pin - Name FSLC FSLB FSLA 4 - iAMT_EN 3 2 1 - Reserved SRC_Main_SEL SATA_SEL 0 - PD_Restore Description CPU Freq. Sel. Bit (Most Significant) CPU Freq. Sel. Bit CPU Freq. Sel. Bit (Least Significant) Set via SMBus or dynamically by CK505 if detects dynamic M1 Reserved Select source for SRC Main Select source for SATA clock 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold power-on and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode. Type R R R RW 0 1 See Table 1 : CPU Frequency Select Table Legacy Mode RW SRC Main = PLL1 R RW SATA = SRC_Main Default Latch Latch Latch iAMT Enabled 0 SRC Main = PLL3 SATA = PLL2 0 0 0 RW Configuration Not Saved Configuration Saved 1 0 SRC0 Down spread 1 DOT96 Center spread Default 0 0 Byte 1 DOT96 Select and PLL3 Quick Config Register Bit 7 6 Pin 13/14 - Name SRC0_SEL PLL1_SSC_SEL Description Select SRC0 or DOT96 Select 0.5% down or center SSC Type RW RW 5 Reserved Reserved RW 4 3 2 1 PLL3_CF3 PLL3_CF2 PLL3_CF1 PLL3_CF0 0 PCI_SEL PLL3 Quick PLL3 Quick PLL3 Quick PLL3 Quick Config Bit Config Bit Config Bit Config Bit 3 2 1 0 R R R R PCI_SEL R Description Output enable for REF, if disabled output is tri-stated Output enable for USB Output enable for PCI5 Output enable for PCI4 Reserved Reserved Reserved Output enable for PCI0 Type RW RW RW RW RW RW RW RW 1 25MHz from PLL3 Quick Config 1 1 0 0 PCI from SRC_MAIN 1 PCI from PLL1 Byte 2 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name REF_OE USB_OE PCIF5_OE PCI4_OE Reserved Reserved Reserved PCI0_OE Output Output Output Output 0 Disabled Disabled Disabled Disabled Output Output Output Output 1 Enabled Enabled Enabled Enabled Output Disabled Output Enabled 0 1 Output Disabled Output Disabled Output Enabled Output Enabled Output Disabled Output Disabled Output Enabled Output Enabled Default 1 1 1 1 1 1 1 1 Byte 3 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved SRC8/ITP_OE SRC7_OE Reserved SRC5_OE SRC4_OE Description Reserved Reserved Reserved Output enable for SRC8 or ITP Output enable for SRC7 Reserved Output enable for SRC5 Output enable for SRC4 1461A—07/28/09 11 Type RW RW RW RW RW RW RW RW Default 1 1 1 1 1 1 1 1 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet Byte 4 Output Enable and Spread Spectrum Disable Register Bit 7 6 5 4 3 2 1 Pin 0 Name SRC3_OE SATA/SRC2_OE Reserved SRC0/DOT96_OE CPU1_OE CPU0_OE PLL1_SSC_ON Description Output enable for SRC3 Output enable for SATA/SRC2 Reserved Output enable for SRC0/DOT96 Output enable for CPU1 Output enable for CPU0 Enable PLL1's spread modulation Type RW RW RW RW RW RW RW Reserved Reserved RW 0 Output Disabled Output Disabled 1 Output Enabled Output Enabled Output Disabled Output Disabled Output Disabled Spread Disabled Output Enabled Output Enabled Output Enabled Spread Enabled Default 1 1 0 1 1 1 1 0 Byte 5 Clock Request Enable/Configuration Register Bit Pin Name Type 0 1 Default RW Disable CR#_A Enable CR#_A 0 CR#_A_SEL Reserved Reserved CR#_C_EN CR#_C_SEL CR#_D_EN Description Enable CR#_A (clk req), PCI0_OE must be = 1 for this bit to take effect Sets CR#_A to control either SRC0 or SRC2 Reserved Reserved Enable CR#_C (clk req) Sets CR#_C -> SRC0 or SRC2 Enable CR#_D (clk req) RW RW RW RW RW RW CR#_A -> SRC0 CR#_A -> SRC2 Enable CR#_C CR#_C -> SRC2 Enable CR#_D CR#_D_SEL Sets CR#_D -> SRC1 or SRC4 RW Disable CR#_C CR#_C -> SRC0 Disable CR#_D NA, SRC1 not present 0 0 0 0 0 0 CR#_D -> SRC4 0 0 1 Disable CR#_F Enable CR#_F Default 0 0 7 CR#_A_EN 6 5 4 3 2 1 0 Byte 6 Clock Request Enable/Configuration and Stop Control Register Bit 7 6 Pin Name Reserved CR#_F_EN Description Reserved Enable CR#_F (clk req) -> SRC8 Type RW RW 5 Reserved Reserved RW 0 4 3 2 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW 0 0 0 0 0 SRC_STP_CRTL If set, SRCs (except SRC1) stop with PCI_STOP# RW Free Running Stops with PCI_STOP# assertion Description Type R R R R R R R R 0 1 0 Byte 7 Vendor ID/ Revision ID Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit 3 Rev Code Bit 2 Rev Code Bit 1 Rev Code Bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 Revision ID Rev B = 0001 Rev C = 0010 Vendor ID ICS is 0001, binary 1461A—07/28/09 12 B rev = 0001 C rev = 0010 ICS is 0001 Default X X X X 0 0 0 1 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet Byte 8 Device ID and Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved SE1_OE Reserved Description Reserved Reserved Output enable for SE1 Reserved Type R R R R RW RW RW RW Disabled - Enabled - Name Description Type 0 7 PCIF5 STOP EN Allows control of PCIF5 with assertion of PCI_STOP# RW Free running 6 5 4 3 2 1 0 TME_Readback REF Strength Test Mode Select Test Mode Entry IO_VOUT2 IO_VOUT1 IO_VOUT0 Truested Mode Enable (TME) strap status Sets the REF output drive strength Allows test select, ignores REF/FSC/TestSel Allows entry into test mode, ignores FSB/TestMode IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) R RW RW RW RW RW RW normal operation 1X (2Loads) Outputs HI-Z Normal operation 1 Stops with PCI_STOP# assertion no overclocking 2X (3 Loads) Outputs = REF/N Test mode Name Description Type 7 SRC5_EN Readback Readback of SRC5 enable latch 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved CPU 1 Stop Enable CPU 0 Stop Enable 0 CPU/PCI Stop Enabled TBD TBD TBD TBD TBD Free Running Free Running Table of Device identifier codes, used for differentiating between CK505 package options, etc. 0 1 See Device ID Table Default 0 1 1 0 0 0 1 0 Byte 9 Output Control Register Bit Pin See Table 3: V_IO Selection (Default is 0.8V) Default 0 0 1 0 0 1 0 1 Byte 10 Stop Enable Register Bit Pin Reserved Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP# R RW RW RW RW RW RW RW 1 Default SRC5 Enabled Latch TBD TBD TBD TBD TBD Stoppable Stoppable 0 0 0 0 0 1 1 Default 0 0 Default 0 0 0 0 1 1 0 1 Byte 11 iAMT Enable Register Bit 7 6 Pin 5 WOL_STOP_EN 4 3 2 Reserved CPU2_AMT_EN CPU1_AMT_EN Description Reserved Reserved Enable 25MHz WLAN clock during M1 or Power Down. This bit is sticky 1. Reserved M1 mode clk enable, only if ITP_EN=1 M1 mode clk enable PCI-E_GEN2 Determines if PCI-E Gen2 compliant 1 0 Name Reserved Reserved CPU 2 Stop Enable Enables control of CPU 2 (ITP)with CPU_STOP# Note Rev B device default is 0. Rev C device is 1 Type RW RW R non-Gen2 RW Free Running 1 25MHz enabled in Powerdown or M1 Enable Enable PCI-E Gen2 Compliant Stoppable Type RW RW RW RW RW RW RW RW 0 1 RW RW RW RW 0 25MHz disabled in Powerdown or M1 Disable Disable NOTE 1 0 1 1 1 Byte 12 Byte Count Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Description Read Back byte count register, max bytes = 32 1461A—07/28/09 13 Byte count is 13 decimal. ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet Test Clarification Table Comments HW FSLC/ TEST_SEL HW PIN Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control SW FSLB/ TEST_MOD TEST E ENTRY BIT HW PIN B9b3 REF/N or HI-Z B9b4 <2.0V >2.0V >2.0V >2.0V X 0 0 1 0 X X X 0 0 1 0 OUTPUT NORMAL HI-Z REF/N REF/N >2.0V 1 X 1 REF/N <2.0V X 1 0 HI-Z <2.0V X 1 1 REF/N B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B9b4: 1= REF/N, Default = 0 (HI-Z) 1461A—07/28/09 14 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet SYMBOL A A1 b c D E E1 e h L N a 300 mil SSOP In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS N 48 D mm. MIN 15.75 D (inch) MAX 16.00 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 1461A—07/28/09 15 MIN .620 MAX .630 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet c N L E1 INDEX AREA E 1 2 a D A A2 A1 -Ce 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N α 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS SEATING PLANE b N aaa C 48 D mm. MIN MAX 12.40 12.60 D (inch) MIN .488 MAX .496 Reference Doc.: JEDEC Publicat ion 95, M O-153 10-0039 Ordering Information Part / Order Number 9LPRS535BFLF 9LPRS535BFLFT 9LPRS535BGLF 9LPRS535BGLFT 9LPRS535CFLF 9LPRS535CFLFT 9LPRS535CGLF 9LPRS535CGLFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 48-pin SSOP 48-pin SSOP 48-pin TSSOP 48-pin TSSOP 48-pin SSOP 48-pin SSOP 48-pin TSSOP 48-pin TSSOP 1461A—07/28/09 16 Temperature 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C Wake-on LAN Default Disabled Enabled ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet Revision History Rev. 0.1 0.2 0.4 Issue Date Description Page # 3/10/2008 1. Intial release 4/23/2008 1. Updated SMBus, front page, block diagram and deleted page 5 1, 4, 12-13 1. Corrected typo in CPU power management table. Wrong column heading 2. Corrected typo in PD# Power Management Table SE1 should be low when B11b5 = 0 3. Corrected Byte 5 bit 0 to be NA when set to 0. SRC1 is not present. Various 5/7/2008 4. Byte 6, bit 6 restored. CR_F# is present and can control SRC8 1. Corrected Power management table to remove the stop mode drive bits, which do not exist in this device. 7/7/2008 2. Updated Differential clock period table. Various 0.5 7/10/2008 0.6 0.7 7/13/2009 7/21/2009 A 7/28/2009 0.3 1. 2. 1. 2. 1. 1. 2. Updated pin names to reflect LPR output type. Pin descriptions updated too. SMBus updated to indicate PCIe Gen2 status Removed references to CR# inputs that do not exist in this part. Clarified functionality of Byte 11, bit 5. Lowered Idd values to reflect performance of the device. Moved to final Added "Wake-on LAN Default" parameter to ordering info table. 1461A—07/28/09 17 Various Various