AMICC A81L801

A81L801
Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit
Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM
Preliminary
Document Title
Stacked Multi-chip Package (MCP) 1M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory
and 128K x 8 Low Voltage CMOS SRAM
Revision History
Rev.
0.0
History
Issue Date
Initial issue
March 25, 2005
PRELIMINARY
(March, 2005, Version 0.0)
Remark
Preliminary
AMIC Technology, Corp.
A81L801
Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit
Boot Sector Flash Memory and 128K x 8 Bit Low Voltage CMOS SRAM
Preliminary
MCP Features
Single power supply operation 2.7 to 3.6 volt
High Performance
- Access time as fast as 70ns
Package
- 69-Ball FBGA (8x11x1.4 mm)
Industrial operating temperature range: -25°C to 85°C for –I
Flash Features
Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
Access times:
- 70 (max.)
Current:
- 9 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that sector.
Temporary Sector Unprotect feature allows code changes
in previously locked sectors
Extended operating temperature range: -25°C ~ +85°C for –
I series
Unlock Bypass Program Command
- Reduces overall programming time when issuing multiple
program command sequence
Top or bottom boot block configurations available
Embedded Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies data at specified addresses
Typical 100,000 program/erase cycles per sector
20-year data retention at 125°C
- Reliable operation for the life of the system
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Data Polling and toggle bits
- Provides a software method of detecting completion of
program or erase operations
Ready / BUSY pin (RY / BY )
- Provides a hardware method of detecting completion of
program or erase operations
Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
Hardware reset pin ( RESET )
- Hardware method to reset the device to reading array data
LP SRAM Features
Power supply range: 2.7V to 3.6V
Access times: 70 ns (max.)
Current:
Very low power version: Operating: 30mA(max.)
Standby: 5uA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Output enable and two chips enable inputs for easy
application
Data retention voltage: 2.0V (min.)
AMIC Technology, Corp.
A81L801
General Description
The Flash memory of A81L801 is an 8Mbit, 3.0 volt-only
memory organized as 1,048,576 bytes of 8 bits or 524,288
words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7;
the 16 bits of data appear on I/O0~I/O15. The A81L801 is
offered in 69-ball TFBGA package. This device is designed to
be programmed in-system with the standard system 3.0 volt
VCC supply. Additional 12.0 volt VPP is not required for insystem write or erase operations. However, the A81L801 can
also be programmed in standard EPROM programmers.
The Flash memory of A81L801 has the first toggle bit, I/O6,
which indicates whether an Embedded Program or Erase is in
progress, or it is in the Erase Suspend. Besides the I/O6 toggle
bit, the Flash memory of A81L801 also has a second toggle
bit, I/O2, to indicate whether the addressed sector is being
selected for erase. The A81L801 also offers the ability to
program in the Erase Suspend mode. The standard A81L801
offers access times of 70 and 90ns, allowing high-speed
microprocessors to operate without wait states. To eliminate
bus contention the device has separate chip enables ( CE_F ,
and CE_S ), write enable ( WE ) and output enable ( OE )
controls.
The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The Flash memory of A81L801 is entirely software command
set compatible with the JEDEC single-power-supply Flash
standard. Commands are written to the command register
using standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
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Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies proper
erase margin. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to
program data instead of four.
The host system can detect whether a program or erase
operation is complete by observing the RY / BY pin, or by
reading the I/O7 ( Data Polling) and I/O6 (toggle) status bits.
After a program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The Flash memory of A81L801 is fully erased
when shipped from the factory.
The hardware sector protection feature disables operations for
both program and erase in any combination of the sectors
of memory. This can be achieved via programming equipment.
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET pin terminates any operation in
progress and resets the internal state machine to reading
array data. The RESET pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The A81L801 device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
AMIC Technology, Corp.
A81L801
Pin Configurations
69-Ball FBGA
Top View
Flash only
A1
A5
A6
A10
NC
NC
NC
NC
Shared
B1
B3
B4
B5
B6
B7
B8
NC
A7
NC
NC
WE
A8
A11
C2
C3
C4
C5
C6
C7
C8
C9
A3
A6
NC
RESET
NC
NC
A12
A15
D2
D4
D4
D5
D6
D7
D8
D9
A2
A5
A18
RY/BY
NC
A9
A13
NC
E1
E2
E3
E4
E7
E8
E9
E10
NC
A1
A4
A17
A10
A14
NC
NC
F1
F2
F3
F4
F7
F8
F9
F10
NC
A0
VSS
I/O1
I/O6
NC
A16
NC
G2
G3
G4
G7
G8
G9
G5
G6
BYTE_
I/O15(A-1)
F
CE_F
OE
I/O9
I/O3
I/O4
I/O13
H2
H3
H4
H5
H6
H7
CE_S
I/O0
I/O10
VCC_F
J3
J4
J5
J6
J7
J8
I/O8
I/O2
I/O11
NC
I/O5
I/O14
K1
K5
K6
K10
NC
NC
NC
NC
VCC_S
I/O12
SRAM only
H8
H9
I/O7
VSS
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time
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AMIC Technology, Corp.
A81L801
Product Information Guide
Part Number
A81L801
Standard Voltage Range:
VCC_F/VCC_S=2.7-3.6V
Speed Options
70
Max Access Time (ns)
CE_F / CE_S Access (ns)
70
70
OE Access (ns)
40
MCP Block Diagram
VCC_F
VSS
A18 to A0
A18 to A0
RY/BY
BYTE_F
RESET
8M Bit
Flash Memory
CE_F
I/O15 (A-1) to I/O0
I/O15 (A-1) to I/O0
VCC_S
VSS
A16 to A0
WE
1M Bit
Static RAM
I/O15 (A-1) to I/O0
OE
CE_S
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(March, 2005, Version 0.0)
4
AMIC Technology, Corp.
A81L801
Flash Memory Block Diagram
RY/BY
I/O0 - I/O15 (A-1)
VCC_F
VSS
Sector Switches
RESET
WE
Input/Output
Buffers
Erase Voltage
Generator
State
Control
BYTE_F
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE_F
OE
VCC Detector
Address Latch
STB
Timer
A0-A18
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STB
Data Latch
Y-Decoder
Y-Gating
X-decoder
Cell Matrix
AMIC Technology, Corp.
A81L801
SRAM Block Diagram
A0
A14
A15
ROW
512 X 2048
DECODER
MEMORY ARRAY
INPUT DATA
CIRCUIT
COLUMN I/O
VCC_S
VSS
A16
I/O0
I/O7
OE
CE_S
WE
PRELIMINARY
CONTROL
CIRCUIT
(March, 2005, Version 0.0)
6
AMIC Technology, Corp.
A81L801
Pin Description
Logic Symbol
Pin No.
A18-A0
I/O14 - I/O0
Description
18 Address Inputs (Common)
18
15 Data Inputs/Outputs (Common)
I/O15 Data Input/Output, Word Mode
I/O15 (A-1)
A-1
CE_F
Chip Enable (Flash)
CE_S
A17-A0
LSB Address Input, Byte Mode
I/O15-I/O0
Chip Enable (SRAM)
OE
Output Enable (Common)
WE
Write Enable (Common)
CE_F
CE_S
RY/BY
OE
RY/ BY
Ready/ BUSY - Output
RESET
Hardware Reset Pin, Active Low
WE
BYTE_F
Select Byte Mode or Word Mode
BYTE_F
VCC_F
Power Supply (Flash)
RESET
VCC_S
Power Supply (SRAM)
VSS
Device Ground (Common)
NC
Pin Not Connected Internally
PRELIMINARY
16 or 8
A-1
(March, 2005, Version 0.0)
7
AMIC Technology, Corp.
A81L801 Series
Absolute Maximum Ratings*
*Comments
Storage Temperature Plastic Packages. . . . . .-65°C to + 150°C
Ambient Temperature with Power Applied . . . -55°C to + 125°C
Voltage with Respect to Ground VCC_F/VCC_S . . . . (Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V
A9, OE & RESET (Note 2) . . . . . . . . . . . . . . . . -0.5 to +12.5V
All other pins (Note 1) . . . . . .. -0.5V to VCC_F/VCC_ S + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . 200mA
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device. These
are
stress
ratings
only.
Functional
operation
of
this device at these or any other conditions above
those indicated in the operational sections of this specification
is
not
implied
or
intended.
Exposure
to
the absolute maximum rating conditions for extended periods
may affect device reliability.
Notes:
Operating Ranges
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS to
-2.0V for periods of up to 20ns. Maximum DC voltage on
input and I/O pins is VCC_F/VCC_S +0.5V. During voltage
transitions, input or I/O pins may overshoot to
VCC_F/VCC_S +2.0V for periods up to 20ns.
2. Minimum DC input voltage on A9, OE and RESET is 0.5V. During voltage transitions, A9, OE and RESET may
overshoot VSS to -2.0V for periods of up to 20ns. Maximum
DC input voltage on A9 is +12.5V which may overshoot to
14.0V for periods up to 20ns.
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . .. . . .. . . . . 0°C to +70°C
Extended Range Devices
Ambient Temperature (TA)
For – I series . . . . . . . . . . . . . . . . . .. . . . . . . . . -25°C to + 85°C
VCC Supply Voltages
VCC_F/VCC_S ……. … . . . . . . . . . . . . . . . . . . +2.7V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the device
bus operations, which are initiated through the internal
command register. The command register itself does not
occupy any addressable memory location. The register is
composed of latches that store the commands, along with the
address and data information needed to execute the
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command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
AMIC Technology, Corp.
A81L801
Table 1.1 Device Bus Operations—Flash Word Mode BYTE_F = VIH
Operation
I/O7-I/O0
I/O15-I/O8
CE_F
CE_S
OE
WE
A0-A18
Read from Flash
L
H
L
H
AIN
H
DOUT
DOUT
Standby
H
H
X
X
X
H
High-Z
High-Z
Output Disable
L
H
H
H
X
H
High-Z
High-Z
Write to Flash (Program/Erase)
L
H
H
L
AIN
H
DIN
DIN
Sector Protect
L
H
H
Sector Address,
A6=L, A1=H, A0=L
H
DIN
X
Sector Unprotect
L
H
L
L
Sector Address,
A6=L, A1=H, A0=L
H
DIN
X
Temporary Sector Unprotection
X
H
X
X
AIN
VID
DIN
X
Flash Reset (Hardware) / Standby
X
H
X
X
X
L
High-Z
High-Z
Boot Block Sector Write Protect
X
H
X
X
X
X
X
X
DOUT
DOUT
High-Z
DOUT
DOUT
High-Z
DIN
DIN
High-Z
DIN
DIN
High-Z
RESET
(Notes 1,2)
Read from SRAM
Write to SRAM
H
H
L
L
L
H
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5V,
H
L
AIN
AIN
H
H
= Pulse input, X = Don’t Care, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE_F = VIL, CE_S = VIL at the same time.
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AMIC Technology, Corp.
A81L801
Table 1.2 Device Bus Operations—Flash Word Mode BYTE_F = VIL
Flash Operation
CE_F
CE_S
OE
WE
I/O15
A0-A18
RESET
I/O7-I/O0
I/O14-I/O8
(A-1)
(Notes 1,2)
Read from Flash
L
H
L
H
A-1
AIN
H
DOUT
High-Z
Standby
H
H
X
X
X
X
H
High-Z
High-Z
Output Disable
L
H
H
H
X
X
H
High-Z
High-Z
Write to Flash (Program/Erase)
L
H
H
L
A-1
AIN
H
DIN
High-Z
Sector Protect
L
H
VID
L
Sector Address,
A6=L, A1=H, A0=L
VID
X
High-Z
Sector Unprotect
L
H
L
H
L
Sector Address,
A6=L, A1=H, A0=L
VID
Code
High-Z
Temporary Sector Unprotection
X
H
X
X
X
AIN
VID
X
High-Z
Flash Reset (Hardware)/
X
H
X
X
X
X
L
High-Z
High-Z
X
H
X
X
X
X
X
X
High-Z
DOUT
DOUT
High-Z
High-Z
High-z
DOUT
DOUT
DIN
DIN
DIN
High-Z
High-Z
DIN
DIN
Standby
Boot Block Sector Write Protect
DOUT
Read from SRAM
Write to SRAM
H
H
L
L
L
H
H
L
DOUT
DIN
High-z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5V,
A0
A0
H
H
= Pulse input, X = Don’t Care, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE_F = VIL, CE_S = VIL at the same time.
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AMIC Technology, Corp.
A81L801
Word/Byte Configuration
The BYTE_F pin determines whether the I/O pins I/O15-I/O0
operate in the byte or word configuration. If the BYTE_F pin is
set at logic ”1”, the device is in word configuration, I/O15-I/O0
are active and controlled by CE_F and OE .
If the BYTE_F pin is set at logic “0”, the device is in byte
configuration, and only I/O0-I/O7 are active and controlled by
CE_F and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is used
as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the
CE_F and OE pins to VIL. CE_F is the power control and
selects the device. OE is the output control and gates array
data to the output pins. WE should remain at VIH all the time
during read operation. The BYTE_F pin determines whether
the device outputs array data in words and bytes. The internal
state machine is set for reading array data upon device powerup, or after a hardware reset. This ensures that no spurious
alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce valid
data on the device data outputs. The device remains enabled
for read access until the command register contents are
altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
lCC1 in the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE_F to VIL, and
OE to VIH. For program operations, the BYTE_F pin
determines whether the device accepts program data in bytes
or words, Refer to “Word/Byte Configuration” for more
information. The device features an Unlock Bypass mode to
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “
Word / Byte Program Command Sequence” section has details
on programming data to the device using both standard and
Unlock Bypass command sequence. An erase operation can
erase one sector, multiple sectors, or the entire device. The
Sector Address Tables indicate the address range that each
sector occupies. A "sector address" consists of the address
inputs required to uniquely select a sector. See the "Command
Definitions" section for details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the auto-select command sequence,
the device enters the auto-select mode. The system can then
read auto-select codes from the internal register (which is
separate from the memory array) on I/O7 - I/O0. Standard read
cycle timings apply in this mode. Refer to the "Auto-select
Mode" and "Auto-select Command Sequence" sections for
more information.
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ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables and
timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check
the status of the operation by reading the status bits on I/O7 I/O0. Standard read cycle timings and ICC read specifications
apply. Refer to "Write Operation Status" for more information,
and to each AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE input.
The device enters the CMOS standby mode when the CE_F &
RESET pins are both held at VCC_F ± 0.3V. (Note that this is
a more restricted voltage range than VIH.) If CE_F and RESET
are held at VIH, but not within VCC_F ± 0.3V, the device will be
in the standby mode, but the standby current will be greater.
The device requires the standard access time (tCE) before it is
ready to read data.
If the device is deselected during erasure or programming, the
device draws active current until the operation is completed.
ICC3 and ICC4 in the DC Characteristics tables represent the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
sleep mode is independent of the CE_F , WE and OE control
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. ICC4 in the
DC Characteristics table represents the automatic sleep mode
current specification.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
RESET : Hardware Reset Pin
The RESET pin provides a hardware method of resetting the
device to reading array data. When the system drives the
RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tri-states all
data output pins, and ignores all read/write attempts for the
duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation that
was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET pulse. When
RESET is held at VSS ± 0.3V, the device draws CMOS
standby current (ICC4). If RESET is held at VIL but not within
VSS ± 0.3V, the standby current will be greater.
AMIC Technology, Corp.
A81L801
to determine whether the reset operation is complete. If
RESET is asserted when a program or erase operation is not
executing (RY/ BY pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algorithms). The
system can read data tRH after the RESET pin return to VIH.
Refer to the AC Characteristics tables for RESET parameters
and diagram.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory, enabling
the system to read the boot-up firmware from the Flash
memory.
If RESET is asserted during a program or erase operation,
the RY/ BY pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor RY/ BY
Table 2. A81L801 Top Boot Block Sector Address Table
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Byte Mode (x 8)
Word Mode (x16)
SA0
0
0
0
0
X
X
X
64/32
00000h - 0FFFFh
00000h - 07FFFh
SA1
0
0
0
1
X
X
X
64/32
10000h - 1FFFFh
08000h - 0FFFFh
SA2
0
0
1
0
X
X
X
64/32
20000h - 2FFFFh
10000h - 17FFFh
SA3
0
0
1
1
X
X
X
64/32
30000h - 3FFFFh
18000h - 1FFFFh
SA4
0
1
0
0
X
X
X
64/32
40000h - 4FFFFh
20000h - 27FFFh
SA5
0
1
0
1
X
X
X
64/32
50000h - 5FFFFh
28000h - 2FFFFh
SA6
0
1
1
0
X
X
X
64/32
60000h - 6FFFFh
30000h - 37FFFh
SA7
0
1
1
1
X
X
X
64/32
70000h - 7FFFFh
38000h - 3FFFFh
SA8
1
0
0
0
X
X
X
64/32
80000h - 8FFFFh
40000h - 47FFFh
SA9
1
0
0
1
X
X
X
64/32
90000h - 9FFFFh
48000h - 4FFFFh
SA10
1
0
1
0
X
X
X
64/32
A0000h - AFFFFh
50000h - 57FFFh
SA11
1
0
1
1
X
X
X
64/32
B0000h - BFFFFh
58000h - 5FFFFh
SA12
1
1
0
0
X
X
X
64/32
C0000h - CFFFFh
60000h - 67FFFh
SA13
1
1
0
1
X
X
X
64/32
D0000h - DFFFFh
68000h - 6FFFFh
SA14
1
1
1
0
X
X
X
64/32
E0000h - EFFFFh
70000h - 77FFFh
SA15
1
1
1
1
0
X
X
32/16
F0000h - F7FFFh
78000h - 7BFFFh
SA16
1
1
1
1
1
0
0
8/4
F8000h - F9FFFh
7C000h - 7CFFFh
SA17
1
1
1
1
1
0
1
8/4
FA000h - FBFFFh
7D000h - 7DFFFh
SA18
1
1
1
1
1
1
X
16/8
FC000h - FFFFFh
7E000h - 7FFFFh
Note:
Address range is A18: A-1 in byte mode and A18: A0 in word mode. See “Word/Byte Configuration” section.
PRELIMINARY
(March, 2005, Version 0.0)
12
AMIC Technology, Corp.
A81L801
Table 3. A81L801 Bottom Boot Block Sector Address Table
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Byte Mode (x 8)
Word Mode (x16)
SA0
0
0
0
0
0
0
X
16/8
00000h - 03FFFh
00000 - 01FFF
SA1
0
0
0
0
0
1
0
8/4
04000h - 05FFFh
02000 - 02FFF
SA2
0
0
0
0
0
1
1
8/4
06000h - 07FFFh
03000 - 03FFF
SA3
0
0
0
0
1
X
X
32/16
08000h - 0FFFFh
04000 - 07FFF
SA4
0
0
0
1
X
X
X
64/32
10000h - 1FFFFh
08000 - 0FFFF
SA5
0
0
1
0
X
X
X
64/32
20000h – 2FFFFh
10000 - 17FFF
SA6
0
0
1
1
X
X
X
64/32
30000h - 3FFFFh
18000 - 1FFFF
SA7
0
1
0
0
X
X
X
64/32
40000h - 4FFFFh
20000 - 27FFF
SA8
0
1
0
1
X
X
X
64/32
50000h - 5FFFFh
28000 - 2FFFF
SA9
0
1
1
0
X
X
X
64/32
60000h - 6FFFFh
30000 - 37FFF
SA10
0
1
1
1
X
X
X
64/32
70000h - 7FFFFh
38000 - 3FFFF
SA11
1
0
0
0
X
X
X
64/32
80000h - 8FFFFh
40000 - 47FFF
SA12
1
0
0
1
X
X
X
64/32
90000h - 9FFFFh
48000 - 4FFFF
SA13
1
0
1
0
X
X
X
64/32
A0000h - AFFFFh
50000 - 57FFF
SA14
1
0
1
1
X
X
X
64/32
B0000h - BFFFFh
58000 - 5FFFF
SA15
1
1
0
0
X
X
X
64/32
C0000h - CFFFFh
60000 - 67FFF
SA16
1
1
0
1
X
X
X
64/32
D0000h - DFFFFh
68000 - 6FFFF
SA17
1
1
1
0
X
X
X
64/32
E0000h - EFFFFh
70000 - 77FFF
SA18
1
1
1
1
X
X
X
64/32
F0000h - FFFFFh
78000 - 7FFFF
Note:
Address range is A18: A-1 in byte mode and A18: A0 in word mode. See “Word/Byte Configuration” section.
PRELIMINARY
(March, 2005, Version 0.0)
13
AMIC Technology, Corp.
A81L801
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match a
device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pin A9. Address pins
A6, A1, and A0 must be as shown in autoselect Codes (High
Voltage Method) table. In addition, when verifying sector
protection, the sector address must appear on the appropriate
highest order address bits. Refer to the corresponding Sector
Address Tables. The Command Definitions table shows the
remaining address bits that are don't care. When all necessary
bits have been set as required, the programming equipment
may then read the corresponding identifier code on I/O7 I/O0.To access the autoselect codes in-system, the host
system can issue the autoselect command via the command
register, as shown in the Command Definitions table. This
method does not require VID. See "Command Definitions" for
details on using the autoselect mode.
Table 4. A81L801 Autoselect Codes (High Voltage Method)
Description
Mode
Manufacturer ID: AMIC
Device ID:
A81L801
(Top Boot Block)
Word
Device ID:
A81L801
(Bottom Boot Block)
Word
Byte
Byte
Continuation ID
Sector Protection Verification
CE_F
OE
WE
A18
to
A12
A11
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
I/O8
to
I/O15
L
L
H
X
X
VID
X
L
X
L
L
X
37h
B3h
1Ah
X
1Ah
B3h
9Bh
X
9Bh
X
7Fh
X
01h
(protected)
X
00h
(unprotected)
L
L
H
X
X
VID
X
L
X
L
H
L
L
H
X
X
VID
X
L
X
L
H
L
L
H
X
X
VID
X
L
X
H
H
L
L
H
SA
X
VID
X
L
X
H
L
I/O7
to
I/O0
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care, CE_S = VIH
Note: The autoselect codes may also be accessed in-system via command sequences.
PRELIMINARY
(March, 2005, Version 0.0)
14
AMIC Technology, Corp.
A81L801
Sector Protection/Unprotection
Temporary Sector Unprotect
The hardware sector protection feature disables both program
and erase operations in any sector. The hardware sector
unprotection features re-enables both program and erase
operations in previously protected sectors.
It is possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
Sector protection / unprotection can be implemented via two
methods. The primary method requires VID on the RESET pin
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithm and the
Sector Protect / Unprotect Timing Diagram illustrates the timing
waveforms for this feature. This method uses standard
microprocessor bus cycle timing. For sector unprotect, all
unprotected sectors must first be protected prior to the first
sector unprotect write cycle. The alternate method must be
implemented using programming equipment. The procedure
requires a high voltage (VID) on address pin A9 and the control
pins.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET pin to VID.
During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once VID is removed from the RESET pin, all the previously
protected sectors are protected again. Figure 1 shows the
algorithm, and the Temporary Sector Unprotect diagram shows
the timing waveforms, for this feature.
Hardware Data Protection
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table). In
addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device is
powered up to read array data to avoid accidentally writing
data to the array.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE , CE_F or WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE =VIL,
CE_F = VIH or WE = VIH. To initiate a write cycle, CE_F
and WE must be a logical zero while OE is a logical one.
START
RESET = VID
(Note 1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotect
Completed (Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 1. Temporary Sector Unprotect Operation
Power-Up Write Inhibit
If WE = CE_F = VIL and OE = VIH during power up, the
device does not accept commands on the rising edge of WE .
The internal state machine is automatically reset to reading
array data on the initial power-up.
PRELIMINARY
(March, 2005, Version 0.0)
15
AMIC Technology, Corp.
A81L801
START
START
Protect all sectors:
The indicated portion of
the sector protect
algorithm must be
performed for all
unprotected sectors prior
to issuing the first sector
unprotect address
PLSCNT=1
RESET=V ID
Wait 1 us
No
Temporary Sector
Unprotect Mode
PLSCNT=1
RESET=V ID
Wait 1 us
No
First Write
Cycle=60h?
First Write
Cycle=60h?
All sectors
protected?
Sector Protect
Write 60h to sector
address with A6=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 150 us
Increment
PLSCNT
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
No
Reset
PLSCNT=1
Wait 15 ms
Read from
sector address
with A6=0,
A1=1, A0=0
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Increment
PLSCNT
No
PLSCNT
=25?
No
Read from sector
address with A6=1,
A1=1, A0=0
Data=01h?
No
Set up
next sector
address
Yes
Yes
Protect another
sector?
Device failed
PLSCNT=
1000?
Yes
No
Remove V ID
from RESET
Device failed
Write reset
command
Sector Protect
complete
Yes
Yes
No
Sector Protect
Algorithm
Data=00h?
Last sector
verified?
No
Yes
Remove V ID
from RESET
Sector Unprotect
Algorithm
Write reset
Command
Sector Unprotect
complete
Figure 2. In-System Sector Protect/Unprotect Algorithms
PRELIMINARY
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16
AMIC Technology, Corp.
A81L801
Command Definitions
Autoselect Command Sequence
Writing specific address and data commands or sequences into
the command register initiates device operations. The
Command Definitions table defines the valid register command
sequences. Writing incorrect address and data values or writing
them in the improper sequence resets the device to reading
array data.
All addresses are latched on the falling edge of WE or CE_F ,
whichever happens later. All data is latched on the rising edge
of WE or CE_F , whichever happens first. Refer to the
appropriate timing diagrams in the "AC Characteristics" section.
The autoselect command sequence allows the host system to
access the manufacturer and devices codes, and determine
whether or not a sector is protected. The Command Definitions
table shows the address and data requirements. This method is
an alternative to that shown in the Autoselect Codes (High
Voltage Method) table, which is intended for PROM
programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The device
then enters the autoselect mode, and the system may read at
any address any number of times, without initiating another
command sequence.
A read cycle at address XX00h retrieves the manufacturer code
and another read cycle at XX03h retrieves the continuation
code. A read cycle at address XX01h returns the device code. A
read cycle containing a sector address (SA) and the address
02h in returns 01h if that sector is protected, or 00h if it is
unprotected. Refer to the Sector Address tables for valid sector
addresses.
The system must write the reset command to exit the autoselect
mode and return to reading array data.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The device is also ready to read array data after completing an
Embedded Program or Embedded Erase algorithm. After the
device accepts an Erase Suspend command, the device enters
the Erase Suspend mode. The system can read array data
using the standard read timings, except that if it reads at an
address within erase-suspended sectors, the device outputs
status data. After completing a programming operation in the
Erase Suspend mode, the system may once again read array
data with the same exception. See "Erase Suspend/Erase
Resume Commands" for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the "Device
Bus Operations" section for more information. The Read
Operations table provides the read parameters, and Read
Operation Timings diagram shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to
reading array data. Addresses bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data (also
applies to programming in Erase Suspend mode). Once
programming begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to return
to reading array data (also applies to autoselect during Erase
Suspend).
If I/O5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
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17
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE_F pin. Programming is a
four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data are
written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further controls
or timings. The device automatically provides internally
generated program pulses and verify the programmed cell
margin. Table 5 shows the address and data requirements for
the byte program command sequence.
When the Embedded Program algorithm is complete, the device
then returns to reading array data and addresses are longer
latched. The system can determine the status of the program
operation by using I/O7, I/O6, or RY/ BY . See “White Operation
Status” for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the programming operation. The Byte
Program command sequence should be reinitiated once the
device has reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0” back to a
“1”. Attempting to do so may halt the operation and set I/O5 to
“1”, or cause the Data Polling algorithm to indicate the
operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can convert
a “0” to a “1”.
AMIC Technology, Corp.
A81L801
Addresses are don’t care for both cycle. The device returns to
reading array data.
Figure 3 illustrates the algorithm for the program operation. See
the Erase/Program Operations in “AC Characteristics” for
parameters, and to Program Operation Timings for timing
diagrams.
START
Write Program
Command
Sequence
Embedded
Program
algorithm in
progress
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which in
turn invokes the Embedded Erase algorithm. The device does
not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the Embedded Erase
algorithm are ignored. The system can determine the status of
the erase operation by using I/O7, I/O6, or I/O2. See "Write
Operation Status" for information on these status bits. When the
Embedded Erase algorithm is complete, the device returns to
reading array data and addresses are no longer latched.
Figure 4 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics" for
parameters, and to the Chip/Sector Erase Operation Timings
for timing waveforms.
Data Poll
from System
Verify Data ?
No
Yes
Increment Address
Last Address ?
Yes
Sector Erase Command Sequence
Programming
Completed
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 3. Program Operation
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes
or words to the device faster than using the standard program
command sequence. The unlock bypass command sequence
is initiated by first writing two unlock cycles. This is followed by
a third write cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h;
the second cycle contains the program address and data.
Additional data is programmed in the same manner. This mode
dispenses with the initial two unlock cycles required in the
standard program command sequence, resulting in faster total
programming time. Table 5 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the twocycle unlock bypass reset command sequence. The first cycle
must contain the data 90h; the second cycle the data 00h.
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18
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements for
the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out
of 50µs begins. During the time-out period, additional sector
addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any sequence,
and the number of sectors may be from one sector to all
sectors. The time between these additional cycles must be less
than 50µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that
processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after
the last Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be less
than 50µs, the system need not monitor I/O3. Any command
other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data. The system must
rewrite the command sequence and any additional sector
addresses and commands.
The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
AMIC Technology, Corp.
A81L801
section.) The time-out begins from the rising edge of the final
WE pulse in the command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, or I/O2. Refer to "Write Operation
Status" for information on these status bits.
4 illustrates the algorithm for the erase operation. Refer to the
Erase/Program Operations tables in the "AC Characteristics"
section for parameters, and to the Sector Erase Operations
Timing diagram for timing waveforms.
The system may also write the autoselect command sequence
when the device is in the Erase Suspend mode. The device
allows reading autoselect codes even at addresses within
erasing sectors, since the codes are not stored in the memory
array. When the device exits the autoselect mode, the device
reverts to the Erase Suspend mode, and is ready for another
valid operation. See "Autoselect Command Sequence" for
more information.
The system must write the Erase Resume command (address
bits are "don't care") to exit the erase suspend mode and
continue the sector erase operation. Further writes of the
Resume command are ignored. Another Erase Suspend
command can be written after the device has resumed erasing.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a
sector erase operation and then read data from, or program
data to, any sector not selected for erasure. This command is
valid only during the sector erase operation, including the 50µs
time-out period during the sector erase command sequence.
The Erase Suspend command is ignored if written during the
chip erase operation or Embedded Program algorithm. Writing
the Erase Suspend command during the Sector Erase time-out
immediately terminates the time-out period and suspends the
erase operation. Addresses are "don't cares" when writing the
Erase Suspend command.
When the Erase Suspend command is written during a sector
erase operation, the device requires a maximum of 20µs to
suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-out,
the device immediately terminates the time-out period and
suspends the erase operation.
After the erase operation has been suspended, the system can
read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all sectors
selected for erasure.) Normal read and write timings and
command definitions apply. Reading at any address within
erase-suspended sectors produces status data on I/O7 - I/O0.
The system can use I/O7, or I/O6 and I/O2 together, to
determine if a sector is actively erasing or is erase-suspended.
See "Write Operation Status" for information on these status
bits.
After an erase-suspended program operation is complete, the
system can once again read array data within non-suspended
sectors. The system can determine the status of the program
operation using the I/O7 or I/O6 status bits, just as in the
standard program operation. See "Write Operation Status" for
more information.
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(March, 2005, Version 0.0)
19
START
Write Erase
Command
Sequence
Data Poll
from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
Yes
Erasure Completed
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O3 : Sector Erase Timer" for more information.
Figure 4. Erase Operation
AMIC Technology, Corp.
A81L801
Cycles
Table 5. A81L801 Command Definitions
Command
Sequence
(Note 1)
Bus Cycles (Notes 2 - 5)
First
Addr Data
Read (Note 6)
1
RA
RD
Reset (Note 7)
1
XXX
F0
Word
Autoselect (Note 8)
Manufacturer ID
Device ID,
Top Boot Block
Device ID,
Bottom Boot Block
Continuation ID
Sector Protect Verify
(Note 9)
Program
Byte
4
Word
Byte
4
Word
AAA
555
AA
AA
AAA
Word
Byte
555
4
4
555
Second
Addr Data
2AA
555
2AA
555
55
AAA
2AA
555
55
555
555
AA
2AA
90
90
AAA
90
AAA
555
55
90
X00
37
X01
B31A
X02
1A
X01
B39B
X02
9B
X03
AAA
555
AAA
X06
Word
555
2AA
555
(SA)
X02
4
AA
55
90
Byte
AAA
555
AAA
Word
555
2AA
555
Word
Byte 3
Unlock Bypass Program (Note 10) 2
AA
AAA
555
AAA AA
XXX A0
555
2AA
555
PA
4
55
2
XXX 90
XXX
00
Unlock Bypass
Unlock Bypass Reset (Note 11)
Word
Byte
6
Word
Sector Erase
AAA
Byte
Byte
Chip Erase
555
55
555
AA
Third
Fourth
Addr Data Addr Data
Byte
6
555
AAA
555
Erase Suspend (Note 12)
1
AAA
XXX
Erase Resume (Note 13)
1
XXX
AA
AA
B0
30
2AA
555
2AA
555
55
AAA
555
AAA
(SA)
X04
A0
PA
Fifth
Addr Data
Sixth
Addr Data
7F
XX00
XX01
00
01
PD
20
PD
555
55
AAA
555
55
AAA
80
80
555
AAA
555
AAA
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE_F pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE_F pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18 - A12 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Data bits I/O15~I/O8 are don’t care for unlock and command cycles.
5. Address bits A18 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high (while
the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
13. The Erase Resume command is valid only during the Erase Suspend mode.
PRELIMINARY
(March, 2005, Version 0.0)
20
AMIC Technology, Corp.
A81L801
Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/ BY are provided in
the A81L801 to determine the status of a write operation in the
flash memory. Table 6 and the following subsections describe
the functions of these status bits. I/O7, I/O6 and RY/ BY each
offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
START
Read I/O7-I/O0
Address = VA
I/O7: Data Polling
The Data Polling bit, I/O7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data Polling is
valid after the rising edge of the final WE pulse in the program
or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7. This
I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
protected sector, Data Polling on I/O7 is active for
approximately 2µs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data Polling produces
a "0" on I/O7. When the Embedded Erase algorithm is
complete, or if the device enters the Erase Suspend mode,
Data Polling produces a "1" on I/O7.This is analogous to the
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in a
sector to "1"; prior to this, the device outputs the "complement,"
or "0." The system must provide an address within any of the
sectors selected for erasure to read valid status information on
I/O7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on I/O7 is
active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors,
and ignores the selected sectors that are protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0 on
the following read cycles. This is because I/O7 may change
asynchronously with I/O0 - I/O6 while Output Enable ( OE ) is
asserted low. The Data Polling Timings (During Embedded
Algorithms) in the "AC Characteristics" section illustrates this.
Table 6 shows the outputs for Data Polling on I/O7. Figure 5
shows the Data Polling algorithm.
Yes
I/O7 = Data ?
No
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Address = VA
Yes
I/O7 = Data ?
No
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O7 should be rechecked even if I/O5 = "1" because
I/O7 may change simultaneously with I/O5.
Figure 5. Data Polling Algorithm
PRELIMINARY
(March, 2005, Version 0.0)
21
AMIC Technology, Corp.
A81L801
RY/ BY : Read/ Busy
The RY/ BY is a dedicated, open-drain output pin that indicates
whether an Embedded algorithm is in progress or complete.
The RY/ BY status is valid after the rising edge of the final WE
pulse in the command sequence. Since RY/ BY is an opendrain output, several RY/ BY pins can be tied together in
parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 6 shows the outputs for RY/ BY . Refer to “ RESET
Timings”, “Timing Waveforms for Program Operation” and
“Timing Waveforms for Chip/Sector Erase Operation” for more
information.
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I may
be read at any address, and is valid after the rising edge of the
final WE pulse in the command sequence (prior to the
program or erase operation), and during the sector erase timeout.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
(The system may use either OE or CE_F to control the read
cycles.) When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100µs, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the device
enters the Erase Suspend mode, I/O6 stops toggling. However,
the system must also use I/O2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system can use
I/O7 (see the subsection on " I/O7: Data Polling").
If a program address falls within a protected sector, I/O6 toggles
for approximately 2µs after the program command sequence is
written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode, and
stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for Toggle
Bit I on I/O6. Refer to Figure 6 for the toggle bit algorithm, and
to the Toggle Bit Timings figure in the "AC Characteristics"
section for the timing diagram. The I/O2 vs. I/O6 figure shows
the differences between I/O2 and I/O6 in graphical form. See
also the subsection on " I/O2: Toggle Bit II".
I/O2: Toggle Bit II
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE pulse in the command sequence.
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(March, 2005, Version 0.0)
22
I/O2 toggles when the system reads at addresses within those
sectors that have been selected for erasure. (The system may
use either OE or CE_F to control the read cycles.) But I/O2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer
to Table 6 to compare outputs for I/O2 and I/O6.
Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle
Bit Timings figure for the toggle bit timing diagram. The I/O2
vs. I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form.
Reading Toggle Bits I/O6, I/O2
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7 - I/O0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and store
the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O7 - I/O0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit is
no longer toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the device did
not complete the operation successfully, and the system must
write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6).
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and when
the operation has exceeded the timing limits, I/O5 produces a
"1."
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
AMIC Technology, Corp.
A81L801
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase operation
has begun. (The sector erase timer does not apply to the chip
erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector
erase command. When the time-out is complete, I/O3 switches
from "0" to "1." The system may ignore I/O3 if the system can
guarantee that the time between additional sector erase
commands will always be less than 50µs. See also the "Sector
Erase Command Sequence" section.
After the sector erase command sequence is written, the
system should read the status on I/O7 ( Data Polling) or I/O6
(Toggle Bit I) to ensure the device has accepted the command
sequence, and then read I/O3. If I/O3 is "1", the internally
controlled erase cycle has begun; all further commands (other
than Erase Suspend) are ignored until the erase operation is
complete. If I/O3 is "0", the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status of I/O3
prior to and following each subsequent sector erase
command. If I/O3 is high on the second status check, the last
command might not have been accepted. Table 6 shows the
outputs for I/O3.
START
Read I/O7-I/O0
Read I/O7-I/O0
Toggle Bit
= Toggle ?
(Note 1)
No
Yes
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Twice
Toggle Bit
= Toggle ?
(Notes 1,2)
No
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O5
changes to "1". See text.
Figure 6. Toggle Bit Algorithm
PRELIMINARY
(March, 2005, Version 0.0)
23
AMIC Technology, Corp.
A81L801
Table 6. Write Operation Status
I/O7
Operation
I/O6
(Note 1)
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspended Sector
Erase-Suspend-Program
I/O5
I/O3
(Note 2)
I/O2
RY/ BY
(Note 1)
I/O7
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
0
1
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
I/O7
Toggle
0
N/A
N/A
0
Notes:
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See
“I/O5: Exceeded Timing Limits” for more information.
Maximum Negative Input Overshoot
20ns
20ns
+0.8V
-0.5V
-2.0V
20ns
Maximum Positive Input Overshoot
20ns
VCC_F+2.0V
VCC_F+0.5V
2.0V
20ns
PRELIMINARY
(March, 2005, Version 0.0)
20ns
24
AMIC Technology, Corp.
A81L801
DC Characteristics
CMOS Compatible (TA=0°C to 70°C or -25°C to + 85°C for –I)
Parameter
Symbol
Parameter Description
ILI
Input Load Current
ILIT
ILO
A9 Input Load Current
Output Leakage Current
ICC1
ICC2
ICC3
Max.
Unit
VIN = VSS to VCC_F.
VCC_F = VCC_F Max
VCC_F = VCC_F Max, A9 =12.5V
±1.0
µA
35
µA
VOUT = VSS to VCC_F.
VCC_F = VCC_F Max
±1.0
µA
9
16
Byte Mode
1 MHz
2
4
CE_F = VIL, OE = VIH
5 MHz
9
16
Word Mode
1 MHz
2
4
VCC_F Active Write (Program/Erase)
CE_F = VIL, OE =VIH
Current (Notes 2, 3, 4)
VCC_F Standby Current (Note 2)
CE_F = VIH, RESET = VCC_F ± 0.3V
20
30
mA
0.2
5
µA
RESET = VSS ± 0.3V
0.2
5
µA
VIH = VCC_F ± 0.3V; VIL = VSS ± 0.3V
0.2
5
µA
VCC_F Active Read Current
(Notes 1, 2)
VIL
Input High Level
VID
Voltage for Autoselect and
Temporary Unprotect Sector
Output Low Voltage
VOL
Typ.
5 MHz
VIH
ICC5
Min.
CE_F = VIL, OE = VIH
VCC_F Standby Current During
Reset (Note 2)
Automatic Sleep Mode
(Note 2, 4, 5)
Input Low Level
ICC4
Test Description
VOH1
Output High Voltage
VCC_F = 3.3 V
IOH = -100 µA, VCC_F = VCC_F Min
VOH2
-0.5
0.8
V
0.7 x
VCC_F
VCC_F +
0.3
V
11.5
12.5
V
0.45
V
IOL = 4.0mA, VCC_F = VCC_F Min
IOH = -2.0 mA, VCC_F = VCC_F Min
mA
0.85 x
VCC_F
VCC_F 0.4
V
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE at VIH. Typical VCC_F is 3.0V.
2. Maximum ICC specifications are tested with VCC_F = VCC_F max.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current is
200nA.
5. Not 100% tested.
PRELIMINARY
(March, 2005, Version 0.0)
25
AMIC Technology, Corp.
A81L801
DC Characteristics (continued)
Zero Power Flash
Supply Current in mA
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1MHz
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
3.6V
8
Supply Current in mA
2.7V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note : T = 25 ° C
Typical ICC1 vs. Frequency
PRELIMINARY
(March, 2005, Version 0.0)
26
AMIC Technology, Corp.
A81L801
AC Characteristics
Read Only Operations (TA=0°C to 70°C or -25°C to + 85°C for –I)
Parameter Symbols
Speed
Description
JEDEC
Std
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
Unit
Test Setup
-70
CE_F = VIL
Min.
70
ns
Max.
70
ns
Max.
70
ns
Max.
30
ns
Min.
0
ns
Min.
10
Max.
25
ns
25
ns
0
ns
OE = VIL
Chip Enable to Output Delay
tELQV
TCE_F
tGLQV
tOE
Output Enable to Output Delay
tOEH
Output Enable Hold
Time (Note 1)
OE = VIL
Read
Toggle and
Data Polling
tEHQZ
tDF
Chip Enable to Output High Z
(Notes 1)
tGHQZ
tDF
Output Enable to Output High Z
(Notes 1)
tAXQX
tOH
Output Hold Time from Addresses, CE or
OE , Whichever Occurs First (Note 1)
Min.
ns
Notes:
1. Not 100% tested.
2. See Test Conditions and Test Setup for test specifications.
Timing Waveforms for Read Only Operation
tRC
Addresses
Addresses Stable
tACC
CE_F
tDF
tOE
OE
tOEH
WE
tCE
tOH
High-Z
Output
Output Valid
High-Z
RESET
RY/BY
0V
PRELIMINARY
(March, 2005, Version 0.0)
27
AMIC Technology, Corp.
A81L801
AC Characteristics
Hardware Reset ( RESET ) (TA=0°C to 70°C or -25°C to + 85°C for –I)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max
20
µs
tREADY
RESET Pin Low (Not During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
RESET Pulse Width
RESET High Time Before Read (See Note)
RY/ BY Recovery Time
RESET Low to Standby Mode
Min
500
ns
Min
50
ns
tRP
tRH
tRB
tRPD
Min
0
ns
Min
20
µs
Note: Not 100% tested.
RESET Timings
RY/BY
CE_F, OE
tRH
RESET
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
~
~ ~
~
tReady
RY/BY
tRB
CE_F, OE
~
~
RESET
tRP
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(March, 2005, Version 0.0)
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AMIC Technology, Corp.
A81L801
Temporary Sector Unprotect (TA=0°C to 70°C or -25°C to + 85°C for –I)
Parameter
JEDEC
Std
tVIDR
Description
tRSP
All Speed Options
Unit
VID Rise and Fall Time (See Note)
Min
500
ns
RESET Setup Time for Temporary Sector
Unprotect
Min
4
µs
Note: Not 100% tested.
Temporary Sector Unprotect Timing Diagram
~
~
12V
0 or 3V
RESET
0 or 3V
tVIDR
Program or Erase Command Sequence
tVIDR
CE_F
~
~
WE
RY/BY
PRELIMINARY
(March, 2005, Version 0.0)
~ ~
~
~
tRSP
29
AMIC Technology, Corp.
A81L801
AC Characteristics
Word/Byte Configuration ( BYTE_F ) (TA=0°C to 70°C or -25°C to + 85°C for – I)
Parameter
JEDEC
Speed Option
Description
Std
Unit
-70
tELFL/tELFH
CE_F to BYTE_F Switching Low or High
Max
5
ns
tFLQZ
BYTE_F Switching Low to Output High-Z
Max
25
ns
tHQV
BYTE_F Switching High to Output Active
Min
70
ns
BYTE_F Timings for Read Operations
CE_F
OE
BYTE_F
tELFL
BYTE_F
Switching
from word to
byte mode
Data Output
(I/O0-I/O14)
I/O0-I/O14
I/O15
Output
I/O15 (A-1)
Data Output
(I/O0-I/O7)
Address Input
tFLQZ
tELFH
BYTE_F
BYTE_F
Switching
from byte to
word mode
I/O0-I/O14
Data Output
(I/O0-I/O7)
I/O15 (A-1)
Address Input
Data Output
(I/O0-I/O14)
I/O15
Output
tFHQV
BYTE_F Timings for Write Operations
CE_F
The falling edge of the last WE signal
WE
BYTE_F
tSET
(tAS)
tHOLD(tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
PRELIMINARY
(March, 2005, Version 0.0)
30
AMIC Technology, Corp.
A81L801
AC Characteristics
Erase and Program Operations (TA=0°C to 70°C or -25°C to + 85°C for –I)
Parameter
Speed
Description
Unit
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
70
ns
tAVWL
tAS
Address Setup Time
Min.
0
ns
tWLAX
tAH
Address Hold Time
Min.
45
ns
tDVWH
tDS
Data Setup Time
Min.
35
ns
tWHDX
tDH
Data Hold Time
Min.
0
ns
tOES
Output Enable Setup Time
Min.
0
ns
Read Recover Time Before Write
Min.
0
ns
tGHWL
tGHWL
-70
( OE high to WE low)
tELWL
tCS
CE_F Setup Time
Min.
0
ns
tWHEH
tCH
CE_F Hold Time
Min.
0
ns
tWLWH
tWP
Write Pulse Width
Min.
35
ns
tWHWL
tWPH
Write Pulse Width High
Min.
30
ns
Byte
Typ.
5
tWHWH1
tWHWH1
Word
Typ.
7
Sector Erase Operation (Note 2)
Typ.
0.7
sec
tvcs
VCC_F Set Up Time (Note 1)
Min.
50
µs
tRB
Recovery Time from RY/ BY
Min
0
ns
Program/Erase Valid to RY/ BY Delay
Min
90
ns
tWHWH2
tWHWH2
tBUSY
Byte Programming Operation
(Note 2)
µs
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
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31
AMIC Technology, Corp.
A81L801
Timing Waveforms for Program Operation
Program Command Sequence (last two cycles)
PA
555h
PA
tAH
PA
~
~ ~
~
Addresses
tAS
~
~
tWC
Read Status Data (last two cycles)
CE_F
~
~
tCH
OE
tWP
~
~
tWHWH1
WE
tCS
tWPH
DATA
A0h
tDH
PD
~
~
tDS
Status
DOUT
tRB
tBUSY
~
~ ~
~
RY/BY
tVCS
VCC_F
Note :
1. PA = program addrss, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
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(March, 2005, Version 0.0)
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AMIC Technology, Corp.
A81L801
Timing Waveforms for Chip/Sector Erase Operation
Erase Command Sequence (last two cycles)
tAS
~
~
tWC
SA
2AAh
VA
555h for chip erase
tAH
VA
~
~ ~
~
Addresses
Read Status Data
~
~
CE_F
OE
tCH
~
~
tWP
WE
tWPH
tWHWH2
tCS
Data
tDH
55h
30h
~
~
tDS
10h for chip erase
tBUSY
In
Progress
Complete
tRB
~
~
RY/BY
~
~
tVCS
VCC_F
Note :
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Illustratin shows device in word mode.
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AMIC Technology, Corp.
A81L801
Timing Waveforms for Data Polling (During Embedded Algorithms)
~
~
tRC
Addresses
VA
tACC
tCE_F
CE_F
tCH
VA
~
~ ~
~
VA
~
~
tOE
OE
tDF
~
~
tOEH
WE
tOH
Status Data
~
~
Complement
Complement
True
Valid Data
~
~
High-Z
I/O7
Status Data
True
Valid Data
High-Z
I/O0 - I/O6
High-Z
tBUSY
~
~
RY/BY
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
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AMIC Technology, Corp.
A81L801
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
~
~
tRC
Addresses
VA
VA
tACC
tCE_F
CE_F
VA
~
~ ~
~
VA
tCH
tOE
~
~ ~
~
OE
tDF
tOEH
WE
I/O6 , I/O2
High-Z
tBUSY
~
~
tOH
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stop togging)
~
~
RY/BY
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Timing Waveforms for Sector Protect/Unprotect
VID
VIH
~
~
RESET
SA, A6,
A1, A0
Valid*
Valid*
~
~
Valid*
Verify
~
~
Sector Protect/Unprotect
60h
60h
40h
Status
~
~
Data
1us
CE_F
Sector Protect:150us
Sector Unprotect:15ms
WE
OE
Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0
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AMIC Technology, Corp.
A81L801
Timing Waveforms for I/O2 vs. I/O6
~
~
~
~
~
~
~
~
Erase
~
~
~
~
~
~
Erase Suspend
Read
~
~
~
~
I/O2
~
~
I/O6
Erase
Suspend
Program
Erase Suspend
Read
~
~
Erase
Erase
Resume
~
~
WE
Enter Erase
Suspend Program
~
~
~
~
Erase
Suspend
~
~
Enter
Embedded
Erasing
Erase
Complete
I/O2 and I/O6 toggle with OE and CE_F
Note : Both I/O6 and I/O2 toggle with OE or CE_F. See the text on I/O6 and I/O2 in the section "Write Operation Status" for
more information.
AC Characteristics
Erase and Program Operations
Alternate CE_F Controlled Writes (TA=0°C to 70°C or -25°C to + 85°C for –I)
Parameter
Speed
Description
Unit
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
70
ns
tAVEL
tAS
Address Setup Time
Min.
0
ns
tELAX
tAH
Address Hold Time
Min.
45
ns
tDVEH
tDS
Data Setup Time
Min.
35
ns
tEHDX
-70
tDH
Data Hold Time
Min.
0
ns
tOES
Output Enable Setup Time
Min.
0
ns
tGHEL
tGHEL
Read Recover Time Before Write
( OE High to WE Low)
Min.
0
ns
tWLEL
tWS
WE Setup Time
Min.
0
ns
tEHWH
tWH
WE Hold Time
Min.
0
ns
tELEH
tCP
CE Pulse Width
Min.
35
ns
tEHEL
tCPH
CE Pulse Width High
Min.
30
ns
tWHWH1
tWHWH1
Byte
Typ.
5
µs
Word
Typ.
7
Typ.
0.7
tWHWH2
tWHWH2
Programming Operation
(Note 2)
Sector Erase Operation (Note 2)
sec
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
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AMIC Technology, Corp.
A81L801
Timing Waveforms for Alternate CE_F Controlled Write Operation
PA for program
SA for sector erase
555 for chip erase
Data Polling
~
~
555 for program
2AA for erase
PA
~
~
Addresses
tAS
tWH
tAH
~
~
tWC
~
~
WE
OE
tWHWH1 or 2
~
~
tCP
tBUSY
tCPH
CE_F
tWS
tDS
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
I/O7
DOUT
~
~
~
~
tDH
RESET
~
~
RY/BY
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Sector Erase Time
Chip Erase Time
Byte Programming Time
Typ. (Note 1)
1.0
35
35
Max. (Note 2)
8
Unit
sec
sec
300
µs
12
500
Byte Mode
11
33
µs
sec
Word Mode
7.2
21.6
sec
Word Programming Time
Chip Programming Time
(Note 3)
Comments
Excludes 00h programming
prior to erasure
Excludes system-level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC_F, 10,000 cycles. Additionally, programming
typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC_F = 2.7V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does
the device set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 5 for
further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.
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AMIC Technology, Corp.
A81L801
SRAM
DC Electrical Characteristics
Symbol
(TA = -25°C to +85°C, VCC_S = 2.7V to 3.6V, GND = 0V)
Parameter
⎜ILI⎥
Input Leakage Current
⎜ILO⎥
Output Leakage Current
ICC
70ns
Unit
Min.
Max.
-
1
µA
-
1
µA
-
3
mA
Conditions
VIN = GND to VCC_S
CE_S = VIH
Active Power Supply
Current
or OE = VIH or WE = VIL
VI/O = GND to VCC_S
CE_S = VIL
II/O = 0mA
-
30
mA
ICC2
-
3
mA
ISB
-
0.5
mA
-
5
µA
ICC1
Dynamic Operating
Min. Cycle, Duty = 100%
CE_S = VIL, CE2 = VIH
II/O = 0mA
Current
ISB1
CE_S = VIL
Standby Power Supply
Current
VIH = VCC_S, VIL = 0V
f = 1 MHZ, II/O = 0mA
VCC_S ≤ 3.3V, CE_S = VIH
VCC_S ≤ 3.3V,
CE_S ≥ VCC_S - 0.2V or VIN ≥ 0V
VOL
Output Low Voltage
-
0.4
V
IOL = 2.1mA
VOH
Output High Voltage
2.2
-
V
IOH = -1.0mA
Truth Table
Mode
I/O Operation
Supply Current
CE_S
OE
WE
H
X
X
High Z
ISB, ISB1
X
X
X
High Z
ISB, ISB1
Output Disable
L
H
H
High Z
ICC, ICC1, ICC2
Read
L
L
H
DOUT
ICC, ICC1, ICC2
Write
L
X
L
DIN
ICC, ICC1, ICC2
Standby
Note: X = H or L
PRELIMINARY
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AMIC Technology, Corp.
A81L801
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CIN*
Input Capacitance
6
pF
VIN = 0V
CI/O*
Input/Output Capacitance
8
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics
(TA = -25°C to +85°C, VCC_S = 2.7V to 3.6V)
Symbol
70 ns
Parameter
Unit
Min.
Max.
70
-
ns
-
70
ns
-
70
ns
-
35
ns
10
-
ns
5
-
ns
0
25
ns
Read Cycle
tRC
Read Cycle Time
tAA
Address Access Time
tACE1_S
tOE
CE_S
Chip Enable Access Time
Output Enable to Output Valid
tCLZ1
Chip Enable to Output in Low Z
tOLZ
Output Enable to Output in Low Z
tCHZ1
Chip Disable to Output in High Z
tOHZ
Output Disable to Output in High Z
0
25
ns
tOH
Output Hold from Address Change
10
-
ns
tWC
Write Cycle Time
70
-
ns
tCW
Chip Enable to End of Write
60
-
ns
tAS
Address Setup Time
0
-
ns
tAW
Address Valid to End of Write
60
-
ns
tWP
Write Pulse Width
50
-
ns
tWR
Write Recovery Time
0
-
ns
tWHZ
Write to Output in High Z
0
25
ns
tDW
Data to Write Time Overlap
30
-
ns
tDH
Data Hold from Write Time
0
-
ns
tOW
Output Active from End of Write
5
-
ns
CE_S
CE_S
Write Cycle
Notes: tCHZ1, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
PRELIMINARY
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AMIC Technology, Corp.
A81L801
SRAM Timing Waveforms
Read Cycle 1 (1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 2 (1, 3, 4, 6)
CE_S
tACE1
tCLZ15
tCHZ15
DOUT
PRELIMINARY
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AMIC Technology, Corp.
A81L801
Timing Waveforms (continued)
Read Cycle 3 (1)
tRC
Address
tAA
OE
tOE
tOH
tOLZ
5
CE_S
tACE1
tACE2
tOHZ5
tCHZ25
tCLZ25
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE_S = VIL.
3. Address valid prior to or coincident with CE_S transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE_S is low.
Write Cycle 1 (6)
(Write Enable Controlled)
tWC
Address
tAW
tWR3
tCW5
CE_S
(4)
tAS1
tWP2
WE
tDW
tDH
DIN
tWHZ
tOW
DOUT
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AMIC Technology, Corp.
A81L801
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
tWR3
tAW
tCW5
CE_S
tAS1
(4)
tCW5
WE
tDW
tDH
DIN
tWHZ7
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE_S , and a low WE .
3. tWR is measured from the earliest of CE_S or WE going high going low to the end of the Write cycle.
4. If
the
CE_S
low
transition
occurs
simultaneously
with
the
WE
low
transition
or
after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE_S going low going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
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AMIC Technology, Corp.
A81L801
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figures 7 and 8
TTL
TTL
CL
CL
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 8. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1 tWHZ, and tOW
Figure 7. Output Load
Retention Characteristics (TA = -25°C to 85°C)
Symbol
VDR1
Parameter
VCC for Data Retention
Min.
Max.
Unit
Conditions
2.0
3.6
V
CE_S ≥ VCC_S - 0.2V
-
1*
µA
CE_S ≥ VCC - 0.2V,
VCC_S = 1.5V,
ICCDR1
VIN ≥ 0V
Data Retention Current
-
1*
µA
VCC_S = 1.5V,
VIN ≥ 0V
Chip Disable to Data Retention Time
0
-
ns
See Retention Waveform
Operation Recovery Time
5
-
ms
ICCDR2
tCDR
tR
*
55 ns – 70 ns
PRELIMINARY
ICCDR: max.
(March, 2005, Version 0.0)
1µA at TA = 0°C to + 40°C
43
AMIC Technology, Corp.
A81L801
Low VCC Data Retention Waveform (1) ( CE_S Controlled)
DATA RETENTION MODE
VCC_S
3.0V
3.0V
tCDR
CE_S
VDR ≥ 1.5V
VIH
tR
VIH
CE_S ≥ VDR - 0.2V
PRELIMINARY
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AMIC Technology, Corp.
A81L801
Ordering Information
Top Boot Sector Flash & SRAM
Access Time
(ns)
Part No.
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby
Current
Typ. (µA)
A81L801TG-70
Package
69-ball FBGA
A81L801TG-70F
69-ball Pb-Free FBGA
70
9
20
0.2
A81L801TG-70I
69-ball FBGA
A81L801TG-70IF
69-ball Pb-Free FBGA
Note: Industrial operating temperature range: -25°C to 85°C for –I
Bottom Boot Sector Flash & SRAM
Access Time
(ns)
Part No.
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby
Current
Typ. (µA)
A81L801UG-70
Package
69-ball FBGA
A81L801UG-70F
69-ball Pb-Free FBGA
70
9
20
A81L801UG-70I
0.2
69-ball FBGA
A81L801UG-70IF
69-ball Pb-Free FBGA
Note: Industrial operating temperature range: -25°C to 85°C for –I
PRELIMINARY
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AMIC Technology, Corp.
A81L801
Package Information
69LD STF BGA (8 x 11mm) Outline Dimensions
Pin #1
-A-
D
unit: mm
D1
aaa
e
-B-
aaa
E1
E
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10
See Detail B
ddd M C
eee M C A B
See Detail A
C
CAVITY
// bbb C
b
A
A1
c
A
A2
B
-Cccc C
SOLDER BALL
1
SEATING PLANE
Detail A
Symbol
A
A1
A2
c
D
E
D1
E1
e
b
aaa
bbb
ccc
ddd
eee
MD/ME
2
3
Detail B
Dimensions in mm
Min
Nom
Max
1.40
0.25
0.30
0.35
0.91
0.96
1.01
0.22
0.26
0.30
7.90
8.00
8.10
10.90
11.00
11.10
7.20
7.20
0.80
0.35
0.40
0.45
0.15
0.20
0.12
0.15
0.08
10/10
Dimensions in inches
Min
Nom
Max
0.055
0.010
0.012
0.014
0.036
0.038
0.040
0.009
0.010
0.012
0.311
0.315
0.319
0.429
0.433
0.437
0.283
0.283
0.031
0.14
0.16
0.18
0.006
0.008
0.005
0.006
0.003
10/10
Notes:
1. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
2. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL
DIAMETER, PARALLEL TO PRIMARY DATUM C.
3. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE
EDGE OF THE SOLDER BALL AND THE BODY EDGE.
4. REFERENCE DOCUMENT : JEDEC MO-219
5. THE PATTERN OF PIN 1 FIDUCIAL IS FOR REFERENCE ONLY.
PRELIMINARY
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AMIC Technology, Corp.