ACMDM Series Advanced CMOS Logic Buffered 5-Tap Delay Modules 74ACT type input is compatible with TTL Low Profile 8-Pin Package Two Surface Mount Versions Available in Low Voltage CMOS 74LVC Logic version LVMDM Series 5 Equal Delay Taps Operating Temp. -40OC to +85OC ACMDM 8-Pin Schematic Vcc Tap1 Tap3 Tap5 8 7 6 5 1 2 3 4 IN Tap2 Tap4 Outputs can Source / Sink 24 mA Electrical Specifications at 25OC Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns) 74ACT 5 Tap 8-Pin DIP P/N Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5 ACMDM-30 ACMDM-35 ACMDM-40 ACMDM-50 ACMDM-60 ACMDM-75 ACMDM-80 ACMDM-100 ACMDM-125 ACMDM-150 ACMDM-200 ACMDM-250 6.0 7.0 8.0 10.0 12.0 15.0 16.0 20.0 25.0 30.0 40.0 50.0 12.0 14.0 16.0 20.0 24.0 30.0 32.0 40.0 50.0 60.0 80.0 100.0 18.0 21.0 24.0 30.0 36.0 45.0 48.0 60.0 75.0 90.0 120.0 150.0 24.0 28.0 32.0 40.0 48.0 60.0 64.0 80.0 100.0 120.0 160.0 200.0 30 ± 2.0 35 ± 2.0 40 ± 2.0 50 ± 2.5 60 ± 3.0 75 ± 3.75 80 ± 4.0 100 ± 5.0 125 ± 6.25 150 ± 7.5 200 ± 10.0 250 ± 12.5 Tap-to-Tap (ns) 6 ± 2.0 7 ± 2.0 8 ± 2.0 10 ± 2.0 12 ± 2.0 15 ± 2.5 16 ± 3.0 20 ± 3.0 25 ± 3.0 30 ± 3.0 40 ± 4.0 50 ± 5.0 GND TEST CONDITIONS -- Advanced CMOS, 74ACT Dimensions in Inches (mm) VCC Supply Voltage ................................................ 5.00VDC Input Pulse Voltage ................................................... 3.00V Input Pulse Rise Time ....................................... 3.0 ns max. Input Pulse Width / Period ........................... 1000 / 2000 ns 1. Measurements made at 25OC 2. Delay Times measured at 1.50V level of input to +2.50V level of Output on leading edge. 3. Rise Times measured from 10% to 90% points. 4. 50pf probe and fixture load on output under test. .120 (3.05) MIN. .020 .050 (0.51) (1.27) TYP. TYP. Supply Voltage, VCC ...................................... 5.00 ± 0.50 VDC Supply Current, ICC ........................... 14 mA typ., 28 mA max. ICCH, VIN = VCC, VCC = 5.5V ............................. 40 µA typ. ICCL, VIN = 0V, VCC = 5.5V ............................. 25 mA typ. Logic “1” Input: VIH ........................... 2.00 V min., 5.50V max. Logic “0” Input: VIL .............................................. 0.80 V max. Logic “1” Voltage Out, VOH ...................................... 3.8 V min. Logic “0” Voltage Out, VOL ................................... 0.44 V max. Max. Input Current, IIN ................................................ ± 1.0 µA Minimum Input Pulse Width ........................ 40% of Delay min. Operating Temperature Range ......................... -40O to +85OC Storage Temperature Range ......................... -65O to +150OC G-SMD .020 .050 (0.51) (1.27) TYP. TYP. J-SMD .020 .050 (0.51) (1.27) TYP. TYP. Examples: ACMDM-25G = 25ns (5ns per tap) 74ACT, 8-Pin G-SMD ACMDM-100 = 100ns (20ns per tap) 74ACT, 8-Pin DIP UKRPEXV LQGXVWULHV LQF .100 (2.54) TYP. .300 (7.62) .010 (0.25) TYP. .285 (7.24) MAX. .250 (6.35) MAX. .015 (0.38) TYP. G-SMD .030 (0.76) TYP. .430 (10.92) .400 (10.16) .008 R (0.20) .010 (0.25) TYP. .285 (7.24) MAX. .505 (12.83) MAX. 74ACT Buffered 5 Tap Delay Molded Package Series: 8-pin DIP: ACMDM Total Delay in nanoseconds (ns) Lead Style: Blank = Thru-hole G = “Gull Wing” SMD J = “J” Bend SMD www.rhombus-ind.com .100 (2.54) TYP. DIP .365 (9.27) MAX. .100 (2.54) TYP. .505 (12.83) MAX. ACMDM - XXX X 6SHFLILFDWLRQV VXEMHFW WR FKDQJH ZLWKRXW QRWLFH .020 (0.51) .250 TYP. (6.35) MAX. DIP OPERATING SPECIFICATIONS P/N Description .285 (7.24) MAX. .505 (12.83) MAX. .265 (6.73) MAX. .030 (0.76) TYP. J-SMD .285 (7.24) .260 (6.60) .330 (8.38) MAX. .020 R (0.51) )RU RWKHU YDOXHV &XVWRP 'HVLJQV FRQWDFW IDFWRU\ [email protected] 17 TEL: (714) 898-0960 FAX: (714) 896-0971 ACMDM 2001-01