AVAGO ACPL-M60L

ACPL-M60L
Small Outline, 5 Leads, High CMR, High Speed,
Logic Gate Optocouplers
Data Sheet
Description
Features
The ACPL-M60L is an optically coupled gate that combines a GaAsP light emitting diode and an integrated
high gain photo detector. The output of the detector
IC is an open collector Schottky-clamped transistor. The
internal shield provides a guaranteed common mode
transient immunity specification of 15 kV/µs at 3.3V operation.
• Dual Voltage Operation (3.3V/5V)
This unique design provides maximum AC and DC circuit
isolation while achieving LVTTL/LVCMOS compatibility.
The optocoupler AC and DC operational parameters are
guaranteed from –40˚C to +85˚C, allowing trouble-free
system performance.
• Low input current capability: 5 mA
These optocouplers are suitable for high speed logic
interfacing, input/output buffering, as line receivers in
environments that conventional line receivers cannot
tolerate and are recommended for use in extremely high
ground or induced noise environments.
• Low power consumption
• 15 kV/µs minimum Common Mode Rejection (CMR)
at VCM = 1000 V (3.3V operating voltage)
• High speed: 15 MBd typical
• LVTTL/LVCMOS compatible
• Guaranteed AC and DC performance over temperature: –40˚C to +85˚C
• Safety approvals; UL, CSA, IEC/EN/DIN EN 60747-5-2
• Surface mountable
• Very small, low profile JEDEC Registered package
outline
Applications
• Isolated line receiver
Functional Diagram
• Computer-peripheral interfaces
• Microprocessor system interfaces
ANODE 1
6 VCC
5 VO
CATHODE 3
4 GND
• Digital isolation for A/D, D/A conversion
• Switching power supply
• Instrument input/output isolation
• Ground loop elimination
• Pulse transformer replacement
• Field buses
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577 and is approved under CSA Component Acceptance Notice #5, File CA 88324.
Option
RoHS
Part Number
Compliant
Package
Surface Mount
Tape & Reel
IEC/EN/DIN EN 60747-5-2
Quantity
ACPL-M60L
-000E
SO-5
-500E
X
X
X
100 per tube
1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry. Combination of Option 020 and Option 060 is not available.
Example 1:
ACPL-M60L-500E to order product of Surface Mount SO-5 in Tape and Reel packaging with RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Schematic
+
IF
ICC
6
1
IO
5
–
4
3
VCC
VO
GND
ACPL-M60L SHIELD
USE OF A 0.1 µF BYPASS CAPACITOR
MUST BE CONNECTED BETWEEN PINS
6 AND 4 (SEE NOTE 1).
TRUTH TABLE
(POSITIVE LOGIC)
LED
OUTPUT
ON
L
OFF
H
Package Outline Drawing
ANODE
M60L
XXX
4.4 ± 0.1
(0.173 ± 0.004)
1
7.0 ± 0.2
(0.276 ± 0.008)
CATHODE
3
6
VCC
5
VOUT
4
GND
0.4 ± 0.05
(0.016 ± 0.002)
3.6 ± 0.1*
(0.142 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
2.5 ± 0.1
(0.098 ± 0.004)
0.15 ± 0.025
(0.006 ± 0.001)
7 MAX.
0.71 MIN.
(0.028)
1.27 BSC
(0.050)
MAX. LEAD COPLANARITY
= 0.102 (0.004)
DIMENSIONS IN MILLIMETERS (INCHES)
* MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006)
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
Land Pattern
4.4
(0.17)
1.3
(0.05)
2.5
(0.10)
2.0
(0.080)
0.64
(0.025)
8.27
(0.325)
Solder Reflow Temperature Profile
300
TEMPERATURE (°C)
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
200
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
2.5°C ± 0.5°C/SEC.
30
SEC.
160°C
150°C
140°C
SOLDERING
TIME
200°C
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
TIME (SECONDS)
Note: Non-halide flux should be used
Recommended PB-Free IR Profile
tp
Tp
TEMPERATURE
TL
Tsmax
260 +0/-5 °C
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
217 °C
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
25
tL
60 to 150 SEC.
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Note: Non-halide flux should be used
PEAK
TEMP.
230°C
200
250
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air Gap L (I01)
≥ 5
mm
(Clearance)
Measured from input terminals to output
terminals
Minimum External Tracking Path
L (I02)
≥ 5
mm
(Creepage)
Measured from input terminals to output
terminals
Minimum Internal Plastic Gap
0.08
mm
(Clearance)
Through insulation distance, conductor to
conductor
Tracking Resistance DIN IEC 112/VDE 0303 Part 1
CTI
Isolation Group (per DIN VDE 0109)
175
V
IIIa
Material Group DIN VDE 0109
Absolute Maximum Ratings (No Derating Required up to 85˚C)
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
–55
125
˚C
Operating Temperature†
TA
–40
85
˚C
Average Forward Input Current
IF
20
mA
Reverse Input Voltage
VR
5
V
Input Power Dissipation
PI
40
mW
Supply Voltage (1 minute maximum)
VCC
7
V
Output Collector Current
IO
50
mA
Output Collector Voltage
VO
7
V
Output Collector Power Dissipation
PO
85
mW
Solder Reflow Temperature Profile
See Package Outline Drawings section
Recommended Operating Conditions
Parameter Symbol
Min.
Max.
Units
Input Current, Low Level
IFL*
0
250
µA
Input Current, High Level[1]
IFH**
5
15
mA
2.7
4.5
3.6
5.5
V
V
–40
85
˚C
Power Supply Voltage
VCC
Operating Temperature
TA
Fan Out (at RL = 1 kΩ)[1]
N
5
TTL Loads
Output Pull-up Resistor
RL
4 k
Ω
330
*The off condition can also be guaranteed by ensuring that VFL ≤ 0.8 volts.
**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be
used for best performance and to permit at least a 20% LED degradation guardband.
Note
1
Electrical Specifications
Over recommended Operating Condition (TA = –40°C to +85°C , 2.7V ≤ VDD ≤ 3.6V) unless otherwise specified.
All Typicals at VCC = 3.3 V, TA = 25°C.
Parameter
Symbol
High Level
Output Current
Min.
Typ.
Max.
Units
Test Conditions
Fig.
IOH*
4.5
50
µA
VCC = 3.3 V, VO = 3.3 V
IF = 250 µA
1
Input Threshold
Current
ITH
3.0
5.0
mA
VCC = 3.3 V, VO = 0.6 V,
IOL (Sinking) = 13 mA
Low Level
Output Voltage
VOL*
0.35
0.6
V
VCC = 3.3 V, IF = 5 mA
IOL (Sinking) = 13 mA
High Level Supply Current
ICCH
4.7
7.0
mA
IF = 0 mA, VCC = 3.3 V
Low Level Supply Current
ICCL
7.0
10.0
mA
IF = 10 mA, VCC = 3.3 V
Input Forward
Voltage
VF
1.4
1.5
1.75*
V
TA = 25˚C, IF = 10 mA
Input Reverse
Breakdown Voltage
BVR*
5
V
IR = 10 µA
Input Diode
Temperature
Coefficient
∆VF/
∆TA
mV/˚C
IF = 10 mA
Input-Output Insulation
VISO
VRMS
RH ≤ 50%, t = 1 min.
Input Capacitance
CIN
pF
f = 1 MHz, VF = 0 V
–1.6
3750
60
Note
2
5
12, 13
*The JEDEC Registration specifies 0˚C to +70˚C. Avago specifies –40˚C to +85˚C.
Electrical Specifications
Over recommended temperature (TA = –40°C to +85°C , 4.5V ≤ VDD ≤ 5.5V) unless otherwise specified.
All Typical specification at VCC = 5V, TA = 25 °C
Parameter
Symbol
High Level
Output Current
Typ.*
Max.
Units
Test Conditions
Fig.
IOH
5.5
100
µA
VCC = 5.5 V, VO = 5.5 V
IF = 250 µA
1
Input Threshold
Current
ITH
2
5
mA
VCC = 5.5 V, IO ≥13 mA,
VO = 0.6 V
Low Level
Output Voltage
VOL
0.4
0.6
V
VCC = 5.5 V, IF = 5 mA,
IOL (Sinking) = 13 mA
High Level Supply Current
ICCH
4
7.5
mA
VCC = 5.5 V, IF = 0 mA,
Low Level Supply Current
ICCL
6
10.5
Input Forward
Voltage
V­F
1.5
1.75
Input Reverse
Breakdown Voltage
BVR
Input Diode
Temperature
Coefficient
∆VF/∆TA
Input-Output Insulation
VISO
Input Capacitance
CIN
*All typicals at TA = 25°C, VCC = 5 V.
Min.
1.4
1.3
Note
2
VCC = 5.5 V, IF = 10 mA,
V
1.85
TA = 25°C, IF = 10 mA
5
IF = 10 mA
5
IR = 10 µA
-1.6
3750
60
mV/°C
IF = 10 mA
VRMS
RH ≤ 50%, t = 1 min.
pF
VF = 0V, f = 1 MHz
12, 13
Switching Specifications
Over recommended temperature (TA = –40˚C to +85˚C), VCC = 3.3 V, IF = 7.5 mA unless otherwise specified. All Typicals at TA = 25˚C, VCC = 3.3 V.
Parameter
Symbol
Propagation Delay
Time to High Output
Level
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
tPLH
90
ns
RL = 350 Ω
CL = 15 pF
6, 7, 8
5
Propagation Delay
Time to Low Output
Level
tPHL
75
ns
RL = 350 Ω
CL = 15 pF
6, 7, 8
6
Pulse Width
Distortion
|tPHL – tPLH|
25
ns
RL = 350 Ω
CL = 15 pF
9
8
Propagation Delay
Skew
tPSK
40
ns
RL = 350 Ω
CL = 15 pF
Output Rise Time
(10-90%)
tr
45
ns
RL = 350 Ω
CL = 15 pF
Output Fall Time
(90-10%)
tf
20
ns
RL = 350 Ω
CL = 15 pF
*JEDEC registered data for the 6N137.
Switching Specifications
Over recommended temperature (TA = -40°C to 85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified.
All Typicals at TA = 25˚C, VCC = 5 V.
Parameter
Symbol
Min.
Typ.*
Max.
Unit
Test Conditions
Fig.
Note
Propagation Delay
Time to High
Output Level
tPLH
20
48
75
ns
TA = 25°C, RL=350 Ω
CL=15pF
6, 7, 8
5
Propagation Delay
Time to Low
Output Level
tPHL
6, 7, 8
6
Pulse Width
Distortion
|tPHL - tPLH|
9
8
Propagation
Delay Skew
tPSK
Output Rise Time
(10%-90%)
trise
Output Fall Time
(10%-90%)
tfall
100
50
75
ns
100
*All typicals at TA = 25°C, VCC = 5 V.
25
RL=350 Ω, CL=15pF
3.5
TA = 25°C, RL=350 Ω
CL=15pF
RL=350 Ω, CL=15pF
35
ns
RL= 350 Ω
CL = 15 pF
40
ns
RL= 350 Ω
CL = 15 pF
24
ns
RL= 350 Ω
CL = 15 pF
10
ns
RL= 350 Ω
CL = 15 pF
Parameter
Sym.
Device
Min.
Typ.
Units
Test Conditions
Logic High
Common
Mode
Transient
Immunity
|CMH|
ACPL-M60L
15,000
25,000
V/µs
|VCM| = 1000 V
10,000
15,000
Logic Low
Common
Mode
Transient
Immunity
|CML|
15,000
25,000
10,000
15,000
ACPL-M60L
V/µs
|VCM| = 1000 V
Fig.
Note
VCC = 3.3 V, IF = 0 mA,
VO(MIN) = 2 V,
RL = 350 Ω, TA = 25˚C
9
9, 11
VCC = 5 V, IF = 0 mA,
VO(MIN) = 2 V,
RL = 350 Ω, TA = 25˚C
9
9, 11
VCC = 3.3 V, IF = 7.5 mA,
VO(MAX) = 0.8 V,
RL = 350 Ω, TA = 25˚C
9
10, 11
VCC = 5 V, IF = 7.5 mA,
VO(MIN) = 0.8 V,
RL = 350 Ω, TA = 25˚C
9
10, 11
Notes:
1. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 20 mA.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 15 mA.
3. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-5 package.
4. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
5. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge
of the output pulse.
6. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge
of the output pulse.
7. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test conditions.
8. See test circuit for measurement details.
9. CMH is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state
(i.e., Vo > 2.0 V).
10. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., Vo < 0.8 V).
11. For sinusoidal voltages, (|dVCM | / dt)max = πfCMVCM (p-p).
12.Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.
13.In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (Leakage
detection current limit, II-O ≤ 5 µA).
VCC = 3.3 V
VO = 3.3 V
IF = 250 µA
10
5
0
-60 -40
-20
0
20
40
60
80 100
15
I OH - HIGH LEVEL OUTPUT CURRENT - µA
IOH – HIGH LEVEL OUTPUT CURRENT – µA
15
10
5
0
-60 -40
TA – TEMPERATURE – C
Figure 1. Typical high level output current vs. temperature.
V CC = 5.5 V
V O = 5.5 V
I F = 250 µA
-20
0
20
40
60
T A - TEMPERATURE - °C
80 100
10
VCC = 3.3 V
VO = 0.6 V
8
RL = 350 KΩ
6
RL = 1 KΩ
4
2
RL = 4 KΩ
0
-60 -40 -20
0
20
40
60
80 100
ITH – INPUT THRESHOLD CURRENT – mA
ITH – INPUT THRESHOLD CURRENT – mA
12
6
5
VCC = 5.0 V
VO = 0.6 V
4
3
RL = 350 Ω
RL = 1 kΩ
2
1
RL = 4 kΩ
0
-60 -40 -20
0
20
40
60
80 100
TA – TEMPERATURE – C
TA – TEMPERATURE – C
Figure 2. Typical input threshold current vs. Temperature
HCPL-M600 fig 13
0.5
VCC = 3.3 V
IF = 5.0 mA
V OL - LOW LEVEL OUTPUT VOLTAGE - V
VOL – LOW LEVEL OUTPUT VOLTAGE – V
0.8
0.7
0.6
0.5
0.4
IO = 13 mA
0.3
0.2
0.1
0
-60 -40
-20
0
20
40
60
80
100
V CC = 5.5 V
I F = 5.0 mA
0.4
I O = 12.8 mA
0.3
0.2
0.1
-60 -40
-20
0
20
40
60
80
100
T A - TEMPERATURE - °C
TA – TEMPERATURE – °C
Figure 3. Typical low level output voltage vs. temperature.
60
50
IF = 5.0 mA
40
20
-60 -40
-20
0
20
40
60
80
100
80
TA = 25 °C
60
40
I F = 5.0 mA
20
0
-60 -40
TA – TEMPERATURE – °C
Figure 4. Typical low level output current vs. temperature.
1000
V CC = 5.0 V
V OL = 0.6 V
IF – FORWARD CURRENT – mA
VCC = 3.3 V
VOL = 0.6 V
I OL - LOW LEVEL OUTPUT CURRENT - mA
IOL – LOW LEVEL OUTPUT CURRENT – mA
70
-20
0
20
40
60
T A - TEMPERATURE - °C
80 100
100
10
+
IF
VF
–
1.0
0.1
0.01
0.001
1.1
1.2
1.3
1.4
1.5
VF – FORWARD VOLTAGE – V
Figure 5. Typical input diode forward characteristic.
1.6
3.3 V
IF
PULSE GEN.
ZO = 50 Ω
tf = tr = 5 ns
VCC 6
1
0.1 µF
BYPASS
5
RL
OUTPUT VO
MONITORING
NODE
*CL
INPUT
MONITORING
NODE
3
GND
RM
IF = 7.50 mA
INPUT
IF
IF = 3.75 mA
tPHL
tPLH
OUTPUT
VO
4
1.5 V
*CL IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
PULSE GEN.
Z O = 50 Ω
t f = t r = 5 ns
+5 V
IF
V CC 6
1
5
INPUT
MONITORING
NODE
3
GND
RL
0.1µF
BYPASS
*C L
4
I F = 7.5 mA
INPUT
IF
OUTPUT V O
MONITORING
NODE
I F = 3.75 mA
t PHL
OUTPUT
VO
RM
1.5 V
*C L IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
Figure 6. Test circuit for tPHL and tPLH.
120
100
VCC = 3.3 V
IF = 7.5 mA
t P - PROPAGATION DELAY - ns
tP – PROPAGATION DELAY – ns
150
tPLH , RL = 350 Ω
90
60
tPHL , RL = 350 Ω
30
0
-60
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE – C
Figure 7. Typical propagation delay vs. temperature.
10
80
V CC = 5.0 V
I F = 7.5 mA
t PHL , R L = 350Ω
60
40
20
0
-60
t PLH , R L = 350Ω
-40
-20
0
20
40
60
T A - TEMPERATURE - °C
80
t PLH
100
40
VCC = 3.3 V
IF = 7.5 mA
40
PWD - PULSE WIDTH DISTORTION - ns
PWD – PULSE WIDTH DISTORTION – ns
50
30
RL = 350 Ω
20
10
0
-60
-40
-20
0
20
40
60
80
30
20
R L = 350 kΩ
10
0
-10
100
V CC = 5.0 V
I F = 7.5 mA
-60
-40
TA – TEMPERATURE – C
-20
0
20
40
60
80
100
T A - TEMPERATURE - °C
Figure 8. Typical pulse width distortion vs. temperature.
IF
B
VCC 6
1
A
5
VFF
3
GND
3.3 V
0.1 µF
BYPASS
350 Ω
OUTPUT VO
MONITORING
NODE
VCM
VO
VCM (PEAK)
0V
3.3 V
SWITCH AT A: IF = 0 mA
SWITCH AT B: IF = 7.5 mA
4
VO
0.5 V
VO (MIN.)
VO (MAX.)
CMH
CML
+
–
PULSE
GENERATOR
ZO = 50 Ω
IF
B
+5 V
1
VCC 6
A
5
VFF
3
GND
0.1 µF
BYPASS
350 Ω
OUTPUT VO
MONITORING
NODE
VCM
VO
4
VCM (PEAK)
0V
5V
VO
0.5 V
SWITCH AT A: IF = 0 mA
VO (MIN.)
SWITCH AT B: IF = 7.5 mA
VO (MAX.)
_
+
PULSE
GENERATOR
ZO = 50 Ω
Figure 9. Test circuit for common mode transient immunity and typical waveforms.
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0273EN
AV02-0891EN - December 18, 2007
CMH
CML