FEATURES 128-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Ultracompact SC70-6 (2 mm × 2.1 mm) package I2C® compatible interface Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Rheostat mode temperature coefficient: 45 ppm/°C Low power, IDD = 0.9 µA at 3.3 V typical Wide operating temperature –40°C to +125°C APPLICATIONS FUNCTIONAL BLOCK DIAGRAM VDD SCL I2C INTERFACE SDA A W B WIPER REGISTER 03875-001 Data Sheet 128-Position I2C-Compatible Digital Resistor AD5246 GND Figure 1. Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment GENERAL OVERVIEW The AD5246 provides a compact 2 mm × 2.1 mm packaged solution for 128-position adjustment applications. This device performs the same electronic adjustment function as a variable resistor. Available in four different end-to-end resistance values (5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ), these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments. The wiper settings are controllable through the I2C compatible digital interface, which can also be used to read back the present wiper register control word. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC1 latch. Operating from a 2.7 V to 5.5 V power supply and consuming 0.9 µA (3.3 V) allows for usage in portable battery-operated applications. 1 The terms digital potentiometer, VR, and RDAC are used interchangeably in this document. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113© 2003–2012 Analog Devices, Inc. All rights reserved. AD5246 Data Sheet TABLE OF CONTENTS Specifications..................................................................................... 3 Programming the Variable Resistor ......................................... 13 Electrical Characteristics—5 kΩ Version .................................. 3 I2C Compatible 2-Wire Serial Bus ........................................... 13 Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions .. 4 Level Shifting for Bidirectional Interface ................................ 14 Timing Characteristics ................................................................ 5 ESD Protection ........................................................................... 14 Absolute Maximum Ratings ............................................................ 6 Terminal Voltage Operating Range ......................................... 14 ESD CAUTION ............................................................................ 6 Maximum Operating Current .................................................. 14 Pin Configuration and Function Descriptions ............................. 7 Power-Up Sequence ................................................................... 14 Typical Performance Characteristics ............................................. 8 Layout and Power Supply Bypassing ....................................... 15 Test Circuits ..................................................................................... 11 Constant Bias to Retain Resistance Setting............................. 15 I2C Interface ..................................................................................... 12 Outline Dimensions ....................................................................... 16 Operation ......................................................................................... 13 Ordering Guide .......................................................................... 16 REVISION HISTORY 5/12—Rev. B to Rev. C Changes to Features and General Description Sections.............. 1 Changes to IDD Parameters, Table 1 ................................................ 3 Changes to IDD Parameters, Table 2 ................................................ 4 Changes to Figure 10 ........................................................................ 9 Removed Evaluation Board Section ............................................. 15 Changes to Ordering Guide .......................................................... 16 8/09—Rev. A to Rev. B Changes to Power Supply Sensitivity Parameter .......................... 3 Updated Outline Dimensions ........................................................16 Changes to Ordering Guide ...........................................................16 7/05—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Absolute Maximum Ratings ....................................... 6 Moved Pin Configuration and Function Descriptions ................ 7 Deleted Table 7 ................................................................................12 Changes to Operation Section .......................................................13 Deleted Figure 31.............................................................................14 Changes to Figure 30 and Figure 32 .............................................14 9/03—Revision 0: Initial Version Rev. C | Page 2 of 16 Data Sheet AD5246 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 kΩ VERSION VDD = 5 V ± 10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance 3 Resistance Temperature Coefficient RWB RESISTOR TERMINALS Voltage Range 4 Capacitance 5 B Capacitance5 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance5 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation 6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7 Bandwidth –3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Density Symbol Conditions Min Typ 1 Max Unit R-DNL R-INL ∆RAB (∆RAB/RAB)/∆T RWB RWB RWB TA = 25°C Wiper = no connect Code = 0x00, VDD = 5 V Code = 0x00, VDD = 2.7 V –1.5 –4 –30 ±0.1 ±0.75 +1.5 +4 +30 LSB LSB % ppm/°C Ω Ω VB, W CB CW ICM VIH VIL VIH VIL IIL CIL VDD RANGE IDD 45 75 150 GND f = 1 MHz, measured to GND, code = 0x40 f = 1 MHz, measured to GND, code = 0x40 VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 150 400 VDD 45 60 1 2.4 0.8 2.1 0.6 ±1 5 2.7 V pF pF nA V V V V µA pF 5.5 V VDD = 5.5 V; VIH = VDD or VIL = GND VDD = 5 V; VIH = VDD or VIL = GND VDD = 3.3 V; VIH = VDD or VIL = GND 3 2.5 0.9 7 5.2 2 µA µA µA PDISS PSSR VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V ± 10%, code = midscale ±0.01 40 ±0.025 µW %/% BW_5K THDW tS eN_WB RAB = 5 kΩ, code = 0x40 VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 5 V, ±1 LSB error band RWB = 2.5 kΩ, RS = 0 Ω 1.2 0.05 1 6 Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 Code = 0x7F. 4 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design; not subject to production test. 6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 7 VDD = 5 V. 1 2 Rev. C | Page 3 of 16 MHz % µs nV/√Hz AD5246 Data Sheet ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS, RHEOSTAT MODE Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance 3 Resistance Temperature Coefficient RWB RESISTOR TERMINALS Voltage Range 4 Capacitance 5 B Capacitance5 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance5 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation 6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7 Bandwidth –3 dB Total Harmonic Distortion VW Settling Time (10 kΩ/50 kΩ/100 kΩ) Resistor Noise Voltage Density Symbol Conditions Min Typ 1 Max Unit R-DNL R-INL ∆RAB (∆RAB/RAB)/∆T RWB RWB, VA = no connect RWB, VA = no connect TA = 25°C Wiper = no connect Code=0x00, VDD = 5 V Code=0x00, VDD = 2.7 V –1 –2 –20 ±0.1 ±0.25 +1 +2 +20 LSB LSB % ppm/°C Ω Ω VB, W CB CW ICM VIH VIL VIH VIL IIL CIL VDD RANGE IDD 45 75 150 GND f = 1 MHz, measured to GND, code = 0x40 f = 1 MHz, measured to GND, code = 0x40 VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 150 400 VDD 45 60 1 2.4 0.8 2.1 0.6 ±1 5 2.7 VDD = 5.5 V; VIH = VDD or VIL = GND VDD = 5 V; VIH = VDD or VIL = GND VDD = 3.3 V; VIH = VDD or VIL = GND 5.5 V 7 5.2 2 µA µA µA 40 ±0.02 µW %/% VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V ± 10%, code = midscale ±0.01 BW THDW tS eN_WB RAB = 10 kΩ/50 kΩ/100 kΩ, code = 0x40 VA = 1 V rms, f = 1 kHz, RAB = 10 kΩ VA = 5 V ±1 LSB error band RWB = 5 kΩ, RS = 0 600/100/40 0.05 2 9 Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 Code = 0x7F. 4 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design; not subject to production test. 6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 7 All dynamic characteristics use VDD = 5 V. 2 Rev. C | Page 4 of 16 V V V V µA pF 3 2.5 0.9 PDISS PSSR 1 V pF pF nA kHz % µs nV/√Hz Data Sheet AD5246 TIMING CHARACTERISTICS VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter I2C INTERFACE TIMING CHARACTERISTICS 2, 3, 4 SCL Clock Frequency tBUF Bus Free Time Between STOP and START tHD;STA Hold Time (Repeated START) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for Repeated START Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for STOP Condition Symbol fSCL t1 t2 Conditions Min Typ 1 Max Unit 400 kHz µs 1.3 After this period, the first clock pulse is generated t3 t4 t5 t6 t7 t8 t9 t10 0.6 1.3 0.6 0.6 50 0.9 100 300 300 0.6 Typical specifications represent average readings at 25°C and VDD = 5 V. Guaranteed by design; not subject to production test. See timing diagrams (Figure 26, Figure 27, and Figure 28) for locations of measured values. 4 Specifications apply to all parts. 1 2 3 Rev. C | Page 5 of 16 µs µs µs µs µs ns ns ns µs AD5246 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND VA, VW to GND Terminal Current, A–B, A–W, B–W Pulsed1 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance2 θJA: SC70-6 Value –0.3 V to +7 V VDD ±20 mA ±5 mA 0 V to VDD + 0.3 V –40°C to +125°C 150°C –65°C to +150°C 300°C 340°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX − TA)/θJA. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 6 of 16 Data Sheet AD5246 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 6 B 5 W 4 SDA GND 2 SCL 3 TOP VIEW (Not to Scale) 03875-018 AD5246 Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic VDD GND SCL SDA W B Description Positive Power Supply. Digital Ground. Serial Clock Input. Positive edge triggered. Serial Data Input/Output. W Terminal. B Terminal. Rev. C | Page 7 of 16 AD5246 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.5 TA = 25°C RAB = 10kΩ RHEOSTAT MODE DNL (LSB) VDD = 2.7V 0.4 0.2 0 VDD = 5.5V –0.2 –0.4 –0.6 03875-020 –0.8 –1.0 0 16 32 48 64 80 CODE (Decimal) 96 112 0.3 0.2 TA = –40°C, +25°C, +85°C, +125°C 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 128 0 Figure 3. R-INL vs. Code vs. Supply Voltages 64 80 48 CODE (Decimal) 96 112 128 0 RHEOSTAT MODEERROR INL (LSB) FSE, FULL-SCALE (LSB) 0.3 0.2 VDD = 2.7V 0.1 0 –0.1 VDD = 5.5V –0.2 03875-021 –0.3 –0.4 –0.5 0 16 32 64 80 48 CODE (Decimal) 96 112 –0.5 VDD = 5.5V, VA = 5.5V –1.0 –1.5 –2.0 VDD = 2.7V, VA = 2.7V –2.5 –3.0 –40 128 03875-024 TA = 25°C RAB = 10kΩ 0.4 RHEOSTAT MODE DNL (LSB) 32 Figure 6. R-DNL vs. Code vs. Temperature 0.5 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 7. Full-Scale Error vs. Temperature Figure 4. R-DNL vs. Code vs. Supply Voltages 1.50 1.0 0.8 TA = –40°C 1.25 ZSE, ZERO-SCALE ERROR (LSB) TA = +85°C 0.6 0.4 0.2 TA = +25°C 0 TA = +125°C –0.2 –0.4 TA = –40°C TA = +25°C –0.6 TA = +85°C –0.8 TA = +125°C –1.0 0 16 32 48 64 80 CODE (Decimal) 96 112 03875-022 RHEOSTAT MODE INL (LSB) 16 1.00 VDD = 5.5V, VA = 5.5V 0.75 0.50 0.25 VDD = 2.7V, VA = 2.7V 0 –40 –25 128 Figure 5. R-INL vs. Code vs. Temperature –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 Figure 8. Zero-Scale Error vs. Temperature Rev. C | Page 8 of 16 03875-025 RHEOSTAT MODE INL (LSB) 0.6 VDD = 2.7V RAB = 10kΩ –40°C +25°C +85°C +125°C 0.4 03875-023 0.8 110 125 Data Sheet AD5246 100 0 DIGITAL INPUTS = 0V CODE = 0x40 0x40 –6 0x20 GAIN (dB) 1 VDD = 2.7V 0x04 –30 0x02 –36 0x01 –42 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 100 5V 2.7V 90 –54 –60 1k 125 10k 100k FREQUENCY (Hz) 1M 10M Figure 12. Gain vs. Frequency vs. Code, RAB = 10 kΩ 0 IWB = 200µA RAB = 10kΩ 0x40 –6 –12 70 –18 60 –24 GAIN (dB) 80 50 40 0x20 0x10 0x08 0x04 –30 0x02 –36 –42 20 –48 10 –54 17 25 33 41 49 57 65 73 81 89 97 105 113 121 –60 1k CODE (Decimal) Figure 10. Rheostat Mode Tempco ∆RWB/∆T vs. Code –12 –18 0x20 –12 0x10 0x10 –18 GAIN (dB) 0x04 0x02 0x01 –42 0x08 –24 0x04 –30 0x02 –36 0x01 –42 –48 –48 03875-028 –54 –60 1k 10k 10M 0x40 –6 0x20 0x08 –36 1M 0 0x40 –24 –30 100k FREQUENCY (Hz) Figure 13. Gain vs. Frequency vs. Code, RAB = 50 kΩ 0 –6 10k 100k 1M 03875-031 9 03875-027 1 03875-030 0x01 30 0 03875-029 –48 Figure 9. Supply Current vs. Temperature RTHESOSTAT MODE TEMPCO (ppm/°C) 0x08 –24 0.1 0.01 –40 –25 –10 GAIN (dB) 0x10 –18 VDD = 5.5V 03875-026 IDD, SUPPLY CURRENT (µA) –12 10 –54 –60 1k 10M FREQUENCY (Hz) Figure 11. Gain vs. Frequency vs. Code, RAB = 5 kΩ 10k 100k FREQUENCY (Hz) 1M Figure 14. Gain vs. Frequency vs. Code, RAB = 100 kΩ Rev. C | Page 9 of 16 10M AD5246 Data Sheet 0 TA = 25°C RAB = 10kW FCLK = 100kHz VDD = 5.5V VB = 0V –6 5kΩ –12 10kΩ –18 GAIN (dB) 100kΩ VW 50kΩ –24 –30 –36 5V –42 CLK 0V 03875-032 03875-006 –48 –54 –60 1k 10k 100k FREQUENCY (Hz) 1M 1µs/DIV 10M Figure 15. –3 dB Bandwidth @ Code = 0x80 Figure 18. Digital Feedthrough 0.30 TA = 25°C RAB = 10kΩ B - VDD = 5.5V CODE = 0x7F 0.20 C - VDD = 2.7V CODE = 0x55 0.15 D - VDD = 2.7V CODE = 0x7F VΩ 0.10 A C D 0 1k 03875-007 B 0.05 03875-033 IDD (µA) 0.25 VDD = 5.5V VB = 0V CODE 0x40 to 0x3F TA = 25°C A - VDD = 5.5V CODE = 0x55 10k 100k FREQUENCY (Hz) 200ns/DIV 1M Figure 19. Midscale Glitch, Code 0x40 to 0x3F Figure 16. IDD vs. Frequency 360 TA = 25°C RAB = 50kW CODE = 0x00 300 VDD = 2.7V 240 180 VW 1 120 VDD = 5.5V 03875-005 60 03875-008 RWB (W) TA = 25°C RAB = 10kW IW = 50µA VDD = 5.5V VB = 0V CODE 00H TO 7FH 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 40µs/DIV 5.5 VBIAS (V) Figure 20. Large Signal Settling Time Figure 17. RWB vs. VBIAS vs. VDD Rev. C | Page 10 of 16 Data Sheet AD5246 TEST CIRCUITS Figure 21 to Figure 25 define the test conditions used in the product Specification tables. DUT RSW = DUT IW 0.1V ISW CODE = 0x00 W B VMS 03875-004 B 0.1V ISW 03875-040 W VDD TO GND Figure 24. Test Circuit for Incremental On Resistance Figure 21. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) DUT ∆V MS PSRR (dB) = 20 LOG ∆V∆∆ ∆V MS% PSS (%/%) = ∆V ∆∆% ( V∆∆ W B VMS W B 03875-009 V+ ) NO CONNECT 10kW +15V 10kW W B 2.5V OP27 VOUT –15V 03875-010 VIN VCM Figure 25. Test Circuit for Common-Mode Leakage Current Figure 22. Test Circuit for Power Supply Sensitivity (PSS, PSSR) DUT ICM 03875-012 V+ = V∆∆ ± 10% ∆UT Figure 23. Test Circuit for Gain vs. Frequency Rev. C | Page 11 of 16 AD5246 Data Sheet I2C INTERFACE Table 6. Write Mode S 0 1 0 1 1 1 0 A W X D6 D5 D4 Slave Address Byte D3 D2 D1 D0 A P D2 D1 D0 A P Data Byte Table 7. Read Mode S 0 1 0 1 1 Slave Address Byte 1 0 R A 0 D6 D5 D4 D3 Data Byte S = Start Condition. W = Write. P = Stop Condition. R = Read. A = Acknowledge. D6, D5, D4, D3, D2, D1, D0 = Data Bits. X = Don’t Care. t2 t9 t8 SCL t6 t3 t2 t7 t4 t5 t10 t9 t8 t1 S P S Figure 26. I2C Interface, Detailed Timing Diagram 1 9 1 9 1 SCL 0 1 1 1 0 D6 D4 D5 ACK BY AD5246 FRAME 1 SLAVE ADDRESS BYTE START BY MASTER X R/W D3 D2 D1 D0 ACK BY AD5246 FRAME 2 DATA BYTE STOP BY MASTER 03875-014 1 0 SDA NO ACK BY MASTER STOP BY MASTER 03875-013 P Figure 27. Writing to the RDAC Register 1 9 1 9 SCL SDA START BY MASTER 0 1 0 1 1 1 FRAME 1 SLAVE ADDRESS BYTE 0 0 R/W D6 ACK BY AD5246 D5 D4 D2 FRAME 2 RDAC REGISTER Figure 28. Reading from the RDAC Register Rev. C | Page 12 of 16 D3 D1 D0 03875-019 SDA Data Sheet AD5246 OPERATION I2C COMPATIBLE 2-WIRE SERIAL BUS The AD5246 is a 128-position, digitally controlled variable resistor (VR) device. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminal A and Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two or three digits of the part number determine the nominal resistance value, that is, 10 kΩ = 10, 50 kΩ = 50. The nominal resistance (RAB) of the VR has 128 contact points accessed by the wiper terminal. The 7-bit data in the RDAC latch is decoded to select one of the 128 possible settings. The first byte of the AD5246 is a slave address byte (see Table 6 and Table 7). It has a 7-bit slave address and an R/W bit. The seven MSBs of the slave address are 0101110 followed by 0 for a write command or 1 to place the device in read mode. The 2-wire I2C serial bus protocol operates as follows: 1. The general equation determining the digitally programmed output resistance between W and B is RWB ( D) = D × RAB + 2 × RW 128 The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master reads from the slave device. Conversely, if the R/W bit is low, the master writes to the slave device. (1) where: D is the decimal equivalent of the binary code loaded in the 7-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on resistance of each internal switch. Ax D6 D5 D4 D3 D2 D1 D0 2. In write mode, after acknowledgement of the slave address byte, the next byte is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Table 6). 3. In read mode, after acknowledgment of the slave address byte, data is received over the serial bus in sequences of nine clock pulses (a slight difference from the write mode where eight data bits are followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 28). 4. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 27). In read mode, the master issues a No Acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, which goes high to establish a STOP condition (see Figure 28). RS RS Wx RDAC Bx 03875-015 LATCH AND RS DECODER The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 27). The following byte is the slave address byte, which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). Figure 29. AD5246 Equivalent RDAC Circuit Note that in the zero-scale condition, there is a relatively small finite wiper resistance. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Typical device-to-device matching is process lot dependent and may vary by up to ±30%. Since the resistance element is processed in thin-film technology, the temperature coefficient of RAB is only 45 ppm/°C. Rev. C | Page 13 of 16 AD5246 Data Sheet A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing the part only once. For example, after the RDAC has acknowledged its slave address in write mode, the RDAC output updates on each successive byte. If different instructions are needed, the write/read mode has to start again with a new slave address and data byte. Similarly, a repeated read function of the RDAC is also allowed. VDD LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE GND While most legacy systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, one can use a 1.8 V E2PROM to interface with a 5 V digital potentiometer. A level shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 30 shows one of the implementations. M1 and M2 can be any N channel signal FETs, or if VDD falls below 2.5 V, M1 and M2 can be low threshold FETs such as the FDV301N. VDD2 = 5V VDD1 = 1.8V RP RP RP RP B 03875-016 W Figure 32. Maximum Terminal Voltages Set by VDD and GND MAXIMUM OPERATING CURRENT At low code values, the user should be aware that due to low resistance values, the current through the RDAC may exceed the 5 mA limit. In Figure 33, a 5 V supply is placed on the wiper, and the current through Terminal W and Terminal B is plotted with respect to code. A line is also drawn denoting the 5 mA current limit. Note that at low code values (particularly for the 5 kΩ and 10 kΩ options), the current level increases significantly. Care should be taken to limit the current flow between W and B in this state to a maximum continuous current of 5 mA and a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contacts can occur. G D SDA2 D SCL2 M2 1.8V 5V AD5246 E2PROM 10 IWB CURRENT (mA) S SCL1 100 G M1 03875-011 S Figure 30. Level Shifting for Operation at Different Potentials ESD PROTECTION 5mA CURRENT LIMIT RAB = 5kW 1 RAB = 10kW RAB = 50kW 0.1 All digital inputs are protected with a series input resistor and parallel Zener ESD structures, as shown in Figure 31. This applies to the digital input pins SDA and SCL. 03875-034 SDA1 RAB = 100kW 0.01 0 16 32 64 80 48 CODE (Decimal) 96 112 128 LOGIC 03875-002 Figure 33. Maximum Operating Current 340Ω POWER-UP SEQUENCE GND Figure 31. ESD Protection of Digital Pins TERMINAL VOLTAGE OPERATING RANGE The AD5246 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on Terminal B and Terminal W that exceed VDD or GND are clamped by the internal forward biased diodes (see Figure 32). Since the ESD protection diodes limit the voltage compliance at Terminal B and Terminal W (see Figure 32), it is important to power VDD/GND before applying any voltage to Terminal B and Terminal W; otherwise, the diode is forward biased such that VDD is powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VB/VW. The relative order of powering VB and VW and the digital inputs is not important, providing they are powered after VDD/GND. Rev. C | Page 14 of 16 Data Sheet AD5246 LAYOUT AND POWER SUPPLY BYPASSING The measurement over time shows that the device draws approximately 1.3 µA and consumes negligible power. Over a course of 30 days, the battery was depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself. Similarly, it is good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 34). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. 110% 108% TA = 25°C 106% BATTERY LIFE DEPLETED It is a good practice to use a compact, minimum lead-length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. 104% 102% 100% 98% 96% 94% 03875-035 VDD VDD 92% C1 C3 + 0.1µF 10µF 90% AD5246 0 5 10 15 DAYS 20 25 30 Figure 35. Battery Operating Life Depletion 03875-017 GND Figure 34. Power Supply Bypassing CONSTANT BIAS TO RETAIN RESISTANCE SETTING For users who desire nonvolatility but cannot justify the additional cost for the EEMEM, the AD5246 may be considered as a low cost alternative by maintaining a constant bias to retain the wiper setting. The AD5246 was designed specifically with low power in mind, which allows low power consumption even in battery-operated systems. The graph in Figure 35 demonstrates the power consumption from a 3.4 V 450 mA/hr Li-ion cell phone battery, which is connected to the AD5246. This demonstrates that constantly biasing the pot is not an impractical approach. Most portable devices do not require the removal of batteries for the purpose of charging. Although the resistance setting of the AD5246 will be lost when the battery needs replacement, such events occur rather infrequently, so that this inconvenience is justified by the lower cost and smaller size offered by the AD5246. If and when total power is lost, the user should be provided with a means to adjust the setting accordingly. Rev. C | Page 15 of 16 AD5246 Data Sheet OUTLINE DIMENSIONS 2.20 2.00 1.80 6 5 4 1 2 3 0.65 BSC 1.30 BSC 1.00 0.90 0.70 0.10 MAX COPLANARITY 0.10 2.40 2.10 1.80 1.10 0.80 0.30 0.15 SEATING PLANE 0.40 0.10 0.22 0.08 0.46 0.36 0.26 COMPLIANT TO JEDEC STANDARDS MO-203-AB 072809-A 1.35 1.25 1.15 Figure 36. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD5246BKSZ5-RL7 AD5246BKSZ10-R2 AD5246BKSZ10-RL7 AD5246BKSZ50-RL7 AD5246BKSZ100-R2 AD5246BKSZ100-RL7 EVAL-AD5246DBZ 1 2 RAB (kΩ) 5 10 10 50 100 100 Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 Evaluation Board Package Option KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 Branding D93 D92 D92 D94 D9D D9D Z = RoHS Compliant Part. The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2003–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03875–0–5/12(C) Rev. C | Page 16 of 16