1 MHz to 10 GHz, 55 dB Log Detector/Controller AD8317 FEATURES APPLICATIONS RF transmitter PA setpoint control and level monitoring Power monitoring in radio link transmitters RSSI measurement in base stations, WLANs, WiMAX, and radars FUNCTIONAL BLOCK DIAGRAM VPOS GAIN BIAS DET DET DET TADJ SLOPE I V VSET I V VOUT DET CLPF INHI INLO COMM 05541-001 Wide bandwidth: 1 MHz to 10 GHz High accuracy: ±1.0 dB over temperature 55 dB dynamic range up to 8 GHz ± 3 dB error Stability over temperature: ±0.5 dB Low noise measurement/controller output, VOUT Pulse response time: 6 ns/10 ns (fall/rise) Small footprint, 2 mm × 3 mm LFCSP Supply operation: 3.0 V to 5.5 V @ 22 mA Fabricated using high speed SiGe process Figure 1. GENERAL DESCRIPTION The AD8317 is a demodulating logarithmic amplifier, capable of accurately converting an RF input signal to a corresponding decibel-scaled output. It employs the progressive compression technique over a cascaded amplifier chain, each stage of which is equipped with a detector cell. The device can be used in either measurement or controller modes. The AD8317 maintains accurate log conformance for signals of 1 MHz to 8 GHz and provides useful operation to 10 GHz. The input dynamic range is typically 55 dB (re: 50 Ω) with less than ±3 dB error. The AD8317 has 6 ns/10 ns response time (fall time/rise time) that enables RF burst detection to a pulse rate of beyond 50 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V is required to power the device. Current consumption is typically 22 mA, and it decreases to 200 μA when the device is disabled. The AD8317 can be configured to provide a control voltage to a power amplifier or a measurement output from the VOUT pin. Because the output can be used for controller applications, special attention has been paid to minimize wideband noise. In this mode, the setpoint control voltage is applied to the VSET pin. The feedback loop through an RF amplifier is closed via VOUT, the output of which regulates the output of the amplifier to a magnitude corresponding to VSET. The AD8317 provides 0 V to (VPOS − 0.1 V) output capability at the VOUT pin, suitable for controller applications. As a measurement device, VOUT is externally connected to VSET to produce an output voltage, VOUT, that is a decreasing linear-in-dB function of the RF input signal amplitude. The logarithmic slope is −22 mV/dB, determined by the VSET interface. The intercept is 15 dBm (re: 50 Ω, CW input) using the INHI input. These parameters are very stable against supply and temperature variations. The AD8317 is fabricated on a SiGe bipolar IC process and is available in a 2 mm × 3 mm, 8-lead LFCSP with an operating temperature range of −40°C to +85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2008 Analog Devices, Inc. All rights reserved. AD8317 TABLE OF CONTENTS Features .............................................................................................. 1 Input Signal Coupling ................................................................ 11 Applications ....................................................................................... 1 Output Interface ......................................................................... 11 Functional Block Diagram .............................................................. 1 Setpoint Interface ....................................................................... 11 General Description ......................................................................... 1 Temperature Compensation of Output Voltage ..................... 12 Revision History ............................................................................... 2 Measurement Mode ................................................................... 12 Specifications..................................................................................... 3 Setting the Output Slope in Measurement Mode .................. 13 Absolute Maximum Ratings............................................................ 5 Controller Mode ......................................................................... 13 ESD Caution .................................................................................. 5 Output Filtering .......................................................................... 15 Pin Configuration and Function Descriptions ............................. 6 Operation Beyond 8 GHz ......................................................... 15 Typical Performance Characteristics ............................................. 7 Evaluation Board ............................................................................ 16 Theory of Operation ...................................................................... 10 Die Information .............................................................................. 18 Using the AD8317 .......................................................................... 11 Outline Dimensions ....................................................................... 19 Basic Connections ...................................................................... 11 Ordering Guide .......................................................................... 19 REVISION HISTORY 3/08—Rev. A to Rev. B Changes to Features.......................................................................... 1 Changes to General Description .................................................... 1 Changes to Measurement Mode Section ..................................... 12 Changes to Equation 12 ................................................................. 15 8/07—Rev. 0 to Rev. A Changes to f = 8.0 GHz, ±1 dB Dynamic Range Parameter ....... 4 Changes to Table 2 ............................................................................ 6 Changes to Figure 20 ...................................................................... 10 Changes to Setpoint Interface Section and Figure 22 ................ 12 Changes Figure 27 .......................................................................... 13 Changes to Table 5 .......................................................................... 17 Added Die Information Section ................................................... 19 Changes to Ordering Guide .......................................................... 21 10/05—Revision 0: Initial Version Rev. B | Page 2 of 20 AD8317 SPECIFICATIONS VPOS = 3 V, CLPF = 1000 pF, TA = 25°C, 52.3 Ω termination resistor at INHI, unless otherwise noted. Table 1. Parameter SIGNAL INPUT INTERFACE Specified Frequency Range DC Common-Mode Voltage MEASUREMENT MODE f = 900 MHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope 1 Intercept1 Output Voltage, High Power In Output Voltage, Low Power In f = 1.9 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage, High Power In Output Voltage, Low Power In f = 2.2 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage, High Power In Output Voltage, Low Power In f = 3.6 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage, High Power In Output Voltage, Low Power In Conditions INHI (Pin 1) Min Typ Max Unit 10 VPOS − 0.6 GHz V −25 12 0.42 1.00 1500||0.33 50 46 −3 −53 −22 15 0.58 1.27 −19.5 21 0.78 1.40 Ω||pF dB dB dBm dBm mV/dB dBm V V −25 10 0.35 0.75 950||0.38 50 48 −4.00 −54 −22 14 0.54 1.21 −19.5 20 0.80 1.35 Ω||pF dB dB dBm dBm mV/dB dBm V V 0.001 VOUT (Pin 5) shorted to VSET (Pin 4), sinusoidal input signal RTADJ = 18 kΩ TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −40 dBm RTADJ = 8 kΩ TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −35 dBm RTADJ = 8 kΩ TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −40 dBm RTADJ = 8 kΩ TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −40 dBm Rev. B | Page 3 of 20 810||0.39 50 47 −5 −55 −22 14 0.53 1.20 Ω||pF dB dB dBm dBm mV/dB dBm V V 300||0.33 42 40 −6 −48 −22 11 0.47 1.16 Ω||pF dB dB dBm dBm mV/dB dBm V V AD8317 Parameter f = 5.8 GHz Input Impedance ±1 dB Dynamic Range Conditions RTADJ = 500 Ω Min Typ Max Unit 110||0.05 50 48 −4 −54 −22 16 0.59 1.27 Ω||pF dB dB dBm dBm mV/dB dBm V V 28||0.79 44 35 −2 −46 −22 21 0.70 1.39 Ω||pF dB dB dBm dBm mV/dB dBm V V VPOS − 0.1 10 10 140 90 V mV mA MHz nV/√Hz 18 ns 6 ns 20 ns 10 ns 50 MHz RFIN = −20 dBm, controller mode, VSET = 1 V 0.35 1.40 −45 40 V V dB/V kΩ TADJ INTERFACE Input Resistance Disable Threshold Voltage TADJ (Pin 6) TADJ = 0.9 V, sourcing 50 μA TADJ = open 13 VPOS − 0.4 kΩ V POWER INTERFACE Supply Voltage Quiescent Current vs. Temperature Disable Current VPOS (Pin 7) Maximum Input Level Minimum Input Level Slope1 Intercept1 Output Voltage, High Power In Output Voltage, Low Power In f = 8.0 GHz Input Impedance ±1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope 2 Intercept2 Output Voltage, High Power In Output Voltage, Low Power In OUTPUT INTERFACE Voltage Swing Output Current Drive Small Signal Bandwidth Output Noise Fall Time Rise Time Video Bandwidth (or Envelope Bandwidth) VSET INTERFACE Nominal Input Range Logarithmic Scale Factor Input Resistance 1 2 TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −40 dBm RTADJ = open TA = 25°C −40°C < TA < +85°C ±1 dB error ±1 dB error PIN = −10 dBm PIN = −40 dBm VOUT (Pin 5) VSET = 0 V, RFIN = open VSET = 1.7 V, RFIN = open VSET = 0 V, RFIN = open RFIN = −10 dBm, from CLPF to VOUT RFIN = 2.2 GHz, −10 dBm, fNOISE = 100 kHz, CLPF = open Input level = no signal to −10 dBm, 90% to 10%, CLPF = 8 pF Input level = no signal to −10 dBm, 90% to 10%, CLPF = open, ROUT = 150 Ω Input level = −10 dBm to no signal, 10% to 90%, CLPF = 8 pF Input level = −10 dBm to no signal, 10% to 90%, CLPF = open, ROUT = 150 Ω VSET (Pin 4) RFIN = 0 dBm, measurement mode RFIN = −50 dBm, measurement mode 3.0 18 −40°C ≤ TA ≤ +85°C TADJ = VPOS 22 60 200 5.5 30 Slope and intercept are determined by calculating the best-fit line between the power levels of −40 dBm and −10 dBm at the specified input frequency. Slope and intercept are determined by calculating the best-fit line between the power levels of −34 dBm and −16 dBm at 8.0 GHz. Rev. B | Page 4 of 20 V mA μA/°C μA AD8317 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage, VPOS VSET Voltage Input Power (Single-Ended, Re: 50 Ω) Internal Power Dissipation θJA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.7 V 0 V to VPOS 12 dBm 0.73 W 55°C/W 125°C −40°C to +85°C −65°C to +150°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 5 of 20 AD8317 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8317 7 VPOS CLPF 3 TOP VIEW (Not to Scale) 6 TADJ VSET 4 5 VOUT 05541-002 8 INLO INHI 1 COMM 2 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 Mnemonic INHI COMM CLPF 4 5 VSET VOUT 6 TADJ 7 8 VPOS INLO Paddle Description RF Input. Nominal input range of −50 dBm to 0 dBm, re: 50 Ω; ac-coupled RF input. Device Common. Connect to a low impedance ground plane. Loop Filter Capacitor. In measurement mode, this capacitor sets the pulse response time and video bandwidth. In controller mode, the capacitance on this node sets the response time of the error amplifier/integrator. Setpoint Control Input for Controller Mode or Feedback Input for Measurement Mode. Measurement and Controller Output. In measurement mode, VOUT provides a decreasing linear-in-dB representation of the RF input signal amplitude. In controller mode, VOUT is used to control the gain of a VGA or VVA with a positive gain sense (increasing voltage increases gain). Temperature Compensation Adjustment. Frequency-dependent temperature compensation is set by connecting a ground-referenced resistor to this pin. Positive Supply Voltage: 3.0 V to 5.5 V. RF Common for INHI. AC-coupled RF common. Internally connected to COMM; solder to a low impedance ground plane. Rev. B | Page 6 of 20 AD8317 TYPICAL PERFORMANCE CHARACTERISTICS 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 PIN (dBm) –2.0 Figure 6. VOUT and Log Conformance vs. Input Amplitude at 3.6 GHz, RTADJ = 8 kΩ 2.00 2.0 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 –2.0 PIN (dBm) VOUT (V) 2.0 ERROR (dB) 2.00 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 05541-004 VOUT (V) 5 PIN (dBm) Figure 3. VOUT and Log Conformance vs. Input Amplitude at 900 MHz, RTADJ = 18 kΩ 0 5 –2.0 PIN (dBm) Figure 4. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz, RTADJ = 8 kΩ Figure 7. VOUT and Log Conformance vs. Input Amplitude at 5.8 GHz, RTADJ = 500 Ω 2.00 2.0 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 –2.0 0 5 VOUT (V) 2.0 ERROR (dB) 2.00 05541-005 VOUT (V) 0 ERROR (dB) –2.0 05541-007 5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 –2.0 PIN (dBm) PIN (dBm) Figure 5. VOUT and Log Conformance vs. Input Amplitude at 2.2 GHz, RTADJ = 8 kΩ Figure 8. VOUT and Log Conformance vs. Input Amplitude at 8.0 GHz, RTADJ = Open, Error Calculated from PIN = −34 dBm to PIN = −16 dBm Rev. B | Page 7 of 20 ERROR (dB) 0 05541-008 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 ERROR (dB) 2.0 05541-006 2.00 VOUT (V) 2.0 ERROR (dB) 2.00 05541-003 VOUT (V) VPOS = 3 V; TA = +25°C, −40°C, +85°C; CLPF = 1000 pF, unless otherwise noted. Black: +25°C; Blue: −40°C; Red: +85°C. Error is calculated by using the best-fit line between PIN = −40 dBm and PIN = −10 dBm at the specified input frequency, unless otherwise noted 2.0 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 PIN (dBm) 10 –2.0 Figure 12. VOUT and Log Conformance vs. Input Amplitude at 3.6 GHz, Multiple Devices, RTADJ = 8 kΩ 2.00 2.0 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 –2.0 0 5 VOUT (V) 2.0 ERROR (dB) 2.00 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 05541-010 VOUT (V) 5 PIN (dBm) Figure 9. VOUT and Log Conformance vs. Input Amplitude at 900 MHz, Multiple Devices, RTADJ = 18 kΩ 10 PIN (dBm) –2.0 0 5 10 PIN (dBm) Figure 10. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz, Multiple Devices, RTADJ = 8 kΩ Figure 13. VOUT and Log Conformance vs. Input Amplitude at 5.8 GHz, Multiple Devices, RTADJ = 500 Ω 2.00 2.0 1.75 1.5 1.75 1.5 1.50 1.0 1.50 1.0 1.25 0.5 1.25 0.5 1.00 0 1.00 0 0.75 –0.5 0.75 –0.5 0.50 –1.0 0.50 –1.0 0.25 –1.5 0.25 –1.5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 –2.0 PIN (dBm) Figure 11. VOUT and Log Conformance vs. Input Amplitude at 2.2 GHz, Multiple Devices, RTADJ = 8 kΩ VOUT (V) 2.0 ERROR (dB) 2.00 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 05541-011 VOUT (V) 0 05541-012 –2.0 ERROR (dB) 10 05541-013 5 0 5 ERROR (dB) 0 –2.0 10 PIN (dBm) Figure 14. VOUT and Log Conformance vs. Input Amplitude at 8.0 GHz, Multiple Devices, RTADJ = Open, Error Calculated from PIN = −34 dBm to PIN = −16 dBm Rev. B | Page 8 of 20 05541-014 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 ERROR (dB) 2.00 VOUT (V) 2.0 ERROR (dB) 2.00 05541-009 VOUT (V) AD8317 AD8317 j1 10000 j0.2 1 2 100MHz –j0.2 900MHz 1900MHz 8000MHz –j2 –j0.5 –20dBm –10dBm 100 0dBm 2200MHz 10 1k 3600MHz 5800MHz Figure 15. Input Impedance vs. Frequency; No Termination Resistor on INHI (Impedance De-Embedded to Input Pins), Z0 = 50 Ω 10000 NOISE SPECTRAL DENSITY (nV/ Hz) 05541-017 3 Ch3 500mV Ch4 200mV M4.00µs A Ch3 T 12.7560µs 1000 100 10 1k 620mV 10k 100k 10M 1M FREQUENCY (Hz) Figure 19. Noise Spectral Density of Output Buffer (from CLPF to VOUT); CLPF = 0.1 μF Figure 16. Power-On/Power-Off Response Time; VPOS = 3.0 V; Input AC-Coupling Capacitors = 10 pF; CLPF = Open VOUT (V) CH1 RISE 10.44ns 05541-016 CH1 FALL 6.113ns M20.0ns A CH1 T 943.600ns 10M 1M Figure 18. Noise Spectral Density of Output; CLPF = Open Δ : 1.86V @ : 1.69V CH1 200mV 100k FREQUENCY (Hz) 05541-015 10000MHz 4 10k –j1 START FREQUENCY = 0.05GHz STOP FREQUENCY = 10GHz RF OFF 2.00 2.0 1.75 1.5 1.50 1.0 1.25 0.5 1.00 0 0.75 –0.5 0.50 –1.0 0.25 1.40V 0 –65 Figure 17. VOUT Pulse Response Time; Pulsed RF Input 0.1 GHz, −10 dBm; CLPF = Open; RLOAD = 150 Ω Rev. B | Page 9 of 20 3.3V 3.0V 3.6V –55 ERROR (dB) 0.5 –40dBm –1.5 –45 –35 –25 –15 PIN (dBm) –5 5 15 –2.0 Figure 20. Output Voltage Stability vs. Supply Voltage at 1.9 GHz When VPOS Varies by 10% 05541-020 0.2 1000 05541-019 0 –60dBm 05541-018 NOISE SPECTRAL DENSITY (nV/ Hz) j2 j0.5 AD8317 THEORY OF OPERATION The AD8317 is a 6-stage demodulating logarithmic amplifier, specifically designed for use in RF measurement and power control applications at frequencies up to 10 GHz. A block diagram is shown in Figure 21. Sharing much of its design with the AD8318 logarithmic detector/controller, the AD8317 maintains tight intercept variability vs. temperature over a 50 dB range. Additional enhancements over the AD8318, such as a reduced RF burst response time of 6 ns to 10 ns, 22 mA supply current, and board space requirements of only 2 mm × 3 mm, add to the low cost and high performance benefits of the AD8317. VPOS GAIN BIAS DET DET DET TADJ SLOPE V I VSET I V VOUT DET CLPF INHI COMM 05541-021 INLO Figure 21. Block Diagram A fully differential design, using a proprietary, high speed SiGe process, extends high frequency performance. Input INHI receives the signal with a low frequency impedance of nominally 500 Ω in parallel with 0.7 pF. The maximum input with ±1 dB logconformance error is typically 0 dBm (re: 50 Ω). The noise spectral density referred to the input is 1.15 nV/√Hz, which is equivalent to a voltage of 118 μV rms in a 10.5 GHz bandwidth or a noise power of −66 dBm (re: 50 Ω). This noise spectral density sets the lower limit of the dynamic range. However, the low end accuracy of the AD8317 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. The common pin, COMM, provides a quality low impedance connection to the printed circuit board (PCB) ground. The package paddle, which is internally connected to the COMM pin, should also be grounded to the PCB to reduce thermal impedance from the die to the PCB. The logarithmic function is approximated in a piecewise fashion by six cascaded gain stages. (For a more comprehensive explanation of the logarithm approximation, see the AD8307 data sheet.) The cells have a nominal voltage gain of 9 dB each and a 3 dB bandwidth of 10.5 GHz. Using precision biasing, the gain is stabilized over temperature and supply variations. The overall dc gain is high, due to the cascaded nature of the gain stages. An offset compensation loop is included to correct for offsets within the cascaded cells. At the output of each of the gain stages, a square-law detector cell is used to rectify the signal. The RF signal voltages are converted to a fluctuating differential current having an average value that increases with signal level. Along with the six gain stages and detector cells, an additional detector is included at the input of the AD8317, providing a 50 dB dynamic range in total. After the detector currents are summed and filtered, the following function is formed at the summing node: ID × log10(VIN/VINTERCEPT) (1) where: ID is the internally set detector current. VIN is the input signal voltage. VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT, the output voltage would be 0 V, if it were capable of going to 0 V). Rev. B | Page 10 of 20 AD8317 USING THE AD8317 BASIC CONNECTIONS The AD8317 is specified for operation up to 10 GHz; as a result, low impedance supply pins with adequate isolation between functions are essential. A power supply voltage of between 3.0 V and 5.5 V should be applied to VPOS. Power supply decoupling capacitors of 100 pF and 0.1 μF should be connected close to this power supply pin. VS (3.0V TO 5.5V) C5 R2 0Ω C4 100pF C2 VOUT 8 INLO 7 VPOS R1 52.3Ω 6 TADJ R4 0Ω AD8317 INHI 1 C1 SIGNAL INPUT COMM 2 CLPF 3 47nF OUTPUT INTERFACE 5 VOUT VSET 4 2 1SEE THE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE SECTION. 2SEE THE OUTPUT FILTERING SECTION. 05541-022 47nF 1 The coupling time constant, 50 × CC/2, forms a high-pass corner with a 3 dB attenuation at fHP = 1/(2π × 50 × CC ), where C1 = C2 = CC. Using the typical value of 47 nF, this high-pass corner is ~68 kHz. In high frequency applications, fHP should be as large as possible to minimize the coupling of unwanted low frequency signals. In low frequency applications, a simple RC network forming a low-pass filter should be added at the input for similar reasons. This low-pass filter network should generally be placed at the generator side of the coupling capacitors, thereby lowering the required capacitance value for a given high-pass corner frequency. Figure 22. Basic Connections The VOUT pin is driven by a PNP output stage. An internal 10 Ω resistor is placed in series with the output and the VOUT pin. The rise time of the output is limited mainly by the slew on CLPF. The fall time is an RC-limited slew given by the load capacitance and the pull-down resistance at VOUT. There is an internal pull-down resistor of 1.6 kΩ. A resistive load at VOUT is placed in parallel with the internal pull-down resistor to provide additional discharge current. The paddle of the LFCSP package is internally connected to COMM. For optimum thermal and electrical performance, the paddle should be soldered to a low impedance ground plane. VPOS CLPF 10Ω + 0.8V – INPUT SIGNAL COUPLING The RF input (INHI) is single-ended and must be ac-coupled. INLO (input common) should be ac-coupled to ground. Suggested coupling capacitors are 47 nF ceramic 0402-style capacitors for input frequencies of 1 MHz to 10 GHz. The coupling capacitors should be mounted close to the INHI and INLO pins. The coupling capacitor values can be increased to lower the high-pass cutoff frequency of the input stage. The high-pass corner is set by the input coupling capacitors and the internal 10 pF high-pass capacitor. The dc voltage on INHI and INLO is approximately one diode voltage drop below VPOS. VPOS 5pF 18.7kΩ CURRENT 5pF 400Ω COMM Figure 24. Output Interface To reduce the fall time, VOUT should be loaded with a resistive load of <1.6 kΩ. For example, with an external load of 150 Ω, the AD8317 fall time is <7 ns. SETPOINT INTERFACE The VSET input drives the high impedance (40 kΩ) input of an internal op amp. The VSET voltage appears across the internal 1.5 kΩ resistor to generate ISET. When a portion of VOUT is applied to VSET, the feedback loop forces (2) If VSET = VOUT/2x, then ISET = VOUT/(2x × 1.5 kΩ). INHI 2kΩ 1200Ω −ID × log10(VIN/VINTERCEPT) = ISET FIRST GAIN STAGE 18.7kΩ VOUT 05541-024 0.1µF Figure 22) combines with the relatively high input impedance to give an adequate broadband 50 Ω match. The result is A = 9dB VOUT = (−ID × 1.5 kΩ × 2x) × log10(VIN/VINTERCEPT) gm STAGE OFFSET COMP 05541-023 INLO VSET 20kΩ ISET VSET Figure 23. Input Interface 20kΩ 1.5kΩ COMM COMM Figure 25. VSET Interface Rev. B | Page 11 of 20 05541-025 While the input can be reactively matched, in general, this is not necessary. An external 52.3 Ω shunt resistor (connected on the signal side of the input coupling capacitors, as shown in AD8317 2.00 −ID × 2x × 1.5 kΩ = −22 mV/dB × x For example, if a resistor divider to ground is used to generate a VSET voltage of VOUT/2, x = 2. The slope is set to −880 V/decade or −44 mV/dB. TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE The primary component of the variation in VOUT vs. temperature, as the input signal amplitude is held constant, is the drift of the intercept. This drift is also a weak function of the input signal frequency; therefore, provision is made for the optimization of internal temperature compensation at a given frequency by providing Pin TADJ. 1.50 1.0 1.25 0.5 1.00 0 0.75 –0.5 TADJ 0.25 05541-026 COMM Figure 26. TADJ Interface RTADJ is connected between TADJ and ground. The value of this resistor partially determines the magnitude of an analog correction coefficient, which is used to reduce intercept drift. –1.5 0 5 PIN (dBm) 10 15 INTERCEPT VOUT = X × VSLOPE/DEC × log10(VIN/VINTERCEPT) (3) = X × VSLOPE/dB × 20 × log10(VIN/VINTERCEPT) (4) where: X is the feedback factor in VSET = VOUT/X. VSLOPE/DEC is nominally −440 mV/decade, or −22 mV/dB. VINTERCEPT is the x-axis intercept of the linear-in-dB portion of the VOUT vs. PIN curve (see Figure 27). VINTERCEPT is 2 dBV for a sinusoidal input signal. An offset voltage, VOFFSET, of 0.35 V is internally added to the detector signal, so that the minimum value for VOUT is X × VOFFSET; therefore, for X = 1, the minimum VOUT is 0.35 V. The relationship between output temperature drift and frequency is not linear and cannot be easily modeled. As a result, experimentation is required to choose the correct TADJ resistor. Table 4 shows the recommended values for some commonly used frequencies. The slope is very stable vs. process and temperature variation. When base-10 logarithms are used, VSLOPE/DECADE represents the volts/decade. A decade corresponds to 20 dB; VSLOPE/DECADE/20 = VSLOPE/dB represents the slope in volts/dB. Table 4. Recommended RTADJ Values Frequency 50 MHz 100 MHz 900 MHz 1.8 GHz 1.9 GHz 2.2 GHz 3.6 GHz 5.3 GHZ 5.8 GHz 8 GHz RANGE FOR CALCULATION OF SLOPE AND INTERCEPT 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 RTADJ COMM –1.0 0.50 The output voltage vs. input signal voltage of the AD8317 is linear-in-dB over a multidecade range. The equation for this function is ICOMP 1.5kΩ 1.5 Figure 27. Typical Output Voltage vs. Input Signal AD8317 VINTERNAL VOUT (V) 1.75 2.0 VOUT IDEAL VOUT 25°C ERROR 25°C 05541-027 The slope is given by Recommended RTADJ 18 kΩ 18 kΩ 18 kΩ 8 kΩ 8 kΩ 8 kΩ 8 kΩ 500 Ω 500 Ω Open As noted in Equation 3 and Equation 4, the VOUT voltage has a negative slope. This is also the correct slope polarity to control the gain of many power amplifiers in a negative feedback configuration. Because both the slope and intercept vary slightly with frequency, it is recommended to refer to the Specifications section for application-specific values for slope and intercept. Although demodulating log amps respond to input signal voltage, not input signal power, it is customary to discuss the amplitude of high frequency signals in terms of power. In this case, the characteristic impedance of the system, Z0, must be known to convert voltages to their corresponding power levels. The following equations are used to perform this conversion: MEASUREMENT MODE When the VOUT voltage or a portion of the VOUT voltage is fed back to the VSET pin, the device operates in measurement mode. As seen in Figure 27, the AD8317 has an offset voltage, a negative slope, and a VOUT measurement intercept at the high end of its input signal range. Rev. B | Page 12 of 20 P [dBm] = 10 × log10(VRMS2/(Z0 × 1 mW)) (5) P [dBV] = 20 × log10(VRMS/1 VRMS) (6) 2 P [dBm] = P [dBV] − 10 × log10(Z0 × 1 mW/1 VRMS ) (7) AD8317 PINTERCEPT [dBm] = PINTERCEPT [dBV] − 10 × log10(Z0 × 1 mW/1 VRMS2) = 2 dBV − 10 × log10(50 × 10−3) = 15 dBm (8) For a square wave input signal in a 200 Ω system, PINTERCEPT = −1 dBV − 10 × log10[(200 Ω × 1 mW/1 VRMS2)] = 6 dBm Further information on the intercept variation dependence upon waveform can be found in the AD8313 and AD8307 data sheets. SETTING THE OUTPUT SLOPE IN MEASUREMENT MODE between VOUT and the RF input signal when the device is in measurement mode, the AD8317 adjusts the voltage on VOUT (VOUT is now an error amplifier output) until the level at the RF input corresponds to the applied VSET. When the AD8317 operates in controller mode, there is no defined relationship between the VSET and the VOUT voltage; VOUT settles to a value that results in the correct input signal level appearing at INHI/INLO. For this output power control loop to be stable, a groundreferenced capacitor must be connected to the CLPF pin. This capacitor, CFLT, integrates the error signal (in the form of a current) to set the loop bandwidth and ensure loop stability. Further details on control loop dynamics can be found in the AD8315 data sheet. To operate in measurement mode, VOUT must be connected to VSET. Connecting VOUT directly to VSET yields the nominal logarithmic slope of approximately −22 mV/dB. The output swing corresponding to the specified input range is then approximately 0.35 V to 1.7 V. The slope and output swing can be increased by placing a resistor divider between VOUT and VSET (that is, one resistor from VOUT to VSET and one resistor from VSET to ground). The input impedance of VSET is approximately 40 kΩ. Slope-setting resistors should be kept below 20 kΩ to prevent this input impedance from affecting the resulting slope. If two equal resistors are used (for example, 10 kΩ/10 kΩ), the slope doubles to approximately −44 mV/dB. VGA/VVA DIRECTIONAL COUPLER RFIN GAIN CONTROL VOLTAGE ATTENUATOR VOUT 47nF INHI AD8317 52.3Ω INLO 47nF VSET DAC CLPF CFLT 05541-029 For example, PINTERCEPT for a sinusoidal input signal expressed in terms of dBm (decibels referred to 1 mW), in a 50 Ω system is Figure 29. Controller Mode AD8317 VOUT Decreasing VSET, which corresponds to demanding a higher signal from the VGA, increases VOUT. The gain control voltage of the VGA must have a positive sense. A positive control voltage to the VGA increases the gain of the device. –44mV/dB 10kΩ 10kΩ 05541-028 VSET Figure 28. Increasing the Slope CONTROLLER MODE The AD8317 provides a controller mode feature at the VOUT pin. By using VSET for the setpoint voltage, it is possible for the AD8317 to control subsystems, such as power amplifiers (PAs), variable gain amplifiers (VGAs), or variable voltage attenuators (VVAs), that have output power that increases monotonically with respect to their gain control signal. To operate in controller mode, the link between VSET and VOUT is broken. A setpoint voltage is applied to the VSET input, VOUT is connected to the gain control terminal of the VGA, and the RF input of the detector is connected to the output of the VGA (usually using a directional coupler and some additional attenuation). Based on the defined relationship The basic connections for operating the AD8317 in an automatic gain control (AGC) loop with the ADL5330 are shown in Figure 30. The ADL5330 is a 10 MHz to 3 GHz VGA. It offers a large gain control range of 60 dB with ±0.5 dB gain stability. This configuration is similar to Figure 29. The gain of the ADL5330 is controlled by the output pin of the AD8317. This voltage, VOUT, has a range of 0 V to near VPOS. To avoid overdrive recovery issues, the AD8317 output voltage can be scaled down using a resistive divider to interface with the 0 V to 1.4 V gain control range of the ADL5330. A coupler/attenuation of 21 dB is used to match the desired maximum output power from the VGA to the top end of the linear operating range of the AD8317 (approximately −5 dBm at 900 MHz). Rev. B | Page 13 of 20 AD8317 +5V +5V RF INPUT SIGNAL RF OUTPUT SIGNAL 120nH VPSx 100pF 120nH COMx 100pF OPHI INHI ADL5330 100pF DIRECTIONAL COUPLER OPLO INLO 100pF GAIN 4.12kΩ +5V ATTENUATOR 10kΩ SETPOINT VOLTAGE DAC VOUT VSET VPOS INHI 47nF AD8317 52.3Ω LOG AMP CLPF TADJ 1nF INLO COMM 47nF 05541-030 18kΩ Figure 30. AD8317 Operating in Controller Mode to Provide Automatic Gain Control Functionality in Combination with the ADL5330 Figure 31 shows the transfer function of the output power vs. the setpoint voltage over temperature for a 900 MHz sine wave with an input power of −1.5 dBm. Note that the power control of the AD8317 has a negative sense. Decreasing VSET, which corresponds to demanding a higher signal from the ADL5330, increases gain. 20 3 10 2 0 1 –10 0 –20 –1 –30 –2 –40 –3 –50 0.2 0.4 0.6 0.8 1.0 1.2 1.4 SETPOINT VOLTAGE (V) 1.6 1.8 –4 2.0 1 AD8317 OUTPUT 3 2 05541-032 4 AM MODULATED INPUT ERROR (dB) 30 ADL5330 OUTPUT CH1 200mV Ch2 200mV CH3 50.0mVΩ 05541-031 OUTPUT POWER (dBm) The AGC loop is capable of controlling signals just under the full 60 dB gain control range of the ADL5330. The performance over temperature is most accurate over the highest power range, where it is generally most critical. Across the top 40 dB range of output power, the linear conformance error is well within ±0.5 dB over temperature. For the AGC loop to remain in equilibrium, the AD8317 must track the envelope of the ADL5330 output signal and provide the necessary voltage levels to the ADL5330 gain control input. Figure 32 shows an oscilloscope screenshot of the AGC loop depicted in Figure 30. A 100 MHz sine wave with 50% AM modulation is applied to the ADL5330. The output signal from the VGA is a constant envelope sine wave with amplitude corresponding to a setpoint voltage at the AD8317 of 1.5 V. Also shown is the gain control response of the AD8317 to the changing input envelope. A CH2 M2.00ms T 640.00µs 820mV Figure 32. Oscilloscope Screenshot Showing an AM Modulated Input Signal and the Response from the AD8317 Figure 31. ADL5330 Output Power vs. AD8317 Setpoint Voltage, PIN = −1.5 dBm Rev. B | Page 14 of 20 AD8317 AD8317 ILOG VOUT +4 1.5kΩ 3.5pF CLPF CFLT T AD8317 VSET PULSE 05541-037 Figure 33 shows the response of the AGC RF output to a pulse on VSET. As VSET decreases from 1.7 V to 0.4 V, the AGC loop responds with an RF burst. In this configuration, the input signal to the ADL5330 is a 1 GHz sine wave at a power level of −15 dBm. Figure 34. Lowering the Postdemodulation Bandwidth 1 CFLT is selected by C FLT = ADL5330 OUTPUT 2 2.48V Figure 33. Oscilloscope Screenshot Showing the Response Time of the AGC Loop Response time and the amount of signal integration are controlled by CFLT. This functionality is analogous to the feedback capacitor around an integrating amplifier. Although it is possible to use large capacitors for CFLT, in most applications, values under 1 nF provide sufficient filtering. Calibration in controller mode is similar to the method used in measurement mode. A simple 2-point calibration can be done by applying two known VSET voltages or DAC codes and measuring the output power from the VGA. Slope and intercept can then be calculated by: Slope = (VSET1 − VSET2)/(POUT1 − POUT2) (9) In many log amp applications, it may be necessary to lower the corner frequency of the postdemodulation filter to achieve low output ripple while maintaining a rapid response time to changes in signal level. An example of a 4-pole active filter is shown in the AD8307 data sheet. OPERATION BEYOND 8 GHz The AD8317 is specified for operation up to 8 GHz, but it provides useful measurement accuracy over a reduced dynamic range of up to 10 GHz. Figure 35 shows the performance of the AD8317 over temperature at 10 GHz when the device is configured as shown in Figure 22. Dynamic range is reduced at this frequency, but the AD8317 does provide 30 dB of measurement range within ±3 dB of linearity error. 5 (10) 1.8 4 VSETx = Slope × (POUTX − Intercept) (11) 1.6 3 1.4 2 1.2 1 1.0 0 For applications in which maximum video bandwidth and, consequently, fast rise time are desired, it is essential that the CLPF pin be left unconnected and free of any stray capacitance. 0.8 –1 0.6 –2 0.4 –3 The nominal output video bandwidth of 50 MHz can be reduced by connecting a ground-referenced capacitor (CFLT) to the CLPF pin, as shown in Figure 34. This is generally done to reduce output ripple (at twice the input frequency for a symmetric input waveform such as sinusoidal signals). 0.2 –4 More information on the use of the ADL5330 in AGC applications can be found in the ADL5330 data sheet. OUTPUT FILTERING VOUT (V) 2.0 Intercept = POUT1 − VSET1/Slope 0 –40 ERROR (dB) M10.0µs A CH1 T 699.800µs –5 –35 –30 –25 –20 –15 PIN (dBm) –10 –5 0 5 05541-038 CH2 50mVΩ (12) The video bandwidth should typically be set to a frequency equal to about one-tenth the minimum input frequency. This ensures that the output ripple of the demodulated log output, which is at twice the input frequency, is well filtered. 05541-033 CH1 2.00V 1 − 3.5 pF (2π × 1.5 kΩ × Video Bandwidth) Figure 35. VOUT and Log Conformance vs. Input Amplitude at 10.0 GHz, Multiple Devices, RTADJ = Open, CLPF = 1000 pF Implementing an impedance match for frequencies beyond 8 GHz can improve the sensitivity of the AD8317 and measurement range. Operation beyond 10 GHz is possible, but part-to-part variation, most notably in the intercept, becomes significant. Rev. B | Page 15 of 20 AD8317 EVALUATION BOARD Table 5. Evaluation Board (Rev. A) Configuration Options R5, R7 R2, R3, R4, R6, RL, CL R2, R3 C4, C5 C3 Function Supply and Ground Connections. Input Interface. The 52.3 Ω resistor in Position R1 combines with the internal input impedance of the AD8317 to give a broadband input impedance of about 50 Ω. C1 and C2 are dc-blocking capacitors. A reactive impedance match can be implemented by replacing R1 with an inductor and C1 and C2 with appropriately valued capacitors. Temperature Compensation Interface. The internal temperature compensation network is optimized for input signals up to 3.6 GHz when R7 is 10 kΩ. This circuit can be adjusted to optimize performance for other input frequencies by changing the value of the resistor in Position R7. See Table 4 for specific RTADJ resistor values. Output Interface—Measurement Mode. In measurement mode, a portion of the output voltage is fed back to the VSET pin via R2. The magnitude of the slope of the VOUT output voltage response can be increased by reducing the portion of VOUT that is fed back to VSET. R6 can be used as a back-terminating resistor or as part of a single-pole, low-pass filter. Output Interface—Controller Mode. In this mode, R2 must be open. In controller mode, the AD8317 can control the gain of an external component. A setpoint voltage is applied to Pin VSET, the value of which corresponds to the desired RF input signal level applied to the AD8317 RF input. A sample of the RF output signal from this variable gain component is selected, typically via a directional coupler, and applied to the AD8317 RF input. The voltage at the VOUT pin is applied to the gain control of the variable gain element. A control voltage is applied to the VSET pin. The magnitude of the control voltage can optionally be attenuated via the voltage divider comprising R2 and R3, or a capacitor can be installed in Position R3 to form a low-pass filter along with R2. Power Supply Decoupling. The nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to the AD8317 and a 0.1 μF capacitor placed nearer to the power supply input pin. Filter Capacitor. The low-pass corner frequency of the circuit that drives the VOUT pin can be lowered by placing a capacitor between CLPF and ground. Increasing this capacitor increases the overall rise/fall time of the AD8317 for pulsed input signals. See the Output Filtering section for more details. VPOS RFIN R6 1kΩ 7 VPOS 6 TADJ 5 VOUT AD8317 C2 47nF INHI 1 C4 = 0.1 μF (Size 0603) C5 = 100 pF (Size 0402) C3 = 8.2 pF (Size 0402) R4 OPEN R7 OPEN 100pF R1 52.3Ω R2 = open (Size 0402) R3 = open (Size 0402) VOUT_ALT C5 8 INLO R2 = 0 Ω (Size 0402) R3 = open (Size 0402) R4 = open (Size 0402) R6 = 1 kΩ (Size 0402) RL = CL = open (Size 0402) GND R5 200Ω 0.1µF 47nF R5 = 200 Ω (Size 0402) R7 = open (Size 0402) TADJ C4 C1 Default Conditions Not applicable R1 = 52.3 Ω (Size 0402) C1 = 47 nF (Size 0402) C2 = 47 nF (Size 0402) COMM 2 CLPF 3 CL OPEN RL OPEN VOUT R2 0Ω VSET 4 C3 8.2pF R3 OPEN Figure 36. Evaluation Board Schematic Rev. B | Page 16 of 20 VSET 05541-034 Component VPOS, GND R1, C1, C2 05541-035 05541-036 AD8317 Figure 37. Component Side Layout Figure 38. Component Side Silkscreen Rev. B | Page 17 of 20 AD8317 DIE INFORMATION X 8 7 ADI 2 AD8317 1 2 Y 3 6 4 DB1 5 BOND PAD STATISTICS ALL MEASURMENTS IN MICRONS. MINIMUM PASSIVATION OPENING: 59 × 59 MIN PAD PITCH: 89 DIE THICKNESS = 305 MICRONS BALL BOND SHEAR STRENGTH SPECIFICATION: MINIMUM 15 GRAMS 05541-039 DIE SIZE CALCULATION ALL MEASURMENTS IN MICRONS. DIEX (WIDTH OF DIE IN X DIRECTION) = 670 DIEY (WIDTH OF DIE IN Y DIRECTION) = 1325 Figure 39. Die Outline Dimensions Table 6. Die Pad Function Descriptions Pin No. 1 2, 2 3 Mnemonic INHI COMM CLPF 4 5 VSET VOUT 6 TADJ 7 8 DB1 VPOS INLO COMM Description RF Input. Nominal input range of −50 dBm to 0 dBm, re: 50 Ω; ac-coupled RF input. Device Common. Connect both pads to a low impedance ground plane. Loop Filter Capacitor. In measurement mode, this capacitor sets the pulse response time and video bandwidth. In controller mode, the capacitance on this node sets the response time of the error amplifier/integrator. Setpoint Control Input for Controller Mode or Feedback Input for Measurement Mode. Measurement and Controller Output. In measurement mode, VOUT provides a decreasing linear-in dB representation of the RF input signal amplitude. In controller mode, VOUT is used to control the gain of a VGA or VVA with a positive gain sense (increasing voltage increases gain). Temperature Compensation Adjustment. Frequency-dependent temperature compensation is set by connecting a ground-referenced resistor to this pin. Positive Supply Voltage: 3.0 V to 5.5 V. RF Common for INHI. AC-coupled RF common. Device Common. Connect to a low impedance ground plane. Rev. B | Page 18 of 20 AD8317 OUTLINE DIMENSIONS 3.25 3.00 2.75 1.95 1.75 1.55 SEATING PLANE 0.60 0.45 0.30 8 EXPOSEDPAD 4 BOTTOM VIEW 2.95 2.75 2.55 12° MAX 0.25 0.20 0.15 0.15 0.10 0.05 1 0.50 BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF 031207-A 1.00 0.85 0.80 5 2.25 2.00 1.75 TOP VIEW PIN 1 INDICATOR 1.89 1.74 1.59 0.55 0.40 0.30 Figure 40. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 2 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-1) Dimensions shown in millimeters ORDERING GUIDE Model AD8317ACPZ-R7 1 AD8317ACPZ-R21 AD8317ACPZ-WP1 AD8317ACHIPS AD8317-EVALZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead LFCSP_VD, 7” Tape and Reel 8-Lead LFCSP_VD, 7” Tape and Reel 8-Lead LFCSP_VD, Waffle Pack Die Evaluation Board Z = RoHS Compliant Part. Rev. B | Page 19 of 20 Package Option CP-8-1 CP-8-1 CP-8-1 Branding Q1 Q1 Q1 AD8317 NOTES ©2005–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05541-0-3/08(B) Rev. B | Page 20 of 20