a +5 Volt, Serial Input, Dual 12-Bit DAC AD8522 FEATURES Complete Dual 12-Bit DAC No External Components +5 V Single-Supply Operation 610% 4.095 V Full Scale (1 mV/LSB) Buffered Voltage Outputs Low Power: 5 mW/DAC Space Saving 1.5 mm Height SO-14 Package APPLICATIONS Digitally Controlled Calibration Servo Controls Process Control Equipment Computer Peripherals Portable Instrumentation Cellular Base Stations Voltage Adjustment FUNCTIONAL BLOCK DIAGRAM VDD CS CLK CLK LATCH DAC A REGISTER The AD8522 is a complete dual 12-bit, single-supply, voltage output DAC in a 14-pin DIP, or SO-14 surface mount package. Fabricated in a CBCMOS process, features include a serial digital interface, onboard reference, and buffered voltage output. Ideal for +5 V-only systems, this monolithic device offers low cost and ease of use, and requires no external components to realize the full performance of the device. The serial digital interface allows interfacing directly to numerous microcontroller ports, with a simple high speed, three-wire data, clock, and load strobe format. The 16-bit serial word contains the 12-bit data word and DAC select address, which is decoded internally or can be decoded externally using LDA, LDB 0.6 LINEARITY ERROR – LSB VOUTA SHIFT REGISTER 12 BANDGAP REFERENCE REF BUF VREF REF BUF D DAC B REGISTER SDO 12 LDA LDB DAC B CONTROL LOGIC OP AMP B VOUTB AD8522 MSB RS AGND inputs. A serial data output allows the user to easily daisy-chain multiple devices in conjunction with a chip select input. A reset RS input sets the outputs to zero scale or midscale, as determined by the input MSB. The output 4.095 V full scale is laser trimmed to maintain accuracy over the operating temperature range of the device, and gives the user an easy-to-use one-millivolt-per-bit resolution. A 2.5 V reference output is also available externally for other data acquisition circuitry, and for ratiometric applications. The output buffers are capable of driving ± 5 mA. The AD8522 is available in the 14-pin plastic DIP and low profile 1.5 mm SOIC-14 packages. PACKAGE TYPES AVAILABLE VDD = +4.5V TA = –55°C, +25°C, +85°C, +125°C 0.4 OP AMP A D SDI (DATA) DGND GENERAL DESCRIPTION DAC A 12 +25°C 0.2 –55°C 0 –0.2 –0.4 PDIP-14 +85°C –0.6 SO-14 +125°C –0.8 –1.0 0 1024 2048 3072 DIGITAL INPUT CODE – Decimal 4096 Figure 1. Linearity Error vs. Digital Code & Temperature REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD8522–SPECIFICATIONS(@ V ELECTRICAL CHARACTERISTICS Parameter Symbol STATIC PERFORMANCE Resolution1 Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Voltage2 Full-Scale Tempco2, 3 N INL DNL VZSE VFS TCVFS MATCHING PERFORMANCE Linearity Matching Error ∆VFSA/B ANALOG OUTPUT Output Current Load Regulation at Half-Scale Capacitive Load3 IOUT LDREG CL REFERENCE OUTPUT Output Voltage Output Source Current4 Line Rejection Load Regulation VREF IREF LNREJ LDREG LOGIC INPUTS & OUTPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance3 Logic Output Voltage Low Logic Output Voltage High VIL VIH IIL CIL VOL VOH TIMING SPECIFICATIONS3, 5 Clock Width High Clock Width Low Load Pulse Width Data Setup Data Hold Clear Pulse Width Load Setup Load Hold Select Deselect Clock to SDO Propagation Delay tCH tCL tLDW tDS tDH tCLRW tLD1 tLD2 tCSS tCSH tPD DD = +5.0 V 6 10%, RL = No Load, –408C ≤ TA ≤ +858C, both DACs tested, unless otherwise noted) Condition Min Monotonic Data = 000H Data = FFFH 12 -1.5 -1 4.079 Typ Max Units ± 0.5 ± 0.5 +0.5 4.095 ± 15 +1.5 +1 +3 4.111 Bits LSB LSB mV Volts ppm/°C ±1 Data = 800H, ∆VOUT ≤ 3 LSB RL = 402 Ω to ∞, Data = 800H No Oscillation ∆VREF < 18 mV LSB ±5 3 mA LSB pF 2.516 5 0.08 0.1 V mA %/V %/mA 0.8 3.5 V V µA pF V V 35 35 25 10 20 20 10 10 30 30 20 ns ns ns ns ns ns ns ns ns ns ns 1 500 2.484 2.500 0.025 0.025 IREF = 0 to 5 mA, Data = 800H 2.4 IOL = 1.6 mA IOH = 400 µA 10 10 0.4 45 80 3, 5 AC CHARACTERISTICS Voltage Output Settling Time6 Crosstalk DAC Glitch Digital Feedthrough SUPPLY CHARACTERISTICS Positive Supply Current tS CT Q DFT IDD Power Dissipation7 PDISS Power Supply Sensitivity PSS To ± 1 LSB of Final Value Signal Measured at DAC Output, While Changing Opposite LDA/B Half-Scale Transition Signal Measured at DAC Output, While Changing Data Without LDA/B 16 µs 38 13 dB nV s 2 nV s VDD = 5.5 V, VIH = 2.4 V or VIL = 0.8 V VDD = 5 V, VIL = 0 V VDD = 5 V, VIH = 2.4 V or VIL = 0.8 V VDD = 5 V, VIL = 0 V ∆VDD = ± 5% 3 1 15 5 0.002 5 2 25 10 0.004 mA mA mW mW %/% NOTES 1 1 LSB = 1 mV for 0 V to +4.095 V output range. 2 Includes internal voltage reference error. 3 These parameters are guaranteed by design and not subject to production testing. 4 Very little sink current is available at the V REF pin. Use external buffer if setting up a virtual ground. 5 All input control signals are specified with t r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. 7 Power Dissipation is calculated I DD × 5 V. Specifications subject to change without notice. –2– REV. A AD8522 SDI Sf/Hd B NC A DB11 DB10 DB4 DB3 DB2 DB1 DB0 CLK t CSS t CSH CS tLD2 tLD1 LD tLDW tPD SDO SDI tDS tCH tDH tCL CLK tLD2 tLDW LD tCLRW RS tS tS FS VOUT ±1 LSB ERROR BAND ZS Figure 2. Timing Diagram SERIAL INPUT REGISTER DATA FORMAT Last First D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 NC D13 D14 D15 A B Sf/Hd Table I. Truth Table Data Word Sf/Hd B A Ext Pins LDA LDB DAC Register Hardware Load: L X L X L X L X X X X X ↓ ↓ H H ↓ H ↓ H Loads DACA + DACB with Data from SR Loads DACA with Data from SR Loads DACB with Data from SR No Load Software Decode Load: H L H H H H H L H L H H H H L L L H H H H X ↓ H ↓ H ↓ H X ↓ H ↓ H ↓ H No Load Loads DACB with Data from SR, See Note 1 Below No Load Loads DACA with Data from SR, See Note 1 Below No Load Loads DACA + DACB with Data from SR, See 1 Note Below No Load NOTES 1 In software mode LDA and LDB perform the same function. They can be tied together or the unused pin should be tied high. 2 External Pins LDA and LDB should always be high when shifting Data into the shift register. 3 ↓ symbol denotes negative transition. 1.6mA 1.6 VOLT SDO 200µA Figure 3. AC Timing SDO Pin Load Circuit REV. A –3– AD8522 PIN DESCRIPTION Pin Function SDI CLK CS LDA/B Serial Data Input, input data loads directly into the shift register. Clock input, positive edge clocks data into shift register. Chip Select, active low input. Prevents shift register loading when high. Does not affect LDA and LDB operation. Load DAC register strobes, active low. Transfers shift register data to DAC register. See truth table for operation. Software decode feature only requires one LD strobe. Tie LDA and LDB together or use one of them with the other pin tied high. Serial Data Output. Output of shift register, always active. Resets DAC registers to condition determined by MSB pin. Active low input. Digital input: High presets DAC registers to half scale (800H); Low clears all registers to zero (000H), when RS is strobed to active low. Positive +5 V power supply input. Tolerance ± 10%. Analog Ground Input. Digital Ground Input. Reference Voltage Output, 2.5 V nominal. DAC A/B voltage outputs, 4.095 V full scale, ± 5 mA output. SDO RS MSB VDD AGND DGND VREF VOUT A/B PIN CONFIGURATION 14-Pin Plastic DIP VOUTA 1 14 VOUTB AGND 2 13 VREF DGND 3 CS AD8522 14-Lead SO-14 12 VDD 4 (Not To Scale) 11 MSB CLK 5 10 RS SDI 6 9 LDA SDO 7 8 LDB 1 Table II. Truth Tables RS MSB 0 0 0 1 1 X CS CLK 1 0 X ↑ DAC Register Preset Register Activity Asynchronously Resets DAC Registers to Zero Scale Asynchronously Presets DAC Registers to Half Scale (800H) None ABSOLUTE MAXIMUM RATINGS* VDD to DGND & AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V Logic Inputs and Output to DGND . . . . . –0.3 V, VDD + 0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD IOUT Short Circuit to GND or VDD . . . . . . . . . . . . . . . . 50 mA Package Power Dissipation . . . . . . . . . . . . . . . (TJ max–TA)/θJA Thermal Resistance, θJA 14-Pin Plastic DIP Package (N-14) . . . . . . . . . . . . . 83°C/W 14-Lead SOIC Package (SO-14) . . . . . . . . . . . . . . 120°C/W Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Shift Register Shift Register AD8522AN AD8522AR –40°C to +85°C –40°C to +85°C 14-Pin P-DIP N-14 14-Lead SOIC SO-14 No Effect Shifts Register One Bit, SDO Outputs Data from 16 Clocks Earlier The AD8522 contains 1482 transistors. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8522 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– Package Option WARNING! ESD SENSITIVE DEVICE REV. A AD8522 OPERATION The AD8522 is a complete ready-to-use dual 12-bit digital-toanalog converter. Only one +5 V power supply is necessary for operation. It contains two voltage-switched, 12-bit, lasertrimmed digital-to-analog converters, a curvature-corrected bandgap reference, rail-to-rail output op amps, input registers, and DAC registers. The serial data interface consists of a serial data input (SDI), clock (CLK), and two load strobe pins (LDA, LDB) with an active low CS strobe. In addition, an asynchronous RS pin will set all DAC register bits to zero causing the VOUT to become zero volts, or to midscale for trimming applications when the MSB pin is programmed to Logic 1. This function is useful for power on reset or system failure recovery to a known state. D/A CONVERTER SECTION The internal DAC is a 12-bit voltage-mode device with an output that swings from AGND potential to the 2.5 V internal bandgap voltage. It uses a laser-trimmed R-2R ladder which is switched by N channel MOSFETs. The output voltage of the DAC has a constant resistance independent of digital input code. The DAC output is internally connected to the rail-to-rail output op amp. AMPLIFIER SECTION The internal DAC’s output is buffered by a low power consumption precision amplifier. This low power amplifier contains a differential PNP pair input stage that provides low offset voltage and low noise, as well as the ability to amplify the zero-scale DAC output voltages. The rail-to-rail amplifier is configured in a gain of 1.638 (= 4.095 V/2.5 V) in order to set the 4.095 V full-scale output (1 mV/LSB). See Figure 4 for an equivalent circuit schematic of the analog section. VOLTAGE SWITCHED 12-BIT R-2R D/A CONVERTER BANDGAP REFERENCE 2R VREF 2.5V BUFFER RAIL-TO-RAIL OUTPUT AMPLIFIER VOUT R 2R R2 R 2R SPDT N CH FET SWITCHES R1 A V = 4.096/2.5 = 1.638V/V 2R 2R Figure 4. Equivalent AD8522 Schematic of Analog Portion The op amp has a 16 µs typical settling time to 0.01%. There are slight differences in settling time for negative slewing signals versus positive. See the oscilloscope photos in the “Typical Performance Characteristics” section of this data sheet. OUTPUT SECTION The rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 5 shows an equivalent output schematic of the rail-to-rail amplifier with its N channel pull-down FETs that will pull an output load directly to GND. The output sourcing current is provided by a P channel pull-up device that can supply GND terminated loads, especially important at the –10% supply tolerance value of 4.5 V. REV. A VDD P-CH VOUT N-CH AGND Figure 5. Equivalent Analog Output Circuit Figures 6 and 7 in the typical performance characteristics section provide information on output swing performance near ground and full scale as a function of load. In addition to resistive load driving capability the amplifier has also been carefully designed and characterized for up to 500 pF capacitive load driving capability. REFERENCE SECTION The internal 2.5 V curvature-corrected bandgap voltage reference is laser trimmed for both initial accuracy and low temperature coefficient. The voltage generated by the reference is available at the VREF pin. Since VREF is not intended to drive heavy external loads, it must be buffered. The equivalent emitter follower output circuit of the VREF pin is shown in Figure 4. Bypassing the VREF pin will improve noise performance; however, bypassing is not required for proper operation. Figure 10 shows broad band noise performance. POWER SUPPLY The very low power consumption of the AD8522 is a direct result of a circuit design optimizing use of a CBCMOS process. By using the low power characteristics of the CMOS for the logic, and the low noise, tight matching of the complementary bipolar transistors good analog accuracy is achieved. For power consumption sensitive applications it is important to note that the internal power consumption of the AD8522 is strongly dependent on the actual input voltage levels present on the SDI, CLK, CS, MSB, LDA, LDB and RS pins. Since these inputs are standard CMOS logic structures, they contribute static power dissipation dependent on the actual driving logic VOH and VOL voltage levels. Consequently for optimum dissipation use of CMOS logic versus TTL provides minimal dissipation in the static state. A VINL = 0 V on the logic input pins provides the lowest standby dissipation of 1 mA with a +5 V power supply. As with any analog system, it is recommended that the AD8522 power supply be bypassed on the same PC card that contains the chip. Figure 12 shows the power supply rejection versus frequency performance. This should be taken into account when using higher frequency switched-mode power supplies with ripple frequencies of 100 kHz and higher. One advantage of the rail-to-rail output amplifiers used in the AD8522 is the wide range of usable supply voltage. The part is fully specified and tested over temperature for operation from +4.5 V to +5.5 V. If reduced linearity and source current capability near full scale can be tolerated, operation of the AD8522 –5– AD8522 is possible down to +4.3 V. The minimum operating supply voltage versus load current plot, in Figure 7, provides information for operation below VDD = +4.5 V. input register and transferring the 12 bits of data into the decoded address determined by the address bits A and B in the serial input register. Unipolar Output Operation TIMING AND CONTROL This is the basic mode of operation for the AD8522. The AD8522 has been designed to drive loads as low as 820 Ω in parallel with 500 pF. The code table for this operation is shown in Table III. The AD8522 has a 16-bit serial input register that accepts clocked in data when the CS pin is active low. The DAC registers are updated by the Load Enable (LDA and LDB) pins. The AD8522 offers two modes of data loading. The first mode, hardware-load, directs the data currently clocked into the serial shift register into either the DAC A or the DAC B register or both depending on the external active low strobing of the LDA or LDB pin. Serial data register bit Sf/Hd must be low for this mode to be in effect. Table III. Unipolar Code Table The second mode of operation is software-load which is designed to minimize the number of control lines connected to the AD8522. In this mode of operation the LDA and LDB pins act as one control input taking the present contents of the serial Hexadecimal Number in DAC Register Decimal Number in DAC Register Analog Output Voltage (V) FFF 801 800 7FF 000 4095 2049 2048 2047 0 +4.095 +2.049 +2.048 +2.047 0 Typical Performance Characteristics 5 5.2 5.0 RL TIED TO AGND DATA = FFFH V DD MIN – Volts OUTPUT VOLTAGE – Volts 4 3 VINH = +5V VINL = 0V 2 100 ∆VFS ≤ 1 LSB DATA = FFFH TA = +25°C OUTPUT PULL-DOWN VOLTAGE – mV VDD = +5V TA = +25°C 4.8 4.6 PROPER OPERATION WHEN VDD SUPPLY VOLTAGE IS ABOVE CURVE 4.4 1 4.2 RL TIED TO +5V DATA = 000H 0 10 100 1k 10k LOAD RESISTANCE – Ω 4.0 0.01 100k Figure 6. Output Swing vs. Load 0.1 1.0 10 OUTPUT LOAD CURRENT – mA 100 Figure 7. Minimum Supply Voltage vs. Load Current +85°C 1 –55°C 0.1 +25°C 0.01 1 10 100 OUTPUT SINK CURRENT – µA 1000 Figure 8. Pull-Down Voltage vs. Output Sink Current Capability 9 80 8 POSITIVE CURRENT LIMIT 40 TA = +25°C NBW = 1MHz 100 90 DATA = 800H 0 –20 200µV/DIV 20 10 –40 NEGATIVE CURRENT LIMIT –60 –80 1 2 3 OUTPUT VOLTAGE – Volts Figure 9. IOUT vs. VOUT 0% SUPPLY CURRENT IDD – mA 60 OUTPUT CURRENT – mA VDD = +5V DATA = 000H VIH = 5.0V VIL = 0.0V 10 TA = +25°C 7 6 VDD = +4.5V 5 VDD = +5V 4 3 2 1 100µs/DIV Figure 10. Broadband Noise –6– 0 0 1 2 3 4 LOGIC INPUT VOLTAGE VINH – Volts 5 Figure 11. Supply Current vs. Logic Input Voltage REV. A AD8522 204810 TO 204710 5V LD INPUT VDD = +5V ± 200mVAC TA = +25°C DATA = FFFH 120 100 90 100 RS 5V 100 0V 90 VOUT 4V 80 VOUT 100mV/ DIV 60 OUTPUT POWER SUPPLY REJECTION – dB 140 TA = +25°C VDD = +5V TA = +25°C VDD = +5V 10 0% 10 40 0% #299, DAC A VINH = +5V VINL = 0V 20 0V 100mV 500ns –SR TIME – 500ns/DIV 0 10 100 1k 10k 100k FREQUENCY – Hz 1M Figure 13. Midscale Transition Performance Figure 12. Power Supply Rejection vs. Frequency FULL SCALE VOLTAGE – Volts 20 15 10 4.1 AVG +1σ 4.095 4.09 1.0 105 125 1k 10k FREQUENCY – Hz 100k 1.0 0.8 AVG +1σ 0.6 AVG 0.4 AVG –1σ 5 25 45 65 85 TEMPERATURE – °C 105 125 Figure 17. Zero-Scale Voltage vs. Temperature 4.0 VDD = +4.5V SSZ = 135 UNITS DATA = FFFH 4.095 4.094 4.093 3.5 AVG +1σ 4.092 4.091 4.090 AVG 4.089 4.088 4.087 AVG –1σ 4.086 3.0 VDD = +5.5V 2.5 VDD = +5V 2.0 VDD = +4.5V 1.5 1.0 VIN = +2.4V NO LOAD 0.5 4.085 4.084 100 Figure 18. Output Voltage Noise Density vs. Frequency REV. A 5 25 45 65 85 TEMPERATURE – °C Figure 16. Full-Scale Voltage vs. Temperature FULL-SCALE OUTPUT VOLTAGE – Volts 10 1.2 0.0 –55 –35 –15 4.096 V DD = +5V DATA = FFF H TA = +25°C VDD = +4.5V NO LOAD SSZ = 300 UNITS 0.2 4.075 –55 –35 –15 100 0.1 10 AVG –1σ 4.08 5 Figure 15. Total Unadjusted Error Histogram AVG 4.085 5 –5 –4 –3 –2 –1 0 1 2 3 4 TOTAL UNADJUSTED ERROR – mV 1.4 SUPPLY CURRENT – mA FREQUENCY 4.105 25 OUTPUT NOISE DENSITY – µV/√Hz 1.6 VDD = +4.5V NO LOAD SSZ = 300 UNITS ZERO-SCALE VOLTAGE – mV TUE = ∑ (INL+ZS+FS) SSZ = 300 UNITS VDD = +4.5V TA = +25°C 30 0 Figure 14. Large Signal Settling Time 4.11 40 35 +SR TIME – 20µs/DIV 0 100 200 300 400 500 HOURS OF OPERATION AT +150°C 600 Figure 19. Long Term Drift Accelerated by Burn-In –7– 0 –55 –35 –15 5 25 45 65 85 TEMPERATURE – °C 105 125 Figure 20. Supply Current vs. Temperature AD8522 2.504 2V 5V V DD = +4.5V SSZ = 300 UNITS 0V TA = +25°C NO LOAD VDD = +5V AVG VOUT 20mV/ DIV 2.500 AVG –1σ 2.498 C1942–18–94 90 0V 2.496 10 0% 0V 1µs 1V 2.494 TIME – 5µs/DIV TIME – 1µs/DIV 2.492 –55 –35 –15 0.05 0 V DD = +4.5V SSZ = 300 UNITS ∆ IL = 5mA –0.01 VREF LINE REGULATION – %/Volts VREF LOAD REGULATION – %/mA 105 125 Figure 23. Reference Voltage vs. Temperature Figure 22. Digital Feedthrough vs. Time Figure 21. Reference Startup vs. Time 5 25 45 65 85 TEMPERATURE – °C –0.02 AVG +3σ –0.03 AVG AVG –3σ –0.04 –0.05 –0.06 –55 –35 –15 5 25 45 65 85 TEMPERATURE – °C ∆ V DD = +4.5V TO +5.5V SSZ = 300 UNITS 0.04 AVG +3σ 0.03 AVG 0.02 AVG –3σ 0.01 0 –55 –35 –15 105 125 5 25 45 65 85 TEMPERATURE – °C 105 125 Figure 25. Reference Line Regulation vs. Temperature Figure 24. Reference Load Regulation vs. Temperature OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Narrow Body SOIC (SO-14) 14-Lead Epoxy DIP (N-14) 14 8 14 0.1574 (4.00) 0.1497 (3.80) PIN 1 7 1 8 0.280 (7.11) 0.240 (6.10) PIN 1 1 0.2440 (6.20) 0.2284 (5.80) 7 0.325 (8.25) 0.300 (7.62) 0.795 (20.19) 0.725 (18.42) 0.3444 (8.75) 0.3367 (8.55) 0.0196 (0.50) x 45 ° 0.0099 (0.25) 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0098 (0.25) 0.0075 (0.19) 8° 0° 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.0500 (1.27) 0.0160 (0.41) 0.022 (0.558) 0.014 (0.356) –8– 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) SEATING PLANE REV. A PRINTED IN U.S.A. VREF AVG +1σ 2.502 CLK 100 VREF – Volts VDD