Quad, Serial-Input 12-Bit/10-Bit DACs AD7398/AD7399 FUNCTIONAL BLOCK DIAGRAM FEATURES VDD VREF B VREF A AD7398/AD7399 INPUT REG A DAC A REGISTER DAC A VOUTA DAC B REGISTER DAC B VOUTB DAC C REGISTER DAC C VOUTC DAC D REGISTER DAC D VOUTD SERIAL REGISTER CS INPUT REG B SDI INPUT REG C CLK APPLICATIONS 12/10 Automotive output voltage span Portable communications Digitally controlled calibration PC peripherals INPUT REG D POWER ON RESET VSS RS LDAC VREF C VREF D 02179-001 AD7398—12-bit resolution AD7399—10-bit resolution Programmable power shutdown Single (3 V to 5 V) or dual (±5 V) supply operation 3-wire, serial SPI®-compatible interface Internal power-on reset Double buffered registers for simultaneous multichannel DAC update Four separate rail-to-rail reference inputs Thin profile, TSSOP-16 package available Low tempco: 1.5 ppm/°C Qualified for automotive applications GND Figure 1. GENERAL DESCRIPTION A doubled-buffered serial-data interface offers high speed, 3-wire, SPI- and microcontroller-compatible inputs using serial data-in (SDI), clock (CLK), and a chip-select (CS). A common levelsensitive, load-DAC strobe (LDAC) input allows simultaneous update of all DAC outputs from previously loaded input registers. Additionally, an internal power-on reset forces the output voltage to zero at system turn on. An external asynchronous reset (RS) also forces all registers to the zero code state. A programmable powershutdown feature reduces power dissipation on unused DACs. The AD7398/AD7399 are specified over the extended industrial (−40°C to +125°C) temperature range. Parts are available in 16-lead, wide body SOIC and ultracompact, thin, 1.1 mm TSSOP packages. 0.5 VDD = +5V VSS = –5V VREF = +2.5V TA = 25°C 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 02179-002 The applied external reference, VREF, determines the full-scale output voltage. Valid VREF values include VSS < VREF < VDD that result in a wide selection of full-scale outputs. For multiplying applications, ac inputs can be as large as ±5 VP. Both parts are offered in the same pinout, enabling users to select the appropriate resolution for their application without redesigning the layout. For 8-bit resolution applications, see the pin-compatible AD7304 product. DNL (LSB) The AD7398/AD7399 family of quad, 12-bit/10-bit, voltage output digital-to-analog converters (DACs) is designed to operate from a single 3 V to 5 V supply or a dual ±5 V supply. Built with the Analog Devices, Inc. robust CBCMOS process, these monolithic DACs offer the user low cost with ease-of-use in single or dual-supply systems. –0.4 –0.5 0 512 1024 1536 2048 2560 3072 3584 4096 CODE (Decimal) Figure 2. AD7398 DNL vs. Code (TA = 25°C) Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2011 Analog Devices, Inc. All rights reserved. AD7398/AD7399 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 10 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 14 Functional Block Diagram .............................................................. 1 DAC Operation .......................................................................... 14 General Description ......................................................................... 1 Operation with VREF Equal to the Supply ................................ 15 Revision History ............................................................................... 2 Power Supply Sequencing ......................................................... 15 Specifications..................................................................................... 3 Programmable Power Shutdown.............................................. 15 AD7398 12-Bit Voltage Output DAC ........................................ 3 Worst Case Accuracy ................................................................. 15 AD7399 10-Bit Voltage Output DAC ........................................ 4 Serial Data Interface ................................................................... 15 Timing Diagrams.......................................................................... 5 Power-On Reset .......................................................................... 16 Absolute Maximum Ratings............................................................ 6 Microprocessor Interfacing ....................................................... 16 ESD Caution .................................................................................. 6 Applications Information .............................................................. 18 Pin Configuration And Function Descriptions ............................ 7 Staircase Windows Comparator ............................................... 18 Input Registers .................................................................................. 8 Programmable DAC Reference Voltage .................................. 19 AD7398 Serial Input Register Data Format .............................. 8 Outline Dimensions ....................................................................... 20 AD7399 Serial Input Register Data Format .............................. 8 Ordering Guide .......................................................................... 21 Terminology ...................................................................................... 9 REVISION HISTORY 1/11—Rev. B to Rev. C Added Automotive Model and Information .............. Throughout 12/09—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 21 6/06—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Ordering Guide .......................................................... 21 11/00—Revision 0: Initial Version Rev. C | Page 2 of 24 AD7398/AD7399 SPECIFICATIONS AD7398 12-BIT VOLTAGE OUTPUT DAC VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = −5 V, VREF = +2.5 V, −40°C < TA < +125°C, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE Resolution 1 Relative Accuracy2 Differential Nonlinearity2 Zero-Scale Error Full-Scale Voltage Error Full-Scale Tempco3 REFERENCE INPUT VREFIN Range4 Input Resistance5 Input Capacitance3 ANALOG OUTPUT Output Voltage Range Output Current Capacitive Load3 LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance3 INTERFACE TIMING3, 7 Clock Frequency Clock Width High Clock Width Low CS to Clock Setup Clock to CS Hold Load DAC Pulse Width Data Setup Data Hold Load Setup to CS Load Hold to CS AC CHARACTERISTICS Output Slew Rate Settling Time8 Shutdown Recovery DAC Glitch Digital Feedthrough Feedthrough Symbol 3 V to 5 V ± 10% ±5 V ± 10% Unit 12 ±1.5 ±1 7 ±2.5 1.5 12 ±1.5 ±1 ±2.5 ±2.5 1.5 Bits LSB max LSB max mV max mV max ppm/°C typ 0/VDD 35 5 VSS/VDD 35 5 V min/max kΩ typ6 pF typ 0 to VREF ±5 200 0 to VREF ±5 400 V mA typ pF max IIL CIL 0.5 0.8 80% VDD 2.1 to 2.4 1 10 0.8 4.0 2.4 1 10 V max V max V min V min μA max pF max fCLK tCH tCL tCSS tCSH tLDAC tDS tDH tLDS tLDH 11 45 45 10 20 45 15 10 0 20 16.6 30 30 5 15 30 10 5 0 15 MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min 2 6 6 150 15 −63 2 6 6 150 15 −63 V/μs typ μs typ μs typ nVs typ nVs typ dB typ N INL DNL VZSE VFSE TCVFS VREF RREF CREF VOUT IOUT CL VIL VIH SR tS tSDR Q QDF VOUT/VREF Condition Monotonic Data = 000H Data = FFFH Data = 555H, worst case Data = 800H, ΔVOUT = 4 LSBs No oscillation VDD = 3 V VDD = 5 V CLK only Data = 000H to FFFH to 000H To ±0.1% of full scale Code 7FFH to 800H to 7FFH VREF = 1.5 VDC 1 V p-p, data = 000H, f = 100 kHz Rev. C | Page 3 of 24 AD7398/AD7399 Parameter SUPPLY CHARACTERISTICS Shutdown Supply Current Positive Supply Current Negative Supply Current Power Dissipation Power Supply Sensitivity Symbol Condition 3 V to 5 V ± 10% ±5 V ± 10% Unit IDD_SD IDD IDD ISS PDISS PSS No load VIL = 0 V, no load, −40°C < TA < +125°C VIL = 0 V, no load, −40°C < TA < +85°C VIL = 0 V, no load VIL = 0 V, no load ΔVDD = ±5% 30/60 1.5/2.8 1.5/2.6 1.5/2.5 5 0.006 30/60 1.6/3 1.6/2.8 1.6/2.7 16 0.006 μA typ/max mA typ/max mA typ/max mA typ/max mW typ %/% max One LSB = VREF/4096 V for the 12-bit AD7398. The first eight codes (000H to 007H) are excluded from the linearity error measurement in single-supply operation. These parameters are guaranteed by design and not subject to production testing. 4 When VREF is connected to either the VDD or the VSS power supply, the corresponding VOUT voltage programs between ground and the supply voltage minus the offset voltage of the output buffer, which is the same as the VZSE error specification. See additional information in the Theory of Operation section. 5 Input resistance is code dependent. 6 Typicals represent average readings measured at 25°C. 7 All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 8 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground. 1 2 3 AD7399 10-BIT VOLTAGE OUTPUT DAC VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V; VREF = +2.5 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE Resolution1 Relative Accuracy2 Differential Nonlinearity2 Zero-Scale Error Full-Scale Voltage Error Full-Scale Tempco3 REFERENCE INPUT VREFIN Range4 Input Resistance5 Input Capacitance3 ANALOG OUTPUT Output Voltage Range Output Current Capacitive Load3 LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance3 INTERFACE TIMING3, 7 Clock Frequency Clock Width High Clock Width Low CS to Clock Setup Clock to CS Hold Load DAC Pulse Width Data Setup Data Hold Load Setup to CS Load Hold to CS Symbol 3 V to 5 V ± 10% ±5 V ± 10% Unit 10 ±1 ±1 7 ±15 1.5 10 ±1 ±1 ±4 ±15 1.5 Bits LSB max LSB max mV max mV max ppm/°C typ 0/VDD 40 5 VSS/VDD 40 5 V min/max kΩ typ6 pF typ 0 to VREF ±5 200 0 to VREF ±5 400 V mA typ pF max IIL CIL 0.5 0.8 80% VDD 2.1 to 2.4 1 10 0.8 4.0 2.4 1 10 V max V max V min V min μA max pF max fCLK tCH tCL tCSS tCSH tLDAC tDS tDH tLDS tLDH 11 45 45 10 20 45 15 10 0 20 16.6 30 30 5 15 30 10 5 0 15 MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min N INL DNL VZSE VFSE TCVFS VREF RREF CREF VOUT IOUT CL VIL VIH Condition Monotonic Data = 000H Data = 3FFH Data = 155H, worst case Data = 200H, ΔVOUT = 1 LSB No oscillation VDD = 3 V VDD = 5 V CLK only Rev. C | Page 4 of 24 AD7398/AD7399 Parameter AC CHARACTERISTICS Output Slew Rate Settling Time8 Shutdown Recovery DAC Glitch Digital Feedthrough Feedthrough Symbol Condition 3 V to 5 V ± 10% ±5 V ± 10% Unit SR tS tSDR Q QDF VOUT/VREF Data = 000H to 3FFH to 000H To ±0.1% of full scale 2 6 6 150 15 −63 2 6 6 150 15 −63 V/μs typ μs typ μs typ nVs typ nVs typ dB typ SUPPLY CHARACTERISTICS Shutdown Supply Current Positive Supply Current IDD_SD IDD No load VIL = 0 V, no load, −40°C < TA < +125°C VIL = 0 V, no load, −40°C < TA < +85°C VIL = 0 V, no load VIL = 0 V, no load ΔVDD = ±5% 30/60 1.5/2.8 30/60 1.6/3 μA typ/max mA typ/max 1.5/2.6 1.6/2.8 mA typ/max 1.5/2.5 5 0.006 1.6/2.7 16 0.006 mA typ/max mW typ %/% max Code 1FFH to 200H to 1FFH VREF = 1.5 VDC + 1 V p-p, data = 000H, f = 100 kHz IDD Negative Supply Current Power Dissipation Power Supply Sensitivity ISS PDISS PSS One LSB = VREF/1024 V for the 10-bit AD7399. The first two codes (000H and 001H) are excluded from the linearity error measurement in single-supply operation. 3 These parameters are guaranteed by design and not subject to production testing. 4 When VREF is connected to either the VDD or the VSS power supply, the corresponding VOUT voltage programs between ground and the supply voltage minus the offset voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the Theory of Operation section. 5 Input resistance is code dependent. 6 Typicals represent average readings measured at 25°C. 7 All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 8 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground. 1 2 TIMING DIAGRAMS SDI SA SD A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IN REG LD CLK tDS tDH tCH tCL tCSH tCSS CS tLDH tLDS tLDAC 02179-003 LDAC Figure 3. AD7398 Timing Diagram (AD7399 with SDI = 14 Bits Only) CLK tCH LDAC tCL 1/fCLK tLDH tLDS tLDS CS tCSS tCSH Figure 4. Continuous Clock Timing Diagram Rev. C | Page 5 of 24 tCSS 02179-004 tLDAC AD7398/AD7399 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VDD to GND VSS to GND VREF to GND Logic Inputs to GND VOUT to GND IOUT Short Circuit to GND Thermal Resistance (θJA) 16-Lead SOIC_W Package (RW-16) 16-Lead TSSOP Package (RU-16) Maximum Junction Temperature (TJ Max) Package Power Dissipation Operating Temperature Range Storage Temperature Range Reflow Soldering Peak Temperature SnPb Pb-Free Rating −0.3 V, +7 V +0.3 V, −7 V VSS, VDD −0.3 V, +8 V VSS − 0.3 V, VDD + 0.3 V 50 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 158°C/W 180°C/W 150°C (TJ Max – TA)/θJA −40°C to +125°C −65°C to +150°C 240°C 260°C Rev. C | Page 6 of 24 AD7398/AD7399 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VOUTB 1 16 VOUTC VOUTA 2 15 VOUTD VSS 3 VREF A 4 AD7398/ AD7399 TOP VIEW (Not to Scale) 14 VDD 13 VREF C 12 VREF D GND 6 11 SDI LDAC 7 10 CLK RS 8 9 CS 02179-005 VREF B 5 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic 1 VOUTB Description DAC B Voltage Output. 2 VOUTA DAC A Voltage Output. 3 VSS Negative Power Supply Input. Specified range of operation 0 V to −5.5 V. 4 VREFA DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin or VSS pin. 5 VREFB DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin or VSS pin. 6 GND Ground Pin. 7 LDAC Load DAC Register Strobe. Level sensitive active low. Transfers all input register data to DAC registers. Asynchronous active low input. See Table 5 for operation. 8 RS Resets Input and DAC Registers to All Zero Codes. Shift register contents unchanged. 9 CS Chip Select. Active low input. Disables shift register loading when high. Transfers serial register data to the input register when CS returns high. Does not effect LDAC operation. 10 CLK Schmitt Triggered Clock Input. Positive edge clocks data into shift register. 11 SDI Serial Data Input. Input data loads directly into the shift register. 12 VREFD DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin or VSS pin. 13 VREFC DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin or VSS pin. 14 VDD Positive Power Supply Input. Specified range of operation 3 V to 5 V ± 10%. 15 VOUTD DAC D Voltage Output. 16 VOUTC DAC C Voltage Output. Table 5. Control Logic Truth Table CS CLK LDAC Serial Shift Register Function Input Register Function DAC Register H L L L ↑+ H H X L ↑+ H L/H X X H H H H H L ↑+ No effect No effect Shift register data advanced one bit No effect No effect No effect No effect No effect No effect Latched Latched Updated with shift register contents Latched Latched No effect No effect No effect No effect No effect Transparent Latched NOTES 1. ↑+ = Positive logic transition; ↓– = Negative logic transition; X = Don’t Care. 2. At power-on, both the input register and the DAC register are loaded with all zeros. 3. During power shutdown, reprogramming of any internal registers can take place, but the output amplifiers do not produce the new values until the part is taken out of shutdown mode. 4. The LDAC input is a level-sensitive input that controls the four DAC registers. Rev. C | Page 7 of 24 AD7398/AD7399 INPUT REGISTERS AD7398 SERIAL INPUT REGISTER DATA FORMAT Data is loaded in the MSB first format. MSB B15 SA B14 SD B13 A1 B12 A0 B11 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 LSB B0 D0 NOTE Bit Position B14 and Bit Position B15 are the SD and SA power shutdown control bits. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to Logic 1, the address decoded by Bit B12 and Bit B13 (A0 and A1) determine the DAC channel that is placed in the power shutdown state. AD7399 SERIAL INPUT REGISTER DATA FORMAT Data is loaded in the MSB first format. MSB B13 SA B12 SD B11 A1 B10 A0 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 LSB B0 D0 NOTE Bit Position B12 and Bit Position B13 are the SD and SA power shutdown control bits. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to Logic 1, the address decoded by Bit B10 and Bit B11 (A0 and A1) determine the DAC channel that is placed in the power shutdown state. Table 6. AD7398/AD7399 Address Decode Control SA 1 0 0 0 0 0 0 0 0 SD X 1 1 1 1 0 0 0 0 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 DAC Channel Affected All DACs shutdown DAC A shutdown DAC B shutdown DAC C shutdown DAC D shutdown DAC A input register decoded DAC B input register decoded DAC C input register decoded DAC D input register decoded Rev. C | Page 8 of 24 AD7398/AD7399 TERMINOLOGY Relative Accuracy (INL) For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Figure 6 illustrates a typical INL vs. code plot. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Figure 8 illustrates a typical DNL vs. code plot. Zero-Scale Error (VZSE) Zero-scale error is a measure of the output voltage error from zero voltage when zero code is loaded to the DAC register. Full-Scale Error (VFSE) Full-scale error is a measure of the output voltage error from full-scale voltage when full-scale code is loaded to the DAC register. Full-Scale Temperature Coefficient (TCVFS) This is a measure of the change in full-scale error with a change in temperature. It is expressed in ppm/°C or mV/°C. DAC Glitch Impulse (Q) Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV −s and is measured when the digital input code is changed by 1 LSB at the major carry transition (midscale transition). A plot of the glitch impulse is shown in Figure 15. Digital Feedthrough (QDF) Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. CS is held high while the CLK and SDI signals are toggled. It is specified in nV − s, and is measured with a full-scale code change on the data bus, such as from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in Figure 16. Power Supply Sensitivity (PSS) This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Power supply sensitivity is quoted in terms of % change in output per % change in VDD for full-scale output of the DAC. VDD is varied by ±10%. Reference Feedthrough (VOUT/VREF) This is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in dB or mV p-p. Rev. C | Page 9 of 24 AD7398/AD7399 TYPICAL PERFORMANCE CHARACTERISTICS 1.25 1.00 0.3 0.2 0.50 0.1 DNL (LSB) 0.75 0.25 0 0 –0.1 –0.25 –0.2 –0.50 –0.3 –0.75 –1.00 0 512 1024 1536 2048 2560 3072 3584 AD7398 VDD = +5V VSS = –5V VREF = +2.5V TA = 25°C 0.4 02179-006 INL (LSB) 0.5 AD7398 VDD = +5V VSS = –5V VREF = +2.5V TA = 25°C 02179-008 1.50 –0.4 –0.5 4096 0 512 1024 CODE (Decimal) 0.50 DNL (LSB) INL (LSB) 0.25 0 –0.25 TA = 25°C, VDD = +5V, VSS = –5V, VREF = +2.5V 256 384 3072 TA = 25°C, VDD = +5V, VSS = –5V, VREF = +2.5V DAC D 128 2560 0.25 DAC D –0.25 –0.50 512 640 768 896 1024 0 128 256 384 512 640 768 1024 0.50 DAC C DAC C 0.25 DNL (LSB) INL (LSB) 896 CODE (Decimal) 0.50 0 –0.25 TA = 25°C, VDD = +5V, VSS = –5V, VREF = +2.5V –0.50 0 128 256 384 0.25 0 –0.25 TA = 25°C, VDD = +5V, VSS = –5V, VREF = +2.5V –0.50 512 640 768 896 0 1024 128 256 384 512 640 768 896 1024 CODE (Decimal) CODE (Decimal) 0.50 0.50 DAC B DAC B 0.25 DNL (LSB) INL (LSB) 4096 0 CODE (Decimal) 0 –0.25 TA = 25°C, VDD = +5V, VSS = –5V, VREF = +2.5V –0.50 0 128 256 384 0.25 0 –0.25 TA = 25°C, VDD = +5V, VSS = –5V, VREF = +2.5V –0.50 512 640 768 896 0 1024 128 256 384 512 640 768 896 1024 CODE (Decimal) CODE (Decimal) 0.50 0.50 DAC A 0 02179-007 –0.25 TA = 25°C, VDD = +5V, VSS = –5V, VREF = +2.5V –0.50 0 128 256 384 512 640 768 896 0.25 0 –0.25 TA = 25°C, VDD = +5V, VSS = –5V, VREF = +2.5V –0.50 0 1024 02179-009 0.25 DNL (LSB) DAC A INL (LSB) 3584 Figure 8. AD7398 DNL vs. Code (TA = 25 °C) 0.50 0 2048 CODE (Decimal) Figure 6. AD7398 INL vs. Code (TA = 25°C) –0.50 1536 128 256 384 512 640 768 CODE (Decimal) CODE (Decimal) Figure 7. AD7399 INL vs. Code (TA = 25°C) Figure 9. AD7399 DNL vs. Code (TA = 25 °C) Rev. C | Page 10 of 24 896 1024 AD7398/AD7399 10 AD7398 TA = 25°C VDD = +5V VSS = –5V 0.75 DNL 8 6 VDD = +5V, VSS = –5V 4 ΔVOUT (mV) INL, DNL, FSE (LSB) 0.50 0.25 INL 0 FSE –0.25 2 0 VDD = +5V, VSS = 0V –2 –4 SOURCING CURRENT FROM VOUT VDD = +5V, VSS = –5V VDD = +5V, VSS = 0V VDD = +3V, VSS = 0V –0.50 –6 –1.00 –5 02179-010 –0.75 –4 –3 –2 –1 0 1 2 3 4 –8 –10 –20 5 –15 Figure 10. AD7398 INL, DNL, FSE vs. Reference Voltage 5 10 15 20 AD7398 SAMPLE SIZE = 125 –40°C TO +125°C 20 70 COUNTS 60 50 40 15 10 30 20 0 0 512 1024 1536 2048 2560 3072 3584 0 0.4 4096 CODE (Decimal) 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 FULL-SCALE ERROR TEMPCO (ppm/°C) Figure 11. AD7398 Reference Input Current vs. Code 1000 02179-014 5 10 Figure 14. AD7398 Full-Scale Error Tempco AD7398 VDD = +5V VSS = –5V TA = 25°C 100 90 100 CS (5V/DIV) VOUT (0.2V/DIV) 10 10 0 512 1024 1536 2048 2560 3072 3584 0% 02179-015 02179-012 REFERENCE INPUT RESISTANCE (kΩ) 0 25 02179-011 REFERENCE INPUT CURRENT (µA) 80 –5 Figure 13. ΔVOUT vs. Load Current AD7398 VDD = +5V VSS = –5V VREF = +2.5V TA = 25°C 90 –15 SOURCE OR SINK CURRENT FROM VOUT (mA) REFERENCE VOLTAGE (V) 100 AD7398/AD7399 TA = 25°C SINKING CURRENT INTO VOUT VDD = +3V, VSS = 0V 02179-013 1.00 4096 CODE (Decimal) TIME (2µs/DIV) Figure 12. AD7398 Reference Input Resistance vs. Code Figure 15. AD7398 Midscale Glitch Rev. C | Page 11 of 24 AD7398/AD7399 VOUT (50mV/DIV) –24 –36 –48 –60 –72 –84 CLOCK (5V/DIV) 10 0x000 02179-016 0% –96 VDD = +5V VSS = –5V VREF = +100mV rms TA = 25°C 100 1k 100k 10k TIME (100ns/DIV) ATTENUATION (dB) 90 –12 02179-019 100 0 0xFFF 0x800 0x400 0x200 0x100 0x080 0x040 0x020 0x010 0x008 0x004 0x002 0x001 –108 1M FREQUENCY (Hz) Figure 19. AD7398 Multiplying Gain vs. Frequency Figure 16. AD7398 Digital Feedthrough 5 VDD = +5V, VSS = –5V, VREF = +5V 100 VOUT (2V/DIV) 90 SUPPLY CURRENT (mA) DLY 54µs TA = 25°C 1. VDD = +5V, 3. VDD = +5V, 4 3. VDD = +5V, 4. VDD = +5V, 5. VDD = +3V, 6. VDD = +3V, VSS VSS VSS VSS VSS VSS = –5V, CODE = 0x000, 0xFFF = –5V, CODE = 0x555 = 0V, CODE = 0x000, 0xFFF = 0V, CODE = 0x555 = 0V, CODE = 0x000, 0xFFF = 0V, CODE = 0x555 2 4 3 1 6 3 2 5 1 02179-020 10 0% 5µs 02179-017 CS (5V/DIV) 2v 5V 0 1k 10k 100k 1M 10M 100M CLOCK FREQUENCY (Hz) TIME (5µs/DIV) Figure 17. AD7398 Large Signal Settling Time Figure 20. AD7398 Supply Current vs. Clock Frequency VDD = +5V, VSS = –5V, VREF = +5V AD7398 TA = 25°C VREF = +2.5V DLY 67µs 100 VOUT (2V/DIV) 90 10 CS (5V/DIV) ±5V DUAL SUPPLY 1.75 ±3V SINGLE SUPPLY 1.50 1.25 02179-021 0.8V POWER SUPPLY CURRENT (mA) A2 2.00 5V 2V 2µs 02179-018 0% 1.00 2 3 4 5 POWER SUPPLY VOLTAGE (V) TIME (2µs/DIV) Figure 18. AD7398 Shutdown Recovery Figure 21. AD7398 Supply Current vs. Supply Voltage Rev. C | Page 12 of 24 6 AD7398/AD7399 1.00 2.0 1.5 1.0 02179-022 0.5 0 –50 0 50 100 34 33 32 02179-023 SHUTDOWN CURRENT (µA) 35 20 40 60 0.25 CODE = 0x000 100 200 300 400 Figure 24. AD7398 Long-Term Drift AD7398/AD7399 VDD = +5V VSS = –5V 0 CODE = 0xFFF HOURS OF OPERATION AT 150°C 36 –20 0.50 0 Figure 22. Supply Current vs. Temperature –40 0.75 0 150 TEMPERATURE (°C) 31 –60 AD7398 SAMPLE SIZE = 135 VREF = 2.5V 80 100 120 02179-024 SUPPLY CURRENT (mA) 2.5 AD7398/AD7399 VDD = +5V VSS = –5V NOMINAL CHANGE IN VOLTAGE (mV) 3.0 140 TEMPERATURE (°C) Figure 23. Shutdown Current vs. Temperature Rev. C | Page 13 of 24 500 600 AD7398/AD7399 THEORY OF OPERATION VDD VREF A VREF B VREF C VREF D AD7398/AD7399 CS INPUT REGISTER DAC REGISTER DAC A VOUTA INPUT REGISTER DAC REGISTER DAC B VOUTB INPUT REGISTER DAC REGISTER DAC C VOUTC INPUT REGISTER DAC REGISTER DAC D VOUTD LDAC VSS CLK ADDRESS DECODE 4 SDI SERIAL REGISTER 12/10 RS GND 02179-025 POWER ON RESET Figure 25. Simplified Block Diagram The AD7398/AD7399 contain four 12-bit and 10-bit, respectively, voltage output, digital-to-analog converters. Each DAC has its own independent multiplying reference input. Both the AD7398 and AD7399 use a 3-wire, SPI-compatible serial data interface, with an asynchronous RS pin for zero-scale reset. In addition, an LDAC strobe enables four-channel simultaneous updates for hardware-synchronized output voltage changes. VDD VOUTA 02179-026 R VSS (1) VOUT = VREF × D/1024 (For AD7399) (2) where: In order to maintain good analog performance, the user should bypass power supplies with 0.01 μF ceramic capacitors (mount them close to the supply pins) and 1 μF to 10 μF tantalum capacitors in parallel. In addition, clean power supplies with low ripple voltage capability should be used. Switching power supplies can be used for this application, but beware of its higher ripple voltage and PSS frequency-dependent characteristics. It is also best to supply power to the AD7398/AD7399 from the system’s analog supply voltages. Do not use the digital 5 V supply. VREF GND VOUT = VREF × D/4096 (For AD7398) D is the 12-bit or 10-bit decimal equivalent of the data word. VREF is the externally applied reference voltage. AD7398/AD7399 R The nominal DAC output voltage is determined by the externally applied VREF and the digital data (D) as Figure 26. Simplified DAC Channel DAC OPERATION The internal R-2R ladder of the AD7398/AD7399 operates in the voltage switching mode, maintaining an output voltage that is the same polarity as the input reference voltage. A proprietary scaling technique is used to attenuate the input reference voltage in the DAC. The output buffer amplifies the internal DAC output to achieve a VREF to VOUT gain of unity. The reference input resistance is code dependent, exhibiting worst case 35 kΩ for AD7398 when the DAC is loaded with alternating codes 010101010101. Similarly, the reference input resistance is 40 kΩ for AD7399 when the DAC is loaded with 0101010101. Rev. C | Page 14 of 24 AD7398/AD7399 OPERATION WITH VREF EQUAL TO THE SUPPLY SERIAL DATA INTERFACE The AD7398/AD7399 are designed to approach the full output voltage swing from ground to VDD or VSS. The maximum output swing is achieved when the corresponding VREF input pin is tied to the same power supply. This power supply should be low noise and low ripple, preferably operated by a suitable reference voltage source such as ADR292 or REF02. The output swing is limited by the internal buffer offset voltage and the output drive current capability of the output stage. Users should at least budget the VZSE offset voltage as the closest the output voltage can get to either supply voltage under a no load condition. Under a loaded output, degrade the headroom by a factor of 2 mV per 1 mA of load current. Also note that the internal op amp has an offset voltage so that the first eight codes of AD7398 may not respond at the supply voltage or at ground until the internal DAC voltage exceeds the offset voltage of the output buffers. Similarly, the first two codes of AD7399 should not be used. The AD7398/AD7399 uses a 3-wire (CS, SDI, CLK) SPIcompatible serial data interface. Serial data of the AD7398 and AD7399 is clocked into the serial input register in a 16-bit and 14bit data-word format, respectively. MSBs are loaded first. The Input Registers section defines the 16 data-word bits for AD7398 and the 14 data-word bits for the AD7399. Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK, subject to the data setup and data hold time requirements specified in the Specifications section. Data can only be clocked in while the CS chip select pin is active low. For the AD7398, only the last 16 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state, and extra data bits are ignored. For the AD7399, only the last 14 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state. Because most microcontrollers output serial data is in eight-bit bytes, two right-justified data bytes can be written to the AD7398 and AD7399. Keeping the CS line low between the first and second byte transfers results in a successful serial register update. POWER SUPPLY SEQUENCING VDD/VSS of AD7398/AD7399 should be powered from the system analog supplies. The external reference input can be supplied from the same supply to avoid a possible latch-up when the reference is powered on prior to VDD/VSS, or powered off subsequent to VDD/VSS. If VDD/VSS and VREF have separate power sources, ensure the power-up sequence is GND, VDD, VSS, VREF/digital input/digital output. The reverse sequence applies to the power-down sequence. The order of VREF and digital input/digital output is not important. In addition, VREF pins of the unused DACs should be connected to GND or some other power sources to ensure a similar powerup/power-down sequence. PROGRAMMABLE POWER SHUTDOWN The two MSBs of the serial input register, SA and SD, are used to program various shutdown modes. If SA is set to Logic 1, all DACs are placed in shutdown mode. If SA = 0 and SD = 1, a corresponding DAC is shutdown addressed by Bit A0 and Bit A1 (see the Input Registers section). Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new data to the target DAC register, determined by the decoding of Address Bit A1 and Address Bit A0. For the AD7398, Table 5, Table 6, the Input Registers section, Figure 3, and Figure 4 define the characteristics of the serial interface. For the AD7399, Table 5, Table 6, the Input Registers section, and Figure 4 (with a 14-bit exception) define the characteristics of the serial interface. Figure 27 and Figure 28 show the equivalent logic interface for the key digital control pins for AD7398 and AD7399. An asynchronous RS provides hardware control reset to zerocode state over the preset function and DAC register loading. If this function is not needed, the RS pin can be tied to logic high. TO INPUT REGISTER CS ADDRESS DECODER WORST CASE ACCURACY VOUT VREF VFSE VZSE INL 2N D EN CLK SHIFT REGISTER 02179-027 Assuming a perfect reference, the worst-case output voltage can be calculated from the following equation: SDI (3) where: D = decimal code loaded to DAC ranges 0 ≤ D ≤ 2N–1. N = number of bits. VREF = applied reference voltage. VFSE = full-scale error in volts. VZSE = zero-scale error in volts. INL = integral nonlinearity in volts. INL is 0 at full scale or zero scale. Rev. C | Page 15 of 24 A B C D Figure 27. Equivalent Logic Interface AD7398/AD7399 68HC11/68L11 to AD7398/AD7399 Interface When the VDD power supply is turned on, an internal reset strobe forces all the input and DAC registers to the zero-code state. The VDD power supply should have a smooth positive ramp without drooping in order to have consistent results, especially in the region of VDD = 1.5 V to 2.2 V. The VSS supply has no effect on the power-on reset performance. The DAC register data stays at zero until a valid serial register data load takes place. Figure 30 shows a serial interface between the AD7398/AD7399 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/ 68L11 drives the CLK of the DAC, and the MOSI output drives the serial data lines SDI. CS signal is driven from one of the port lines. The 68HC11/68L11 are configured for master mode; MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI output is valid on the rising edge of SCK. AD7398/ AD7399 68HC11/ 68L111 ESD Protection Circuits All logic input pins contain back-biased ESD protection Zeners connected to ground (GND) and VDD as shown in Figure 28. PC6 LDAC PC7 CS MOS1 SDI SCK CLK VDD 1ADDITIONAL DIGITAL INPUTS 5kΩ 02179-028 Figure 30. 68HC11/68L11 to AD7398/AD7399 Interface MICROWIRE™ to AD7398/AD7399 Interface MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD7398/AD7399 is via a serial bus that uses standard protocol compatible with DSP processors and microcontrollers. The communications channel requires a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD7398/AD7399 require a 16-bit/14-bit data word with data valid on the rising edge of CLK. The DAC update can be done automatically when all the data is clocked in, or it can be done under control of LDAC. Figure 31 shows an interface between the AD7398/AD7399 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD7398/ AD7399 on the rising edge of the serial clock. No glue logic is required as the DAC clocks data into the input shift register on the rising edge. MICROWIRE1 Figure 29 shows a serial interface between the AD7398/AD7399 and the ADSP-2101. The ADSP-2101 is set to operate in the serial port (SPORT) transmit alternate framing mode. The ADSP-2101 is programmed through the SPORT control register and should be configured as follows: Internal clock operation, active low framing, 16-bit-word length. For the AD7398, transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. For the AD7399, the first two bits are don’t care as the AD7399 keeps the last 14 bits. Similarly, transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. Because of the edge-triggered difference, an inverter is required at the SCLKs between the DSP and the DAC. DT SDI SCLK 1ADDITIONAL CLK PINS OMITTED FOR CLARITY. A serial interface between the AD7398/AD7399 and the 80C51/ 80L51 microcontroller is shown in Figure 32. TxD of the microcontroller drives the CLK of the AD7398/AD7399, and RxD drives the serial data line of the DAC. P3.3 is a bit-programmable pin on the serial port that is used to drive CS. AD7398/ AD7399 80C51/ 80L511 P3.4 LDAC P3.3 CS RxD SDI TxD CLK 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 32. 80C51/80L51 to AD7398/AD7399 Interface CLK PINS OMITTED FOR CLARITY. SDI 80C51/80L51 to AD7398/AD7399 Interface LDAC CS SO Figure 31. MICROWIRE to AD7398/AD7399 Interface 02179-029 FO CS 1ADDITIONAL AD7398/ AD7399 TFS CS SCK ADSP-2101 to AD7398/AD7399 Interface AD7398/ AD7399 02179-031 Figure 28. Equivalent ESD Protection Circuits 02179-032 GND ADSP-21011 PINS OMITTED FOR CLARITY. 02179-030 POWER-ON RESET Figure 29. ADSP-2101 to AD7398/AD7399 Interface Rev. C | Page 16 of 24 AD7398/AD7399 Note that the 80C51/80L51 provide the LSB first, although the AD7398/AD7399 expect the MSB of the 16-bit/14-bit word first. Care should be taken to ensure the transmit routine takes this into account. This can usually be done with software by shifting out and accumulating the bits in the correct order before inputting to the DAC. In addition, 80C51 outputs two byte words/16 bits of data. Thus for AD7399, the first two bits, after rearrangement, should be don’t care as they are dropped from the 14-bit word of the AD7399. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the DAC clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 transmit their data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. As the AD7399 requires a 14-bit word, P3.3 (or any one of the other programmable bits) is the CS input signal to the DAC; therefore P3.3 should be brought low at the beginning of the 16-bit write cycle 2 × 8 bit-words, and held low until the 16-bit 2 × 8 cycle is completed. After that, P3.3 is brought high again and the new data loads to the DAC. Again, the first two bits, after rearranging, should be don’t care. LDAC on the AD7398/AD7399 can also be controlled by the 80C51/80L51 serial port output by using another bit-programmable pin, P3.4. Rev. C | Page 17 of 24 AD7398/AD7399 APPLICATIONS INFORMATION STAIRCASE WINDOWS COMPARATOR VTEST Many applications need to determine whether voltage levels are within predetermined limits. Some requirements are for nonoverlapping windows and others for overlapping windows. Both circuit configurations are shown in Figure 33 and Figure 34, respectively. + AD7398/ AD7399 VOUTC VREF C – VOUTA + V+ 10kΩ WINDOW 2 – + – 1/2 AD8564 + VREF A – WINDOW 1 – VDD VOUTB VREF B 10kΩ + WINDOW 1 + VOUTA VREF A V+ AD8564 10kΩ – VDD VTEST VREF V+ AD8564 VREF V+ GND 10kΩ + VOUTD VREF D WINDOW 2 – + V+ 10kΩ WINDOW 3 – + – Figure 35. Overlapping Windows Comparator V+ AD8564 VREF 10kΩ + WINDOW 3 – VOUTB – VREF C VOUTC WINDOW 2 V+ VOUTD 10kΩ + VOUTC WINDOW 4 – GND + 1/2 AD8564 VOUTD V+ 10kΩ + WINDOW 5 – GND + 02179-033 – The nonoverlapping circuit employs one AD7398/AD7399 and ten comparators to achieve five voltage windows. These windows range between VREF and analog ground as shown in Figure 34. Similarly, the overlapping circuit employs six comparators to achieve three overlapping windows (see Figure 36). Figure 33. Nonoverlapping Windows Comparator VREF WINDOW 1 VOUTA VOUTB WINDOW 2 WINDOW 3 VOUTC GND WINDOW 5 02179-034 WINDOW 4 VOUTD WINDOW 3 Figure 36. Overlapping Windows Range – VREF D WINDOW 1 VOUTA + 02179-036 VOUTB VREF B 02179-035 – + AD7398/ AD7399 Figure 34. Nonoverlapping Windows Range Rev. C | Page 18 of 24 AD7398/AD7399 PROGRAMMABLE DAC REFERENCE VOLTAGE Table 7. VREFX vs. R1 and R2 With the flexibility of the AD7398/AD7399, one of the internal DACs can be used to control a common programmable VREFX for the remainder of the DACs. R1, R2 R1 = R2 R1 = R2 R1 = R2 R1 = 3R2 R1 = 3R2 R1 = 3R2 The circuit configuration is shown in Figure 37. The relationship of VREFX to VREF is dependent upon the digital code and the ratio of R1 and R2, and is given by R2 D R2 VREFX = VREF × 1 + − VREFX × N × R1 2 R1 VREFX (5) where: D = decimal equivalent of input code. N = number of bits. VREF = applied external reference. VREFX = reference voltage for DAC A to DAC D. AD7398/AD7399 VREF A VOUTA R2 ±0.1% R1 ±0.1% VREF DAC A VIN VREF B ADR293 VOUTB DAC B VREF C VOUTC DAC C TO OTHER COMPONENTS VOUTD 02179-037 VREF D VREFX 2 VREF 1.3 VREF VREF 4 VREF 1.6 VREF VREF The accuracy of VREFX is affected by the quality of R1 and R2. Therefore, tight tolerance, low tempco, thin film resistors should be used. (4) R2 VREF × 1 + R1 = D R2 1 + N × R1 2 Digital Code 0000 0000 0000 1000 0000 0000 1111 1111 1111 0000 0000 0000 1000 0000 0000 1111 1111 1111 DAC D Figure 37. Programmable DAC Reference Rev. C | Page 19 of 24 AD7398/AD7399 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 8° 0° 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) 03-27-2007-B COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 38. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 39. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. C | Page 20 of 24 0.75 0.60 0.45 AD7398/AD7399 ORDERING GUIDE Model1, 2 AD7398BR AD7398BR-REEL AD7398BRZ AD7398BRZ-REEL AD7398BRU AD7398BRU-REEL7 AD7398BRUZ AD7398BRUZ-REEL7 AD7398WBRUZ-RL7 AD7399BR AD7399BR-REEL AD7399BRZ AD7399BRZ-REEL AD7399BRU AD7399BRU-REEL7 AD7399BRUZ AD7399BRUZ-REEL7 1 2 Resolution (Bits) 12 12 12 12 12 12 12 12 12 10 10 10 10 10 10 10 10 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP Package Option RW-16 RW-16 RW-16 RW-16 RU-16 RU-16 RU-16 RU-16 RU-16 RW-16 RW-16 RW-16 RW-16 RU-16 RU-16 RU-16 RU-16 Ordering Quantity 47 1,000 47 1,000 96 1,000 96 1,000 1,000 47 1,000 47 1,000 96 1,000 96 1,000 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. The AD7398 contains 3254 transistors. The die size measures 108 mils × 144 mils. AUTOMOTIVE PRODUCTS The AD7398WBRUZ-RL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. Rev. C | Page 21 of 24 AD7398/AD7399 NOTES Rev. C | Page 22 of 24 AD7398/AD7399 NOTES Rev. C | Page 23 of 24 AD7398/AD7399 NOTES ©2000–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02179-0-1/11(C) Rev. C | Page 24 of 24