a FEATURES Low Cost Replaces 12 Potentiometers Individually Programmable Outputs 3-Wire SPI Compatible Serial Input Power Shutdown <55 mWatts Including IDD & IREF Midscale Preset, AD8802 Separate VREFL Range Setting, AD8804 +3 V to +5 V Single Supply Operation APPLICATIONS Automatic Adjustment Trimmer Replacement Video and Audio Equipment Gain and Offset Adjustment Portable and Battery Operated Equipment 12 Channel, 8-Bit TrimDACs with Power Shutdown AD8802/AD8804 FUNCTIONAL BLOCK DIAGRAM AD8802/AD8804 CS VREFH CLK DAC 1 D7 D11 D10 D9 D8 D7 DAC REG #1 EN ADDR DEC D0 R SER REG SDI VDD D D0 DAC 12 D7 8 D0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 DAC REG #12 R SHDN GENERAL DESCRIPTION The 12-channel AD8802/AD8804 provides independent digitallycontrollable voltage outputs in a compact 20-lead package. This potentiometer divider TrimDAC® allows replacement of the mechanical trimmer function in new designs. The AD8802/ AD8804 is ideal for dc voltage adjustment applications. Easily programmed by serial interfaced microcontroller ports, the AD8802 with its midscale preset is ideal for potentiometer replacement where adjustments start at a nominal value. Applications such as gain control of video amplifiers, voltage controlled frequencies and bandwidths in video equipment, geometric correction and automatic adjustment in CRT computer graphic displays are a few of the many applications ideally suited for these parts. The AD8804 provides independent control of both the top and bottom end of the potentiometer divider allowing a separate zero-scale voltage setting determined by the VREFL pin. This is helpful for maximizing the resolution of devices with a limited allowable voltage control range. GND RS (AD8802 ONLY) VREFL (AD8804 ONLY) Each DAC has its own DAC latch that holds its output state. These DAC latches are updated from an internal serial-toparallel shift register that is loaded from a standard 3-wire serial input digital interface. The serial-data-input word is decoded where the first 4 bits determine the address of the DAC latches to be loaded with the last 8 bits of data. The AD8802/ AD8804 consumes only 10 µA from 5 V power supplies. In addition, in shutdown mode reference input current consumption is also reduced to 10 µA while saving the DAC latch settings for use after return to normal operation. The AD8802/AD8804 is available in the 20-pin plastic DIP, the SOIC-20 surface mount package, and the 1 mm thin TSSOP-20 package. Internally the AD8802/AD8804 contains 12 voltage-output digital-to-analog converters, sharing a common referencevoltage input. TrimDAC is a registered trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 +3 V 6 10% or +5 V 6 10%, V AD8802/AD8804–SPECIFICATIONS ≤T(V ≤=+858C unless otherwise noted) DD REFH = +VDD, VREFL = 0 V, –408C A Parameter Symbol STATIC ACCURACY Specifications apply to all DACs Resolution Differential Nonlinearity Error Integral Nonlinearity Error Full-Scale Error Zero Code Error DAC Output Resistance Output Resistance Match N DNL INL GFSE VZSE ROUT ∆R/RO REFERENCE INPUT Voltage Range2 REFH Input Resistance REFL Input Resistance 3 Reference Input Capacitance3 VREFH VREFL RREFH RREFL CREF0 CREF1 Conditions Guaranteed Monotonic Pin Available on AD8804 Only Digital Inputs = 55H, VREFH = VDD Digital Inputs = 55H, VREFL = VDD Digital Inputs all Zeros Digital Inputs all Ones Min 8 –1 –1.5 –1 –1 3 Typ1 Max Units ± 1/4 ± 1/2 1/2 1/4 5 1.5 +1 +1.5 +1 +1 8 Bits LSB LSB LSB LSB kΩ % 0 0 VDD VDD 1.2 1.2 32 32 DIGITAL INPUTS Logic High Logic Low Logic High Logic Low Input Current Input Capacitance3 VIH VIL VIH VIL IIL CIL POWER SUPPLIES4 Power Supply Range Supply Current (CMOS) Supply Current (TTL) Shutdown Current Power Dissipation Power Supply Sensitivity VDD Range IDD IDD IREFH PDISS PSRR VIH = VDD or VIL = 0 V VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V SHDN = 0 VIH = VDD or VIL = 0 V, VDD = +5.5 V VDD = +5 V ± 10% 0.01 1 0.2 tS CT ± 1/2 LSB Error Band Between Adjacent Outputs 5 0.6 50 tCH, tCL tDS tDH tCSS tCSW tRS tCSH tCS1 Clock Level High or Low DYNAMIC PERFORMANCE VOUT Settling Time Crosstalk VDD = +5 V VDD = +5 V VDD = +3 V VDD = +3 V VIN = 0 V or + 5 V 2.4 0.8 2.1 0.6 ±1 5 2.7 0.001 5.5 10 4 10 55 0.002 V V kΩ kΩ pF pF V V V V µA pF V µA mA µA µW %/% 3 SWITCHING CHARACTERISTICS 3, 6 Input Clock Pulse Width Data Setup Time Data Hold Time CS Setup Time CS High Pulse Width Reset Pulse Width CLK Rise to CS Rise Hold Time CS Rise to Clock Rise Setup 15 5 5 10 10 90 20 10 µs dB ns ns ns ns ns ns ns ns NOTES 1 Typicals represent average readings at +25°C. 2 VREFH can be any value between GND and V DD, for the AD8804 V REFL can be any value between GND and V DD. 3 Guaranteed by design and not subject to production test. 4 Digital Input voltages V IN = 0 V or VDD for CMOS condition. DAC outputs unloaded. P DISS is calculated from (I DD × VDD). 5 Measured at a VOUT pin where an adjacent VOUT pin is making a full-scale voltage change (f = 100 kHz). 6 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. –2– REV. 0 AD8802/AD8804 PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, + 8 V VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD Digital Input Voltage to GND . . . . . . . . . . . . . . . . . 0 V, +8 V Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Package Power Dissipation . . . . . . . . . . . . (TJ MAX – TA)/θJA Thermal Resistance θJA, SOIC (SOL-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W P-DIP (N-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W TSSOP-20 (RU-20) . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W VREFH 1 20 VDD O1 2 19 RS O1 2 19 O12 O2 3 18 O12 O2 3 18 O11 O3 4 17 O11 O3 4 16 O10 O4 5 O4 5 TOP VIEW 15 O9 (Not to Scale) 14 O8 O6 7 SHDN 8 VREF Common DAC Reference Input 2 O1 DAC Output #1, addr = 00002 3 O2 DAC Output #2, addr = 00012 4 O3 DAC Output #3, addr = 00102 5 O4 DAC Output #4, addr = 00112 6 O5 DAC Output #5, addr = 01002 7 O6 DAC Output #6, addr = 01012 8 SHDN Reference input current goes to zero. DAC latch settings maintained 9 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded based on the address bits and loaded into the target DAC register 13 O7 CS 9 12 SDI GND 10 11 CLK 17 O10 AD8804 16 O9 TOP VIEW 15 O8 (Not to Scale) 14 O7 O6 7 O5 6 SHDN 8 13 SDI CS 9 12 CLK GND 10 11 VREFL AD8804 PIN DESCRIPTIONS Pin Name Description 1 AD8802 O5 6 AD8802 PIN DESCRIPTIONS Pin Name 20 VDD VREFH 1 1 2 3 4 5 6 7 8 VREFH O1 O2 O3 O4 O5 O6 SHDN 9 CS 10 11 12 13 14 15 16 17 18 19 20 GND VREFL CLK SDI O7 O8 O9 O10 O11 O12 VDD Description Common High-Side DAC Reference Input DAC Output #1, addr = 00002 DAC Output #2, addr = 00012 DAC Output #3, addr = 00102 DAC Output #4, addr = 00112 DAC Output #5, addr = 01002 DAC Output #6, addr = 01012 Reference input current goes to zero DAC latch settings maintained Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded based on the address bits and loaded input the target DAC register Ground Common Low-Side DAC Reference Input Serial Clock Input, Positive Edge Triggered Serial Data Input DAC Output #7, addr = 01102 DAC Output #8, addr = 01112 DAC Output #9, addr = 10002 DAC Output #10, addr = 10012 DAC Output #11, addr = 10102 DAC Output #12, addr = 10112 Positive power supply, specified for operation at both +3 V and +5 V 10 GND Ground 11 CLK Serial Clock Input, Positive Edge Triggered 12 SDI Serial Data Input 13 O7 DAC Output #7, addr = 01102 14 O8 DAC Output #8, addr = 01112 15 O9 DAC Output #9, addr = 10002 16 O10 DAC Output #10, addr = 10012 17 O11 DAC Output #11, addr = 10102 18 O12 DAC Output #12, addr = 10112 19 RS Asynchronous Preset to Midscale Output Setting. Loads all DAC Registers with 80H Model FTN Temperature Range Package Description Package Option 20 VDD Positive Power Supply, Specified for Operation at Both +3 V and +5 V AD8802AN AD8802AR AD8802ARU AD8804AN AD8804AR AD8804ARU RS RS RS REFL REFL REFL – 40°C/+85°C – 40°C/+85°C – 40°C/+85°C – 40°C/+85°C – 40°C/+85°C – 40°C/+85°C PDIP-20 SOL-20 TSSOP-20 PDIP-20 SOL-20 TSSOP-20 N-20 R-20 RU-20 N-20 R-20 RU-20 ORDERING GUIDE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE AD8802/AD8804–Typical Performance Characteristics 1 160 VDD = +5V VREFH = +5V VREFL = 0V 0.75 TA = +85°C TA = +25°C TA = –40°C 140 0.5 IREF CURRENT – µA 120 INL – LSB 0.25 0 –0.25 100 80 60 –0.5 40 –0.75 20 0 –1 0 32 64 96 128 160 CODE – Decimal 192 224 0 256 Figure 1. INL vs. Code 32 64 96 128 160 CODE – Decimal 192 224 256 Figure 4. Input Reference Current vs. Code 1 10k VDD = +5V VREFH = +5V VREFL = 0V 0.5 SHUTDOWN CURRENT – nA TA = +85°C TA = +25°C TA = –40°C 0.75 0.25 INL – LSB VDD = +5V VREFH = +2V VREFL = 0V ONE DAC CHANGING WITH CODE, OTHER DACs SET TO 00H TA = +25°C 0 –0.25 –0.5 1k VDD = +5.5V VREF = +5.5V 100 10 VDD = +2.7V VREF = +2.7V –0.75 0 –55 –1 0 32 64 96 128 160 CODE – Decimal 192 224 256 –35 –15 5 25 45 65 TEMPERATURE – °C 85 105 125 Figure 5. Shutdown Current vs. Temperature Figure 2. Differential Nonlinearity Error vs. Code 100k 1600 VDD = +4.5V VREFL = 0V SUPPLY CURRENT – µA TA = +25°C SS = 3600 PCS FREQUENCY VDD = +5.5V VIN = +2.4V 10k VREF = +4.5V 1280 960 640 1k 100 10 VDD = +5.5V VIN = +5.5V 1 0.1 320 0.01 0.001 –55 0 0 0.2 0.4 0.6 0.8 1.0 ABSOLUTE VALUE TOTAL UNADJUSTED ERROR – LSB Figure 3. Total Unadjusted Error Histogram –35 –15 5 25 45 65 TEMPERATURE – °C 85 105 125 Figure 6. Supply Current vs. Temperature –4– REV. 0 AD8802/AD8804 100 SUPPLY CURRENT – mA 10 1.0 OUTPUT2 – 10mV/DIV TA = +25°C ALL DIGITAL INPUTS TIED TOGETHER VDD = +5V 0.1 0.01 VDD = +3V OUTPUT1: OOH → FFH VDD = +5V VREF = +5V f = 1MHz 100 90 10 0% 10mV 0.001 200ns TIME – 0.2µs/DIV 0.0001 0 0.5 3 3.5 2.5 1.5 2 INPUT VOLTAGE – Volts 1 4 4.5 5 Figure 10. Adjacent Channel Clock Feedthrough Figure 7. Supply Current vs. Logic Input Voltage 80 5mV PSRR – dB 60 OUT1 5mV/DIV VDD = +5V ALL OUTPUTS SET TO MIDSCALE (80H) 100 90 OUTPUT1: 7FH → 80H VDD = +5V VREF = +5V 40 CS 5V/DIV 1µs 10 0% 20 5V TIME – 1µs/DIV 0 10 100 1k FREQUENCY – Hz 10k 100k Figure 11. Midscale Transition Figure 8. Power Supply Rejection vs. Frequency 2V CHANGE IN ZERO-SCALE ERROR – LSB 0.01 5µs 6V 100 4V 90 OUT 2V 0V VDD = +5V VREF = +5V 5V CS 10 0% 0V 0% 5V TIME – 5µs/DIV VDD = +4.5V VREF = +4.5V SS = 176 PCS VREFL = 0V 0.005 0 –0.005 –0.01 0 100 200 400 300 HOURS OF OPERATION AT 150°C 500 600 Figure 9. Large-Signal Settling Time Figure 12. Zero-Scale Error Accelerated by Burn-In REV. 0 –5– AD8802/AD8804 1.0 VDD = +4.5V VREF = +4.5V VDD = +4.5V VREF = +4.5V SS = 176 PCS 0.02 x + 2σ x 0 x – 2σ –0.02 –0.04 100 0 400 200 300 HOURS OF OPERATION AT 150°C 500 CODE = 55H INPUT RESISTANCE DRIFT – kΩ CHANGE IN FULL-SCALE ERROR – LSB 0.04 SS = 176 PCS 0.5 x + 2σ x 0 x – 2σ –0.5 –1.0 600 0 100 200 300 400 HOURS OF OPERATION AT 150°C 500 600 Figure 14. REF Input Resistance Accelerated by Burn-In Figure 13. Full-Scale Error Accelerated by Burn-In 1 OPERATION The AD8802/AD8804 provides twelve channels of programmable voltage output adjustment capability. Changing the programmed output voltage of each DAC is accomplished by clocking in a 12-bit serial data word into the SDI (Serial Data Input) pin. The format of this data word is four address bits, MSB first, followed by 8 data bits, MSB first. Table I provides the serial register data word format. The AD8802/AD8804 has the following address assignments for the ADDR decode which determines the location of the DAC register receiving the serial register data in Bits B7 through B0: SDI A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 CLK 0 1 CS DAC REGISTER LOAD 0 +5V VOUT 0V Figure 15a. Timing Diagram DAC# = A3 × 8 + A2 × 4 + A1 × 2 + A0 + 1 DETAIL SERIAL DATA INPUT TIMING (RS = "1") DAC outputs can be changed one at a time in random sequence. The fast serial-data loading of 33 MHz makes it possible to load all 12 DACs in as little time as 4.6 µs (13 × 12 × 30 ns). The exact timing requirements are shown in Figure 15. SDI (DATA IN) 1 AX OR DX AX OR DX 0 tDS tCH 1 tDH tCS1 CLK 0 Table I. Serial-Data Word Format tCSS 1 tCL tCSH tCSW CS ADDR B11 B10 B9 B8 DATA B7 B6 B5 0 B4 B3 B2 B1 B0 tS ±1/2 LSB +5V VOUT A3 A2 A1 MSB 2 11 A0 LSB MSB 2 10 9 2 2 8 7 2 LSB 6 2 2 5 4 2 2 3 2 2 2 1 ±1/2 LSB ERROR BAND 0V D7 D6 D5 D4 D3 D2 D1 D0 Figure 15b. Detail Timing Diagram 0 2 RESET TIMING 1 The AD8802 offers a midscale preset activated by the RS pin simplifying initial setting conditions at first power-up. The AD8804 has both a VREFH and a VREFL pin to establish independent positive full-scale and zero-scale settings to optimize resolution. Both parts offer a power shutdown SHDN which places the DAC structure in a zero power consumption state resulting in only leakage currents being consumed from the power supply and VREF inputs. In shutdown mode the DACX register settings are maintained. When returning to operational mode from power shutdown the DAC outputs return to their previous voltage settings. tRS RS 0 tS +5V ±1 LSB VOUT 2.5V ±1 LSB ERROR BAND Figure 15c. Reset Timing Diagram –6– REV. 0 AD8802/AD8804 PROGRAMMING THE OUTPUT VOLTAGE ladder, while the REFH reference is sourcing current into the DAC ladder. The DAC design minimizes reference glitch current maintaining minimum interference between DAC channels during code changes. The output voltage range is determined by the external reference connected to VREFH and VREFL pins. See Figure 16 for a simplified diagram of the equivalent DAC circuit. In the case of the AD8802 its VREFL is internally connected to GND and therefore cannot be offset. VREFH can be tied to VDD and VREFL can be tied to GND establishing a basic rail-to-rail voltage output programming range. Other output ranges are established by the use of different external voltage references. The general transfer equation which determines the programmed output voltage is: VO (Dx) = (Dx)/256 × (VREFH – VREFL) + VREFL DAC OUTPUTS (O1–O12) The twelve DAC outputs present a constant output resistance of approximately 5 kΩ independent of code setting. The distribution of ROUT from DAC-to-DAC typically matches within ± 1%. However device-to-device matching is process lot dependent having a ± 20% variation. The change in ROUT with temperature has a 500 ppm/°C temperature coefficient. During power shutdown all twelve outputs are open-circuited. Eq. 1 where Dx is the data contained in the 8-bit DACx register. TO OTHER DACS N CH DAC 1 D7 MSB 2R OX D11 D10 D9 D8 D7 R DAC REGISTER DAC REG #1 EN ADDR DEC D0 R SER REG D7 SDI 2R D D0 D7 D6 D0 R .. .. .. VDD VREFH CLK P CH VREFH AD8802/AD8804 CS 8 .. . D0 DAC REG #12 DAC 12 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 R SHDN LSB 2R GND 2R GND VREFL DIGITAL INTERFACING The AD8802/AD8804 contains a standard three-wire serial input control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. Figure 17 block diagram shows more detail of the internal digital circuitry. When CS is taken active low, the clock can load data into the serial register on each positive clock edge, see Table II. For example, when VREFH = +5 V and VREFL = 0 V, the following output voltages will be generated for the following codes: VOx Output State (VREFH = +5 V, VREFL = 0 V) 255 128 1 0 4.98 V 2.50 V 0.02 V 0.00 V Full Scale Half Scale (Midscale Reset Value) 1 LSB Zero Scale VREFL (AD8804 ONLY) Figure 17. Block Diagram Figure 16. AD8802/AD8804 Equivalent TrimDAC Circuit D RS (AD8802 ONLY) Table II. Input Logic Control Truth Table REFERENCE INPUTS (V REFH, VREFL) The reference input pins set the output voltage range of all twelve DACs. In the case of the AD8802 only the VREFH pin is available to establish a user designed full-scale output voltage. The external reference voltage can be any value between 0 and VDD but must not exceed the VDD supply voltage. The AD8804 has access to the VREFL which establishes the zero-scale output voltage, any voltage can be applied between 0 V and VDD. VREFL can be smaller or larger in voltage than VREFH since the DAC design uses fully bidirectional switches as shown in Figure 16. The input resistance to the DAC has a code dependent variation which has a nominal worst case measured at 55H, which is approximately 1.2 kΩ. When VREFH is greater than VREFL, the REFL reference must be able to sink current out of the DAC REV. 0 CS CLK Register Activity 1 0 X P P 1 No effect. Shifts Serial Register One bit loading the next bit in from the SDI pin. Clock should be high when the CS returns to the inactive state. P = Positive Edge, X = Don’t Care. The data setup and data hold times in the specification table determine the data valid time requirements. The last 12 bits of the data word entered into the serial register are held when CS returns high. At the same time CS goes high it gates the address decoder which enables one of the twelve positive-edge triggered DAC registers, see Figure 18 detail. –7– AD8802/AD8804 +5V DAC 1 CS .. . DAC 2 ADDR DECODE VDD DAC 12 AD8802/ AD8804 + 10µF SERIAL REGISTER CLK SDI 0.1µF DGND Figure 18. Equivalent Control Logic The target DAC register is loaded with the last eight bits of the serial data-word completing one DAC update. Twelve separate 12-bit data words must be clocked in to change all twelve output settings. All digital inputs are protected with a series input resistor and parallel Zener ESD structure shown in Figure 19. Applies to digital input pins CS, SDI, RS, SHDN, CLK 1kΩ LOGIC Figure 19. Equivalent ESD Protection Circuit Digital inputs can be driven by voltages exceeding the AD8802/ AD8804 VDD supply value. This allows 5 V logic to interface directly to the part when it is operated at 3 V. Figure 21. Recommended Supply Bypassing for the AD8802/AD8804 Buffering the AD8802/AD8804 Output In many cases, the nominal 5 kΩ output impedance of the AD8802/AD8804 is sufficient to drive succeeding circuitry. If a lower output impedance is required, an external amplifier can be added. Several examples are shown in Figure 22. One amplifier of an OP291 is used as a simple buffer to reduce the output resistance of DAC A. The OP291 was chosen primarily for its rail-to-rail input and output operation, but it also offers operation to less than 3 V, low offset voltage, and low supply current. The next two DACs, B and C, are configured in a summing arrangement where DAC C provides the coarse output voltage setting and DAC B can be used for fine adjustment. The insertion of R1 in series with DAC B attenuates its contribution to the voltage sum node at the DAC C output. APPLICATIONS Supply Bypassing +5V Precision analog products, such as the AD8802/AD8804, require a well filtered power source. Since the AD8802/AD8804 operate from a single +3 V to +5 V supply, it seems convenient to simply tap into the digital logic power supply. Unfortunately, the logic supply is often a switch-mode design, which generates noise in the 20 kHz to 1 MHz range. In addition, fast logic gates can generate glitches hundred of millivolts in amplitude due to wiring resistances and inductances. VREFH VDD OP291 VH VL SIMPLE BUFFER 0V TO 5V VH VL R1 100kΩ VH VL If possible, the AD8802/AD8804 should be powered directly from the system power supply. This arrangement, shown in Figure 20, will isolate the analog section from the logic switching transients. Even if a separate power supply trace is not available, however, generous supply bypassing will reduce supply-line induced errors. Local supply bypassing consisting of a 10 µF tantalum electrolytic in parallel with a 0.1 µF ceramic capacitor is recommended (Figure 21). SUMMER CIRCUIT WITH FINE TRIM ADJUSTMENT AD8802/ AD8804 VREFL GND DIGITAL INTERFACING OMITTED FOR CLARITY Figure 22. Buffering the AD8802/AD8804 Output Increasing Output Voltage Swing TTL/CMOS LOGIC CIRCUITS + 10µF TANT 0.1µF AD8802/ AD8804 +5V POWER SUPPLY An external amplifier can also be used to extend the output voltage swing beyond the power supply rails of the AD8802/AD8804. This technique permits an easy digital interface for the DAC, while expanding the output swing to take advantage of higher voltage external power supplies. For example, DAC A of Figure 23 is configured to swing from –5 V to +5 V. The actual output voltage is given by: Figure 20. Use Separate Traces to Reduce Power Supply Noise ( ) R VOUT = 1 + F × D × 5 V – 5 V RS 256 where D is the DAC input value (i.e., 0 to 255). This circuit can be combined with the “fine/coarse” circuit of Figure 22 if, for example, a very accurate adjustment around 0 V is desired. –8– REV. 0 AD8802/AD8804 RS 100kΩ +5V +5V 0.1µF +5V VREFH VDD RF 100kΩ –5V TO +4.98V A VDD VREFH OP191 –5V AD8802/ AD8804 SBUF +12V SHIFT CLOCK RxD P3.0 TxD P1.2 P1.1 VREFL 100kΩ AD8804 ONLY PORT 1 1.3 1.2 1.1 AD8802 SDI O1 P3.1 P1.3 8051 µC 0V TO +10V GND SERIAL DATA SHIFT REGISTER OP193 B 10µF SCLK RESET SHDN O12 CS GND 100kΩ Figure 24. Interfacing the 8051 µ C to an AD8802/AD8804, Using the Serial Port Figure 23. Increasing Output Voltage Swing DAC B of Figure 24 is in a noninverting gain of two configurations, which increases the available output swing to +10 V. The feedback resistors can be adjusted to provide any scaling of the output voltage, within the limits of the external op amp power supplies. Software for the 8051 Interface Microcomputer Interfaces The subroutine begins by setting appropriate bits in the Serial Control register to configure the serial port for Mode 0 operation. Next the DAC’s Chip Select input is set low to enable the AD8802/AD8804. The DAC address is obtained from memory location DAC_ADDR, adjusted to compensate for the 8051’s serial data format, and moved to the serial buffer register. At this point, serial data transmission begins automatically. When all 8 bits have been sent, the Transmit Interrupt bit is set, and the subroutine then proceeds to send the DAC value stored at location DAC_VALUE. Finally the Chip Select input is returned high, causing the appropriate AD8802/AD8804 output voltage to change, and the subroutine ends. A software for the AD8802/AD8804 to 8051 interface is shown in Listing 1. The routine transters the 8-bit data stored at data memory location DAC_VALUE to the AD8802/AD8804 DAC addressed by the contents of location DAC_ADDR. The AD8802/AD8804 serial data input provides an easy interface to a variety of single-chip microcomputers (µCs). Many µCs have a built-in serial data capability that can be used for communicating with the DAC. In cases where no serial port is provided, or it is being used for some other purpose (such as an RS-232 communications interface), the AD8802/AD8804 can easily be addressed in software. Twelve data bits are required to load a value into the AD8802/ AD8804 (4 bits for the DAC address and 8 bits for the DAC value). If more than 12 bits are transmitted before the Chip Select input goes high, the extra (i.e., the most-significant) bits are ignored. This feature is valuable because most µCs only transmit data in 8-bit increments. Thus, the µC will send 16 bits to the DAC instead of 12 bits. The AD8802/AD8804 will only respond to the last 12 bits clocked into the SDI port, however, so the serial data interface is not affected. The 8051 sends data out of its shift register LSB first, while the AD8802/AD8804 require data MSB first. The subroutine therefore includes a BYTESWAP subroutine to reformat the data. This routine transfers the MSB-first byte at location SHIFT1 to an LSB-first byte at location SHIFT2. The routine rotates the MSB of the first byte into the carry with a Rotate Left Carry instruction, then rotates the carry into the MSB of the second byte with a Rotate Right Carry instruction. After 8 loops, SHIFT2 contains the data in the proper format. An 8051 µC Interface A typical interface between the AD8802/AD8804 and an 8051 µC is shown in Figure 24. This interface uses the 8051’s internal serial port. The serial port is programmed for Mode 0 operation, which functions as a simple 8-bit shift register. The 8051’s Port 3.0 pin functions as the serial data output, while Port 3.1 serves as the serial clock. The BYTESWAP routine in Listing 1 is convenient because the DAC data can be calculated in normal LSB form. For example, producing a ramp voltage on a DAC is simply a matter of repeatedly incrementing the DAC_VALUE location and calling the LD_8802 subroutine. When data is written to the Serial Buffer Register (SBUF, at Special Function Register location 99H), the data is automatically converted to serial format and clocked out via Port 3.0 and Port 3.1. After 8 bits have been transmitted, the Transmit Interrupt flag (SCON.1) is set and the next 8 bits can be transmitted. If the µC’s hardware serial port is being used for other purposes, the AD8802/AD8804 DAC can be loaded by using the parallel port. A typical parallel interface is shown in Figure 25. The serial data is transmitted to the DAC via the 8051’s Port 1.6 output, while Port 1.6 acts as the serial clock. The AD8802 and AD8804 require the Chip Select to go low at the beginning of the serial data transfer. In addition, the SCLK input must be high when the Chip Select input goes high at the end of the transfer. The 8051’s serial clock meets this requirement, since Port 3.1 both begins and ends the serial data in the high state. REV. 0 Software for the interface of Figure 25 is contained in Listing 2. The subroutine will send the value stored at location DAC_VALUE to the AD8802/AD8804 DAC addressed by location DAC_ADDR. The program begins by setting the AD8802/AD8804’s Serial Clock and Chip Select inputs high, then setting Chip Select low –9– AD8802/AD8804 ; ; This subroutine loads an AD8802/AD8804 DAC from an 8051 microcomputer, ; using the 8051’s serial port in MODE 0 (Shift Register Mode). ; The DAC value is stored at location DAC_VAL ; The DAC address is stored at location DAC_ADDR ; ; Variable declarations ; PORT1 DATA 90H DAC_VALUE DATA 40H DAC_ADDR DATA 41H SHIFT1 DATA 042H SHIFT2 DATA 043H SHIFT_COUNT DATA 44H ; ORG 100H DO_8802: CLR SCON.7 CLR SCON.6 CLR SCON.5 CLR SCON.1 ORL PORT1.1,#00001110B CLR PORT1.1 MOV SHIFT1,DAC_ADDR ACALL BYTESWAP MOV SBUF,SHIFT2 ADDR_WAIT: JNB SCON.1,ADDR_WAIT CLR SCON.1 MOV SHIFT1,DAC_VALUE ACALL BYTESWAP MOV SBUF,SHIFT2 VALU_WAIT: JNB SCON.1,VALU_WAIT CLR SCON.1 SETB PORT1.1 RET ; BYTESWAP: MOV SHIFT_COUNT,#8 SWAP_LOOP: MOV A,SHIFT1 RLC A MOV SHIFT1,A MOV A,SHIFT2 RRC A MOV SHIFT2,A DJNZ SHIFT_COUNT,SWAP_LOOP RET END ;SFR register for port 1 ;DAC Value ;DAC Address ;high byte of 16-bit answer ;low byte of answer ; ;arbitrary start ;set serial ;data mode 0 ;clr transmit flag ;/RS, /SHDN, /CS high ;set the /CS low ;put DAC value in shift register ; ;send the address byte ;wait until 8 bits are sent ;clear the serial transmit flag ;send the DAC value ; ; ;wait again ;clear serial flag ;/CS high, latch data ; into AD8801 ;Shift 8 bits ;Get source byte ;Rotate MSB to carry ;Save new source byte ;Get destination byte ;Move carry to MSB ;Save ;Done? Listing 1. Software for the 8051 to AD8802/AD8804 Serial Port Interface +5V VDD 8051 µC AD8804 P1.7 P1.6 P1.5 P1.4 PORT 1 1.7 1.6 1.5 1.4 VREFH SDI O1 CLK CS O12 SHDN GND VREFL Figure 25. An AD8802/AD8804-8051 µ C Interface Using Parallel Port 1 to start the serial interface process. The DAC address is loaded into the accumulator and four Rotate Right shifts are performed. This places the DAC address in the 4 MSBs of the accumulator. The address is then sent to the AD8802/AD8804 via the SEND_SERIAL subroutine. Next, the DAC value is loaded into the accumulator and sent to the AD8802/AD8804. Finally, the Chip Select input is set high to complete the data transfer Unlike the serial port interface of Figure 24, the parallel port interface only transmits 12 bits to the AD8802/AD8804. Also, the BYTESWAP subroutine is not required for the parallel interface, because data can be shifted out MSB first. However, the results of the two interface methods are exactly identical. In most cases, the decision on which method to use will be determined by whether or not the serial data port is available for communication with the AD8802/AD8804. –10– REV. 0 AD8802/AD8804 ; This 8051 µC subroutine loads an AD8802 or AD8804 DAC with an 8-bit value, ; using the 8051’s parallel port #1. ; The DAC value is stored at location DAC_VALUE ; The DAC address is stored at location DAC_ADDR ; ; Variable declarations PORT1 DATA 90H DAC_VALUE DATA 40H DAC_ADDR DATA 41H LOOPCOUNT DATA 43H ; ORG 100H LD_8804: ORL PORT1,#11110000B CLR PORT1.5 MOV LOOPCOUNT,#4 MOV A,DAC_ADDR RR A RR A RR A RR A ACALL SEND_SERIAL MOV LOOPCOUNT,#8 MOV A,DAC_VALUE ACALL SEND_SERIAL SETB PORT1.5 RET SEND_SERIAL: RLC MOV CLR SETB DJNZ RET; END A PORT1.7,C PORT1.6 PORT1.6 LOOPCOUNT,SEND_SERIAL ;SFR register for port 1 ;DAC Value ;DAC Address (0 through 7) ;COUNT LOOPS ;arbitrary start ;set CLK, /CS and /SHDN high ;Set Chip Select low ;Address is 4 bits ;Get DAC address ;Rotate the DAC ;address to the Most ;Significant Bits (MSBs) ; ;Send the address ;Do 8 bits of data ;Send the data ;Set /CS high ;DONE ;Move next bit to carry ;Move data to SDI ;Pulse the ;CLK input ;Loop if not done Listing 2. Software for the 8051 to AD8802/AD8804 Parallel Port Interface An MC68HC11-to-AD8802/AD8804 Interface Like the 8051 µC, the MC68HC11 includes a dedicated serial data port (labeled SPI). The SPI port provides an easy interface to the AD8802/AD8804 (Figure 27). The interface uses three lines of Port D for the serial data, and one or two lines from Port C to control the SHDN and RS (AD8802 only) inputs. AD8802/ AD8804* MC68HC11* (PD3) MOSI SDI (PD4) SCK CLK (PD5) SS CS PC0 SHDN PC1 RS (AD8802 ONLY) A software routine for loading the AD8802/AD8804 from a 68HC11 evaluation board is shown in Listing 3. First, the MC68HC11 is configured for SPI operation. Bits CPHA and CPOL define the SPI mode wherein the serial clock (SCK) is high at the beginning and end of transmission, and data is valid on the rising edge of SCK. This mode matches the requirements of the AD8802/AD8804. After the registers are saved on the stack, the DAC value and address are transferred to RAM and the AD8802/AD8804’s CS is driven low. Next, the DAC’s address byte is transferred to the SPDR register, which automatically initiates the SPI data transfer. The program tests the SPIF bit and loops until the data transfer is complete. Then the DAC value is sent to the SPI. When transmission of the second byte is complete, CS is driven high to load the new data and address into the AD8802/AD8804. *ADDITIONAL PINS OMITTED FOR CLARITY Figure 26. An AD8802/AD8804-to-MC68HC11 Interface REV. 0 –11– AD8802/AD8804 * * AD8802/AD8804 to M68HC11 Interface Assembly Program * * M68HC11 Register definitions * PORTC EQU $1003 Port C control register * “0,0,0,0;0,0,RS/, SHDN/” DDRC EQU $1007 Port C data direction PORTD EQU $1008 Port D data register * “0,0,/CS,CLK;SDI,0,0,0” DDRD EQU $1009 Port D data direction SPCR EQU $1028 SPI control register * “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0” SPSR EQU $1029 SPI status register * “SPIF,WCOL,0,MODF;0,0,0,0” SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * SDI RAM variables: SDI1 is encoded from 0H to 7H * SDI2 is encoded from 00H to FFH * AD8802/AD8804 requires two 8-bit loads; upper 4 bits * of SDI1 are ignored. AD8802/AD8804 address bits in last * four LSBs of SDI1. * SDI1 EQU $00 SDI packed byte 1 “0,0,0,0;A3,A2,A1,A0” SDI2 EQU $01 SDI packed byte 2 “DB7–DB4;DB3–DB0” * * Main Program * ORG $C000 Start of user’s RAM in EVB INIT LDS #$CFFF Top of C page RAM * * Initialize Port C Outputs * LDAA #$03 0,0,0,0;0,0,1,1 * /RS-Hi, /SHDN-Hi STAA PORTC Initialize Port C Outputs LDAA #$03 0,0,0,0;0,0,1,1 STAA DDRC /RS and /SHDN are now enabled as outputs * * Initialize Port D Outputs * LDAA #$20 0,0,1,0;0,0,0,0 * /CS-Hi,/CLK-Lo,SDI-Lo STAA PORTD Initialize Port D Outputs LDAA #$38 0,0,1,1;1,0,0,0 STAA DDRD /CS,CLK, and SDI are now enabled as outputs * * Initialize SPI Interface * LDAA #$53 STAA SPCR SPI is Master,CPHA=0,CPOL=0,Clk rate=E/32 * * Call update subroutine * BSR UPDATE Xfer 2 8-bit words to AD8402 JMP $E000 Restart BUFFALO * * Subroutine UPDATE * UPDATE PSHX Save registers X, Y, and A PSHY PSHA * * Enter Contents of SDI1 Data Register –12– REV. 0 AD8802/AD8804 * LDAA STAA $0000 SDI1 Hi-byte data loaded from memory SDI1 = data in location 0000H * * Enter Contents of SDI2 Data Register * LDAA $0001 Low-byte data loaded from memory STAA SDI2 SDI2 = Data in location 0001H * LDX #SDI1 Stack pointer at 1st byte to send via SDI LDY #$1000 Stack pointer at on-chip registers * * Reset AD8802 to one-half scale (AD8804 does not have a Reset input) * BCLR PORTC,Y $02 Assert /RS BSET PORTC,Y $02 De-Assert /RS * * Get AD8802/04 ready for data input * BCLR PORTD,Y $02 Assert /CS * TFRLP LDAA 0,X Get a byte to transfer for SPI STAA SPDR Write SDI data reg to start xfer * WAIT LDAA SPSR Loop to wait for SPIF BPL WAIT SPIF is the MSB of SPSR * INX Increment counter to next byte for xfer CPX #SDI2+1 Are we done yet ? BNE TFRLP If not, xfer the second byte * * Update AD8802 output * BSET PORTD,Y $20 Latch register & update AD8802 * PULA When done, restore registers X, Y & A PULY PULX RTS ** Return to Main Program ** Listing 3. AD8802/AD8804 to MC68HC11 Interface Program Source Code An Intelligent Temperature Control System—Interfacing the 8051 mC with the AD8802/AD8804 and TMP14 Connecting the 80CL51 µC, or any modern microcontroller, with the TMP14 and AD8802/AD8804 yields a powerful temperature control tool, as shown in Figure 27. For example, the 80CL51 µC controls the TrimDACs allowing the user to automatically set the temperature setpoints voltages of the TMP14 via computer or touch pad, while the TMP14 senses the temperature and outputs four open-collector trip-points. Feeding these trip-point outputs back to the 80CL51 µC allow it to sense whether or not a setpoint has been exceeded. Additional 80CL51 µC port pins or TMP14 trip-point outputs may then be used to change fan speed (i.e., high, medium, low, off), or increase/decrease the power level to a heater. (Please refer to the TMP14 data sheet for more applications information.) The CS (Chip Select) on the AD8802/AD8804 makes applications that call for large temperature sensor arrays possible. In addition, the 12 channels of the AD8802/AD8804 allow independent setpoint control for all four trip-point outputs on up to three TMP14 temperature sensors. For example, assume that the 80CL51 µC has eight free port pins available after all user REV. 0 interface lines, interrupts, and the serial port lines have been assigned. The eight port pins may be used as chip selects, in which case an array of eight AD8802/AD8804s controlling twenty-four TMP14 sensors is possible. The AD8802/AD8804 and TMP14 are also ideal choices for low power applications. These devices have power shutdown modes and operate on a single 5 Volt supply. When their shutdown modes are activated current consumption is reduced to less than 35 µA. However, at high operating frequencies (12 MHz) the 80CL51 consumes far more energy (18 mA typ) than the AD8802/AD8804 and TMP14 combined. Therefore, to achieve a low power design the 80CL51 should operate at its lowest possible frequency or be placed in its power-down mode at the end of each instruction sequence. To use the power-down mode of the 80CL51 µC set PCON.1 as the last instruction executed prior to going into the powerdown mode. If INT2 and INT9 are enabled, the 80CL51 µC can be awakened from power-down mode with external interrupts. As shown in Figure 28, the TLC555 outputs a pulse every few seconds providing the interrupt to restart the 80CL51 µC which then samples the user input pins, the outputs of the –13– AD8802/AD8804 P0.0 P3.2 P3.1 USER INPUTS P3.0 80CL51 µC O1 CLK SDI O2 O3 SET 1 SET 2 SET 3 SET 4 O4 3 4 4 SLEEP +5V 0.1µF GND TO 3rd TEMP SENSOR IF NEEDED 09–12 +5V VDD 0.1µF SHDN HYS TRIP 1 TRIP 2 TRIP 3 TRIP 4 V+ TO 2nd TEMP SENSOR IF NEEDED 05–8 TO 2nd AD8802/4 ARRAY IF NEEDED P2.0 P2.1 P2.2 P2.3 P2.4 P1.0/INT2 2.5 VREF CS P3.3 P0.7 TMP14 VREFH AD8802/4 10µF GND +5V 0.01µF 3 VCC RS TLC555 DIS OUT THR GND TRIG Figure 27. Temperature Sensor Array with Programmable Setpoints The gain of the SSM2018T is controlled by the voltage at Pin 11. For maximum attenuation of –100 dB a control signal of 3.0 V typ is necessary. The control signal has a scale of –30 mV/dB centered around 0 dB gain for 0 V of control voltage, therefore, for a maximum gain of 40 dB a control voltage of –1.2 volts is necessary. Now notice that the normal +5 V to GND voltage range of the AD8802/AD8804 does not cover the 3.0 V to –1.2 V operational gain control range of the SSM2018T. To cover the operating gain range fully and not exceed the maximum specified power supply rating requires the O1 output of AD8802/AD8804 to be level shifted down. In Figure 28, the level shifting is accomplished by a Zener diode and 1/4 of an OP420 quad op amp. For applications that require only TMP14, and makes the necessary adjustments to the AD8802/ AD8804 before shutting down again. The 80CL51 consumes only 50 µA when operating at 32 kHz, in which case there would be no need for the TLC555, which consumes 1 mW typ. 12 Channel Programmable Voltage Controlled Amplifier The SSM2018T is a trimless Voltage Controlled Amplifier (VCA) for volume control in audio systems. The SSM2018T is the first professional quality audio VCA in the marketplace that does not require an external trimming potentiometer to minimize distortion. The TrimDAC shown in Figure 28 is not being used to trim distortion, but rather to control the gain of the amplifier. In this configuration up to twelve SSM2018T can be digitally controlled. (Please refer to the SSM2018T data sheet for more specifications and applications information.) 18kΩ 50pF VOUT 2 3 1µF 18kΩ 1µF 18kΩ SSM2018T +15V –15V 16 1 +15V OPTIONAL FOR 0 TO 40dB GAIN 15 1.2V 50kΩ 14 4 13 5 12 6 11 7 10 8 9 NC RO 150kΩ OP420A +V AD8802/4 O1 47pF O2– O12 O2 CS O3 TO 8 MORE CHANNELS VREFH VREFL (AD8804 ONLY) REF195 V+ CLK O4–O12 SDI 1µF OUT IN GND +15V GND 3 TO µC Figure 28. 12-Channel Programmable Voltage Controlled Amplifier –14– REV. 0 AD8802/AD8804 +12V VCC R ∆GAIN B ∆GAIN G ∆GAIN 9 13 15 RGB VIDEO INPUT 5 7, 11, 17 43 22 CRT VIDEO AMP 40, 35, 30 LM1204 21 –H SYNC OUTPUT 38, 28, 33 24 BLANK GATE INPUT RGB FEEDBACK CRT CATHODE +4V 20 VCC (+12V) O1 O2 O3 04 O5 O6 O7 VREFH REF195 CS TO µC CLK AD8802/4 0.1µF OUT IN GND 10µF 10µF 0.1µF +12V VCC SDI O1 = 2V O2 = CONTRAST O3 = BP CLAMP WIDTH ADJUST O4 = BLANK LEVEL ADJUST (FOR BRIGHTNESS CONTROL) O5 = R AGAIN O6 = B AGAIN O7 = G AGAIN O8 – O12 = NOT USED Figure 29. A Digitally Controlled LM1204—150 MHz RGB Amplifier System attenuation the optional circuitry inside the dashed box may be removed and replaced with a direct connection from O1 of AD8802/AD8804 to Pin 11 of SSM2018T. between Pins 5 and 7. The input referred noise spectral density is only 1.3 nV√Hz and power consumption is 125 mW at the recommended ± 5 V supplies. When high gain resolution is desired, VREFH and VREFL may be decoupled from the power rails and shifted closer together. This technique increases the gain resolution with the unfortunate penalty of decreased gain range. The decibel gain is “linear in dB,” accurately calibrated, and stable over temperature and supply. The gain is controlled at a high impedance (50 MΩ), low bias (200 nA) differential input; the scaling is 25 mV/dB, requiring a gain-control voltage of only 1 V to span the central 40 dB of the gain range. An overrange and underrange of 1 dB is provided whatever the selected range. The gain-control response time is less than 1 µs for a 40 dB change. The settling time of the AD8802/AD8804 to within a ± 1/2 LSB band is 0.6 µs making it an excellent choice for control of the AD603. A Digitally Controlled LM1204 150 MHz RGB Amplifier System The LM1204 is an industry standard video amplifier system. Figure 29 illustrates a configuration that removes the usual seven level setting potentiometers and replaces them with only one IC. The AD8802/AD8804, in addition to being smaller and more reliable than mechanical potentiometers, has the added feature of digital control. The REF195 is a 5.0 V reference used to supply both the power and reference voltages to the AD8802/AD8804. This is possible because of the high reference output current available (30 mA typical) together with the low power consumption of the AD8802/AD8804. A Low Noise 90 MHz Programmable Gain Amplifier The AD603 is a low noise, voltage-controlled amplifier for use in RF and IF AGC systems. It provides accurate, pin selectable gains of –11 dB to +31 dB with a bandwidth of 90 MHz or +9 dB to +51 dB with a bandwidth of 9 MHz. Any intermediate gain range may be arranged using one external resistor REV. 0 The differential gain-control interface allows the use of either differential or single-ended positive or negative control voltages, where the common-mode range is –1.2 V to 2.0 V. Once again the AD8802/AD8804 is ideally suited to provide the differential input range of 1 V within the common-mode range of 0 V to 2 V. To accomplish this, place VREFH at 2.0 V and VREFL at 1.0 V, then all 256 voltage levels of the AD8804 will fall within the gain-control range of the AD603. Please refer to the AD603 data sheet for further information regarding gain control, layout, and general operation. The dual OP279 is a rail-to-rail op amp used in Figure 30 to drive the inputs VREFH and VREFL because these reference inputs are low impedance (2 kΩ typical). –15– AD8802/AD8804 +10V 0.1µF +10V 0.1µF 0.1µF 8 0.1µF 5 AD603 100Ω 2 4 1 4 2 1 1µF 10µF 1/2 OP279 O1 O2 O3 O4 VDD 2.0V A 20kΩ 7 +5.0V 1/2 OP279 30kΩ 0.1µF 5 OUT GND 10µF 6 AD603 REF195 IN +10V 8 3 7 C2052–10–7/95 6 3 AD8804 VREFH GND SHDN 40kΩ 1.0V VREFL B 10kΩ SDI CLK CS TO µC Figure 30. A Low Noise 90 MHz PGA OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 20-Pin Plastic DIP Package (N-20) 20-Lead SOIC Package (R-20) 1.07 (27.18) MAX 10 PIN 1 0.060 (1.52) 0.015 (0.38) 0.145 (3.683) MAX 0.125 (3.175) MIN 0.011 (0.28) 0.009 (0.23) SEATING 15° PLANE 0 11 1 10 PIN 1 0.011 (0.275) 0.005 (0.125) 0.050 (1.27) BSC 0.107 (2.72) 0.089 (2.26) 0.022 (0.56) 0.014 (0.36) SEATING 0.015 (0.38) PLANE 0.007 (0.18) 8° 0° 0.034 (0.86) 0.018 (0.46) 20-Lead Thin Surface Mount TSSOP Package (RU-20) 0.260 (6.60) 0.252 (6.40) 20 11 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) 0.021 (0.533) 0.11 (2.79) 0.065 (1.66) 0.015 (0.381) 0.09 (2.28) 0.045 (1.15) 20 0.32 (8.128) 0.30 (7.62) 0.135 (3.429) 0.125 (3.17) PRINTED IN U.S.A. 1 0.512 (13.00) 0.496 (12.60) 0.255 (6.477) 0.245 (6.223) 0.419 (10.65) 0.404 (10.00) 11 0.299 (7.60) 0.291 (7.40) 20 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE 10 PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) –16– 8° 0° 0.028 (0.70) 0.020 (0.50) REV. 0