a FEATURES Low Cost Replaces 8 Potentiometers 50 kHz 4-Quadrant Multiplying Bandwidth Low Zero Output Error Eight Individual Channels 3-Wire Serial Input 500 kHz Update Data Loading Rate ±3 V Output Swing Midscale Preset, Zero Volts Out APPLICATIONS Automatic Adjustment Trimmer Replacement Vertical Deflection Amplitude Adjustment Waveform Generation and Modulation GENERAL DESCRIPTION The AD8842 provides eight general purpose digitally controlled voltage adjustment devices. The TrimDAC® capability allows replacement of the mechanical trimmer function in new designs. The AD8842 is ideal for ac or dc gain control of up to 50 kHz bandwidth signals. The four-quadrant multiplying capability is useful for signal inversion and modulation often found in video vertical deflection circuitry. Internally the AD8842 contains eight voltage output digital-toanalog converters, each with separate voltage inputs. A new current conveyor amplifier design performs the four-quadrant multiplying function with a single amplifier at the output of the current steering digital-to-analog converter. This approach offers an improved constant input resistance performance versus previous voltage switched DACs used in TrimDAC circuits, eliminating the need for additional input buffer amplifiers. Each DAC has its own DAC register that holds its output state. These DAC registers are updated from an internal serial-toparallel shift register that is loaded from a standard 3-wire serial input digital interface. Twelve data bits make up the data word clocked into the serial input register. This data word is decoded where the first 4 bits determine the address of the DAC register to be loaded with the last 8 bits of data. A serial data output pin at the opposite end of the serial register allows simple daisy chaining in multiple DAC applications without additional external decoding logic. TrimDAC is a registered trademark of Analog Devices, Inc. The current conveyor amplifier is a patented circuit belonging to Analog Devices, Inc. 8-Bit Octal, 4-Quadrant Multiplying, CMOS TrimDAC AD8842 FUNCTIONAL BLOCK DIAGRAM VIN A DECODED ADDRESS VDD 8 8X 8 4 DAC R E G I S T E R S LOGIC LD DATA 8 SERIAL REGISTER SDI 8 G DAC A VOUT A AD8842 VIN H 8 G DAC H VOUT H CLK GND SDO VSS PR The AD8842 consumes only 95 mW from ± 5 V power supplies. For single 5 V supply applications consult the DAC-8841. The AD8842 is pin compatible with the 1 MHz multiplying bandwidth DAC8840. The AD8842 is available in 24-pin plastic DIP and surface mount SOL-24 packages. R R VIN VOUT VOUT = V IN • (D/128 – 1) Figure 1. Functional Circuit of One 4-Quadrant Multiplying Channel VIN CURRENT CONVEYOR AMPLIFIER REF D 256 R VIN R (1- D) 256 I1 VIN R = V IN VOUT (D/128–1) I2 R Figure 2. Actual Current Conveyor Implementation of Multiplying DAC Channel REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD8842–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (V Parameter Symbol DD = +5 V, VSS = –5 V, All VINx = +3 V, TA = –40°C to +85°C, unless otherwise noted.) Conditions Min STATIC ACCURACY—All Specifications Apply for DACs A, B, C, D, E, F, G, H Resolution N Integral Nonlinearity Error INL Differential Nonlinearity DNL All Devices Monotonic Full-Scale Gain Error GFSE PR = 0, Sets D = 80 H Output Offset VBZE Output Offset Drift TCVBZ PR = 0, Sets D = 80 H VOLTAGE INPUTS—Applies to All Inputs V INx IVR Input Voltage Range 1 Input Resistance RIN Input Capacitance CIN DAC OUTPUTS—Applies to All Outputs V OUTx OVR Voltage Range 1 Output Current IOUT Capacitive Load CL RL = 10 kΩ ∆VOUT < 1.5 LSB No Oscillation DYNAMIC PERFORMANCE—Applies to All DACs GBW VINx = ± 3 V P, RL = 2 kΩ, CL = 10 pF Full Power Gain Bandwidth1 Slew Rate Measured 10% to 90% Positive SR+ ∆VOUTx = +5.5 V Negative SR– ∆VOUTx = –5.5 V Total Harmonic Distortion THD VINx = 4 V p-p, D = FFH, f = 1 kHz, fLPF = 80 kHz, RL = 1 kΩ f = 1kHz, VIN = 0 V Spot Noise Voltage eN ± 1 LSB Error Band, D = 00 H to FFH Output Settling Time tS D = FF H to 00H Measured Between Adjacent Channel-to-Channel Crosstalk CT Channels, f = 100 kHz Digital Feedthrough Q VINx = 0 V, D = 0 to 255 10 POWER SUPPLIES Positive Supply Current Negative Supply Current Power Dissipation 2 Power Supply Rejection Power Supply Range DIGITAL INPUTS Logic High Logic Low Input Current Input Capacitance Input Coding IDD ISS PDISS PSRR PSR PR = 0 V, ∆VDD = ± 5% VDD, |VSS| VOH VOL TIMING SPECIFICATIONS1 Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay DAC Register Load Pulse Width Preset Pulse Width Clock Edge to Load Time Load Edge to Next Clock Edge tCH, tCL tDS tDH tPD tLD tPR tCKLD tLDCK Max ± 0.2 ± 0.4 2 5 5 ±1 ±1 25 Bits LSB LSB LSB mV µV/°C ±4 19 9 V kΩ pF ±3 ±3 ±4 500 V mA pF 10 50 kHz 0.5 1.0 1.0 1.8 0.01 V/µs V/µs % 78 2.9 5.4 nV/√Hz µs µs 72 5 dB nV-s 4.75 10 9 95 0.0001 5.00 14 13 135 0.01 5.25 mA mA mW %/% V 0.8 ± 10 V V µA pF 2.4 7 Offset Binary IOH = –0.4 mA IOL = 1.6 mA Units ±3 12 PR = 0 V PR = 0 V VIH VIL IL CIL DIGITAL OUTPUT Logic High Logic Low 8 Typ 3.5 0.4 60 40 20 80 70 50 30 60 V V ns ns ns ns ns ns ns ns NOTES 1 Guaranteed by design, not subject to production test. 2 Calculated limit = 5 V × (IDD + ISS ). Specifications subject to change without notice. –2– REV. 0 AD8842 1 SDI CLK A3 0 1 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 0 DAC REGISTER LOAD 1 LD D0 0 +3V VOUT 0V DETAIL SERIAL DATA INPUT TIMING (PR = “1”) 1 SDI (DATA IN) 0 Ax or Dx tDS tDH 1 SDO (DATA OUT) 0 CLK tPD tCH 1 0 tCL LD tCKLD tLD 1 0 tLDCK tS +3V VOUT 0V ±1 LSB ±1 LSB ERROR BAND PRESET TIMING PR tPR 1 0 +3V VOUT 0V tS ±1 LSB ±1 LSB ERROR BAND Figure 3. Timing Diagram ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE (TA = +25°C unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V VINx to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD , VSS VOUTx to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD , VSS Short Circuit IOUTx to GND . . . . . . . . . . . . . . . . . Continuous Digital Input & Output Voltage to GND . . . . . . . . . . VDD, 0 V Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature (TJ Max) . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Package Power Dissipation . . . . . . . . . . . . . . . (TJ Max–TA)/θJA Thermal Resistance θJA, SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W Model Temperature Range* AD8842AN XIND AD8842AR XIND Package Option 24-Pin 300mil P-DIP N-24 24-Pin 300mil SOIC SOL-24 *XIND = –40°C to +85°C. The AD8842 contains 2452 transistors. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8842 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 Package Description –3– WARNING! ESD SENSITIVE DEVICE AD8842 PIN CONFIGURATION PIN DESCRIPTION Pin 1 2 3 4 5 6 7 Mnemonic Description VOUTC VOUTB VOUTA VINB VINA GND PR DAC C Output DAC B Output DAC A Output DAC B Reference Input DAC A Reference Input Ground Preset Input, active low, all DAC registers = 80H DAC E Reference Input DAC F Reference Input DAC E Output DAC F Output DAC G Output DAC H Output DAC G Reference Input DAC H Reference Input Load DAC Register Strobe, activehigh input that transfers the data bits from the serial-input register into the decoded DAC register. SDI and CLK inputs are disabled when LD is high. See Tables I and II Serial Clock Input, positive edge triggered Serial Data Output, active totem pole output Negative 5 V Power Supply Serial Data Input Positive 5 V Power Supply DAC D Reference Input DAC C Reference Input DAC D Output 8 9 10 11 12 13 14 15 16 VINE VINF VOUTE VOUTF VOUTG VOUTH VING VINH LD 17 CLK 18 SDO 19 20 21 22 23 24 VSS SDI VDD VIND VINC VOUTD –4– VOUT C 1 24 VOUT D VOUT B 2 23 VINC VOUT A 3 22 VIND VIN B 4 21 VDD VIN A 5 GND 6 PR 7 VIN E 8 VIN F 20 SDI AD8842 19 VSS TOP VIEW 18 SDO (Not to Scale) 17 CLK 9 16 LD VOUT E 10 15 VINH VOUT F 11 14 VING VOUT G 12 13 VINH REV. 0 AD8842 Table I. Serial Input Decode Table LAST LSB D0 FIRST D1 D2 D3 D4 D5 D6 MSB LSB D7 A0 DATA A1 A2 MSB A3 ADDRESS MSB LSB A3 A2 A1 A0 DAC UPDATED 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 NO OPERATION DAC A DAC B DAC C DAC D 1 1 0 0 0 0 0 1 DAC H NO OPERATION 1 1 NO OPERATION 1 MSB 1 • • • • • • LSB D7 D6 D5 D4 D3 D2 D1 D0 DAC OUTPUT VOLTAGE VOUT = (D/128 –1) x VIN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 –V IN (1/128–1) x VIN 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 (127/128–1) x VIN (128/128–1) x VIN = 0V; (PRESET VALUE) (129/128–1) x VIN 1 1 1 1 1 1 0 1 (254/128–1) x VIN (255/128–1) x VIN ≈ VIN • • • • • • 1 1 1 1 1 1 1 1 Table II. Input Logic Control Truth Table CLK LD PR Input Shift Register Operation L ↑ X X X L L L Η H H H L H X No Operation Shift One Bit in from SDI (Pin 20), Shift One Bit* Out from SDO (Pin 18) All DAC Registers = 80H Load Serial Register Data into DAC(X) Register Serial Data Input Register Loading Disabled *Data shifted into the SDI pin appears twelve clocks later at the SDO pin. REV. 0 –5– AD8842–Typical Performance Characteristics 0.4 TA = +25°C VDD = +5V VSS = – 5V VIN X = +3V +1/2 0 DACs E, F, G, H SUPERIMPOSED 0 0.2 0 –0.1 –0.3 64 128 192 DIGITAL INPUT CODE – Decimal VDD = +5V VSS = –5V VIN X = +3V DAC A –0.4 256 0 64 128 192 DIGITAL INPUT CODE – Decimal 2 0 –2 TOTAL HARMONIC DISTORTION – % 20 AVG +2σ 19 AVG 18 AVG –2σ 17 V DD = +4.75V V SS = –4.75V –8 –10 256 –75 –25 0 25 50 75 TEMPERATURE – °C 100 25 50 75 –50 –25 0 TEMPERATURE – °C 100 125 4 VIN = +4Vp-p fLPF = 80kHz CODE = FF H 10 1 0.1 0.01 125 R L = 2kΩ 10 100 1k 10k 3 SR+ SR– 1 0 –75 100k VDD = +4.75V VSS = –4.75V ∆VIN = ±3V 2 –50 –25 0 25 50 75 100 125 TEMPERATURE – °C FREQUENCY – Hz Figure 9. VOUT Slew Rate vs. Temperature Figure 8. Total Harmonic Distortion vs. Frequency Figure 7. Input Resistance (VIN) vs. Temperature VDD = +4.75V VSS = –4.75V Figure 6. VOUT Half Scale (80H) vs. Temperature 0.001 –50 V IN X = –3V –4 100 V IN = +3V V IN X = +3V 4 Figure 5. Linearity Error vs. Digital Code vs. Temperature 21 REFERENCE INPUT RESISTANCE – kΩ TA = –55 °C –0.2 Figure 4. Linearity Error vs. Digital Code 16 –75 TA = +25 °C 0.1 6 VOUT – SLEW RATE – V/µs –1/2 TA = +125 °C V OUT HALF SCALE – mV 0 –1/2 8 0.3 DACs A, B, C, D SUPERIMPOSED LINEARITY ERROR – LSB LINEARITY ERROR – LSB +1/2 1 0 –10 –20 –90 –30 –135 –40 –180 –225 –270 –315 –360 PHASE CODE = ALL ZEROS 15 30 45 60 75 90 105 V IN = ± 100mV T A = +25°C 100k 1M FREQUENCY – Hz 0.8 0.6 0.4 0.2 120 135 10k TA = +25°C VIN = 0V V IN A = 100mVpp V IN B = 0V T A = +25°C en – NOISE VOLTAGE (µV/√Hz) +FS PHASE CODE = ALL ONES INPUT A dB OUTPUT B 0 GAIN – dB PHASE – Degrees 0 –45 –FS CROSSTALK – dB GAIN 10M Figure 10. Gain and Phase vs. Frequency (Code = 00H or FFH) 1k 10k 100k 1M FREQUENCY – Hz Figure 11. DAC Crosstalk vs. Frequency –6– 10M 0 10 100 1k 10k FREQUENCY – Hz 100k Figure 12. Voltage Noise Density vs. Frequency REV. 0 AD8842 5µs 5V 5µs 100 100 90 90 10 10 0% 0% 2V 2V 5µS 5µs Figure 16. Settling Time—Upper Trace LD @ 5 V/Div, Lower Trace VOUT @ 2 V/Div Figure 13. Pulse Response—Upper Trace VIN @ 2 V/Div Lower Trace VOUT @2 V/Div 5V 5µs 10mV 5µs 100 100 90 90 10 10 0% 0% 50mV 2V 50ns 500ns 5µS Figure 17. Digital Feedthrough—VOUT @ 10 mV/Div, VIN = 0 V; Code 7FH to 80H Figure 14. Worst Case 1 LSB Step Change Code 80H to 7FH, Upper Trace LD @ 5 V/Div, Lower Trace VOUT @ 50 mV/Div 5µs 5V 5µs 100 100 90 90 10 10 0% 0% 5mV 2V 5µS 50ns 5mV Figure 15. Crosstalk—VOUT @ 5 mV/Div REV. 0 5µs 2µs Figure 18. Clock Feedthrough—VOUT @ 5 mV/Div –7– AD8842 80 2V –3dB FREQUENCY 60 OUTPUT AMPLITUDE – mV 100 90 40 20 0 –20 10 0% –40 2V 20µs 100 mVp-p INPUT AMPLITUDE –80 –100 0 1 2 3 4 5 FREQUENCY – MHz Figure 19. 10 kHz Sawtooth Waveform, Upper Trace VIN, Lower Trace VOUT Figure 20. AC Sweep Frequency 100 mV p-p Amplitude Response 12 SUPPLY CURRENT – mA OUTPUT AMPLITUDE – mV 300 200 100 0 –100 –200 I DD @ V DD = +6V AND V SS = –5V 11 10 I DD @ V DD = +4V AND V SS = –5V 9 –ISS @ V DD = +5V AND V SS = –4V OR –6V 8 500 mVp-p INPUT AMPLITUDE –300 –400 0 1 2 3 4 POWER SUPPLY REJECTION – dB –3dB FREQUENCY 30 20 –PSRR + PSRR: V DD = +5V±250mV –PSRR: V SS = –5V±250mV 10 V IN X = +3V 7 –75 –50 –25 0 25 50 75 TEMPERATURE – °C 5 FREQUENCY – MHz Figure 21. AC Sweep Frequency 500 mV p-p Amplitude Response 0 100 100 125 1k 10k 100k 1M FREQUENCY – Hz Figure 23. PSRR vs. Frequency Figure 22. Supply Current vs. Voltage and Temperature 6 24 15 12 DATA = ØØ H 0 10 CØ H –12 IOUT – mA AØ H 9Ø H 88 H –24 84 H 82 H –36 81 H 80 H –48 –60 10k 100k 1M FREQUENCY – Hz Figure 24. Gain (VOUT/VIN) and Feedthrough vs. Frequency 5 0 –5 SHORT CIRCUIT CURRENT LIMITING –15 –72 1k SHORT CIRCUIT CURRENT LIMITING –10 T A = +25°C V DD = +5V V SS = –5V 10M –4 –3 –2 VIN = +3V 5 TA = +25°C VDD = +5V VSS = –5V CODE = 80H HALF SCALE OFFSET – mV V IN = 100mV AC GAIN – dB + PSRR 40 –1 0 1 VOUT X – Volts 3 2 1 χ + 2σ 0 χ –1 –2 χ – 2σ –3 –4 –5 2 3 Figure 25. Short Circuit Limit Output Current vs. Voltage –8– 4 4 –6 0 100 200 300 400 500 600 T = HOURS OF OPERATION AT 150°C Figure 26. Output Voltage Drift Accelerated by Burn-In REV. 0 AD8842 can be activated at any time to force the DAC registers to the half-scale code 80H. This is generally the most convenient place to start general purpose adjustment procedures. CIRCUIT OPERATION The AD8842 is a general purpose 8-channel ac or dc signallevel adjustment device designed to replace potentiometers used in the three-terminal connection mode. Eight independent channels of programmable signal level control are available in this 24-pin package device. The outputs are completely buffered providing up to 3 mA of output drive-current to drive external loads. The functional equivalent DAC and amplifier combination shown in Figure 27 produces four-quadrant multiplication of the signal inputs applied to VIN times the digital input control word. In addition the AD8842 provides a 50 kHz full power bandwidth in each four-quadrant multiplying channel. Operating from plus and minus 5 V power supplies, analog inputs and outputs of ± 3 V are easily accommodated. R Achieving 4-Quadrant Multiplying with a Current Conveyor Amplifier The traditional current output CMOS digital-to-analog converter requires two amplifiers to perform the current-to-voltage translation and the half-scale offset to achieve four-quadrant multiplying capability. The circuit shown in Figure 28 shows one such traditional connection. R/2 A1 I1 R REF VIN R/2 VIN CURRENT OUT DAC R VOUT GND A2 VDAC VDAC = D/256 × VIN VOUT = 2 × VDAC – V IN = 2 (D/256) × V IN – V IN = (D/128 – 1) × V IN Figure 28. One Traditional Technique to Achieve FourQuadrant Multiplying with a Complementary Current Output DAC A single new current conveyor amplifier design emulates amplifiers A1 and A2 shown in Figure 28. Figure 29 shows the connection and equations that define this new circuit that achieves four-quadrant multiplication with only one amplifier. AD8842 INPUT-OUTPUT VOLTAGE RANGE 4 D = FFH 2 VOUT – Volts VO I2 D = C0H D = 80H 0 VIN D = 40H CURRENT CONVEYOR AMPLIFIER REF D 256 –2 D = 00H R VREF R (1- D) VREF 256 R I1 VOUT X I2 = V IN –4 VOUT (D/128–1) R –4 –2 0 VIN – Volts 2 4 VOUT = VIN (D/128 – 1), WHERE D = 0 TO 255 Figure 29. Current Conveyor Amplifier Figure 27. Functional Equivalent Circuit to the AD8842 Results in a 4-Quadrant Multiplying Channel Using the equations given in Figure 29 one can calculate the final output equation as follows: In order to simplify use with a controlling microprocessor a PCB space saving three-wire serial data interface was chosen. This interface can be easily adapted to almost all microcomputer and microprocessor systems. A clock (CLK), serial data input (SDI) and a load (LD) strobe pins make up the three-wire interface. The 12-bit input data word used to change the value of the internal DAC registers contains a 4-bit address and 8-bits of data. Using this word combination any DAC register can be changed at a given time without disturbing the other channels. A serial data output SDO pin simplifies cascading multiple AD8842s without adding address decoder chips to the system. –D V IN D V IN V O = – 1 – × × R – 256 × R × R 256 R D D – 1 V IN + ×V IN 256 256 2D = – 1 V IN 256 D = – 1 V IN 128 During system power up a logic low on the preset PR pin forces all DAC registers to 80H which in turn forces all the buffer amplifier outputs to zero volts. This asynchronous input pin PR REV. 0 –9– AD8842 tance. The amplifier output stage can handle shorts to GND; however, care should be taken to avoid continuous short circuit operation. ADJUSTING AC OR DC SIGNAL LEVELS The four-quadrant multiplication operation of the AD8842 is shown in Figure 27. For dc operation the equation describing the relationship between VIN, digital inputs and VOUT is: VOUT(D) = (D/128-1) × VIN (1) where D is a decimal number between 0 and 255 The actual output voltages generated with a fixed 3 V dc input applied to VIN are summarized in this table. Table III. Decimal Input (D) VOUT(D) 0 1 127 128 129 254 255 –3.00 V –2.98 –0.02 0.00 0.02 2.95 2.98 Comments (VIN = 3 V) The low output impedance of the buffers minimizes crosstalk between analog input channels. A graph (Figure 11) of analog crosstalk between channels is provided in the typical performance characteristics section. At 100 kHz 70 dB of channel-tochannel isolation exists. It is recommended to use good circuit layout practice such as guard traces between analog channels and power supply bypass capacitors. A 0.01 µF ceramic in parallel with a 1 µF–10 µF tantalum capacitor provides a good power supply bypass for most frequencies encountered. DIGITAL INTERFACING The four digital input pins (CLK, SDI, LD, PR) of the AD8842 were designed for TTL and 5 V CMOS logic compatibility. The SDO output pin offers good fanout in CMOS logic applications and can easily drive several AD8842s. Inverted FS Zero Output Full Scale (FS) Notice that the output polarity is the same as the input polarity when the DAC register is loaded with 255 (in binary = all ones). Also note that the output does not exactly equal the input voltage. This is a result of the R-2R ladder DAC architecture chosen. When the DAC register is loaded with 0, the output polarity is inverted and exactly equals the magnitude of the input voltage VIN. The actual voltage measured when setting up a DAC in this example will vary within the ±1 LSB linearity error specification of the AD8842. The calculated voltage error would be ±0.023 V (= ± 3 V/128). The Logic Contro Input Truth Table II describes how to shift data into the internal 12-bit serial input register. Note that the CLK is a positive-edge sensitive input. If mechanical switches are used for breadboard evaluation, they should be debounced by a flipflop or other suitable means. The basic three-wire serial data interface setup is shown in Figure 30. ZERO VOLTAGE OUTPUT PRESET AD8842 SERIAL DATA 6 (2) where ω = 2 πf, A = sine wave amplitude, and D = decimal input code. SIGNAL INPUTS (VINA, B, C, D, E, F, G, H) The eight independent VIN inputs have a constant inputresistance nominal value of 19 kΩ as specified in the electrical characteristics table. These signal-inputs are designed to receive not only dc, but ac input voltages. The signal-input voltage range can operate to within one volt of either supply. That is, the operating input-voltage-range is: (3) DAC OUTPUTS (VOUTA, B, C, D, E, F, G, H) The eight D/A converter outputs are fully buffered by the AD8842’s internal amplifier. This amplifier is designed to drive up to 1 kΩ loads in parallel with 100 pF. However, in order to minimize internal device power consumption, it is recommended whenever possible to use larger values of load resis- CLOCK 17 CLK LOAD STROBE 16 LD 19 –5V Figure 30. Basic Three-Wire Serial Interface This transfer characteristic Equation 2 lends itself to amplitude and phase control of the incoming signal VIN. When the DAC is loaded with all zeros, the output sine wave is shifted by 180° with respect to the input sine wave. This powerful multiplying capability can be used for a wide variety of modulation, waveform adjustment and amplitude control. VSS + 1 V < VINx < (VDD – 1 V) 21 +5V 20 SDI If VIN is an ac signal such as a sine wave, then we can use Equation 2 to describe circuit performance. VOUT (t, D) = (D/128-1) × A sin (ωt) 7 PR The required address plus data input format is defined in the serial input decode Table I. Note there are 8 address states that result in no operation (NOP) or activity in the AD8842 when the positive edge triggered load-strobe (LD) is activated. This NOP can be used in cascaded applications where only one DAC out of several packages needs updating. The packages not requiring data changes would receive the NOP address, that is, all zeros. It takes 12 clocks on the CLK pin to fully load the serialinput shift-register. Data on the SDI input pin is subject to the timing diagram (Figure 3) data setup and data hold time requirements. After the twelfth clock pulse the processor needs to activate the LD strobe to have the AD8842 decode the serialregister contents and update the target DAC register with the 8bit data word. This needs to be done before the thirteenth positive clock edge. The timing requirements are provided in the electrical characteristic table and in the Figure 3 timing diagram. After twelve clock edges, data initially loaded into the shift register at SDI appears at the shift register output SDO. A multiple package interface circuit is shown in Figure 31. In this topology all the devices are clocked with the new data; however, only the decoded package address signal updates the target package LD strobe which is being used as a chip select. –10– REV. 0 AD8842 CLOCK Figure 32 shows a three-wire interface for a single AD8842 that easily cascades for multiple packages. This circuit topology often called daisy chaining requires preformating all the serial data for each package in the chain. In the case of the 3 packages shown a 36 bit data word must be completely clocked into all the AD8842 serial data input registers then the LD strobe would transfer the data bits into the DAC registers updating one DAC in each package. LD CLK DATA AD8842 #1 SDI CODED PACKAGE ADDRESS ADDRESSS DECODE LD • • • EN CLK AD8842 #2 SDI µC • • • WR PA0 CLOCK LD CLK DATA PA1 AD8842 #N PA2 LD SDI SDI DAC A CLK ANALOG CONNECTIONS OMITTED FOR CLARITY VOU • AD8842 #1 • • Figure 31. Addressing Multiple AD8842 Packages VO LD There is some digital feedthrough from the digital input pins. Operating the clock only when the DAC registers require updating minimizes the effect of the digital feedthrough on the analog signal channels. Measurements of DAC switch feedthrough shown in the electrical characteristics table were accomplished by grounding the VINx inputs and cycling the data codes between all zeros and all ones. Under this condition 5 nV-s of feedthrough was measured on the output of the switched DAC channel. An adjacent channel measured less than 1 nV-s of digital crosstalk. The digital feedthrough and crosstalk photographs shown in the typical performance characteristics section display these characteristics (Figures 15 and 17). SDO DAC H SDI DAC A CLK AD8842 #2 • LD SDO DAC H SDI DAC A CLK AD8842 #3 • LD SDO DAC H Figure 32. Three-Wire Interface Updates Multiple AD8842s REV. 0 –11– AD8842 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24 13 1 12 C1904–18–4/94 24-Pin Narrow Body Plastic DIP Package 0.280 (7.11) 0.240 (6.10) PIN 1 1.275 (32.30) 1.125 (28.60) 0.325 (8.25) 0.300 (7.62) 0.015 (0.38) MIN 0.210 (5.33) MAX 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.92) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.015 (0.381) 0.008 (0.203) SEATING PLANE 24-Pin Wide Body SOIC Package 24 13 0.2992 (7.60) 0.2914 (7.40) PIN 1 12 1 0.1043 (2.65) 0.0926 (2.35) 0.6141 (15.60) 0.5985 (15.20) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0125 (0.32) 0.0091 (0.23) 0.0291 (0.74) x 45 ° 0.0098 (0.25) 8° 0° 0.0500 (1.27) 0.0157 (0.40) PRINTED IN U.S.A. 0.0118 (0.30) 0.0040 (0.10) 0.4193 (10.65) 0.3937 (10.00) –12– REV. 0