8-Bit, High Bandwidth Multiplying DAC with Serial Interface AD5425 Data Sheet FEATURES GENERAL DESCRIPTION 2.5 V to 5.5 V supply operation 50 MHz serial interface 2.47 MSPS update rate INL of ±0.25 LSB 10 MHz multiplying bandwidth ±10 V reference input Low glitch energy: <2 nV-s Extended temperature range: −40°C to +125°C 10-lead MSOP package Guaranteed monotonic 4-quadrant multiplication Power-on reset with brownout detection LDAC function 0.4 µA typical power consumption The AD5425 1 is a CMOS, 8-bit, current output digital-to-analog converter that operates from a 2.5 V to 5.5 V power supply, making it suitable for battery-powered applications and many other applications. This DAC utilizes a double buffered, 3-wire serial interface that is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP interface standards. An LDAC pin is also provided, which allows simultaneous updates in a multi-DAC configuration. On power-up, the internal shift register and latches are filled with 0s and the DAC outputs are 0 V. As a result of manufacturing on a CMOS submicron process, this DAC offers excellent 4-quadrant multiplication characteristics with large signal multiplying bandwidths of 10 MHz. APPLICATIONS The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor, RFB, provides temperature tracking and full-scale voltage output when combined with an external I-to-V precision amplifier. Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming The AD5425 is available in a small, 10-lead MSOP package. FUNCTIONAL BLOCK DIAGRAM VREF VDD R AD5425 RFB IOUT1 IOUT2 8-BIT R-2R DAC DAC REGISTER LDAC POWER-ON RESET INPUT LATCH CONTROL LOGIC AND INPUT SHIFT REGISTER GND 03161-001 SYNC SCLK SDIN Figure 1. 1 U.S. Patent No. 5,969,657. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved. Powered by TCPDF (www.tcpdf.org) IMPORTANT LINKS for the AD5425* Last content update 10/02/2013 05:42 pm PARAMETRIC SELECTION TABLES Data Converters: Overview of AD54xx Devices Find Similar Products By Operating Parameters AD5450 8-Bit High Bandwidth Multiplying DACs with Serial Interface AD5432 High Bandwidth CMOS 10-Bit Serial Interface Multiplying D/A Converter AD5443 High Bandwidth CMOS 12-Bit Serial Interface Multiplying D/A Converter AD5453 14-Bit High Bandwidth Multiplying DACs with Serial Interface DESIGN COLLABORATION COMMUNITY Collaborate Online with the ADI support team and other designers about select ADI products. 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AD5425 Data Sheet TABLE OF CONTENTS Revision History ............................................................................... 2 Positive Output Voltage ............................................................. 16 Specifications..................................................................................... 3 Adding Gain ................................................................................ 17 Timing Characteristics ..................................................................... 5 DACs Used as a Divider or Programmable Gain Element ... 17 Absolute Maximum Ratings ............................................................ 6 Reference Selection .................................................................... 17 ESD Caution .................................................................................. 6 Amplifier Selection .................................................................... 18 Pin Configuration and Function Descriptions ............................. 7 Serial Interface ............................................................................ 19 Typical Performance Characteristics ............................................. 8 Microprocessor Interfacing ....................................................... 19 Terminology .................................................................................... 13 PCB Layout and Power Supply Decoupling................................ 22 Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 23 Circuit Operation ....................................................................... 14 Ordering Guide .......................................................................... 23 Single-Supply Applications ....................................................... 16 REVISION HISTORY 9/12—Rev. B to Rev. C Change to Features ............................................................................ 1 6/12—Rev. A to Rev. B Deleted ADSP-2103 and changed ADSP-2191 to ADSP-2191M Throughout ............................................................ 19 Deleted Evaluation Board Section and Operating the Evaluation Board Section, deleted Figure 46 to Figure 49, and deleted Table 11 ............................................................................................ 23 Changes to Ordering Guide .......................................................... 23 3/05—Rev. 0 to Rev. A Updated Format ................................................................ Universal Changes to Specifications Section ................................................. 3 Added Figure 18, Figure 20, Figure 21 .......................................10 Change to Table 7 ..........................................................................18 2/04—Revision 0: Initial Version Rev. C | Page 2 of 24 Data Sheet AD5425 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177, ac performance with AD8038, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temperature Coefficient Output Leakage Current REFERENCE INPUT 1 Reference Input Range VREF Input Resistance RFB Resistance Input Capacitance Code Zero Scale Code Full Scale DIGITAL INPUT/OUTPUT1 Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Min Typ Max Unit 8 ±0.25 ±0.5 ±10 ±10 ±20 Bits LSB LSB mV ppm FSR/°C nA nA Data = 0x0000, TA = 25°C, IOUT1 Data = 0x0000, T = −40°C to +125°C, IOUT 1 ±10 10 10 12 12 V kΩ kΩ Input resistance TC = −50 ppm/°C Input resistance TC = −50 ppm/°C 3 5 6 8 pF pF ±5 8 8 1.7 0.6 VDD − 1 VDD − 0.5 Output Low Voltage, VOL Input Leakage Current, IIL Input Capacitance DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth Output Voltage Settling Time Measured to ±1 mV Measured to ±4 mV Measured to ±16 mV Digital Delay 10% to 90% Settling Time Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error 4 0.4 0.4 1 10 10 90 55 50 40 15 2 MHz 160 110 100 75 30 70 48 Output Capacitance IOUT1 Digital Feedthrough 12 25 22 10 0.1 Analog THD 81 IOUT2 V V V V V V µA pF ns ns ns ns ns nV-s dB dB 17 30 25 12 pF pF pF pF nV-s dB Rev. C | Page 3 of 24 Conditions/Comments Guaranteed monotonic VDD = 4.5 V to 5 V, ISOURCE = 200 µA VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA VDD = 4.5 V to 5 V, ISINK = 200 µA VDD = 2.5 V to 3.6 V, ISINK = 200 µA VREF = ±3.5 V, DAC loaded all 1s VREF = ±3.5 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s Interface delay time Rise and fall time, VREF = 10 V, RLOAD = 100 Ω 1 LSB change around major carry VREF = 0 V DAC latch loaded with all 0s. VREF = ±3.5 V 1 MHz 10 MHz All 0s loaded All 1s loaded All 0s loaded All 1s loaded Feedthrough to DAC output with SYNC high and alternate loading of all 0s and all 1s VREF = 3.5 V p-p; all 1s loaded, f = 1 kHz AD5425 Parameter Digital THD 50 kHz fOUT 20 kHz fOUT Output Noise Spectral Density SFDR Performance (Wide Band) 50 kHz fOUT 20 kHz fOUT SFDR Performance (Narrow Band) 50 kHz fOUT 20 kHz fOUT Intermodulation Distortion POWER REQUIREMENTS Power Supply Range IDD Data Sheet Min Typ Max 70 73 25 dB dB nV√Hz 67 68 dB dB 73 75 79 dB dB dB Conditions/Comments Clock = 1 MHz, VREF = 3.5 V, CCOMP = 1.8 pF @ 1 kHz Clock = 2 MHz , VREF = 3.5 V Clock = 2 MHz, VREF = 3.5 V 2.5 5.5 0.6 5 0.001 0.4 Power Supply Sensitivity 1 Unit V µA µA %/% Guaranteed by design and characterization, not subject to production test. Rev. C | Page 4 of 24 f1 = 20 kHz, f2 = 25 kHz, clock = 2 MHz, VREF = 3.5 V TA = 25°C, logic inputs = 0 V or VDD Logic inputs = 0 V or VDD, T = −40°C to +125°C ΔVDD = ±5% Data Sheet AD5425 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD =2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C ; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 fSCLK t1 t2 t3 t4 2 t5 t6 t7 t8 t9 t10 t11 2 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments Maximum clock frequency SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time Data setup time Data hold time SYNC rising edge to SCLK falling edge Minimum SYNC high time SCLK falling edge to LDAC falling edge LDAC pulse width SCLK falling edge to LDAC rising edge Guaranteed by design and characterization, not subject to production test. Falling or rising edge as determined by control bits of serial word. t1 SCLK t2 t8 t4 t3 t7 SYNC t6 t5 DIN DB7 DB0 t10 t9 LDAC1 t11 LDAC2 NOTES: 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. 03161-002 1 VDD = 2.5 V to 5.5 V 50 20 8 8 13 5 3 5 30 0 12 10 Figure 2. Timing Diagram Rev. C | Page 5 of 24 AD5425 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Parameter VDD to GND VREF, RFB to GND IOUT1, IOUT2 to GND Logic Input and Output 1 Operating Temperature Range Extended Industrial (Y Version) Storage Temperature Range Junction Temperature 10-lead MSOP θJA Thermal Impedance Lead Temperature, Soldering (10 secs) IR Reflow, Peak Temperature (<20 secs) 1 Rating −0.3 V to +7 V −12 V to +12 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 206°C/W 300°C 235°C Overvoltages at SCLK, SYNC, DIN, and LDAC are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. C | Page 6 of 24 Data Sheet AD5425 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IOUT2 2 GND 3 SCLK 4 SDIN 5 AD5425 TOP VIEW (Not to Scale) 9 VREF 8 VDD 7 LDAC 6 SYNC 03161-003 10 RFB IOUT1 1 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic IOUT1 IOUT2 GND SCLK 5 6 SDIN SYNC 7 LDAC 8 9 10 VDD VREF RFB Function DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Digital Ground Pin. Serial Clock Input. Data is clocked into the input shift register on each falling edge of the serial clock input. This device can accommodate clock rates of up to 50 MHz. Serial Data Input. Data is clocked into the 8-bit input register on each falling edge of the serial clock input. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on each falling edge of the following 8 clocks. Load DAC Input. Updates the DAC output. The DAC is updated when this signal goes low or alternatively; if this line is held permanently low, an automatic update mode is selected whereby the DAC is updated after 8 SCLK falling edges with SYNC low. Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. DAC Reference Voltage Input Terminal. DAC Feedback Resistor Pin. Establishes voltage output for the DAC by connecting to external amplifier output. Rev. C | Page 7 of 24 AD5425 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.4 0.20 TA = 25°C VREF = 10V 0.15 VDD = 5V TA = 25°C VDD = 5V 0.2 0.10 MIN DNL DNL (LSB) INL (LSB) 0.05 0 –0.05 0 –0.2 MAX DNL –0.10 –0.4 0 50 100 150 200 250 CODE –0.6 03161-004 –0.20 2 3 8 9 10 1.6 0.20 TA = 25°C VREF = 10V 0.15 VDD = 5V 1.4 1.2 0.05 0 –0.05 0.8 0.6 –0.10 0.4 –0.15 0.2 0 50 100 150 200 250 CODE IOUT1 VDD 3V 0 –40 03161-005 –0.20 IOUT1 VDD 5V 1.0 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 03161-008 IOUT LEAKAGE (nA) 0.10 Figure 8. IOUT1 Leakage Current vs. Temperature Figure 5. DNL vs. Code (8-Bit DAC) 0.3 5 TA = 25°C VDD = 5V VREF = 10V 4 0.2 3 MAX INL VDD = 5V 2 ERROR (mV) 0.1 0 MIN INL –0.1 1 0 VDD = 2.5V –1 –2 –3 –0.2 –4 2 3 4 5 6 7 REFERENCE VOLTAGE 8 9 10 –5 –60 03161-006 –0.3 Figure 6. INL vs. Reference Voltage –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 Figure 9. Gain Error vs. Temperature Rev. C | Page 8 of 24 120 140 03161-009 INL (LSB) 5 6 7 REFERENCE VOLTAGE Figure 7. DNL vs. Reference Voltage Figure 4. INL vs. Code (8-Bit DAC) INL (LSB) 4 03161-007 –0.15 Data Sheet 0.5 AD5425 2.5 TA = 25°C VDD = 3V VREF = 0V VDD = 5V VREF = 0V 2.0 0.3 GAIN ERROR MAX INL 1.5 LSBs VOLTAGE (mV) MAX DNL 0.1 –0.1 MIN DNL 1.0 0.5 MIN INL OFFSET ERROR –0.3 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VBIAS (V) –0.5 0.5 03161-010 –0.5 0.5 Figure 10. Linearity vs. VBIAS Voltage Applied to IOUT2 1.0 1.5 VBIAS (V) 2.0 2.5 03161-013 0 Figure 13. Gain and Offset Errors vs. Voltage Applied to IOUT2 1.4 10.0 TA = 25°C V = 3V 1.2 DD VREF = 0V TA = 25°C VDD = 5V 8.0 VREF = 2.5V 1.0 6.0 GAIN ERROR VOLTAGE (mV) VOLTAGE (mV) 0.8 0.6 0.4 OFFSET ERROR 0.2 4.0 2.0 OFFSET ERROR 0 0 –2.0 –0.2 1.5 03161-011 1.0 VBIAS (V) –4.0 0 1.0 1.5 2.0 2.5 VBIAS (V) Figure 11. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2 0.5 0.5 03161-014 GAIN ERROR –0.4 0.5 Figure 14. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2 1.0 VDD = 5V VREF = 0V TA = 25°C 0.8 VDD = 5V VREF = 2.5V 0.3 0.6 MIN INL BIAS 0.4 MAX INL MAX DNL MAX INL BIAS 0.2 LSBs LSBs 0.1 0 –0.2 –0.1 MIN DNL MIN INL MAX DNL BIAS –0.4 MIN DNL BIAS –0.6 –0.3 1.5 2.0 VBIAS (V) 2.5 Figure 12. Linearity vs. VBIAS Voltage Applied to IOUT2 –1.0 0 0.5 1.0 VBIAS (V) 1.5 Figure 15. Linearity vs. VBIAS Voltage Applied to IOUT2 Rev. C | Page 9 of 24 2.0 03161-015 1.0 03161-012 –0.8 –0.5 0.5 AD5425 0.7 Data Sheet 0.060 TA = 25°C 0.6 0.3 0.2 VDD = 2.5V 0.1 VDD 3V, 0V REF NRG = 1.877nVs 0x7FF TO 0x800 0.010 0 VDD 5V, 0V REF NRG = 0.119nVs, 0x800 TO 0x7FF 4 5 –0.020 0 TA = 25°C 1.6 VIH 1.2 GAIN (dB) THRESHOLD VOLTAGE (V) 1.4 VIL 0.8 0.6 0.4 3.0 3.5 4.0 VOLTAGE (V) 4.5 5.0 5.5 03161-017 0.2 0 2.5 100 150 TIME (ns) 200 250 300 Figure 19. Midscale Transition, VREF = 3.5 V Figure 16. Supply Current vs. Input Voltage 1.0 50 6 T = 25°C 0 A LOADING –6 ZS TO FS –12 –18 –24 –30 –36 –42 –48 –54 –60 –66 –72 –78 –84 –90 –96 –102 1 10 ALL ON DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ALL OFF 100 1k 10k 100k FREQUENCY (Hz) TA = 25°C VDD = 5V VREF = ±3.5V INPUT CCOMP = 1.8pF AD8083 AMPLIFIER 1M 10M 100M 03161-020 2 3 INPUT VOLTAGE (V) 03161-016 0 1 0.020 –0.010 VDD = 3V 0 VDD 3V, 0V REF NRG = 0.088nVs 0x800 TO 0x7FF 0.030 03161-019 OUTPUT VOLTAGE (V) VDD = 5V 0.4 1.8 TA = 25°C VREF = 0V AD8038 AMPLIFIER CCOMP = 1.8pF 0.040 0.5 CURRENT (mA) VDD 5V, 0V REF NRG = 2.049nVs 07xFF TO 0x800 0.050 Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code Figure 17. Threshold Voltages vs. Supply Voltage 3 0.2 VREF = ±0.15V, AD8038 CC 1pF VREF = ±2V, AD8038 CC 1pF 0 0 VREF = ±3.51V, AD8038 CC 1.8pF GAIN (dB) –0.4 VREF = ±2V, AD8038 CC 1.47pF –3 VREF = ±0.15V, AD8038 CC 1.47pF –0.8 TA = 25°C VDD = 5V VREF = ±3.5V CCOMP = 1.8pF AD8083 AMPLIFIER 1 10 100 TA = 25°C VDD = 5V AD8038 AMPLIFIER 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M –9 10k 100k 1M FREQUENCY (Hz) 10M 100M Figure 21. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor Figure 18. Reference Multiplying Bandwidth—All 1s Loaded Rev. C | Page 10 of 24 03161-021 –6 –0.6 03161-018 GAIN (dB) –0.2 Data Sheet –60 AD5425 0 TA = 25°C VDD = 3V VREF = 3.5V p-p –65 TA = 25°C VDD = 5V VREF = 3.5V AD8038 AMPLIFIER –10 –20 –30 –40 SFDR (dB) THD + N (dB) –70 –75 –80 –50 –60 –70 –80 –90 –85 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M –110 03161-022 –90 0 400k 600k FREQUENCY (Hz) 0 VDD = 3V AMPLIFIER = AD8038 1M TA = 25°C VDD = 5V VREF = 3.5V AD8038 AMPLIFIER –10 0 –20 –30 –20 –40 –40 –60 SFDR (dB) POWER SUPPLY REJECTION 800k Figure 25. Wideband SFDR, Clock = 2 MHz, fOUT = 20 kHz Figure 22. THD and Noise vs. Frequency 20 200k 03161-025 –100 FULL SCALE –80 –50 –60 –70 –80 ZERO SCALE –90 –100 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 10M –110 10k 03161-023 –120 0 18k 20k 22k 24k FREQUENCY (Hz) 26k 28k 30k TA = 25°C VDD = 5V VREF = 3.5V AD8038 AMPLIFIER –10 –20 –30 –30 –40 –40 SFDR (dB) –50 –60 –70 –80 –50 –60 –70 –90 –100 –100 –110 0 200k 400k 600k FREQUENCY (Hz) 800k 1M –110 25k 30k 35k 40k 45k 50k 55k 60k FREQUENCY (Hz) 65k 70k 75k Figure 27. Narrowband SFDR, Clock = 2 MHz, fOUT = 50 kHz Figure 24. Wideband SFDR, Clock = 2 MHz, fOUT = 50 kHz Rev. C | Page 11 of 24 03161-027 –80 –90 03161-024 SFDR (dB) 16k 0 TA = 25°C VDD = 5V VREF = 3.5V AD8038 AMPLIFIER –20 14k Figure 26. Narrowband SFDR, Clock = 2 MHz, fOUT = 20 kHz Figure 23. Power Supply Rejection vs. Frequency –10 12k 03161-026 –100 AD5425 Data Sheet 0 VDD = 5V VREF = 3.5V AD8038 AMPLIFIER –10 –20 –30 –50 –60 –70 –80 –90 –100 10k 15k 20k 25k FREQUENCY (Hz) 30k 35k 03161-028 IMD (dB) –40 Figure 28. Narrowband IMD (±50%) Clock = 2 MHz, fOUT1 = 20 kHz, fOUT2 = 25 kHz Rev. C | Page 12 of 24 Data Sheet AD5425 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of −1 LSB maximum over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF − 1 LSB. Gain error of the DACs is adjustable to 0 with external resistance. Output Leakage Current Output leakage current is current that flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND. Output Current Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 Ω resistor to ground. The settling time specification includes the digital delay from SYNC rising edge to the full-scale output charge. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s depending upon whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs can be capacitively coupled to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second to fifth. THD = 20 log (V 2 2 + V3 + V4 + V5 2 2 2 ) V1 Digital Intermodulation Distortion Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa − fb and 2fb − fa. Spurious-Free Dynamic Range (SFDR) SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. It is the measure of the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or fS/2). Narrow band SFDR is a measure of SFDR over an arbitrary window size, in this case 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave. Rev. C | Page 13 of 24 AD5425 Data Sheet THEORY OF OPERATION The AD5425 is an 8-bit current output DAC consisting of a standard inverting R-2R ladder configuration. A simplified diagram is shown in Figure 29. The feedback resistor, RFB, has a value of R. The value of R is typically 10 kΩ� (minimum 8 kΩ and maximum 12 kΩ). If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant and nominally of value R. The DAC output, IOUT, is code-dependent, producing various resistances and capacitances. When choosing the external amplifier, take into account the variation in impedance generated by the DAC on the amplifiers inverting input node. R 2R 2R 2R 2R S1 S2 S3 S8 2R DAC DATA LATCHES AND DRIVERS R Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. This DAC is designed to operate with either negative or positive reference voltages. The VDD power pin is used by only the internal digital logic to drive the DAC switches’ on and off states. This DAC is also designed to accommodate ac reference input signals in the range of −10 V to +10 V. With a fixed 10 V reference, the circuit shown in Figure 30 gives a unipolar 0 V to −10 V output voltage swing. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. Table 5 shows the relationship between digital code and the expected output voltage for unipolar operation. RFB IOUT1 IOUT2 Table 5. Unipolar Code Table Figure 29. Simplified Ladder Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output, bipolar output, or in single-supply modes of operation in unipolar mode or 4-quadrant multiplication in bipolar mode. Note that a matching switch is used in series with the internal RFB feedback resistor. If users attempt to measure RFB, power must be applied to VDD to achieve continuity. Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 VDD VDD VREF VREF CIRCUIT OPERATION AD5425 R2 C1 RFB IOUT1 A1 A1 IOUT2 R1 VOUT = 0 TO –VREF SYNC SCLK SDIN GND Unipolar Mode MICROCONTROLLER Using a single op amp, this device can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 30. When an output amplifier is connected in unipolar mode, the output voltage is given by VOUT = − V REF × Analog Output (V) −VREF (255/256) −VREF (128/256) = −VREF/2 −VREF (1/256) −VREF (0/256) = 0 D 2n Rev. C | Page 14 of 24 AGND NOTES: 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 30. Unipolar Operation 03161-030 R 03161-029 VREF R where D is the fractional representation of the digital word loaded to the DAC, in this case 0 to 255, and n is the number of bits. Data Sheet AD5425 R3 20kΩ VDD R5 20kΩ R2 C1 VREF R1 ±10V VREF RFB AD5425 IOUT1 IOUT2 A1 A1 R4 10kΩ A2 SYNC SCLK SDIN GND MICROCONTROLLER VOUT = –VREF TO +VREF AGND NOTES: 1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0 V WITH CODE 10000000 LOADED TO DAC. 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER. 03161-031 VDD Figure 31. Bipolar Operation (4-Quadrant Multiplication) Bipolar Operation Stability In some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and some external resistors, as shown in Figure 31. In this circuit, the second amplifier, A2, provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage, results in full 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are created as the input data, D, is incremented from code zero (VOUT = −VREF) to midscale (VOUT = 0 V ) to full scale (VOUT = +VREF). In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as closely as possible and proper PCB layout techniques must be employed. Since every code change corresponds to a step function, gain peaking can occur if the op amp has limited GBP and there is excessive parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into the open-loop response, which can cause ringing or instability in closed-loop applications. VOUT = (VREF × D − 2n−1 ) − VREF Where D is the fractional representation of the digital word loaded to the DAC and n is the resolution of the DAC. An optional compensation capacitor, C1, can be added in parallel with RFB for stability, as shown in Figure 30 and Figure 31. Too small a value of C1 can produce ringing at the output, while too large a value can adversely affect the settling time. C1 should be found empirically, but 1 pF to 2 pF is generally adequate for compensation. When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation. Table 6. Bipolar Code Table Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 Analog Output (V) +VREF (127/128) 0 −VREF (127/128) −VREF (128/128) Rev. C | Page 15 of 24 AD5425 Data Sheet SINGLE-SUPPLY APPLICATIONS VDD R1 R2 Current Mode Operation In the current mode circuit of Figure 32, IOUT2 and hence IOUT1 is biased positive by an amount applied to VBIAS. In this configuration, the output voltage is given by RFB VIN VDD A1 A1 IOUT1 VOUT VREF IOUT2 GND VOUT = [D × (RFB/RDAC) × (VBIAS − VIN)] + VBIAS As D varies from 0 to 255, the output voltage varies from VDD 03161-033 NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. VOUT = VBIAS to VOUT = 2VBIAS − VIN Figure 33. Single-Supply Voltage Switching Mode Operation RFB IOUT1 VIN VREF A1 A1 It is important to note that VIN is limited to low voltage because the switches in the DAC ladder no longer have the same source drain drive voltage. As a result, their on resistance differs, which degrades the linearity of the DAC. VOUT IOUT2 GND VIN must also not go negative by more than 0.3 V, otherwise an internal diode turns on, exceeding the maximum ratings of the device. In this type of application, the full range of the DAC multiplying capability is lost. VBIAS POSITIVE OUTPUT VOLTAGE 03161-032 NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 32. Single-Supply Current Mode Operation VBIAS should be a low impedance source capable of sinking and sourcing all possible variations in current at the IOUT2 terminal without any problems. It is important to note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same sourcedrain drive voltage. As a result, their on resistance differs and this degrades the linearity of the DAC. Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. To achieve a positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistor tolerance errors. To generate a negative reference, the reference can be level shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and −2.5 V respectively, as shown in Figure 34. VDD = 5V ADR03 Voltage Switching Mode of Operation VOUT VIN GND Figure 33 shows this DAC operating in the voltage switching mode. The reference voltage VIN is applied to the IOUT1 pin, IOUT2 is connected to AGND, and the output voltage is available at the VREF terminal. In this configuration, a positive reference voltage results in a positive output voltage, making singlesupply operation possible. The output from the DAC is voltage at a constant impedance (the DAC ladder resistance), thus an op amp is necessary to buffer the output voltage. The reference input no longer sees constant input impedance, but one that varies with code. So, the voltage input should be driven from a low impedance source. C1 +5V VDD RFB IOUT1 VREF IOUT2 –2.5V –5V GND A1 VOUT = 0V TO +2.5V NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Rev. C | Page 16 of 24 Figure 34. Positive Voltage Output with Minimum of Components 03161-034 VDD C1 Data Sheet AD5425 ADDING GAIN In applications where the output voltage is required to be greater than VIN, gain can be added with an additional external amplifier or it can be achieved in a single stage. It is important to take into consideration the effect of temperature coefficients of the thin film resistors of the DAC. Simply placing a resistor in series with the RFB resistor causes mismatches in the temperature coefficients and results in larger gain temperature coefficient errors. Instead, the circuit of Figure 35 is a recommended method of increasing the gain of the circuit. R1, R2, and R3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains of greater than 1 are required. VDD R1 RFB IOUT1 VREF IOUT2 C1 A1 VOUT R3 GND R2 RFB VDD IOUT1 VREF GND NOTE: 1. ADDITIONAL PINS OMITTED FOR CLARITY. 03161-036 VOUT Figure 36. Current Steering DAC Used as a Divider or Programmable Gain Element DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the DAC. Since only a fraction, D, of the current into the VREF terminal is routed to the IOUT1 terminal, the output voltage has to change as follows: VDD VIN VDD VIN GAIN = R2 + R3 R2 R1 = R2R3 R2 + R3 03161-035 NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 35. Increasing the Gain of Current Output DAC DACS USED AS A DIVIDER OR PROGRAMMABLE GAIN ELEMENT Current steering DACs are very flexible and lend themselves to many different applications. If this type of DAC is connected as the feedback element of an op amp and RFB is used as the input resistor as shown in Figure 36, then the output voltage is inversely proportional to the digital input fraction, D. For D = 1 − 2−n, the output voltage is VOUT = −VIN/D = −VIN/(1 − 2−n) As D is reduced, the output voltage increases. For small values of D, it is important to ensure that the amplifier does not saturate and that the required accuracy is met. For example, an 8-bit DAC driven with the Binary Code 0x10 (00010000), that is, 16 decimal, in the circuit of Figure 36, should cause the output voltage to be 16 × VIN. However, if the DAC has a linearity specification of ±0.5 LSB, then D can in fact have a weight anywhere in the range 15.5/256 to 16.5/256. Therefore, the possible output voltage is in the range of 15.5 VIN to 16.5 VIN— an error of 3%, even though the DAC itself has a maximum error of 0.2%. Output Error Voltage Due to DAC Leakage = (Leakage × R)/D where R is the DAC resistance at the VREF terminal. For a DAC leakage current of 10 nA, R = 10 kΩ. With a gain (that is, 1/D) of 16 the error voltage is 1.6 mV. REFERENCE SELECTION When selecting a reference for use with the AD5425 current output DAC, pay attention to the reference’s output voltage temperature coefficient specification. This parameter not only affects the full-scale error, but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range 0°C to 50°C dictates that the maximum system drift with temperature should be less than 78 ppm/°C. A 12-bit system with the same temperature range to overall specification within 2 LSB requires a maximum drift of 10 ppm/°C. By choosing a precision reference with a low output temperature coefficient, this error source can be minimized. Table 7 suggests some of the references available from Analog Devices that are suitable for use with this range of current output DACs. Rev. C | Page 17 of 24 AD5425 Data Sheet AMPLIFIER SELECTION The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. The input offset voltage of an op amp is multiplied by the variable gain (due to the code dependent output resistance of the DAC) of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which if large enough, could cause the DAC to be nonmonotonic. The input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, RFB. Most op amps have input bias currents low enough to prevent any significant errors. Common-mode rejection of the op amp is important in voltage switching circuits, since it produces a code dependent error at the voltage output of the circuit. Most op amps have adequate common-mode rejection for use at an 8-bit resolution. Provided the DAC switches are driven from true wideband low impedance sources (VIN and AGND), they settle quickly. Consequently, the slew rate and settling time of a voltage switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it is important to minimize capacitance at the VREF node (voltage output node in this application) of the DAC. This is done by using low inputs capacitance buffer amplifiers and careful board design. Most single-supply circuits include ground as part of the analog signal range, which in turns requires an amplifier that can handle rail-to-rail signals. There is a large range of single-supply amplifiers available from Analog Devices. Table 7. Suitable ADI Precision References Part No. ADR01 ADR01 ADR02 ADR02 ADR03 ADR03 ADR06 ADR06 ADR431 ADR435 ADR391 ADR395 Output Voltage (V) 10 10 5 5 2.5 2.5 3 3 2.5 5 2.5 5 Initial Tolerance (%) 0.05 0.05 0.06 0.06 0.10 0.10 0.10 0.10 0.04 0.04 0.16 0.10 Temp Drift (ppm/°C) 3 9 3 9 3 9 3 9 3 3 9 9 ISS (mA) 1 1 1 1 1 1 1 1 0.8 0.8 0.12 0.12 Output Noise (µV p-p) 20 20 10 10 6 6 10 10 3.5 8 5 8 Package SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 SOIC-8 TSOT-23 TSOT-23 Supply Current (µA) 600 500 975 50 850 Package SOIC-8 MSOP, SOIC-8 MSOP, SOIC-8 TSOT TSOT, SOIC-8 Table 8. Suitable Precision ADI Op Amps Part No. OP97 OP1177 AD8551 AD8603 AD8628 Supply Voltage (V) ±2 to ±20 ±2.5 to ±15 2.7 to 5 1.8 to 6 2.7 to 6 VOS (Max) (µV) 25 60 5 50 5 IB (Max) (nA) 0.1 2 0.05 0.001 0.1 0.1 Hz to 10 Hz Noise (µV p-p) 0.5 0.4 1 2.3 0.5 Table 9. Suitable High Speed ADI Op Amps Part No. AD8065 AD8021 AD8038 AD9631 Supply Voltage (V) 5 to 24 ±2.5 to ±12 3 to 12 ±3 to ±6 BW @ ACL (MHz) 145 490 350 320 Slew Rate (V/µs) 180 120 425 1300 Rev. C | Page 18 of 24 VOS (Max) (µV) 1500 1000 3000 10000 IB (Max) (nA) 6000 10500 750 7000 Package SOIC-8, SOT-23,MSOP SOIC-8, MSOP SOIC-8, SC70-5 SOIC-8 Data Sheet AD5425 SERIAL INTERFACE AD54251 ADSP-2191M1 The AD5425 has a simple 3-wire interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. Data is written to the device in 8-bit words. This 8-bit word consists of 8 data bits, as shown in Figure 37. DB7 (MSB) SPIxSEL SYNC MOSI SDIN SCK SCLK 03161-038 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 38. ADSP-2191M SPI-to-AD5425 Interface Figure 37. 8-Bit Input Shift Register Contents SYNC is an edge-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC falling to SCLK falling edge setup time, t4. After loading eight data bits to the shift register, the SYNC line is brought high. The contents of the DAC register and the output are updated by bringing LDAC low any time after the 8-bit data transfer is complete, as seen in the timing diagram of Figure 2. LDAC can be tied permanently low if required. For another serial transfer to take place, the interface must be enabled by another falling edge of SYNC. A serial interface between the DAC and DSP SPORT is shown in Figure 39. In this interface example, SPORT0 is used to transfer data to the DAC shift register. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. In a write sequence, data is clocked out on each rising edge of the DSP’s serial clock and clocked into the DAC input shift register on the falling edge of its SCLK. The update of the DAC output takes place on the rising edge of the SYNC signal. AD54251 ADSP-2101/ ADSP-2191M1 TFS SYNC DT SDIN SCLK SCLK Low Power Serial Interface To minimize the power consumption of the device, the interface fully powers up only when the device is being written to, that is, on the falling edge of SYNC. The SCLK and SDIN input buffers are powered down on the rising edge of SYNC. MICROPROCESSOR INTERFACING Microprocessor interfacing to this DAC is via a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. An LDAC pin is also included. The AD5425 requires an 8-bit word with the default being data valid on the falling edge of SCLK, but this is changeable via the control bits in the data-word. ADSP-21xx-to AD5425 Interface The ADSP-21xx family of DSPs is easily interfaced to this family of DACs without extra glue logic. Figure 38 shows an example of an SPI interface between the DAC and the ADSP-2191M. SCK of the DSP drives the serial data line, DIN. SYNC is driven from one of the port lines, in this case SPIxSEL. 1 ADDITIONAL PINS OMITTED FOR CLARITY. 03161-039 DATA BITS 03161-037 DB0 (LSB) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Figure 39. ADSP-2101/ADSP-2191M SPORT-to-AD5425 Interface Communication between two devices at a given clock speed is possible when the following specifications from one device to the other are compatible: frame sync delay and frame sync setup and hold, data delay and data setup and hold, and SCLK width. The DAC interface expects a t4 (SYNC falling edge to SCLK falling edge setup time) of 13 ns minimum. Consult the ADSP21xx user manual for information on clock and frame sync frequencies for the SPORT register. Table 10. SPORT Control Register Setup Name TFSW INVTFS DTYPE ISCLK TFSR ITFS SLEN Rev. C | Page 19 of 24 Setting 1 1 00 1 1 1 0111 Description Alternate framing Active low frame signal Right-justify data Internal serial clock Frame every word Internal framing signal 8-bit data-word AD5425 Data Sheet ADSP-BF5xx-to-AD5425 Interface 80C51/80L51-to-AD5425 Interface The ADSP-BF5xx family of processors has an SPI-compatible port that enables the processor to communicate with SPIcompatible devices. A serial interface between the ADSP-BF5xx and the AD5425 DAC is shown in Figure 40. In this configuration, data is transferred through the MOSI (master output/slave input) pin. SYNC is driven by the SPI chip select pin, which is a reconfigured programmable flag pin. A serial interface between the DAC and the 8051 is shown in Figure 42. TxD of the 8051 drives SCLK of the DAC serial interface, while RxD drives the serial data line, DIN. P3.3 is a bitprogrammable pin on the serial port that drives SYNC. When data is transmitted to the switch, P3.3 is taken low. The 80C51/ 80L51 transmits data in 8-bit bytes, which fits the AD5425 since it only requires an 8-bit word. Data on RxD is clocked out of the microcontroller on the rising edge of TxD and is valid on the falling edge. As a result, no glue logic is required between the DAC and microcontroller interface. P3.3 is taken high at the completion of this cycle. The 8051 provides the LSB of its SBUF register as the first bit in the data stream. The DAC input register requires that the MSB is the first bit received. The transmit routine should take this into account. MOSI SDIN SCK SCLK 03161-040 1 ADDITIONAL SYNC PINS OMITTED FOR CLARITY. Figure 40. ADSP-BF5xx-to-AD5425 Interface The ADSP-BF5xx processor incorporates channel synchronous serial ports (SPORT). A serial interface between the DAC and the DSP SPORT is shown in Figure 41. When the SPORT is enabled, initiate transmission by writing a word to the Tx register. The data is clocked out on each rising edge of the DSP’s serial clock and clocked into the DAC’s input shift register on the falling edge of its SCLK. The DAC output is updated by using the transmit frame synchronization (TFS) line to provide a SYNC signal. AD54251 ADSP-BF5xx1 TFS SYNC DT SDIN 1 ADDITIONAL SCLK PINS OMITTED FOR CLARITY. Figure 41. ADSP-BF5xx-to-AD5425 Interface 03161-041 SCLK AD54251 80511 1 ADDITIONAL TxD SCLK RxD SDIN P1.1 SYNC 03161-042 SPIxSEL PINS OMITTED FOR CLARITY. Figure 42. 80C51/80L51-to-AD5425 Interface MC68HC11 Interface-to-AD5425 Interface Figure 43 shows an example of a serial interface between the DAC and the MC68HC11 microcontroller. The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR) (see the MC68HC11 user manual). SCK of the MC68HC11 drives the SCLK of the DAC interface, the MOSI output drives the serial data line, DIN, of the AD5425. The SYNC signal is derived from a port line, PC7. When data is being transmitted to the AD5425, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the MC68HC11 is transmitted in 8-bit bytes with only 8 falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. PC7 is taken high at the end of the write. MC68HC111 1 ADDITIONAL AD54251 PC7 SYNC SCK SCLK MOSI SDIN PINS OMITTED FOR CLARITY. Figure 43. 68HC11/68L11-to-AD5425 Interface Rev. C | Page 20 of 24 03161-043 AD54251 ADSP-BF5xx1 Data Sheet AD5425 MICROWIRE-to-AD5425 Interface PIC16C6x/7x-to-AD5425 Figure 44 shows an interface between the DAC and any MICROWIRE™-compatible device. Serial data is shifted out on the falling edge of the serial clock, SK, and is clocked into the DAC input shift register on the rising edge of SK, which corresponds to the falling edge of the DAC’s SCLK. The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit (CKP) = 0. This is done by writing to the synchronous serial port control register (SSPCON) (see the PIC16/17 microcontroller user manual). In this example, I/O Port RA1 is being used to provide a SYNC signal and enable the DAC serial port. This microcontroller transfers eight bits of data during each serial transfer operation. Figure 45 shows the connection diagram. SK SYNC SO SCLK CS SDIN PINS OMITTED FOR CLARITY. PIC16C6x/7x1 AD54251 SCK/RC3 SCLK SDI/RC4 SDIN RA1 SYNC Figure 44. MICROWIRE-to-AD5425 Interface 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 45. PIC16C6x/7x-to-AD5425 Interface Rev. C | Page 21 of 24 03161-045 1 ADDITIONAL AD54251 03161-044 MICROWIRE1 AD5425 Data Sheet PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5425 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. These DACs should have an ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply and located as close to the package as possible—ideally up against the device. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as found in the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and to filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize high frequency performance, the I-to-V amplifier should be located as close to the device as possible. Rev. C | Page 22 of 24 Data Sheet AD5425 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.70 0.55 0.40 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 46. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 AD5425YRM AD5425YRM-REEL AD5425YRM-REEL7 AD5425YRMZ AD5425YRMZ-REEL AD5425YRMZ-REEL7 1 Resolution (Bits) 8 8 8 8 8 8 INL (LSBs) ±0.25 ±0.25 ±0.25 ±0.25 ±0.25 ±0.25 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Z = ROHS Compliant Part. Rev. C | Page 23 of 24 Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Branding D1P D1P D1P D9U D9U D9U Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 AD5425 Data Sheet NOTES ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03161-0-9/12(C) Rev. C | Page 24 of 24