6-Channel SD/ED/HD Video Filter with Charge Pump ADA4424-6 FEATURES APPLICATIONS DVD players and recorders Set-top boxes Projectors Personal video recorders FUNCTIONAL BLOCK DIAGRAM +3.3V VDD3_SD +5V VDD3_HD D1 D2 D3 VDD5 L1_OUT L1 HD_ENB L2_OUT L2 D/S TERMINAL CONTROL L3_OUT L3 S S1/S2 SD_ENB Y_IN S1/S2_OUT ×1 ×2 Y_OUT LPF ×2 C_IN ×1 CVBS_OUT ×2 C_OUT LPF MODE0 MODE1 OFFSET_ENB OFFSET CANCELLATION ADA4424-6 FC_SEL HY_IN ×1 ×2 HY_OUT ×2 HPb_OUT ×2 HPr_OUT LPF FC_SEL HPb_IN ×1 LPF FC_SEL HPr_IN ×1 LPF FC_SEL SD_ENABLE HD_ENABLE VSS_SD SD_ENB HD_ENB VSS_HD POWER MANAGEMENT VDD3_CP CHARGE PUMP C1b C2/CP_OUT C1a +3.3V C1 GND_CP C2 08550-001 3 SD channels; 18 MHz typical 1 dB bandwidth (BW) 3 ED/HD channels; 25 MHz or 34 MHz typical 1 dB BW Fixed gain of 6.2 dB (2.042 V/V) On-board negative supply for output coupling without capacitors Minimal dc offset at the output pins Internal summation of Y and C channels for CVBS output Flexible input dc offset cancellation for luma channels D-terminal (EIAJ RC-5237 D5) and S-terminal (S1/S2) support Capable of driving 2 back-terminated 75 Ω video loads simultaneously Separate power-down pins for SD and ED/HD sections 38-lead TSSOP package Sony Green Partner Environmental Quality Approval Program compliant Figure 1. GENERAL DESCRIPTION The ADA4424-6 is a high performance video reconstruction filter specifically designed for consumer applications. It consists of a standard definition (SD) section with two fifth-order Butterworth filters and a high definition (HD) section with three fifth-order filters. The SD section contains an internal Y/C summer for CVBS output, whereas the HD section provides selectable corner frequencies for either extended definition (ED) or HD signals. The ADA4424-6 filter/buffer section operates from a single 3.3 V supply. Full support for D-terminal (EIAJ RC-5237 D5) and S1/S2 signaling is provided, along with a dedicated 5 V supply pin. Separate enable pins are provided for the SD and HD sections. The luma channels (Y_IN, HY_IN) of the ADA4424-6 are capable of detecting and cancelling dc input offsets of up to 1.1 V. Four distinct modes of detection/cancellation are available. The output drivers on the ADA4424-6 feature rail-to-rail outputs with 6.2 dB gain. An on-board charge pump allows the outputs to swing up to 1.4 V below ground, eliminating the need for large coupling capacitors. Each output is capable of driving two 75 Ω doubly terminated cables. The ADA4424-6 is available in a 38-lead TSSOP and operates in the industrial temperature range of −40°C to +85°C. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009-2010 Analog Devices, Inc. All rights reserved. ADA4424-6 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................9 Applications ....................................................................................... 1 Applications Information .............................................................. 11 Functional Block Diagram .............................................................. 1 CVBS Output .............................................................................. 11 General Description ......................................................................... 1 Corner Frequency Selection ..................................................... 11 Revision History ............................................................................... 2 Input DC Offset Cancellation ................................................... 11 Specifications..................................................................................... 3 D-Terminal and S-Terminal Support ...................................... 12 Absolute Maximum Ratings............................................................ 6 Power-Down ............................................................................... 13 Thermal Resistance ...................................................................... 6 Charge Pump .............................................................................. 13 Maximum Power Dissipation ..................................................... 6 Printed Circuit Board (PCB) Layout ....................................... 13 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 15 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 15 REVISION HISTORY 07/10—Rev. B to Rev. C Change to General Description Section ........................................ 1 05/10—Rev. A to Rev. B Change to Table 1, Overall Performance ....................................... 3 Change to Ordering Guide ............................................................ 15 12/09—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 5 Changes to Table 5 .......................................................................... 10 Changes to Table 8 to Table 11...................................................... 11 Change to Table 12 and Table 13 .................................................. 12 10/09—Revision 0: Initial Version Rev. C | Page 2 of 16 ADA4424-6 SPECIFICATIONS VDD3 = 3.3 V, TA = 25°C, VO = 2.042 V p-p, RL = 150 Ω, dc-coupled outputs, unless otherwise noted. Charge pump configured as shown in Figure 18. Table 1. Parameter OVERALL PERFORMANCE DC Voltage Gain Input Voltage Range, All Inputs Output Voltage Range, All Outputs Input Bias Current Input Impedance Output Resistance SD CHANNEL DYNAMIC PERFORMANCE In-Band Peaking 1 dB Bandwidth Out-of-Band Rejection Crosstalk Total Harmonic Distortion Signal-to-Noise Ratio Group Delay Variation Differential Gain Differential Phase ED CHANNEL DYNAMIC PERFORMANCE In-Band Peaking 1 dB Bandwidth Out-of-Band Rejection Crosstalk Total Harmonic Distortion Signal-to-Noise Ratio Group Delay Variation HD CHANNEL DYNAMIC PERFORMANCE In-Band Peaking 1 dB Bandwidth Out-of-Band Rejection Crosstalk Total Harmonic Distortion Signal-to-Noise Ratio Group Delay Variation DC CHARACTERISTICS Operating Voltage, 3.3 V Supply Quiescent Supply Current, 3.3 V Supply Test Conditions/Comments Min Typ Max Unit All channels Not including dc offset 6.0 6.2 −0.6 to +1.4 −1.6 to +3.0 30 800 0.5 6.4 dB V V pA kΩ Ω Y_IN, HY_IN, dc-coupled C_IN, HPb_IN, HPr_IN, ac-coupled Y_OUT, C_OUT, CVBS_OUT, HY_OUT, HPb_OUT, HPr_OUT, dc-coupled L1_OUT, L2_OUT, L3_OUT, S1/S2_OUT, dc-coupled 10.5 f = 100 kHz to 6.75 MHz f = 148.5 MHz f = 1 MHz f = 1 MHz, VO = 1.4 V p-p f = 100 kHz to 6 MHz, unweighted f = 100 kHz to 5 MHz NTSC NTSC FC_SEL = low (0) f = 100 kHz to 13.5 MHz f = 148.5 MHz f = 1 MHz f = 5 MHz, VO = 1.4 V p-p f = 100 kHz to 13.5 MHz, unweighted f = 100 kHz to 13.5 MHz FC_SEL = high (1) f = 100 kHz to 30 MHz Y Channel (HY_OUT) P Channels (HPb_OUT, HPr_OUT) f = 148.5 MHz f = 1 MHz f = 10 MHz, VO = 1.4 V p-p f = 100 kHz to 30 MHz, unweighted f = 100 kHz to 30 MHz Both active, SD_ENABLE = high, HD_ENABLE = high, no load, no signal, not including D/S terminal outputs SD disabled, SD_ENABLE = low, HD_ENABLE = high HD disabled, SD_ENABLE = high, HD_ENABLE = low Both disabled, SD_ENABLE = low, HD_ENABLE = low Operating Voltage, 5 V Supply Rev. C | Page 3 of 16 14 38 21 38 30 25 33 kΩ 0.00 18 42 67 0.07 68 1 0.2 0.5 0.01 dB MHz dB dB % dB ns % Degrees 0.02 25 42 65 0.45 66 1.5 0.1 dB MHz dB dB % dB ns 0.1 39 34 37 65 1.2 65 2.2 0.2 dB MHz MHz dB dB % dB ns 3.14 to 3.46 93 54 45 6.1 4.75 to 5.25 133 10 V mA mA mA mA V ADA4424-6 Parameter Quiescent Supply Current, 5 V Supply PSRR DC Offset Input Referred, Offset Cancellation Disabled Mode SD Channels CVBS Channel ED/HD Channels Input Referred, Fixed Offset Cancellation Mode SD Fixed High Offset Mode ED/HD Fixed High Offset Mode SD Fixed Low Offset Mode ED/HD Fixed Low Offset Mode Input Referred, Auto Offset Cancellation Mode SD Auto Offset Mode Sync Tip Sampling ED/HD Auto Offset Mode Sync Tip Sampling SD Auto Offset Mode Back Porch Sampling ED/HD Auto Offset Mode Back Porch Sampling FC_SEL Input Logic Low Level FC_SEL Input Logic High Level xD_ENABLE, OFFSET_ENB, MODEx Input Logic Low Level xD_ENABLE, OFFSET_ENB, MODEx Input Logic High Level xD_ENABLE Assert Time xD_ENABLE Deassert Time xD_ENABLE Input Bias Current Input-to-Output Isolation D- and S-Terminal Input Logic Low Level D- and S-Terminal Input Logic Mid Level D- and S-Terminal Input Logic High Level D- and S-Terminal Input Logic Open (Hi-Z) Resistance Value D-Terminal (L1_OUT, L2_OUT, L3_OUT) Low Level Output D-Terminal (L1_OUT, L3_OUT) Mid Level Output D-Terminal (L1_OUT, L2_OUT, L3_OUT) High Level Output S-Terminal (S1/S2_OUT) Low Level Output Test Conditions/Comments SD_ENABLE = high, HD_ENABLE = high, RL = 100 kΩ, D1, D2, D3 = high, S = high SD_ENABLE = low, HD_ENABLE = low ED/HD channels, output referred SD channels, output referred See Table 6 and Table 7 OFFSET_ENB = low Min Typ 190 Max 200 Unit μA 5 −42 −41 15 μA dB dB Y_IN = 0 V dc Y_IN = 0 V dc HY_IN = 0 V dc OFFSET_ENB = high, MODE1 = high −60 −100 −60 −20 −40 −20 +60 +100 +60 mV mV mV Y_IN = 1.0 V dc, MODE0 = low HY_IN = 1.1 V dc, MODE0 = low Y_IN = 0.33 V dc, MODE0 = high HY_IN = 0.33 V dc, MODE0 = high OFFSET_ENB = high, MODE1 = low −100 −100 −90 −100 −30 −38 −17 −25 +100 +100 +90 +100 mV mV mV mV Y_IN = 0 V to 1.0 V dc, MODE0 = low −70 −36 +70 mV HY_IN = 0 V to 1.1 V dc, MODE0 = low −95 −46 +95 mV Y_IN = 0 V to 1.0 V dc, MODE0 = high −25 −6 +25 mV HY_IN = 0 V to 1.1 V dc, MODE0 = high −25 −5 +25 mV 0 1.2 0 0.6 VDD3 0.8 V V V 2.0 VDD3 V xD_ENABLE = low to high xD_ENABLE = high to low Disabled, xD_ENABLE = low Disabled, xD_ENABLE = low, f = 5 MHz RL = 100 kΩ 95 20 6.1 −100 0 0.6 ns ns μA dB V RL = 100 kΩ 0.9 1.9 V RL = 100 kΩ 2.7 VDD3 V RL = 100 kΩ 200 kΩ VDD5 = 5.0 V, RL = 100 kΩ, D1, D2, D3 = low 0.0 V VDD5 = 5.0 V, RL = 100 kΩ, D1, D3 = mid or open 2.1 V VDD5 = 5.0 V, RL = 100 kΩ, D1, D2, D3 = high 4.5 V VDD5 = 5.0 V, RL = 100 kΩ, S = low 0.0 V Rev. C | Page 4 of 16 ADA4424-6 Parameter S-Terminal (S1/S2_OUT) Mid Level Output S-Terminal (S1/S2_OUT) High Level Output CHARGE PUMP CHARACTERISTICS Test Conditions/Comments VDD5 = 5.0 V, RL = 100 kΩ, S = mid or open VDD5 = 5.0 V, RL = 100 kΩ, S = high Min Typ 2.1 Max Unit V 4.5 V −1.66 180 100 V mV p-p kHz All channels operating; C1 = C2 = 4.7 μF, C3 = C4 = 1.0 μF, R1 = 1 Ω (see Figure 18) Output Voltage Output Voltage Ripple Output Ripple Frequency Rev. C | Page 5 of 16 ADA4424-6 ABSOLUTE MAXIMUM RATINGS Rating 3.6 V 5.5 V 3.6 V See Figure 2 −65°C to +125°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Airflow increases heat dissipation, effectively reducing θJA. Figure 2 shows the maximum power dissipation in the package vs. the ambient temperature for the 38-lead TSSOP (67.6°C/W) on a JEDEC standard 4-layer board. θJA values are approximate. 2.4 2.2 THERMAL RESISTANCE θJA is specified for the device soldered to a high thermal conductivity 4-layer (2s2p) circuit board, as described in EIA/JESD 51-7. Table 3. Package Type 38-Lead TSSOP θJA 67.6 θJC 14.0 Unit °C/W 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 10 MAXIMUM POWER DISSIPATION 20 30 40 50 60 70 80 AMBIENT TEMPERATURE (°C) The maximum safe power dissipation in the ADA4424-6 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4424-6. Exceeding a junction temperature of 150°C for an extended time can result in changes in the silicon devices, potentially causing failure. Figure 2. Maximum Power Dissipation vs. Ambient Temperature for a 4-Layer Board ESD CAUTION Rev. C | Page 6 of 16 90 100 08550-002 Parameter 3.3 V Supply Voltage 5 V Supply Voltage Digital Input Voltage (Pin 2 to Pin 5, Pin 8, Pin 12, Pin 15, Pin 16, Pin 23) Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to load drive depends on the particular application. For each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. The power dissipated due to the loads is equal to the sum of the power dissipations due to each individual load. RMS voltages and currents must be used in these calculations. MAXIMUM POWER DISSIPATION (W) Table 2. ADA4424-6 GND5 1 38 VDD5 D1 2 37 L1_OUT D2 3 36 L2_OUT D3 4 35 L3_OUT S 5 34 S1/S2_OUT Y_IN 6 33 Y_OUT VDD3_SD 7 32 VSS_SD SD_ENABLE 8 31 CVBS_OUT C_IN 9 30 C_OUT GND3 10 29 GND3 HY_IN 11 28 HY_OUT FC_SEL 12 27 VSS_HD HPb_IN 13 26 HPb_OUT HPr_IN 14 25 HPr_OUT HD_ENABLE 15 24 VDD3_HD MODE0 16 23 MODE1 OFFSET_ENB 17 22 C2/CP_OUT VDD3_CP 18 21 C1b C1a 19 20 GND_CP ADA4424-6 TOP VIEW (Not to Scale) 08550-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration, Top View Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10, 29 11 12 13 14 15 16 Mnemonic GND5 D1 D2 D3 S Y_IN VDD3_SD SD_ENABLE C_IN GND3 HY_IN FC_SEL HPb_IN HPr_IN HD_ENABLE MODE0 17 18 19, 21 20 22 23 24 25 26 27 OFFSET_ENB VDD3_CP C1a, C1b GND_CP C2/CP_OUT MODE1 VDD3_HD HPr_OUT HPb_OUT VSS_HD 28 30 31 HY_OUT C_OUT CVBS_OUT Description Ground Pin for 5 V Supply. D-Terminal Vertical Resolution Selection Input. D-Terminal Scan Selection Input. D-Terminal Aspect Ratio Selection Input. S-Terminal Aspect Ratio Selection Input. SD Luma (Y) Input. 3.3 V Supply Pin for SD Filter Section. Output Enable Pin for SD (Y, C, CVBS). SD Chroma (C) Input. Ground Pins for 3.3 V Supply. ED/HD Y Component Input. Filter Corner Frequency Selection Pin for HY, HPb, HPr Channels. ED/HD Pb Component Input. ED/HD Pr Component Input. Output Enable Pin for ED/HD (HY, HPb, HPr). This pin selects sync tip or back porch sampling when MODE1 = 0 and selects high or low fixed offset subtraction when MODE1 = 1. Offset Cancellation Enable Pin. 3.3 V Supply Pins for Charge Pump Section. Charge Pump Capacitor C1 Connection Pin. Ground Pin for 3.3 V Charge Pump Supply. Charge Pump Output Pin. Connect Capacitor C2 from this pin to ground. Selects Automatic or Fixed Offset Subtraction Mode. 3.3 V Supply Pin for ED/HD Filter Section. ED/HD Pr Component Output. ED/HD Pb Component Output. Negative Supply Pin for ED/HD Filter Section. This pin should be connected to the charge pump output (Pin 22), as shown in Figure 18. ED/HD Y Component Output. SD Chroma (C) Output. SD Composite Video (CVBS) Output. Rev. C | Page 7 of 16 ADA4424-6 Pin No. 32 Mnemonic VSS_SD 33 34 35 36 37 38 Y_OUT S1/S2_OUT L3_OUT L2_OUT L1_OUT VDD5 Description Negative Supply Pin for SD Filter Section. This pin should be connected to the charge pump output (Pin 22), as shown in Figure 18. SD Luma (Y) Output. S-Terminal Aspect Ratio Selection Output. D-Terminal Aspect Ratio Selection Output. D-Terminal Scan Selection Output. D-Terminal Vertical Resolution Selection Output. 5 V Supply Pin for D-Terminal and S-Terminal Signaling. Rev. C | Page 8 of 16 ADA4424-6 TYPICAL PERFORMANCE CHARACTERISTICS VDD3 = 3.3 V, TA = 25°C, VO = 2.042 V p-p, RL = 150 Ω, dc-coupled outputs, unless otherwise noted. Charge pump configured as shown in Figure 18. 10 0.5 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 –10 –20 –30 –40 Y 0 C Y/CVBS –0.5 C –50 10 –1.0 0.1 08550-004 1 100 FREQUENCY (MHz) 1 100 10 FREQUENCY (MHz) Figure 4. Frequency Response—SD Channels 08550-007 CVBS –60 0.1 Figure 7. Frequency Response Peaking—SD Channels 0.5 10 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 –10 –20 –30 Pr –40 HY HY 0 Pb Pr –0.5 Pb 1 10 100 1k FREQUENCY (MHz) –1.0 0.1 08550-005 –60 0.1 1 100 10 FREQUENCY (MHz) Figure 5. Frequency Response—ED Channels 08550-008 –50 Figure 8. Frequency Response Peaking—ED Channels 10 0.5 NORMALIZED GAIN (dB) –10 –20 –30 Pr –40 HY 0 Pb/Pr –0.5 Pb –50 1 10 100 FREQUENCY (MHz) 1k –1.0 0.1 1 10 FREQUENCY (MHz) Figure 6. Frequency Response—HD Channels Figure 9. Frequency Response Peaking—HD Channels Rev. C | Page 9 of 16 100 08550-009 –60 0.1 HY 08550-006 NORMALIZED GAIN (dB) 0 ADA4424-6 –20 –20 –30 –30 –40 –40 CROSSTALK (dB) CROSSTALK (dB) ALL HOSTILE REFERRED TO INPUT –50 –60 C_OUT ALL HOSTILE REFERRED TO INPUT –50 –60 HPb_OUT, HPr_OUT Y_OUT –70 –70 HY_OUT 1 10 100 FREQUENCY (MHz) –80 0.1 08550-010 45 40 40 35 Y_OUT, C_OUT 20 15 30 25 20 15 10 10 5 5 1 10 100 FREQUENCY (MHz) 0 0.1 100 Figure 14. Group Delay—ED Channels –40 40 –50 INPUT-TO-OUTPUT ISOLATION (dB) 45 35 30 25 20 15 10 VIN = 1.0V p-p RL = 150Ω SD_ENABLE = 0 HD_ENABLE = 0 –60 –70 –80 –90 –100 –110 5 1 10 FREQUENCY (MHz) 100 08550-012 GROUP DELAY (ns) 10 FREQUENCY (MHz) Figure 11. Group Delay—SD Channels 0 0.1 1 08550-014 GROUP DELAY (ns) CVBS_OUT 08550-011 GROUP DELAY (ns) 35 0 0.1 100 Figure 13. Crosstalk—ED and HD Channels 45 25 10 FREQUENCY (MHz) Figure 10. Crosstalk—SD Channels 30 1 Figure 12. Group Delay—HD Channels –120 0.1 1 10 FREQUENCY (MHz) Figure 15. Input-to-Output Isolation—All Channels Rev. C | Page 10 of 16 100 08550-015 –80 0.1 08550-013 CVBS_OUT ADA4424-6 APPLICATIONS INFORMATION CVBS OUTPUT The composite video signal (CVBS_OUT) is produced by passively summing the Y and C channels (see Figure 1), after amplification by their respective gain stages. Each signal experiences a 6.2 dB loss from the passive summation and is subsequently amplified by 6.2 dB in the fixed stage following the summer. The net signal gain through the composite video path is, therefore, 0 dB, and the resulting composite signal present at the ADA4424-6 output is the sum of Y and C with unity gain. BLACK LEVEL BACK PORCH SAMPLE INTERVAL The component channels of the ADA4424-6 allow for a 1 dB filter corner frequency of either 25 MHz or 39 MHz/34 MHz. The FC_SEL pin operates as described in Table 5. SYNC TIP SAMPLE INTERVAL 08550-017 CORNER FREQUENCY SELECTION Figure 16. Back Porch and Sync Tip Sample Intervals (SD/ED) Table 5. ED/HD Bandwidth Selection FC_SEL (Pin 12) Low (0) High (1) HD/ED ED HD −1 dB Corner Frequency (Typ) 25 MHz 39 MHz (HY); 34 MHz (Pb, Pr) INPUT DC OFFSET CANCELLATION The luma channels (Y_IN, HY_IN) of the ADA4424-6 are capable of detecting and cancelling dc input offsets of up to 1.1 V. Four distinct modes of detection/cancellation are available. These are selected via the MODE1 and MODE0 pins. The chroma (C_IN) and color difference (HPb_IN, HPr_IN) inputs do not support offset cancellation. It is recommended that these inputs be accoupled. BLACK LEVEL BACK PORCH SAMPLE INTERVAL There are two modes of automatic operation. The primary mode samples the input signal between the rising edge of the horizontal sync pulse and the start of active video (back porch), averages the value over the sampling interval, and subtracts it from the output signal. This is the more accurate method and is able to reduce the input-referred offsets to less than 25 mV. An alternate method is available for copy-protected signals, where sampling the back porch may not provide a reliable dc average. This method detects the input negative sync tip, and clamps it to a fixed value (−214 mV for SD, and −300 mV for ED/HD). Sample intervals for SD and ED are shown in Figure 16, and the HD sample intervals are shown in Figure 17. Rev. C | Page 11 of 16 SYNC TIP SAMPLE INTERVAL Figure 17. Back Porch and Sync Tip Sample Intervals (HD) 08550-018 Automatic Detection/Cancellation Mode ADA4424-6 Fixed Offset Cancellation Mode D-TERMINAL AND S-TERMINAL SUPPORT In addition to the automatic mode, there are two levels of fixed offset correction available. In high offset mode, fixed voltages of 1.0 V and 1.1 V are subtracted from the Y_IN and HY_IN inputs, respectively. In low offset mode, a fixed voltage of 0.33 V is subtracted from both Y_IN and HY_IN. The various modes of offset cancellation are outlined in Table 6. Full D-terminal support (EIAJ RC-5237 D5) is provided for the component channels (HY_OUT, HPb_OUT, HPr_OUT). Level D1 through Level D5 are supported for vertical resolution, scan type, and aspect ratio selection. Details are shown in Table 8, Table 9, and Table 10. Table 6. Offset Cancellation Mode Selection S-terminal (also known as S_DC or S1/S2) support for S-video aspect ratio selection is also provided, as described in Table 11. MODE1 (Pin 23) Low (0) The VDD5 pin (Pin 38) provides 5 V power for these outputs. If D- or S-terminal support is not required, it is recommended that Pin 2 to Pin 5 and Pin 34 to Pin 38 remain unconnected. MODE0 (Pin 16) Low (0) Low (0) High (1) High (1) Low (0) High (1) High (1) Output Offset Cancellation Auto-cancel, sync-tip sampling mode. Clamps the input referred SD sync tip to −214 mV, and the input referred ED/HD sync tip to −300 mV. Auto-cancel, back porch sampling mode. Sets the output blanking level to 0 V, independent of sync depth. Fixed cancellation mode, high dc offset. Subtracts 1.0 V from the Y_IN signal; subtracts 1.1 V from the HY_IN signal. Fixed cancellation mode, low dc offset. Subtracts 0.33 V from both the Y_IN and HY_IN signals. Table 8. D-Terminal Control for Vertical Resolution Selection Input Logic Level D1 (Pin 2) Low (0) Mid or open High (1) Nominal Output (V) L1_OUT (Pin 37) RL = 100 kΩ 0.0 2.1 4.5 Vertical Resolution (Number of Lines) 480 720 1080 Table 9. D-Terminal Control for Scan Selection Nominal Output (V) L2_OUT (Pin 36) RL = 100 kΩ 0.0 2.1 4.5 The offset cancellation function can be enabled or disabled via the OFFSET_ENB pin, as described in Table 7. Input Logic Level D2 (Pin 3) Low (0) Mid or open High (1) Table 7. Offset Cancellation Enable/Disable Table 10. D-Terminal Control for Aspect Ratio Selection Offset Cancellation Disable OFFSET_ENB (Pin 17) Low (0) High (1) Offset Cancellation State Offset cancellation is disabled. Offset cancellation is enabled. Function is determined by the MODE1 and MODE0 pins (see Table 6). Input Logic Level D3 (Pin 4) Low (0) Mid or open High (1) Nominal Output (V) L3_OUT (Pin 35) RL = 100 kΩ 0.0 2.1 4.5 Scan Type Interlaced N/A Progressive Aspect Ratio 4:3 4:3 letterbox 16:9 Table 11. S-Terminal Control for Aspect Ratio Selection Input Logic Level S (Pin 5) Low (0) Mid or open High (1) Rev. C | Page 12 of 16 Nominal Output (V) S1/S2_OUT (Pin 34) RL = 100 kΩ 0.0 2.1 4.5 Aspect Ratio 4:3 4:3 letterbox 16:9 ADA4424-6 POWER-DOWN CHARGE PUMP The ADA4424-6 provides separate output enable pins for the SD and ED/HD sections. In addition to powering down the Y, C, and CVBS outputs, the SD_ENABLE pin, when driven low, also places the S1/S2 output (S1/S2_OUT, Pin 34) in a high impedance state. Likewise, driving the HD_ENABLE pin low disables the component outputs (HY_OUT, HPb_OUT, and HPr_OUT) and changes the L1, L2, and L3 outputs (Lx_OUT, Pin 35 to Pin 37) to a high impedance state. Control details are shown in Table 12 and Table 13. The ADA4424-6 features an on-chip charge pump that supplies a negative rail voltage for the output stages. To minimize internal noise coupling, the charge pump uses an external connection to the negative supply pins (VSS_SD and VSS_HD). These pins should be connected to the C2/CP_OUT pin, each decoupled with a 1.0 μF capacitor. It is also recommended to place a small (1 Ω) series resistor in this connection. This forms a low-pass filter with the VSS decoupling capacitors and further reduces coupled noise. The charge pump also requires two 4.7 μF ceramic capacitors, one connected across the C1a and C1b pins, and one connected from the C2/CP_OUT pin to ground. The recommended charge pump configuration is shown in the application diagram (Figure 18). Table 12. Power-Down Control for SD Channels SD_ENABLE (Pin 8) Low (0) High (1) SD Outputs (Y, C, CVBS) Disabled Enabled S1/S2_OUT (Pin 34) High-Z (Open) Active Table 13. Power-Down Control for ED/HD Channels HD_ENABLE (Pin 15) Low (0) High (1) ED/HD Outputs (HY, HPb, HPr) Disabled Enabled Lx_OUT (Pin 35, Pin 36, Pin 37) High-Z (Open) Active With the black or zero level of the outputs placed at approximately ground potential, the outputs can swing up to 1.6 V in the negative direction. This eliminates the need for large output coupling capacitors because the input-referred dc offsets does not exceed ±100 mV (depending on the selected cancellation mode). PRINTED CIRCUIT BOARD (PCB) LAYOUT As with all high speed applications, attention to the PCB layout is of paramount importance. When designing with the ADA4424-6, adhere to standard high speed layout practices. A solid ground plane is recommended, and surface-mount, ceramic power supply decoupling capacitors should be placed as close as possible to the supply pins. Connect all of the ADA4424-6 GND pins to the ground plane with traces that are as short as possible. Controlled impedance traces of the shortest length possible should be used to connect to the signal I/O pins and should not pass over any voids in the ground plane. A 75 Ω impedance level is typically used in video applications. When driving transmission lines, include series termination resistors on the signal outputs of the ADA4424-6. Rev. C | Page 13 of 16 ADA4424-6 +3.3V 10µF + OFFSET_ENB ADA4424-6 MODE0 MODE1 VIDEO ENCODER Y_IN DAC1 x1 Y_OUT x2 75Ω LPF x2 100nF CVBS_OUT DAC2 x1 x2 LPF C3 1.0µF 1.0µF x1 x2 HY_OUT LPF HPb_IN DAC4 x1 x2 HPr_IN x1 x2 LPF 1.0µF FC_SEL HD_ENABLE RSET1 RSET2 Y 75Ω Pb 75Ω Pr HPr_OUT GND3 VDD3_HD 75Ω HPb_OUT LPF 1.0µF DAC5 75Ω VSS_SD VDD3_SD HY_IN S-VIDEO C_OUT GND3 SD_ENABLE DAC3 CVBS 75Ω C_IN VSS_HD C4 1.0µF 1.0µF VDD3_CP CHARGE PUMP 1.0µF C1b GND_CP C1 4.7µF +3.3V C2/CP_OUT C2 4.7µF R1 1.0Ω Figure 18. Typical Application Diagram for Using the ADA4424-6 in Auto Offset Cancellation Mode (D and S Terminal Connections Not Shown) Rev. C | Page 14 of 16 08550-019 C1a ADA4424-6 OUTLINE DIMENSIONS 9.80 9.70 9.60 20 38 4.50 4.40 4.30 6.40 BSC 1 19 PIN 1 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.50 BSC 0.27 0.17 SEATING PLANE 0.20 0.09 8° 0° 0.70 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-BD-1 Figure 19. 38-Lead Thin Shrink Small Outline Package [TSSOP] (RU-38) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADA4424-6ARUZ ADA4424-6ARUZ-R7 ADA4424-6ARUZ-RL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 38-Lead Thin Shrink Small Outline Package (TSSOP) 38-Lead Thin Shrink Small Outline Package (TSSOP) 38-Lead Thin Shrink Small Outline Package (TSSOP) Z = RoHS Compliant Part. Rev. C | Page 15 of 16 Package Option RU-38 RU-38 RU-38 Ordering Quantity 50 1,000 2,500 ADA4424-6 NOTES ©2009-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08550-0-7/10(C) Rev. C | Page 16 of 16