Quad Analog-to-Digital Converter (ADC) ADAU1979 Data Sheet FEATURES GENERAL DESCRIPTION Four 4.5 V rms (typical) differential inputs On-chip phase-locked loop (PLL) for master clock Low electromagnetic interference (EMI) design 109 dB (typical) analog-to-digital converter (ADC) dynamic range Total harmonic distortion + noise (THD + N): −95 dB (typical) Selectable digital high-pass filter 24-bit stereo ADC with 8 kHz to 192 kHz sample rates Digital volume control with autoramp function I2C/SPI controllable for flexibility Software-controllable clickless mute Software power-down Right justified, left justified, I2S, and TDM modes Master and slave operation modes 40-lead LFCSP package Qualified for automotive applications The ADAU1979 incorporates four high performance, analog-todigital converters (ADCs) with 4.5 V rms capable ac-coupled inputs. The ADCs use a multibit sigma-delta (Σ-Δ) architecture with continuous time front end for low EMI. An I2C/serial peripheral interface (SPI) control port is included that allows a microcontroller to adjust volume and many other parameters. The ADAU1979 uses only a single 3.3 V supply. The device internally generates the required digital DVDD supply. The low power architecture reduces the power consumption. The onchip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with the frame clock, it eliminates the need for a separate high frequency master clock in the system. The ADAU1979 is available in a 40-lead LFCSP package. Note that throughout this data sheet, multifunction pins, such as SCL/CCLK, are referred to either by the entire pin name or by a single function of the pin, for example, CCLK, when only that function is relevant. APPLICATIONS Automotive audio systems Active noise cancellation systems AVDD2 PROGRAMMABLE GAIN DECIMATOR/HPF DC CALIBRATION AIN1 AIN1 AIN2 AIN2 AIN3 AIN3 AIN4 AIN4 ADC ADC ADC ADC SERIAL AUDIO PORT 3.3V TO 1.8V REGULATOR AVDDx AGNDx IOVDD LRCLK BCLK SDATAOUT1 SDATAOUT2 SCL/CCLK SDA/COUT ADDR1/CIN ADDR0/CLATCH PD/RST SA_MODE AGNDx I2C/SPI CONTROL PLL_FILT AGNDx MCLKIN PLL VREF BG REF DGND AGND6 AGND5 AGND4 AGND3 AGND2 AGND1 AVDDx DVDD 11408-001 AVDD1 ADAU1979 AVDD3 FUNCTIONAL BLOCK DIAGRAM Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADAU1979 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Mode ..................................................................................... 24 Applications ....................................................................................... 1 Register Summary .......................................................................... 26 General Description ......................................................................... 1 Register Details ............................................................................... 27 Functional Block Diagram .............................................................. 1 Master Power and Soft Reset Register ..................................... 27 Revision History ............................................................................... 2 PLL Control Register ................................................................. 28 Specifications..................................................................................... 3 Block Power Control and Serial Port Control Register ......... 29 Analog Performance Specifications ........................................... 3 Serial Port Control Register 1 ................................................... 30 Digital Input/Output Specifications........................................... 3 Serial Port Control Register 2 ................................................... 31 Power Supply Specifications........................................................ 4 Channel 1 and Channel 2 Mapping for Output Serial Ports Register ........................................................................................ 32 Digital Filter Specifications ......................................................... 4 Timing Specifications .................................................................. 5 Absolute Maximum Ratings ............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 12 Overview...................................................................................... 12 Channel 3 and Channel 4 Mapping for Output Serial Ports Register ........................................................................................ 34 Serial Output Drive Control and Overtemperature Protection Status Register ............................................................................. 35 Post ADC Gain Channel 1 Control Register .......................... 36 Post ADC Gain Channel 2 Control Register .......................... 37 Post ADC Gain Channel 3 Control Register .......................... 37 Post ADC Gain Channel 4 Control Register .......................... 38 Power Supply and Voltage Reference ....................................... 12 High-Pass Filter and DC Offset Control Register and Master Mute Register .............................................................................. 38 Power-On Reset Sequence ........................................................ 12 ADC Clipping Status Register .................................................. 39 PLL and Clock............................................................................. 13 Digital DC High-Pass Filter and Calibration Register .......... 40 Analog Inputs .............................................................................. 14 Typical Application Circuit ........................................................... 41 ADC ............................................................................................. 16 Outline Dimensions ....................................................................... 42 ADC Summing Modes .............................................................. 16 Ordering Guide .......................................................................... 42 Serial Audio Data Output Ports, Data Format ....................... 17 Automotive Products ................................................................. 42 Control Ports ................................................................................... 21 I2C Mode ...................................................................................... 21 REVISION HISTORY 11/13—Revision 0: Initial Version Rev. 0 | Page 2 of 44 Data Sheet ADAU1979 SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. AVDDx/IOVDD = 3.3 V; DVDD (internally generated) = 1.8 V; TA = −40°C to +105°C, unless otherwise noted. Master clock = 12.288 MHz (48 kHz fS, 256 × fS mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz; word width = 24 bits; load capacitance (digital output) = 20 pF; load current (digital output) = ±1 mA; digital input voltage high = 2.0 V; and digital input voltage low = 0.8 V. ANALOG PERFORMANCE SPECIFICATIONS Table 1. Parameter LINE INPUT Full Scale AC Differential Input Voltage Full Scale Single-Ended Input Voltage Input Common-Mode Voltage Test Conditions/Comments 1 Typ Max Unit 4.18 2.09 4.5 2.25 1.5 4.82 2.41 V rms V rms V dc VIN, cm at AINx/AINx pins ANALOG-TO-DIGITAL CONVERTERS Differential Input Resistance Single-Ended Input Resistance ADC Resolution Dynamic Range (A-Weighted) Line Input 1 Total Harmonic Distortion + Noise (THD + N) Digital Gain Post ADC Gain Error Interchannel Gain Mismatch Gain Drift Common-Mode Rejection Ratio (CMRR) Power Supply Rejection Ratio (PSRR) Interchannel Isolation Interchannel Phase Deviation REFERENCE Internal Reference Voltage Output Impedance ADC SERIAL PORT Output Sample Rate Min Between AINx and AINx Between AINx and AINx Input = 1 kHz, −60 dBFS (0 dBFS = 4.5 V rms input) Input = 1 kHz, −1 dBFS (0 dBFS = 4.5 V rms input) 103 64.34 32.17 24 109 −95 0 −10 −0.25 400 mV rms, 1 kHz 400 mV rms, 20 kHz 100 mV rms, 1 kHz on AVDD = 3.3 V 50 VREF pin 1.47 −87 60 +10 +0.25 100 65 56 70 100 0 1.50 20 8 kΩ kΩ Bits dB dB dB % dB ppm/°C dB dB dB dB Degrees 1.54 V kΩ 192 kHz This is for a sampling frequency, fS, ranging from 44.1 kHz to 192 kHz. DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter INPUT High Level Input Voltage (VIH) Low Level Input Voltage (VIL) Input Leakage Current Input Capacitance OUTPUT High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Test Conditions/Comments Min Typ Max Unit 0.3 × IOVDD +10 5 V V µA pF 0.4 V V 0.7 × IOVDD −10 IOH = 1 mA IOL = 1 mA IOVDD − 0.60 Rev. 0 | Page 3 of 44 ADAU1979 Data Sheet POWER SUPPLY SPECIFICATIONS AVDD = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V, and fS = 48 kHz (master mode), unless otherwise noted. Table 3. Parameter SUPPLY DVDD AVDDx IOVDD IOVDD CURRENT Normal Operation Power-Down AVDDx CURRENT Normal Operation Power-Down DVDD CURRENT Normal Operation Power-Down POWER DISSIPATION Normal Operation Analog Supply Digital Supply Digital I/O Supply Power-Down, All Supplies Test Conditions/Comments Min Typ Max Unit On-chip low dropout (LDO) regulator 1.62 3.0 1.62 1.8 3.3 3.3 1.98 3.6 3.6 V V V Master clock = 256 × fS fS = 48 kHz fS = 96 kHz fS = 192 kHz fS = 48 kHz to 192 kHz 450 880 1.75 20 µA µA mA µA 4-channel ADC, DVDD internal 4-channel ADC, DVDD external 14 9.5 270 mA mA µA DVDD external 5 65 mA µA 46.2 31 8.1 1.49 960 mW mW mW mW µW Master clock = 256 × fS, 48 kHz DVDD internal DVDD external DVDD external IOVDD = 3.3 V DIGITAL FILTER SPECIFICATIONS Table 4. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay HIGH-PASS FILTER Cutoff Frequency Phase Deviation Settling Time ADC DIGITAL GAIN Gain Step Size Mode All modes, typical at fS = 48 kHz Factor Min 0.4375 × fS Typ Max 21 ±0.015 24 27 0.5 × fS 0.5625 × fS kHz dB kHz kHz dB µs µs 79 fS = 8 kHz to 96 kHz fS = 192 kHz All modes, typical at 48 kHz At −3 dB point At 20 Hz All modes 22.9844/fS 479 35 0.9375 10 1 0 60 0.375 Rev. 0 | Page 4 of 44 Unit Hz Degrees sec dB dB Data Sheet ADAU1979 TIMING SPECIFICATIONS Table 5. Parameter INPUT MASTER CLOCK (MCLK) Duty Cycle fMCLKIN RESET Reset Pulse, tRESET PLL Lock Time ADC SERIAL OUTPUT PORT tABH tABL tALS tALH tABDD SPI PORT fCCLK tCCPH tCCPL tCDS tCDH tCLS tCLH tCLPH tCOE tCOD tCOTS I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tDH tSCR tSCF tSDR tSDF tBFT tSUSTO Limit at tMIN tMAX Unit Description 40 60 See Table 9 % MHz MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS MCLKIN frequency, PLL in MCLK mode 15 ns RST low 10 ms 18 ns ns ns ns ns 10 10 10 5 10 35 35 10 10 10 40 10 30 30 30 400 kHz µs µs µs µs ns 300 300 300 300 ns ns ns ns µs µs 0.6 1.3 0.6 0.6 100 0 1.3 0.6 MHz ns ns ns ns ns ns ns ns ns ns See Figure 2 BCLK high, slave mode BCLK low, slave mode LRCLK setup to BCLK rising, slave mode LRCLK hold from BCLK rising, slave mode SDATAOUTx delay from BCLK falling See Figure 3 CCLK frequency CCLK high CCLK low CIN setup to CCLK rising CIN hold from CCLK rising CLATCH setup to CCLK rising CLATCH hold from CCLK rising CLATCH high COUT enable from CLATCH falling COUT delay from CCLK falling COUT tristate from CLATCH rising See Figure 4 SCL frequency SCL high SCL low Setup time; relevant for repeated start condition Hold time; after this period of time, the first clock pulse is generated Data setup time Data hold time SCL rise time SCL fall time SDA rise time SDA fall time Bus-free time; time between stop and start Setup time for stop condition Rev. 0 | Page 5 of 44 ADAU1979 Data Sheet Timing Diagrams tALS LRCLK tALH tABH BCLK tABL SDATAOUTx LEFT JUSTIFIED MODE tABDD MSB – 1 MSB tABDD SDATAOUTx I2S MODE MSB tABDD SDATAOUTx RIGHT JUSTIFIED MODE LSB MSB 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 11408-002 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 2. ADC Serial Output Port Timing tCLH tCLS tCOE tCLPH tCCPL tCCPH CLATCH CCLK CIN tCDH tCDS tCOTS 11408-003 COUT tCOD Figure 3. SPI Port Timing tSCH tDS tSDR STOP tSCH START SDA tSDF tSCLH tBFT tSCR tSCLL tDH tSCF tSCS Figure 4. I2C Port Timing Rev. 0 | Page 6 of 44 tSUSTO 11408-004 SCL Data Sheet ADAU1979 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Analog (AVDDx) Supply Digital Supply DVDD IOVDD Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Ambient) Junction Temperature Range Storage Temperature Range θJA represents junction-to-ambient thermal resistance, and θJC represents the junction-to-case thermal resistance. All characteristics are for a standard JEDEC board per JESD51. Rating −0.3 V to +3.6 V −0.3 V to +1.98 V −0.3 V to +3.63 V ±20 mA −0.3 V to +3.6 V −0.3 V to +3.6 V −40°C to +105°C −40°C to +125°C −65°C to +150°C Table 7. Thermal Resistance Package Type 40-Lead LFCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 44 θJA 32.8 θJC 1.93 Unit °C/W ADAU1979 Data Sheet 40 39 38 37 36 35 34 33 32 31 AVDD1 AIN4 AIN4 AIN3 AIN3 AIN2 AIN2 AIN1 AIN1 AVDD3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 ADAU1979 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 NC AGND6 AGND5 NC NC NC NC NC AGND4 AGND3 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THESE PINS. LEAVE THE NC PINS OPEN. 2. THE EXPOSED PAD MUST BE CONNECTED TO THE GROUND PLANE ON THE PRINTED CIRCUIT BOARD (PCB). 11408-005 DGND IOVDD SDATAOUT1 SDATAOUT2 LRCLK BCLK SDA/COUT SCL/CCLK ADDR0/CLATCH ADDR1/CIN 11 12 13 14 15 16 17 18 19 20 AGND1 VREF PLL_FILT AVDD2 AGND2 PD/RST MCLKIN NC SA_MODE DVDD Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 Mnemonic AGND1 VREF Type 1 P O 3 PLL_FILT O 4 5 6 7 8, 23 to 27, 30 9 AVDD2 AGND2 PD/RST MCLKIN NC SA_MODE P P I I 10 DVDD O 11 12 13 14 15 16 17 18 19 20 21 22 28 29 DGND IOVDD SDATAOUT1 SDATAOUT2 LRCLK BCLK SDA/COUT SCL/CCLK ADDR0/CLATCH ADDR1/CIN AGND3 AGND4 AGND5 AGND6 P P O O I/O I/O I/O I I I P P P P I Description Analog Ground. Voltage Reference. Decouple VREF to AGND with a 10 µF capacitor in parallel with a 100 nF capacitor. Phase-Locked Loop Filter. Return PLL_FILT to AVDD using recommended loop filter components. Analog Power Supply. Connect AVDD2 to an analog 3.3 V supply. Analog Ground. Power-Down/Reset (Active Low). Master Clock Input. No Connect. Do not connect to these pins. Leave the NC pins open. Standalone Mode. Connect SA_MODE to IOVDD using a 10 kΩ pull-up resistor for standalone mode. 1.8 V Digital Power Supply Output. Decouple DVDD to DGND with 100 nF and 10 µF capacitors. Digital Ground. Digital I/O Power Supply. Connect IOVDD to a supply from 1.8 V to 3.3 V. ADC Serial Data Output Pair 1 (ADC L1 and ADC R1). ADC Serial Data Output Pair 2 (ADC L2 and ADC R2). Frame Clock for ADC Serial Port. Bit Clock for ADC Serial Port. Serial Data Input/Output (I2C)/Control Data Output (SPI). Serial Clock Input (I2C)/Control Clock Input (SPI). Chip Address Bit 0 Setting (I2C)/Chip Select Input for Control Data (SPI). Chip Address Bit 1 Setting (I2C)/Control Data Input (SPI). Analog Ground. Analog Ground. Analog Ground. Analog Ground. Rev. 0 | Page 8 of 44 Data Sheet Pin No. 31 32 33 34 35 36 37 38 39 40 1 Mnemonic AVDD3 AIN1 AIN1 AIN2 AIN2 AIN3 AIN3 AIN4 AIN4 AVDD1 EP ADAU1979 Type 1 P I I I I I I I I P Description Analog Power Supply. Connect AVDD3 to an analog 3.3 V supply. Analog Input Channel 1 Inverting Input. Analog Input Channel 1 Noninverting Input. Analog Input Channel 2 Inverting Input. Analog Input Channel 2 Noninverting Input. Analog Input Channel 3 Inverting Input. Analog Input Channel 3 Noninverting Input. Analog Input Channel 4 Inverting Input. Analog Input Channel 4 Noninverting Input. Analog Power Supply. Connect AVDD1 to an analog 3.3 V supply. Exposed Pad. The exposed pad must be connected to the ground plane on the printed circuit board (PCB). P = power, O = output, I = input, I/O = input/output. Rev. 0 | Page 9 of 44 ADAU1979 Data Sheet 0 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –10 –20 CMRR (dB) –30 –50 –60 –80 1k 10k 20k FREQUENCY (Hz) Figure 6. Fast Fourier Transform, 4.5 mV Differential Input at fS = 48 kHz 100 1k 10k 20k FREQUENCY (Hz) 10k 20k Figure 9. CMRR Differential Input, Referenced to 450 mV Differential Input 11408-007 20 1k FREQUENCY (Hz) AMPLITUDE (dBFS) 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 100 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 20 100 1k 10k FREQUENCY (Hz) 20k 11408-010 100 –100 20 11408-009 –90 20 AMPLITUDE (dBFS) –40 –70 11408-006 AMPLITUDE (dBFS) TYPICAL PERFORMANCE CHARACTERISTICS Figure 10. Fast Fourier Transform, No Input Figure 7. Fast Fourier Transform, −1 dBFS Differential Input 0 0.10 –10 0.08 –20 0.06 0.04 MAGNITUDE (dB) –40 –50 –60 –70 –80 0.02 0 –0.02 –0.04 –90 –0.06 –100 –120 5m 10m 100m 1 INPUT LEVEL (V rms) 5 –0.10 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 FREQUENCY (Hz) Figure 11. ADC Pass-Band Ripple at fS = 48 kHz Figure 8. THD + N vs. Input Amplitude Rev. 0 | Page 10 of 44 11408-011 –0.08 –110 11408-008 THD + N (dBFS) –30 Data Sheet ADAU1979 0 –10 –20 –40 –50 –60 –70 –80 –90 –100 0 5000 10000 15000 20000 25000 30000 35000 40000 FREQUENCY (Hz) 11408-012 MAGNITUDE (dB) –30 Figure 12. ADC Filter Stop-Band Response at fS = 48 kHz Rev. 0 | Page 11 of 44 ADAU1979 Data Sheet THEORY OF OPERATION The ADAU1979 incorporates four high performance ADCs and a phase-locked loop (PLL) circuit for generating the necessary on-chip clock signals. POWER SUPPLY AND VOLTAGE REFERENCE The ADAU1979 requires a single 3.3 V power supply. Decouple all AVDDx pins to the nearest AGNDx pin with 100 nF ceramic chip capacitors placed as near the AVDDx pins as possible to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 10 μF must be provided on the same PCB as the ADC. It is important that the analog supply be as clean as possible for best performance. The supply voltage for the digital core (DVDD) is generated using an internal low dropout regulator. The typical DVDD output is 1.8 V and must be decoupled using a 100 nF ceramic capacitor and a 10 µF capacitor. Place the 100 nF ceramic capacitor as near the DVDD pin as possible. The voltage reference for the analog blocks is generated internally and output at the VREF pin (Pin 2). The typical voltage at the VREF pin is 1.5 V with an AVDDx of 3.3 V. All digital inputs are compatible with TTL and CMOS levels. All outputs are driven from the IOVDD supply. The IOVDD can be in the 1.8 V to 3.3 V range. The IOVDD pin must be decoupled with a 100 nF capacitor placed as near the IOVDD pin as possible. The ADC internal voltage reference is output from the VREF pin and must be decoupled using a 100 nF ceramic capacitor in parallel with a 10 µF capacitor. The VREF pin has limited current capability. The voltage reference is used as a reference to the ADC; therefore, it is recommended not to draw current from this pin for external circuits. When using this reference, use a noninverting amplifier buffer to provide a reference to other circuits in the application. In reset mode, the VREF pin is disabled to save power and is enabled only when the PD/RST pin is pulled high. POWER-ON RESET SEQUENCE The ADAU1979 requires that a single 3.3 V power supply be provided externally at the AVDDx pin. The device internally generates DVDD (1.8 V), which is used for the digital core of the ADC. The DVDD supply output pin (Pin 10) is provided to connect the decoupling capacitors to DGND. The typical recommended values for the decoupling capacitors are 100 nF in parallel with 10 µF. During a reset, the DVDD regulator is disabled to reduce power consumption. After the PD/RST pin (Pin 6) is pulled high, the device enables the DVDD regulator. However, the internal ADC and digital core reset are controlled by the internal power-on reset (POR) signal circuit, which monitors the DVDD level. Therefore, the device does not exit a reset until DVDD reaches 1.2 V and the POR signal is released. The DVDD settling time depends on the charge-up time for the external capacitors and on the AVDDx ramp-up time. The internal POR circuit is provided with hysteresis to ensure that a reset of the device is not initiated by an instantaneous glitch on DVDD. The typical trip points are 1.2 V with PD/RST high and 0.6 V (±20%) with PD/RST low. This ensures that the core is not reset until the DVDD level falls below the 0.6 V trip point. As soon as the PD/RST pin is pulled high, the internal regulator starts charging up CEXT on the DVDD pin. The DVDD charge-up time is based on the output resistance of the regulator and the external decoupling capacitor. The time constant can be calculated as tC = ROUT × CEXT where ROUT = 20 Ω typical. For example, if CEXT is 10 µF, tC is 200 µs and is the time that it takes to reach the DVDD voltage, within 63.6%. The power-on reset circuit releases an internal reset of the core when DVDD reaches 1.2 V (see Figure 13). Therefore, it is recommended to wait for at least the tC period to elapse before sending I2C or SPI control signals. AVDDx PD/RST tRESET tC DVDD (1.8V) 1.2V tD 0.48V 11408-013 OVERVIEW POR Figure 13. Power-On Reset Timing When applying a hardware reset to the device by pulling the PD/RST pin (Pin 6) low and then high, there are certain time restrictions. During the PD/RST low pulse period, the DVDD starts discharging. The discharge time constant is determined by the internal resistance of the regulator and CEXT. Use the following equation to estimate the time required for DVDD to fall from 1.8 V to 0.48 V (0.6 V − 20%): tD = 1.32 × RINT × CEXT where RINT = 64 kΩ typical. (RINT can vary due to process by ±20%.) For example, if CEXT is 10 µF, tD is 0.845 sec. Depending on CEXT, tD may vary and, in turn, affect the minimum hold period for the PD/RST pulse. The PD/RST pulse must be held low for the entire tD time period to initialize the core properly. Rev. 0 | Page 12 of 44 Data Sheet ADAU1979 The PLL_LOCK bit (Bit 7) of Register 0x01 indicates the lock status of the PLL. It is recommended that the PLL lock status be read after initial power-up to ensure that the PLL outputs the correct frequency before unmuting the audio outputs. tD = 1.32 × REQ × CEXT where REQ = 64 kΩ || REXT. The resistor ensures that DVDD not only discharges quickly during a reset or an AVDDx power loss but also resets the internal blocks correctly. Note that some power loss in this resistor is to be expected because the resistor constantly draws current from DVDD. The typical value for CEXT is 10 µF and 3 kΩ for REXT. This results in a time constant of tD = 1.32 × REQ × CEXT = 37.8 ms where REQ = 2.866 kΩ (64 kΩ || 3 kΩ). Using this equation at a set CEXT value, the REXT can be calculated for a desired PD/RST pulse period. There is also a software reset bit (S_RST, Bit 7 of Register 0x00) available that can be used to reset the part, but note that during an AVDDx power loss, the software reset may not ensure proper initialization because DVDD may not be stable. +3.3V AVDD1 AVDD3 AVDD2 3.3V TO 1.8V REGULATOR TO INTERNAL BLOCKS DVDD C 0.1µF CEXT 10µF MLCC X7R REXT 3kΩ +1.8V OR +3.3V IOVDD C 0.1µF 11408-114 ADAU1979 Figure 14. DVDD Regulator Output Connections PLL AND CLOCK The ADAU1979 has a built-in analog PLL to provide a jitter-free master clock to the internal ADC. The PLL must be programmed for the appropriate input clock frequency. The PLL_CONTROL Register 0x01 sets the PLL. The CLK_S bit (Bit 4) of Register 0x01 sets the clock source for the PLL. The clock source can be either the MCLKIN pin or the LRCLK pin (slave mode). In LRCLK mode, the PLL supports sample rates between 32 kHz and 192 kHz. In MCLK input mode, the MCS bits (Bits[2:0] of Register 0x01) must be set to the desired input clock frequency for the MCLKIN pin. Table 9 shows the master clock input frequency required for the most common sample rates and the MCS bit settings. Table 9. Required Master Clock Input Frequency for Common Sample Rates MCS (Bits[2:0]) 000 001 010 011 100 000 001 010 011 100 000 001 010 011 100 000 001 010 011 100 000 001 010 011 100 fS (kHz) 32 32 32 32 32 44.1 44.1 44.1 44.1 44.1 48 48 48 48 48 96 96 96 96 96 192 192 192 192 192 Frequency Multiplication Ratio 128 × fS 256 × fS 384 × fS 512 × fS 768 × fS 128 × fS 256 × fS 384 × fS 512 × fS 768 × fS 128 × fS 256 × fS 384 × fS 512 × fS 768 × fS 64 × fS 128 × fS 192 × fS 256 × fS 384 × fS 32 × fS 64 × fS 96 × fS 128 × fS 192 × fS MCLKIN Frequency (MHz) 4.096 8.192 12.288 16.384 24.576 5.6448 11.2896 16.9344 22.5792 33.8688 6.144 12.288 18.432 24.576 36.864 6.144 12.288 18.432 24.576 36.864 6.144 12.288 18.432 24.576 36.864 The PLL can accept the audio frame clock (sample rate clock) as the input, but the serial port must be configured as a slave, and the frame clock must be fed to the device from the master. It is strongly recommended that the PLL be disabled, reprogrammed with the new setting, and then reenabled. A lock bit is provided that is polled via I2C to check whether the PLL has acquired lock. The PLL requires an external filter, which is connected at the PLL_FILT pin (Pin 3). The recommended PLL filter circuit for MCLK or LRCLK mode is shown in Figure 15. Using NPO capacitors is recommended for temperature stability. Place the filter components near the device for best performance. AVDDx AVDDx 39nF 4.87kΩ PLL_FILT 5.6nF 2.2nF 1kΩ PLL_FILT LRCLK MODE MCLK MODE Figure 15. PLL Filter Rev. 0 | Page 13 of 44 390pF 11408-014 Reduce the required PD/RST low pulse period by adding a resistor across CEXT. Calculate the new tD value c as ADAU1979 Data Sheet 14.3kΩ ANALOG INPUTS The block diagram shown in Figure 16 represents the typical input circuit. In most audio applications, the dc content of the signal is removed by using a coupling capacitor. However, the ADAU1979 consists of a unique input structure that allows ac coupling of the input signals. The typical input resistance is approximately 32 kΩ from each input to AGNDx. The high-pass filter has a 1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate. The cutoff frequency scales directly with the sample frequency. However, care is required in dc-coupled applications to ensure that the common-mode dc voltage does not exceed the specified limit. The input required for the fullscale ADC output (0 dBFS) is typically 4.5 V rms differential. Rev. 0 | Page 14 of 44 AINxP VREF AINxN 32.17kΩ 14.3kΩ VID = V INPUT DIFFERENTIAL VCM AT AINxP/AINxN = 1.5V Figure 16. Analog Input Block 11408-015 The ADAU1979 has four differential analog inputs. The ADCs can accommodate both dc- and ac-coupled input signals. 32.17kΩ Data Sheet ADAU1979 Line Inputs Refer to Figure 18 for information about connecting the line level inputs to the ADAU1979. This section describes some of the possible methods to connect the line level inputs of the ADAU1979. Line Input Unbalanced or Single-Ended, Pseudo Differential AC-Coupled Case Line Input Balanced or Differential Input DC-Coupled Case For a single-ended application, reduce the signal swing by half because only one input is used for the signal and the other is connected to 0 V. Doing this reduces the input signal capability to 2.25 V rms in the single-ended application and measures approximately −6.16 dBFS (ac only with a dc high-pass filter) at the ADC output. For an input signal of 4.5 V rms differential with approximately 1.5 V common-mode dc, the signal at each input pin has a 2.25 V rms or 6.36 V p-p signal swing. At a common-mode dc of 1.5 V, the signal can swing between (1.5 + 3.18) = 4.68 V and (1.5 – 3.18) = −1.68 V at each input. Therefore, this is approximately 12.72 V p-p differential across AINx and AINx and measures near 0 dBFS (ac only with a dc high-pass filter) at the ADC output (see Figure 17). See Figure 19 for additional information. The value of C1/C2 is similar to the balanced ac-coupled case previously mentioned in the Line Input Balanced or Differential Input AC-Coupled Case section. Line Input Balanced or Differential Input AC-Coupled Case For connecting the ADAU1979 to a head unit amplifier output, ac coupling is recommended. In this case, the AINx/AINx pins are at a common-mode level of 1.5 V. Use the attenuator to reduce the input level if it is more than 4.5 V rms. Use the following equation to identify the C1 and C2 values for the required low frequency cutoff: C1 or C2 = 1/(2 × π × fC × Input Resistance) where the Input Resistance of the ADAU1979 is 32.17 kΩ typical. TYPICAL AUDIO POWER AMPLIFIER OUTPUT AINx VDIFF = 4.5V rms AC VCM = 1.5V DC 11408-016 AINx OPTION A: DIFFERENTIAL DC-COUPLED Figure 17. Connecting the Line Level Inputs—Differential DC-Coupled Case TYPICAL AUDIO POWER AMPLIFIER OUTPUT C1 AINx ATTENUATOR AINx VDIFF = 2V rms OPTION B: DIFFERENTIAL AC-COUPLED Figure 18. Connecting the Line Level Inputs—Differential AC-Coupled Case TYPICAL AUDIO POWER AMPLIFIER OUTPUT C2 AINx AINx VIN = 2V rms AC OPTION C: PSEUDO DIFFERENTIAL AC-COUPLED Figure 19. Connecting the Line Level Inputs—Pseudo Differential AC-Coupled Case Rev. 0 | Page 15 of 44 11408-018 C1 11408-017 C2 ADAU1979 Data Sheet ADC 1-Channel Summing Mode The ADAU1979 contains four Σ-Δ ADC channels configured as two stereo pairs with configurable differential/single-ended inputs. The ADC can operate at a nominal sample rate of 32 kHz up to 192 kHz. The ADCs include on-board digital antialiasing filters with 79 dB stop-band attenuation and linear phase response. Digital outputs are supplied through two serial data output pins (one for each stereo pair) and a common frame clock (LRCLK) and bit clock (BCLK). Alternatively, one of the TDM modes can be used to support up to 16 channels on a single TDM data line. When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are set to 10, the Channel 1 through Channel 4 ADC data are combined and output from the SDATAOUT1 pin. As a result, the SNR improves by 6 dB. For this mode, all four channels must be connected to the same input signal source. TYPICAL STEREO OUTPUT With smaller amplitude input signals, a 10-bit programmable digital gain compensation for an individual channel is provided to scale up the output word to full scale. Take care to avoid overcompensation (large gain compensation), which leads to clipping and THD degradation in the ADC. The ADCs also have a dc offset calibration algorithm to null the systematic dc offset of the ADC. This feature is useful for dc measurement applications. ADC SUMMING MODES 2-Channel Summing Mode When the SUM_MODE bits (Bits[7:6] of Register 0x0E) are set to 01, the Channel 1 and Channel 2 ADC data are combined and output from the SDATAOUT1 pin. Similarly, the Channel 3 and Channel 4 ADC data are combined and output from the SDATAOUT2 pin. As a result, the SNR improves by 3 dB. For this mode, both Channel 1 and Channel 2 must be connected to the same input signal source. Similarly, Channel 3 and Channel 4 must be connected to the same input signal source. OPTION B: DIFFERENTIAL AC-COUPLED VDIFF = 4.5V rms C1 AIN1 AIN1 C2 Σ AIN2 AIN2 C3 VDIFF = 4.5V rms C1 AIN1 AIN1 C2 AIN2 AIN2 Σ AIN3 AIN3 AIN4 AIN3 AIN3 C4 Σ AIN4 11408-019 AIN4 Figure 20. 2-Channel Summing Mode Connection Diagram Rev. 0 | Page 16 of 44 AIN4 11408-020 The four ADCs can be grouped into either a single stereo ADC or a single mono ADC to increase the SNR for the application. Two options are available: one option for summing two channels of the ADC and another option for summing all four channels of the ADC. Summing is performed in the digital block. TYPICAL STEREO OUTPUT OPTION B: DIFFERENTIAL AC-COUPLED Figure 21. 1-Channel Summing Mode Connection Diagram Data Sheet ADAU1979 Stereo Mode SERIAL AUDIO DATA OUTPUT PORTS, DATA FORMAT The serial audio port comprises four pins: BCLK, LRCLK, SDATAOUT1, and SDATAOUT2. The ADAU1979 ADC outputs are available on the SDATAOUT1 and SDATAOUT2 pins in serial format. The BCLK and LRCLK pins serve as the bit clock and frame clock, respectively. The port can be operated as a master or slave and can be set either in stereo mode (2-channel mode) or in TDM multichannel mode. The supported popular audio formats are I2S, left justified (LJ), and right justified (RJ). In 2-channel or stereo mode, the SDATAOUT1 outputs ADC data for Channel 1 and Channel 2, and the SDATOUT2 outputs ADC data for Channel 3 and Channel 4. Figure 22 through Figure 24 show the supported audio formats. BCLK LRCLK SDATAOUT1 (I2S MODE) CHANNEL 1 CHANNEL 2 8 TO 32 BCLKs 8 TO 32 BCLKs CHANNEL 4 CHANNEL 3 11408-024 SDATAOUT2 (I2S MODE) NOTES 1. SAI = 0. 2. SDATA_FMT = 0 (I2S). Figure 22. I2S Audio Format BCLK LRCLK SDATAOUT2 (LJ MODE) CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 11408-025 SDATAOUT1 (LJ MODE) NOTES 1. SDATA_FMT = 1 (LJ). Figure 23. Left Justified Audio Format BCLK LRCLK CHANNEL 1 SDATAOUT2 (RJ MODE) CHANNEL 3 CHANNEL 2 CHANNEL 4 11408-026 SDATAOUT1 (RJ MODE) NOTES 1. SDATA_FMT = 2 (RJ, 24-BIT). Figure 24. Right Justified Audio Format Rev. 0 | Page 17 of 44 ADAU1979 Data Sheet TDM Mode (Figure 27 shows the TDM mode slot assignments). During the unused slots, the output pin becomes high-Z so that the same data line can be shared with other devices on the TDM bus. Register 0x05 through Register 0x08 provide programmability for the TDM mode. The TDM slot width, data width, and channel assignment, as well as the pin used to output the data, are programmable. The TDM port can be operated as either a master or a slave. In master mode, the BCLK and LRCLK pins are output from the ADAU1979, whereas in slave mode, the BCLK and LRCLK pins are set to receive the clock from the master in the system. By default, serial data is output on the SDATAOUT1 pin; however, the SDATA_SEL bit (Bit 7 of Register 0x06) can be used to change the setting so that serial data is output from the SDATAOUT2 pin. Both the nonpulse and pulse modes are supported. In nonpulse mode, the LRCLK signal is typically 50% of the duty cycle, whereas in pulse mode, the LRCLK signal must be at least one BCLK wide (see Figure 25 and Figure 26). The TDM mode supports two, four, eight, or 16 channels. The ADAU1979 outputs four channels of data in the assigned slots BCLK 32/24/16 BCLKs 32/24/16 BCLKs 32/24/16 BCLKs LRCLK CHANNEL 1 SDATA I 2S CHANNEL 2 8 TO 32 BCLKs 8 TO 32 BCLKs CHANNEL N 8 TO 32 BCLKs SDATA LJ 8 TO 32 BCLKs 8 TO 32 BCLKs CHANNEL 1 SDATA I 2S 8 TO 32 BCLKs CHANNEL 2 24 OR 16 BCLKs CHANNEL N 24 OR 16 BCLKs 24 OR 16 BCLKs 11408-027 NOTES 1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS). 2. SDATA_FMT = 00 (I2S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT). 3. BCLK_EDGE = 0. 4. LR_MODE = 0. 5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs). Figure 25. TDM Nonpulse Mode Audio Format BCLK 32/24/16 BCLKs 32/24/16 BCLKs 32/24/16 BCLKs LRCLK CHANNEL N CHANNEL 2 CHANNEL 1 SDATA I 2S 8 TO 32 BCLKs 8 TO 32 BCLKs 8 TO 32 BCLKs SDATA LJ SDATA I 2S 8 TO 32 BCLKs 8 TO 32 BCLKs 8 TO 32 BCLKs CHANNEL 1 CHANNEL 2 24 OR 16 BCLKs 24 OR 16 BCLKs 24 OR 16 BCLKs 11408-028 NOTES 1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS) 2. SDATA_FMT = 00 (I2S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT) 3. BCLK_EDGE = 0 4. LR_MODE = 1 5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs) CHANNEL N Figure 26. TDM Pulse Mode Audio Format Rev. 0 | Page 18 of 44 Data Sheet ADAU1979 LRCLK NUMBER OF BCLK CYCLES = (NUMBER OF BCLKs/SLOT) × NUMBER OF SLOTS BCLK SDATAOUTx—TDM2 SLOT1 SDATAOUTx—TDM4 SLOT1 SLOT2 SLOT1 SLOT1 HIGH-Z SLOT2 DATA WIDTH 16/24 BITS SLOT2 SLOT3 SLOT4 SLOT3 SLOT3 SLOT5 SLOT4 SLOT6 SLOT7 SLOT5 SLOT8 SLOT9 SLOT10 SLOT4 SLOT6 SLOT11 SLOT12 SLOT7 SLOT13 SLOT8 SLOT14 SLOT15 SLOT16 HIGH-Z 11408-029 SDATAOUTx—TDM8 SDATAOUTx—TDM16 SLOT2 SLOT WIDTH 16/24/32 BITS Figure 27. TDM Mode Slot Assignment Table 10. Bit Clock Frequency TDM Mode Mode TDM2 TDM4 TDM8 TDM16 BCLK Frequency 24 Bit Clocks Per Slot 48 × fS 96 × fS 192 × fS 384 × fS 16 Bit Clocks Per Slot 32 × fS 64 × fS 128 × fS 256 × fS The bit clock frequency depends on the sample rate, the slot width, and the number of bit clocks per slot. Use Table 10 to calculate the BCLK frequency. The sample rate (fS) can range from 8 kHz up to 192 kHz. However, in master mode, the maximum bit clock frequency (BCLK) is 24.576 MHz. For example, for a sample rate of 192 kHz, 128 × fS is the maximum possible BCLK frequency. Therefore, only 128-bit clock cycles are available per TDM 32 Bit Clocks Per Slot 64 × fS 128 × fS 256 × fS 512 × fS frame. There are two options in this case: either operate with a 32-bit data width in TDM4 or operate with a 16-bit data width in TDM8. In slave mode, this limitation does not exist because the bit clock and frame clock are fed to the ADAU1979. Various combinations of BCLK frequencies and modes are available, but take care to choose the combination that is most suitable for the application. Rev. 0 | Page 19 of 44 ADAU1979 Data Sheet Connection Options Figure 28 through Figure 32 show the available options for connecting the serial audio port in I2S or TDM mode. In TDM mode, it is recommended to include a pull-down resistor on the data signal to prevent the line from floating when the SDATAOUTx pin of the ADAU1979 becomes high-Z during an inactive period. Select a resistor value such that no more than 2 mA is drawn from the SDATAOUTx pin. Although the resistor value is typically in the 10 kΩ to 47 kΩ range, the appropriate resistor value depends on the devices on the data bus. SLAVE SLAVE ADAU1979 DSP BCLK LRCLK SDATAOUTx MASTER ADAU1979 OR SIMILAR ADC MASTER SLAVE BCLK ADAU1979 DSP LRCLK 11408-034 SDATAOUTx BCLK LRCLK Figure 31. Serial Port Connection Option 4—TDM Mode, Second ADC Master 11408-030 SDATAOUT1 SDATAOUT2 Figure 28. Serial Port Connection Option 1—I2S/Left Justified/Right Justified Modes, ADAU1979 Master SLAVE MASTER ADAU1979 DSP SLAVE MASTER ADAU1979 DSP BCLK LRCLK SDATAOUTx BCLK LRCLK SLAVE ADAU1979 11408-033 SDATAOUT1 OR SIMILAR ADC BCLK Figure 29. Serial Port Connection Option 2—I2S/Left Justified/Right Justified Modes, ADAU1979 Slave LRCLK SDATAOUTx MASTER SLAVE ADAU1979 DSP 11408-032 SDATAOUT2 Figure 32. Serial Port Connection Option 5—TDM Mode, DSP Master BCLK LRCLK SDATAOUTx SLAVE ADAU1979 OR SIMILAR ADC BCLK SDATAOUTx 11408-031 LRCLK Figure 30. Serial Port Connection Option 3—TDM Mode, ADAU1979 Master Rev. 0 | Page 20 of 44 Data Sheet ADAU1979 CONTROL PORTS The ADAU1979 control port allows two modes of operation, either 2-wire I2C mode or 4-wire SPI mode, for setting the internal registers of the device. Both the I2C and SPI modes allow read and write capability of the registers. All the registers are eight bits wide. The registers start at Address 0x00 and end at Address 0x1A. The control port in both I2C and SPI modes is slave only and, therefore, requires the master in the system to operate. The registers can be accessed with or without the master clock to the device. However, to operate the PLL, serial audio ports, and boost converter, the master clock is necessary. By default, the ADAU1979 operates in I2C mode, but the device can be put into SPI mode by pulling the CLATCH pin low three times. ADDR1 and ADDR0 pins, which set the chip address to the desired value. The 7-bit I2C device address can be set to one of four of the following possible options using the ADDR1 and ADDR0 pins: • • • • I2C Device Address 0010001 (0x11) I2C Device Address 0110001 (0x31) I2C Device Address 1010001 (0x51) I2C Device Address 1110001 (0x71) In I2C mode, both the SDA and SCL pins require that an appropriate pull-up resistor be connected to IOVDD. Ensure that the voltage on these signal lines does not exceed the voltage on the IOVDD pin. Figure 44 shows a typical connection diagram for the I2C mode. The control port pins are multifunctional, depending on the mode in which the device is operating. Table 12 describes the control port pin functions in both modes. Calculate the value of the pull-up resistor for the SDA or SCL pin as follows. I2C MODE where: IOVDD is the I/O supply voltage, typically ranging from 1.8 V up to 3.3 V. VIL is the maximum voltage at Logic Level 0 (that is, 0.4 V, as per the I2C specifications). ISINK is the current sink capability of the I/O pin. Minimum RPULL UP = (IOVDD − VIL)/ISINK The ADAU1979 supports a 2-wire serial (I2C-compatible) bus protocol. Two pins, serial data (SDA) and serial clock (SCL), are used to communicate with the system I2C master controller. In I2C mode, the ADAU1979 is always a slave on the bus, meaning that it cannot initiate a data transfer. Each slave device on the I2C bus is recognized by a unique device address. The device address and R/W byte for the ADAU1979 are shown in Table 11. The address resides in the first seven bits of the I2C write. Bit 7 and Bit 6 of the I2C address for the ADAU1979 are set by the levels on the ADDR1 and ADDR0 pins. The LSB of the first I2C byte (the R/W bit) from the master identifies whether it is a read or write operation. Logic Level 1 in the LSB (Bit 0) corresponds to a read operation, and Logic Level 0 corresponds to a write operation. Table 11. I2C First Byte Format Bit 7 ADDR1 Bit 6 ADDR0 Bit 5 1 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 1 Bit 0 R/W The first seven bits of the I2C chip address for the ADAU1979 are xx10001. Set Bit 7 and Bit 6 of the address byte using the The SDA pin can sink 2 mA of current; therefore, the minimum value of RPULL UP for an IOVDD of 3.3 V is 1.5 kΩ. Depending on the capacitance of the printed circuit board, the speed of the bus can be restricted to meet the rise time and fall time specifications. For fast mode with a bit rate of around 1 Mbps, the rise time must be less than 550 ns. Use the following equation to determine whether the rise time specification can be met: t = 0.8473 × RPULL UP × CBOARD where CBOARD must be less than 236 pF to meet the 300 ns rise time requirement. For the SCL pin, the calculations depend on the current sink capability of the I2C master used in the system. Table 12. Control Port Pin Functions I2C Mode Pin No. 17 18 19 20 Mnemonic SDA/COUT SCL/CCLK ADDR0/CLATCH ADDR1/CIN Pin Function SDA data SCL clock I2C Device Address Bit 0 I2C Device Address Bit 1 Rev. 0 | Page 21 of 44 Pin Type I/O I I I SPI Mode Pin Function COUT data CCLK clock CLATCH chip select CIN data Pin Type O I I I ADAU1979 Data Sheet Addressing The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master is to write information to the slave, whereas a Logic 1 means that the master is to read information from the slave after writing the address and repeating the start address. A data transfer takes place until a master initiates a stop condition. A stop condition occurs when SDA transitions from low to high while SCL is held high. Initially, each device on the I C bus is in an idle state and monitors the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All devices on the bus respond to the start condition and acquire the next eight bits from the master (the 7-bit address plus the R/W bit) MSB first. The master sends the 7-bit device address with the R/W bit to all the slaves on the bus. The device with the matching address responds by pulling the data line (SDA) low during the ninth clock pulse. This ninth bit is known as an acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. 2 0 1 2 3 4 5 6 7 8 9 10 11 12 Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence during normal read and write operations, the ADAU1979 immediately jumps to the idle condition. Figure 33 and Figure 34 use the following abbreviations: ACK = acknowledge No ACK = no acknowledge 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SCL 1 0 0 0 SECOND BYTE (REGISTER ADDRESS) 1 THIRD BYTE (DATA) R/W ACK ADAU1979 START STOP ACK ADAU1979 2 Figure 33. I C Write to ADAU1979 Single Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SCL FIRST BYTE (DEVICE ADDRESS) ADDR1 ADDR0 SDA 1 0 0 0 SECOND BYTE (REGISTER ADDRESS) R/W 1 19 ACK ADAU1979 ACK ADAU1979 START 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 SCL THIRD BYTE (DEVICE ADDRESS) SDA ADDR1 ADDR0 1 0 0 0 DATA BYTE FROM ADAU1979 R/W 1 NO ACK ACK ADAU1979 REPEAT START 2 Figure 34. I C Read from ADAU1979 Single Byte Rev. 0 | Page 22 of 44 STOP 11408-036 ADDR1 ADDR0 11408-035 FIRST BYTE (DEVICE ADDRESS) SDA Data Sheet ADAU1979 I2C Read and Write Operations Figure 35 shows the format of a single-word I C write operation. Every ninth clock pulse, the ADAU1979 issues an acknowledge by pulling SDA low. followed by the chip address byte with the R/W bit set to 1 (read). This causes the ADAU1979 SDA to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU1979. Figure 36 shows the format of a burst mode I2C write sequence. This figure shows an example of a write to sequential single-byte registers. The ADAU1979 increments its address register after every byte because the requested address corresponds to a register or memory area with a 1-byte word length. Figure 38 shows the format of a burst mode I2C read sequence. This figure shows an example of a read from sequential singlebyte registers. The ADAU1979 increments its address registers after every byte because the ADAU1979 uses an 8-bit register address. Figure 37 shows the format of a single-word I2C read operation. Note that the first R/W bit is 0, indicating a write operation. This is because the address still needs to be written to set up the internal address. After the ADAU1979 acknowledges the receipt of the address, the master must issue a repeated start command Figure 35 to Figure 38 use the following abbreviations: S = start bit P = stop bit AM = acknowledge by master AS = acknowledge by slave S CHIP ADDRESS, R/W = 0 AS REGISTER ADDRESS 8 BITS AS DATA BYTE P 11408-037 2 CHIP ADDRESS, R/W = 0 AS REGISTER CHIP ADDRESS ADDRESS, 8 BITS R/W = 0 AS DATA AS BYTE 1 DATA AS DATA BYTE 2 BYTE 3 AS DATA BYTE 4 AS P ... S CHIP ADDRESS, R/W = 0 AS REGISTER ADDRESS 8 BITS AS S AS CHIP ADDRESS, R/W = 1 DATA BYTE 1 P AM ... 11408-039 Figure 36. Burst Mode I2C Write Format Figure 37. Single-Word I2C Read Format S CHIP ADDRESS, R/W = 0 AS REGISTER ADDRESS 8 BITS AS S CHIP ADDRESS, R/W = 1 AS DATA BYTE 1 Figure 38. Burst Mode I2C Read Format Rev. 0 | Page 23 of 44 AM DATA BYTE 2 P 11408-040 S 11408-038 Figure 35. Single-Word I2C Write Format ADAU1979 Data Sheet Register Address SPI MODE By default, the ADAU1979 is in I C mode. To invoke SPI control mode, pull CLATCH low three times. This is achieved by performing three dummy writes to the SPI port (the ADAU1979 does not acknowledge these three writes, see Figure 39). Beginning with the fourth SPI write, data can be written to or read from the device. The ADAU1979 can be taken out of SPI mode only by a full reset initiated by power cycling the device. 2 The SPI port uses a 4-wire interface, consisting of the CLATCH, CCLK, CIN, and COUT signals, and it is always a slave port. The CLATCH signal goes low at the beginning of a transaction and high at the end of a transaction. The CCLK signal latches COUT on a low-to-high transition. COUT data is shifted out of the ADAU1979 on the falling edge of CCLK and is clocked into a receiving device, such as a microcontroller, on the CCLK rising edge. The CIN signal carries the serial input data, and the COUT signal carries the serial output data. The COUT signal remains tristated until a read operation is requested. This allows direct connection to other SPI-compatible peripheral COUT ports for sharing the same system controller port. All SPI transactions have the same basic generic control word format, as shown in Table 15. A timing diagram is shown in Figure 3. Write all data MSB first. The 8-bit address word is decoded to a location in one of the registers. This address is the location of the appropriate register. Data Bytes The number of data bytes varies according to the register being accessed. During a burst mode SPI write, an initial register address is written followed by a continuous sequence of data for consecutive register locations. A sample timing diagram for a single-word SPI write operation to a register is shown in Figure 40. A sample timing diagram of a single-word SPI read operation is shown in Figure 41. The COUT pin transitions being high-Z to being driven at the beginning of Byte 3. In this example, Byte 0 to Byte 1 contain the device address, the R/W bit, and the register address to be read. Subsequent bytes carry the data from the device. Standalone Mode The ADAU1979 can also operate in standalone mode. However, in standalone mode, the boost converter, microphone bias, and diagnostics blocks are powered down. To set the device in standalone mode, pull the SA_MODE pin to IOVDD. In this mode, some pins change functionality to provide more flexibility (see Table 14 for more information). Chip Address R/W Table 14. Pin Functionality in Standalone Mode The LSB of the first byte of an SPI transaction is a R/W bit. This bit determines whether the communication is a read (Logic Level 1) or a write (Logic Level 0). This format is shown in Table 13. Pin Function1 ADDR0 Setting 0 1 Table 13. SPI Address and R/W Byte Format ADDR1 0 1 0 1 0 1 0 1 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 R/W SDA SCL SDATAOUT2 1 Description I2S SAI format TDM modes, determined by the SDATAOUT2 pin Master mode SAI Slave mode SAI MCLK = 256 × fS, PLL on MCLK = 384 × fS, PLL on 48 kHz sample rate 96 kHz sample rate TDM4—LRCLK pulse TDM8—LRCLK pulse Pin functionality, not full pin names, is listed. See Table 12 for additional information. Table 15. Generic Control Word Format Byte 0 Device Address[6:0], R/W 1 Byte 1 Register Address[7:0] Byte 2 Data[7:0] Continues to end of data. Rev. 0 | Page 24 of 44 Byte 3 1 Data[7:0] Data Sheet 0 ADAU1979 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 16 17 18 19 20 21 22 23 24 25 27 CLATCH 11408-041 CCLK CIN Figure 39. SPI Mode Initial Sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 CLATCH DEVICE ADDRESS (7 BITS) 11408-042 CCLK R/W REGISTER ADDRESS BYTE CIN DATA BYTE Figure 40. SPI Write to ADAU1979 Clocking (Single-Word Write Mode) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CCLK CLATCH DEVICE ADDRESS (7 BITS) DATA BYTE R/W DATA BYTE FROM ADAU1979 COUT 11408-043 REGISTER ADDRESS BYTE CIN Figure 41. SPI Read from ADAU1979 Clocking (Single-Word Read Mode) CLATCH CCLK DEVICE ADDRESS BYTE REGISTER ADDRESS BYTE DATA BYTE1 DATA BYTE2 DATA BYTE n – 1 DATA BYTE n DATA BYTE n – 1 DATA BYTE n 11408-044 CIN Figure 42. SPI Write to ADAU1979 (Multiple Bytes) CLATCH CCLK CIN REGISTER ADDRESS BYTE COUT DATA BYTE1 DATA BYTE2 DATA BYTE3 Figure 43. SPI Read from ADAU1979 (Multiple Bytes) Rev. 0 | Page 25 of 44 11408-045 DEVICE ADDRESS BYTE ADAU1979 Data Sheet REGISTER SUMMARY Table 16. REGMAP_ADAU1979 Register Summary Reg 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A Name M_POWER PLL_CONTROL RESERVED RESERVED BLOCK_POWER_SAI SAI_CTRL0 SAI_CTRL1 SAI_CMAP12 SAI_CMAP34 SAI_OVERTEMP POSTADC_GAIN1 POSTADC_GAIN2 POSTADC_GAIN3 POSTADC_GAIN4 MISC_CONTROL RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ASDC_CLIP DC_HPF_CAL Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit 7 S_RST PLL_LOCK Bit 6 Bit 5 Bit 4 Bit 3 RESERVED CLK_S RESERVED RESERVED RESERVED VREF_EN ADC_EN4 SAI DATA_WIDTH LR_MODE Reset 0x00 PLL_MUTE RESERVED MCS 0x41 Reserved Reserved LR_POL BCLKEDGE LDO_EN ADC_EN3 ADC_EN2 ADC_EN1 0x3F SDATA_FMT FS 0x02 SDATA_SEL SLOT_WIDTH SAI_MSB BCLKRATE SAI_MS 0x00 CMAP_C2 CMAP_C1 0x10 CMAP_C4 CMAP_C3 0x32 SAI_DRV_C4 SAI_DRV_C3 SAI_DRV_C2 SAI_DRV_C1 DRV_HIZ RESERVED RESERVED OT 0xF0 PADC_GAIN1 0xA0 PADC_GAIN2 0xA0 PADC_GAIN3 0xA0 PADC_GAIN4 0xA0 SUM_MODE RESERVED MMUTE RESERVED DC_CAL 0x02 RESERVED RESERVED RESERVED RESERVED 0xFF RESERVED RESERVED RESERVED RESERVED RESERVED 0x0F RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0x00 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0x00 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0x00 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0x00 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0x20 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0x00 RESERVED RESERVED RESERVED RESERVED Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Reserved RESERVED ADC_CLIP4 ADC_CLIP3 ADC_CLIP2 ADC_CLIP1 0x00 DC_SUB_C4 DC_SUB_C3 DC_SUB_C2 DC_SUB_C1 DC_HPF_C4 DC_HPF_C3 DC_HPF_C2 DC_HPF_C1 0x00 Rev. 0 | Page 26 of 44 Bit 2 Bit 1 Bit 0 PWUP RW RW RW Reserved Reserved RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Reserved Reserved RW RW Data Sheet ADAU1979 REGISTER DETAILS MASTER POWER AND SOFT RESET REGISTER Address: 0x00, Reset: 0x00, Name: M_POWER The power management control register enables the boost regulator, microphone bias, PLL, band gap reference, ADC, and LDO regulator. Table 17. Bit Descriptions for M_POWER Bits 7 Bit Name S_RST Settings 0 1 [6:1] 0 RESERVED PWUP 0 1 Description Software Reset. The software reset resets all internal circuitry and all control registers to their respective default states. It is not necessary to reset the ADAU1979 during a powerup or power-down cycle. Normal Operation. Software Reset. Reserved. Master Power-Up Control. The master power-up control fully powers up or powers down the ADAU1979. This must be set to 1 to power up the ADAU1979. Individual blocks can be powered down via their respective power control registers. Full Power-Down. Master Power-Up. Rev. 0 | Page 27 of 44 Reset 0x0 Access RW 0x00 0x0 RW RW ADAU1979 Data Sheet PLL CONTROL REGISTER Address: 0x01, Reset: 0x41, Name: PLL_CONTROL Table 18. Bit Descriptions for PLL_CONTROL Bits 7 Bit Name PLL_LOCK Settings 0 1 6 PLL_MUTE 0 1 5 4 RESERVED CLK_S 0 1 3 [2:0] RESERVED MCS 001 010 011 100 000 101 110 111 Description PLL Lock Status. PLL lock status bit. When set to 1, the PLL is locked. PLL Not Locked. PLL Locked. PLL Unlock Automute. When set to 1, it mutes the ADC output if PLL becomes unlocked. No Automatic Mute on PLL Unlock. Automatic Mute with PLL Unlock. Reserved. PLL Clock Source Select. Selecting input clock source for PLL. MCLK Used for PLL Input. LRCLK Used for PLL Input; Only Supported for Sample Rates in the Range of 32 kHz to 192 kHz. Reserved. Master Clock Select. MCS bits determine the frequency multiplication ratio of the PLL. It must be set based on the input MCLK frequency and sample rate. 256 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates). 384 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates). 512 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates). 768 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates). 128 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates). Reserved. Reserved. Reserved. Rev. 0 | Page 28 of 44 Reset 0x0 Access R 0x1 RW 0x0 0x0 RW RW 0x0 0x1 RW RW Data Sheet ADAU1979 BLOCK POWER CONTROL AND SERIAL PORT CONTROL REGISTER Address: 0x04, Reset: 0x3F, Name: BLOCK_POWER_SAI Table 19. Bit Descriptions for BLOCK_POWER_SAI Bits 7 Bit Name LR_POL Settings 0 1 6 BCLKEDGE 0 1 5 LDO_EN 0 1 4 VREF_EN 0 1 3 ADC_EN4 0 1 2 ADC_EN3 0 1 1 ADC_EN2 0 1 0 ADC_EN1 0 1 Description Sets LRCLK Polarity LRCLK Low then High LRCLK High then Low Sets the Bit Clock Edge on Which Data Changes Data Changes on Falling Edge Data Changes on Rising Edge LDO Regulator Enable LDO Powered Down LDO Enabled Voltage Reference Enable Voltage Reference Powered Down Voltage Reference Enabled ADC Channel 4 Enable ADC Channel Powered Down ADC Channel Enabled ADC Channel 3 Enable ADC Channel Powered Down ADC Channel Enabled ADC Channel 2 Enable ADC Channel Powered Down ADC Channel Enabled ADC Channel 1 Enable ADC Channel Powered Down ADC Channel Enabled Rev. 0 | Page 29 of 44 Reset 0x0 Access RW 0x0 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW ADAU1979 Data Sheet SERIAL PORT CONTROL REGISTER 1 Address: 0x05, Reset: 0x02, Name: SAI_CTRL0 Table 20. Bit Descriptions for SAI_CTRL0 Bits [7:6] Bit Name SDATA_FMT Settings 00 01 10 11 [5:3] SAI 000 001 010 011 100 [2:0] FS 000 001 010 011 100 Description Serial Data Format I2S Data Delayed from Edge of LRCLK by 1 BCLK Left Justified Right Justified, 24-Bit Data Right Justified, 16-Bit Data Serial Port Mode Stereo (I2S, LJ, RJ) TDM2 TDM4 TDM8 TDM16 Sampling Rate 8 kHz to 12 kHz 16 kHz to 24 kHz 32 kHz to 48 kHz 64 kHz to 96 kHz 128 kHz to 192 kHz Rev. 0 | Page 30 of 44 Reset 0x0 Access RW 0x0 RW 0x2 RW Data Sheet ADAU1979 SERIAL PORT CONTROL REGISTER 2 Address: 0x06, Reset: 0x00, Name: SAI_CTRL1 Table 21. Bit Descriptions for SAI_CTRL1 Bits 7 Bit Name SDATA_SEL Settings 0 1 [6:5] SLOT_WIDTH 00 01 10 11 4 DATA_WIDTH 0 1 3 LR_MODE 0 1 2 SAI_MSB 0 1 1 BCLKRATE 0 1 0 SAI_MS 0 1 Description SDATAOUTx Pin Selection in TDM4 or Greater Modes SDATAOUT1 used for output SDATAOUT2 used for output Number of BCLKs per Slot in TDM Mode 32 BCLKs per TDM slot 24 BCLKs per TDM slot 16 BCLKs per TDM slot Reserved Output Data Bit Width 24-bit data 16-bit data Sets LRCLK Mode 50% duty cycle clock Pulse—LRCLK is a single BCLK cycle wide pulse Sets Data to be Input/Output Either MSB or LSB First MSB first data LSB first data Sets the Number of Bit Clock Cycles per Data Channel Generated When in Master Mode 32 BCLKs/channel 16 BCLKs/channel Sets the Serial Port into Master or Slave Mode LRCLK/BCLK slave LRCLK/BCLK master Rev. 0 | Page 31 of 44 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1979 Data Sheet CHANNEL 1 AND CHANNEL 2 MAPPING FOR OUTPUT SERIAL PORTS REGISTER Address: 0x07, Reset: 0x10, Name: SAI_CMAP12 Table 22. Bit Descriptions for SAI_CMAP12 Bits [7:4] Bit Name CMAP_C2 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description ADC Channel 2 Output Mapping. Slot 1 for Channel Slot 2 for Channel Slot 3 for Channel (on SDATAOUT2 in stereo modes) Slot 4 for Channel (on SDATAOUT2 in stereo modes) Slot 5 for Channel (TDM8+ only) Slot 6 for Channel (TDM8+ only) Slot 7 for Channel (TDM8+ only) Slot 8 for Channel (TDM8+ only) Slot 9 for Channel (TDM16 only) Slot 10 for Channel (TDM16 only) Slot 11 for Channel (TDM16 only) Slot 12 for Channel (TDM16 only) Slot 13 for Channel (TDM16 only) Slot 14 for Channel (TDM16 only) Slot 15 for Channel (TDM16 only) Slot 16 for Channel (TDM16 only) Rev. 0 | Page 32 of 44 Reset 0x1 Access RW Data Sheet Bits [3:0] Bit Name CMAP_C1 ADAU1979 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description ADC Channel 1 Output Mapping. If CMAP is set to a slot that does not exist for a given serial mode, that channel is not driven. For example, if CMAP is set to Slot 9 and the serial format is I2S, that channel is not driven. If more than one channel is set to the same slot, only the lowest channel number is driven; other channels are not driven. Slot 1 for Channel Slot 2 for Channel Slot 3 for Channel (on SDATAOUT2 in stereo modes) Slot 4 for Channel (on SDATAOUT2 in stereo modes) Slot 5 for Channel (TDM8+ only) Slot 6 for Channel (TDM8+ only) Slot 7 for Channel (TDM8+ only) Slot 8 for Channel (TDM8+ only) Slot 9 for Channel (TDM16 only) Slot 10 for Channel (TDM16 only) Slot 11 for Channel (TDM16 only) Slot 12 for Channel (TDM16 only) Slot 13 for Channel (TDM16 only) Slot 14 for Channel (TDM16 only) Slot 15 for Channel (TDM16 only) Slot 16 for Channel (TDM16 only) Rev. 0 | Page 33 of 44 Reset 0x0 Access RW ADAU1979 Data Sheet CHANNEL 3 AND CHANNEL 4 MAPPING FOR OUTPUT SERIAL PORTS REGISTER Address: 0x08, Reset: 0x32, Name: SAI_CMAP34 Table 23. Bit Descriptions for SAI_CMAP34 Bits [7:4] Bit Name CMAP_C4 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description ADC Channel 4 Output Mapping Slot 1 for Channel Slot 2 for Channel Slot 3 for Channel (on SDATAOUT2 in stereo modes) Slot 4 for Channel (on SDATAOUT2 in stereo modes) Slot 5 for Channel (TDM8+ only) Slot 6 for Channel (TDM8+ only) Slot 7 for Channel (TDM8+ only) Slot 8 for Channel (TDM8+ only) Slot 9 for Channel (TDM16 only) Slot 10 for Channel (TDM16 only) Slot 11 for Channel (TDM16 only) Slot 12 for Channel (TDM16 only) Slot 13 for Channel (TDM16 only) Slot 14 for Channel (TDM16 only) Slot 15 for Channel (TDM16 only) Slot 16 for Channel (TDM16 only) Rev. 0 | Page 34 of 44 Reset 0x3 Access RW Data Sheet Bits [3:0] Bit Name CMAP_C3 ADAU1979 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description ADC Channel 3 Output Mapping Slot 1 for Channel Slot 2 for Channel Slot 3 for Channel (on SDATAOUT2 in stereo modes) Slot 4 for Channel (on SDATAOUT2 in stereo modes) Slot 5 for Channel (TDM8+ only) Slot 6 for Channel (TDM8+ only) Slot 7 for Channel (TDM8+ only) Slot 8 for Channel (TDM8+ only) Slot 9 for Channel (TDM16 only) Slot 10 for Channel (TDM16 only) Slot 11 for Channel (TDM16 only) Slot 12 for Channel (TDM16 only) Slot 13 for Channel (TDM16 only) Slot 14 for Channel (TDM16 only) Slot 15 for Channel (TDM16 only) Slot 16 for Channel (TDM16 only) Reset 0x2 Access RW SERIAL OUTPUT DRIVE CONTROL AND OVERTEMPERATURE PROTECTION STATUS REGISTER Address: 0x09, Reset: 0xF0, Name: SAI_OVERTEMP Table 24. Bit Descriptions for SAI_OVERTEMP Bits 7 Bit Name SAI_DRV_C4 Settings 0 1 Description Channel 4 Serial Output Drive Enable. Channel Not Driven on Serial Output Port. Channel Driven on Serial Output Port. Slot determined by CMAP_C4. Rev. 0 | Page 35 of 44 Reset 0x1 Access RW ADAU1979 Bits 6 Bit Name SAI_DRV_C3 Data Sheet Settings 0 1 5 SAI_DRV_C2 0 1 4 SAI_DRV_C1 0 1 3 DRV_HIZ 0 1 [2:1] 0 RESERVED OT 0 1 Description Channel 3 Serial Output Drive Enable. Channel Not Driven on Serial Output Port. Channel Driven on Serial Output Port. Slot determined by CMAP_C3. Channel 2 Serial Output Drive Enable. Channel Not Driven on Serial Output Port. Channel Driven on Serial Output Port. Slot determined by CMAP_C2. Channel 1 Serial Output Drive Enable. Channel Not Driven on Serial Output Port. Channel Driven on Serial Output Port. Slot determined by CMAP_C1. Select Whether to Tristate Unused SAI Channels or Actively Drive These Data Slots. Unused outputs driven low. Unused outputs high-Z. Reserved Overtemperature Status Normal Operation. Overtemperature Fault. Reset 0x1 Access RW 0x1 RW 0x1 RW 0x0 RW 0x0 0x0 R R POST ADC GAIN CHANNEL 1 CONTROL REGISTER Address: 0x0A, Reset: 0xA0, Name: POSTADC_GAIN1 Table 25. Bit Descriptions for POSTADC_GAIN1 Bits [7:0] Bit Name PADC_GAIN1 Settings 00000000 00000001 00000010 ... 10011111 10100000 10100001 ... 11111110 11111111 Description Channel 1 Post ADC Gain +60 dB Gain +59.625 dB Gain +59.25 dB Gain ... +0.375 dB Gain 0 dB Gain −0.375 dB Gain ... −35.625 dB Gain Mute Rev. 0 | Page 36 of 44 Reset 0xA0 Access RW Data Sheet ADAU1979 POST ADC GAIN CHANNEL 2 CONTROL REGISTER Address: 0x0B, Reset: 0xA0, Name: POSTADC_GAIN2 Table 26. Bit Descriptions for POSTADC_GAIN2 Bits [7:0] Bit Name PADC_GAIN2 Settings 00000000 00000001 00000010 ... 10011111 10100000 10100001 ... 11111110 11111111 Description Channel 2 Post ADC Gain +60 dB Gain +59.625 dB Gain +59.25 dB Gain ... +0.375 dB Gain 0 dB Gain −0.375 dB Gain ... −35.625 dB Gain Mute Reset 0xA0 Access RW Reset 0xA0 Access RW POST ADC GAIN CHANNEL 3 CONTROL REGISTER Address: 0x0C, Reset: 0xA0, Name: POSTADC_GAIN3 Table 27. Bit Descriptions for POSTADC_GAIN3 Bits [7:0] Bit Name PADC_GAIN3 Settings 00000000 00000001 00000010 ... 10011111 10100000 10100001 ... 11111110 11111111 Description Channel 3 Post ADC Gain +60 dB Gain +59.625 dB Gain +59.25 dB Gain ... +0.375 dB Gain 0 dB Gain −0.375 dB Gain ... −35.625 dB Gain Mute Rev. 0 | Page 37 of 44 ADAU1979 Data Sheet POST ADC GAIN CHANNEL 4 CONTROL REGISTER Address: 0x0D, Reset: 0xA0, Name: POSTADC_GAIN4 Table 28. Bit Descriptions for POSTADC_GAIN4 Bits [7:0] Bit Name PADC_GAIN4 Settings 00000000 00000001 00000010 ... 10011111 10100000 10100001 ... 11111110 11111111 Description Channel 4 Post ADC Gain. +60 dB Gain +59.625 dB Gain +59.25 dB Gain ... +0.375 dB Gain 0 dB Gain −0.375 dB Gain ... −35.625 dB Gain Mute HIGH-PASS FILTER AND DC OFFSET CONTROL REGISTER AND MASTER MUTE REGISTER Address: 0x0E, Reset: 0x02, Name: MISC_CONTROL Rev. 0 | Page 38 of 44 Reset 0xA0 Access RW Data Sheet ADAU1979 Table 29. Bit Descriptions for MISC_CONTROL Bits [7:6] Bit Name SUM_MODE Settings 00 01 10 11 5 4 RESERVED MMUTE 0 1 [3:1] 0 RESERVED DC_CAL 0 1 Description Channel Summing Mode Control for Higher SNR Normal 4-Channel Operation 2-Channel Summing Operation (See the ADC Summing Modes Section) 1-Channel Summing Operation (See the ADC Summing Modes Section) Reserved Reserved Master Mute Normal Operation All Channels Muted Reserved DC Calibration Enable Normal Operation Perform DC Calibration Reset 0x0 Access RW 0x0 0x0 RW RW 0x0 0x0 RW RW ADC CLIPPING STATUS REGISTER Address: 0x19, Reset: 0x00, Name: ASDC_CLIP Table 30. Bit Descriptions for ASDC_CLIP Bits [7:4] 3 Bit Name RESERVED ADC_CLIP4 Settings 0 1 2 ADC_CLIP3 0 1 1 ADC_CLIP2 0 1 0 ADC_CLIP1 0 1 Description Reserved ADC Channel 4 Clip Status Normal Operation ADC Channel Clipping ADC Channel 3 Clip Status Normal Operation ADC Channel Clipping ADC Channel 2 Clip Status Normal Operation ADC Channel Clipping ADC Channel 1 Clip Status Normal Operation ADC Channel Clipping Rev. 0 | Page 39 of 44 Reset 0x0 0x0 Access RW R 0x0 R 0x0 R 0x0 R ADAU1979 Data Sheet DIGITAL DC HIGH-PASS FILTER AND CALIBRATION REGISTER Address: 0x1A, Reset: 0x00, Name: DC_HPF_CAL Table 31. Bit Descriptions for DC_HPF_CAL Bits 7 Bit Name DC_SUB_C4 Settings 0 1 6 DC_SUB_C3 0 1 5 DC_SUB_C2 0 1 4 DC_SUB_C1 0 1 3 DC_HPF_C4 0 1 2 DC_HPF_C3 0 1 1 DC_HPF_C2 0 1 0 DC_HPF_C1 0 1 Description Channel 4 DC Subtraction from Calibration No DC Subtraction DC Value from DC Calibration Is Subtracted Channel 3 DC Subtraction from Calibration No DC Subtraction DC Value from DC Calibration Is Subtracted Channel 2 DC Subtraction from Calibration No DC Subtraction DC Value from DC Calibration Is Subtracted Channel 1 DC Subtraction from Calibration No DC Subtraction DC Value from DC Calibration Is Subtracted Channel 4 DC High-Pass Filter Enable HPF Off HPF On Channel 3 DC High-Pass Filter Enable HPF Off HPF On Channel 2 DC High-Pass Filter Enable HPF Off HPF On Channel 1 DC High-Pass Filter Enable HPF Off HPF On Rev. 0 | Page 40 of 44 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Data Sheet ADAU1979 TYPICAL APPLICATION CIRCUIT +3.3V 10µF MLCC X7R C12 0.1µF C13 0.1µF AVDD1 AVDD3 AVDD2 C14 0.1µF 3.3V TO 1.8V REGULATOR AVDD1 AVDD3 ADAU1979 DVDD AIN1 ADC AIN4 ADC AIN4 AGND1 AVDD2 AGND3 I2C/SPI CONTROL BG REF PLL AGND2 AGND2 IOVDD SCL/CCLK SDA/COUT ADDR1/CIN MICROCONTROLLER ADDR0/CLATCH C19 0.1µF PLL_FILT C18 10µF MCLKIN DGND VREF PD/RST AGND1 AGND2 AGND3 AGND4 AGND5 AGND6 R13 R14 NOTES 1. R9, R10 = TYPICAL 2kΩ FOR IOVDD = 3.3V, 1kΩ FOR IOVDD = 1.8V. 2. R11 THROUGH R14 USED FOR SETTING THE DEVICE IN I 2C MODE. 3. R16 = TYPICAL 47kΩ FOR IOVDD = 3.3V, 22kΩ FOR IOVDD = 1.8V. 4. PLL LOOP FILTER: C21 C20 PLL INPUT OPTION R17 +3.3V (AVDD2) R17 C20 C21 LRCLK MCLK 4.87kΩ 2200pF 39nF 1kΩ 390pF 5600pF Figure 44. Typical Application Circuit, Four Inputs, I2C and I2S Mode Rev. 0 | Page 41 of 44 11408-046 LINE4 TO DSP R16 AIN3 R12 AIN3 C7 0.1µF LRCLK BCLK SDATAOUT1 SDATAOUT2 R11 LINE3 ADC IOVDD R9 AIN2 SERIAL AUDIO PORT PROGRAMMABLE GAIN DECIMATOR/HPF DC CALIBRATION AIN2 LINE2 REXT * +1.8V OR +3.3V ADC AIN1 SA_MODE LINE1 C16 10µF MLCC X7R C15 0.1µF R10 REFER TO THE SPECIFICATIONS SECTION FOR THE TYPICAL DIFFERENTIAL INPUT VOLTAGE * FOR MORE INFORMATION ABOUT CALCULATING THE VALUE FOR REXT , SEE THE POWER-ON RESET SEQUENCE SECTION. ADAU1979 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 31 0.50 BSC 1 TOP VIEW 0.80 0.75 0.70 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.05 3.90 SQ 3.75 EXPOSED PAD 21 0.45 0.40 0.35 PIN 1 INDICATOR 40 30 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 05-06-2011-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 45. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 6 mm × 6 mm Body, Very Very Thin Quad (CP-40-14) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 ADAU1979WBCPZ ADAU1979WBCPZ-RL EVAL-ADAU1979Z 1 2 Temperature Range –40°C to +105°C –40°C to +105°C Package Description 40-Lead LFCSP_WQ 40-Lead LFCSP, 13” Tape and Reel Evaluation Board Package Option CP-40-14 CP-40-14 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADAU1979WBCPZ models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. 0 | Page 42 of 44 Data Sheet ADAU1979 NOTES Rev. 0 | Page 43 of 44 ADAU1979 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11408-0-11/13(0) Rev. 0 | Page 44 of 44