ADC10065 10-Bit 65 MSPS 3V A/D Converter General Description Features The ADC10065 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a fullpower bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 68.4 mW at 65 MSPS, including the reference current. The Standby feature reduces power consumption to just 14 .1 mW. n Single +3.0V operation n Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing n 400 MHz −3 dB input bandwidth n Low power consumption n Standby mode n On-chip reference and sample-and-hold amplifier n Offset binary or two’s complement data format n Separate adjustable output driver supply to accommodate 2.5V and 3.3V logic families n 28-pin TSSOP package The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is 10-bit offset binary, or two’s complement. This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40˚C to +85˚C. Key Specifications n n n n n n n n n Resolution Conversion Rate Full Power Bandwidth DNL SNR (fIN = 11 MHz) SFDR (fIN = 11 MHz) Data Latency Supply Voltage Power Consumption, 65 MHz 10 Bits 65 MSPS 400 MHz ± 0.3 LSB (typ) 59.6 dB (typ) −80 dB (typ) 6 Clock Cycles +3.0V 68.4 mW Applications n n n n n n n n Ultrasound and Imaging Instrumentation Cellular Based Stations/Communications Receivers Sonar/Radar xDSL Wireless Local Loops Data Acquisition Systems DSP Front Ends Connection Diagram 20077901 © 2005 National Semiconductor Corporation DS200779 www.national.com ADC10065 10-Bit 65 MSPS 3V A/D Converter May 2005 ADC10065 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) NS Package ADC10065CIMT 28 Pin TSSOP ADC10065CIMTX 28 Pin TSSOP Tape & Reel Block Diagram 20077902 www.national.com 2 ADC10065 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O Inverting analog input signal. With a 1.2V reference the full-scale input signal level is 1.0 VP-P. This pin may be tied to VCOM (pin 4) for single-ended operation. 12 VIN− 13 VIN+ Non-inverting analog input signal. With a 1.2V reference the full-scale input signal level is 1.0 VP-P. 6 VREF Reference input. This pin should be bypassed to VSSA with a 0.1 µF monolithic capacitor. VREF is 1.20V nominal. This pin may be driven by a 1.20V external reference if desired. 7 VREFT 4 VCOM 8 VREFB These pins are high impedance reference bypass pins only. Connect a 0.1 µF capacitor from each of these pins to VSSA. These pins should not be loaded. VCOM may be used to set the input common voltage VCM. DIGITAL I/O 1 CLK 15 DF 28 STBY 5 Digital clock input. The range of frequencies for this input is 20 MHz to 65 MHz. The input is sampled on the rising edge of this input. DF = “1” Two’s Complement DF = “0” Offset Binary This is the standby pin. When high, this pin sets the converter into standby mode. When this pin is low, the converter is in active mode. IRS = “VDDA” 2.0 VP-P input range IRS = “VSSA” 1.5 VP-P input range IRS = “Floating” 1.0 VP-P input range If using both VIN+ and VIN- pins, (or differential mode), then the peak-to-peak voltage refers to the differential voltage (VIN+ - VIN-). IRS (Input Range Select) 3 www.national.com ADC10065 Pin Descriptions and Equivalent Circuits Pin No. Symbol 16–20, 23–27 D0–D9 Equivalent Circuit (Continued) Description Digital output data. D0 is the LSB and D9 is the MSB of the binary output word. ANALOG POWER 2, 9, 10 VDDA Positive analog supply pins. These pins should be connected to a quiet 3.0V source and bypassed to analog ground with a 0.1 µF monolithic capacitor located within 1 cm of these pins. A 4.7 µF capacitor should also be used in parallel. 3, 11, 14 VSSA Ground return for the analog supply. 22 VDDIO Positive digital supply pins for the ADC10065’s output drivers. This pin should be bypassed to digital ground with a 0.1 µF monolithic capacitor located within 1 cm of this pin. A 4.7 µF capacitor should also be used in parallel. The voltage on this pin should never exceed the voltage on VDDA by more than 300 mV. 21 VSSIO The ground return for the digital supply for the output drivers. This pin should be connected to the digital ground, but not near the analog ground. DIGITAL POWER www.national.com 4 Operating Ratings (Notes 1, 2) Operating Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDDA (Supply Voltage) VDDA, VDDIO Package Dissipation at T = 25˚C Clock Duty Cycle See (Note 4) 2500V Machine Model (Note 5) 250V Soldering Temperature Infrared, 10 sec. (Note 6) Storage Temperature 30 to 70 % NOTE: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability. ESD Susceptibility Human Body Model (Note 5) 1.20V ≤ 100 mV |VSSA–VSSIO| ± 25 mA ± 50 mA Package Input Current (Note 3) +2.5V to VDDA VREF −0.3V to VDDA or VDDIO +0.3V Input Current on Any Pin +2.7V to +3.6V VDDIO (Output Driver Supply Voltage) 3.9V Voltage on Any Pin to GND −40˚C ≤ TA ≤ +85˚C 235˚C −65˚C to +150˚C Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (External Supply) fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units STATIC CONVERTER CHARACTERISTICS No Missing Codes Guaranteed 10 Bits INL Integral Non-Linearity (Note 12) FIN = 500 kHz, −0 dB Full Scale DNL Differential Non-Linearity FIN = 500 kHz, −0 dB Full Scale −0.9 GE Gain Error Positive Error −1.5 +0.4 +1.9 % FS Negative Error −1.5 +0.03 +1.9 % FS OE Offset Error (VIN+ = VIN−) −1.4 0.2 +1.7 % FS FPBW −1.0 ± 0.3 +1.1 LSB ± 0.3 +0.9 LSB Under Range Output Code 0 Over Range Output Code 1023 Full Power Bandwidth 400 MHz REFERENCE AND INPUT CHARACTERISTICS VCM Common Mode Input Voltage VCOM Output Voltage for use as an input common mode voltage (Note 17) 1.45 V VREF Reference Voltage 1.2 V VREFTC Reference Voltage Temperature Coefficient ± 80 ppm/˚C 4 pF CIN 0.5 VIN Input Capacitance (each pin to VSSA) 1.5 V POWER SUPPLY CHARACTERISTICS IVDDA Analog Supply Current IVDDIO Digital Supply Current PWR Power Consumption STBY = 1 4.7 6.0 mA STBY = 0 22 29 mA STBY = 1, fIN = 0 Hz 0 mA STBY 0, fIN = 0 Hz 0.97 1.2 mA STBY = 1 14.1 18.0 mW STBY = 0 68.4 90 mW 5 www.national.com ADC10065 Absolute Maximum Ratings ADC10065 DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (Externally Supplied) fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C Symbol Parameter Conditions Min Typ Max Units 0.8 V +10 µA CLK, DF, STBY, SENSE Logical “1” Input Voltage 2 V Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current −10 µA D0–D9 OUTPUT CHARACTERISTICS Logical “1” Output Voltage IOUT = −0.5 mA Logical “0” Output Voltage IOUT = 1.6 mA VDDIO−0.2 V 0.4 V DYNAMIC CONVERTER CHARACTERISTICS ENOB Effective Number of Bits SNR Signal-to-Noise Ratio SINAD Signal-to-Noise Ratio + Distortion 2nd HD 3rd HD THD SFDR www.national.com fIN = 11 MHz Total Harmonic Distortion (First 6 Harmonics) Spurious Free Dynamic Range (Excluding 2nd and 3rd Harmonic) 9.6 Bits fIN = 32 MHz 9.3, 9.2 9.5 Bits fIN = 11 MHz 58.6, 58 59.6 dB fIN = 32 MHz 58.5, 57.9 59.3 dB fIN = 11 MHz 58.3, 57.6 59.4 dB fIN = 32 MHz 58, 57.4 59 dB fIN = 11 MHz −75.6, −69.7 −90 dBc fIN = 32 MHz −72.7, −68.9 −82 dBc fIN = 11 MHz −66.2, −63 −74 dBc −65.4, −63.3 −72 dBc fIN = 11 MHz −66.2, −63 −74 dB fIN = 32 MHz −65.4, −63.3 −72 dB fIN = 11 MHz −75.8, −74.5 −80 dBc fIN = 32 MHz −74.4, −73.3 −80 dBc 2nd Harmonic 3rd Harmonic 9.4, 9.3 fIN = 32 MHz 6 Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (Externally Supplied) fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C Symbol Parameter Conditions Min (Note 12) Typ (Note 12) Max (Note 12) Units 65 MHz (min) CLK, DF, STBY, SENSE fCLK1 Maximum Clock Frequency fCLK2 Minimum Clock Frequency 20 MHz tCH Clock High Time 7.69 ns tCL Clock Low Time 7.69 ns tCONV Conversion Latency tOD Data Output Delay after a Rising Clock Edge tAD Aperture Delay tAJ Aperture Jitter Over Range Recovery Time tSTBY T = 25˚C 2 3.4 1 Differential VIN step from ± 3V to 0V to get accurate conversion Standby Mode Exit Cycle 6 Cycles 5 ns 6 ns 1 ns 2 ps (RMS) 1 Clock Cycle 20 Cycles Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = VSSA = VSSIO = 0V, unless otherwise specified. Note 3: When the voltage at any pin exceeds the power supplies (VIN < VSSA or VIN > VDDA, VDDIO), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. In the 28-pin TSSOP, θJA is 96˚C/W, so PDMAX = 1,302 mW at 25˚C and 677 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this device under normal operation will typically be about 68.6 mW. The values for maximum power dissipation listed above will be reached only when the ADC10065 is operated in a severe fault condition. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR) the following conditions apply: Maintain the temperature at the top of the package body above 183˚C for a minimum of 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above 183˚C is allowed per reflow cycle. The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this device. However, input errors will be generated if the input goes above VDDA or VDDIO and below VSSA or VSSIO. Note 7: VCOM is a typical value, measured at room temperature. It is not guaranteed by test. 20077907 Note 8: To guarantee accuracy, it is required that |VDDA–VDDIO| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. Note 9: With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV. Note 10: Typical figures are at TA = TJ = 25˚C and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. Note 12: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge, and VIH = 2.4V for a rising edge. Note 13: Optimum dynamic performance will be obtained by keeping the reference input in the +1.2V. Note 14: IDDIO is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR x (C0 x f0 + C1 x f1 + C2 + f2 +....C11 x f11) where VDR is the output driver supply voltage, Cn is the total load capacitance on the output pin, and fn is the average frequency at which the pin is toggling. Note 15: Power consumption includes output driver power. (fIN = 0 MHz). Note 16: The input bandwidth is limited using a 10 pF capacitor between VIN− and VIN+. Note 17: VCOM is a typical value, measured at room temperature, and is not guaranteed by test. 7 www.national.com ADC10065 AC Electrical Characteristics ADC10065 PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 11⁄2 LSB below positive full scale. Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC. CONVERSION LATENCY See PIPELINE DELAY. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or dc. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and states that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding dc. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first six harmonic levels at the output to the level of the fundamental at the output. THD is calculated as: FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full-Scale Error − Negative FullScale Error INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2 LSB below the first code transition) through positive full scale (1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC10065 is guaranteed not to have any missing codes. NEGATIVE FULL SCALE ERROR is the difference between the input voltage (VIN+ − VIN−) just causing a transition from negative full scale to the first code and its ideal value of 0.5 LSB. OFFSET ERROR is the input voltage that will cause a transition from a code of 01 1111 1111 to a code of 10 0000 0000. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. www.national.com where f1 is the RMS power of the fundamental (output) frequency and f2 through f6 are the RMS power in the first 6 harmonic frequencies. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. 8 ADC10065 Timing Diagram 20077909 FIGURE 1. Clock and Data Timing Diagram Transfer Characteristics 20077910 FIGURE 2. Input vs. Output Transfer Characteristic 9 www.national.com ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. DNL DNL vs. fCLK 20077912 20077915 DNL vs. Clock Duty Cycle (DC input) DNL vs. Temperature 20077913 20077916 INL INL vs. fCLK 20077917 20077914 www.national.com 10 INL vs. Clock Duty Cycle SNR vs. VDDIO 20077918 20077919 SNR vs. VDDA SNR vs. fCLK 20077920 20077921 INL vs. Temperature SNR vs. Clock Duty Cycle 20077922 20077923 11 www.national.com ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued) ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued) SNR vs. Temperature THD vs. VDDA 20077924 20077925 THD vs. VDDIO THD vs. fCLK 20077926 20077927 SNR vs. IRS THD vs. IRS 20077928 www.national.com 20077929 12 SINAD vs. VDDA SINAD vs. VDDIO 20077930 20077931 THD vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle 20077932 20077933 THD vs. Temperature SINAD vs. Temperature 20077934 20077935 13 www.national.com ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued) ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued) SINAD vs. fCLK SFDR vs. VDDIO 20077936 20077937 SINAD vs. IRS SFDR vs. fCLK 20077939 20077938 SFDR vs. VDDA SFDR vs. IRS 20077940 www.national.com 20077941 14 Spectral Response @ 11 MHz Input SFDR vs. Clock Duty Cycle 20077942 20077943 Spectral Response @ 32 MHz Input SFDR vs. Temperature 20077944 20077945 Power Consumption vs. fCLK 20077946 15 www.national.com ADC10065 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz, fIN = 11 MHz, 50% Duty Cycle. (Continued) ADC10065 Functional Description The ADC10065 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 10 bits. In differential mode, each analog input signal should have a peak-to-peak voltage equal to 1.0V, 0.75V or 0.5V, depending on the state of the IRS pin (pin 5), and be centered around VCM and be 180˚ out of phase with each other. If single ended operation is desired, VIN- may be tied to the VCOM pin (pin 4). A single ended input signal may then be applied to VIN+, and should have an average value in the range of VCM. The signal amplitude should be 2.0V, 1.5V or 1.0V peak-to-peak, depending on the state or the IRS pin (pin 5). 20077948 FIGURE 4. Input Voltage Waveform for a 2VP-P Single Ended Input Applications Information The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving source tries to compensate for this, it adds noise to the signal. To prevent this, use 18Ω series resistors at each of the signal inputs with a 25 pF capacitor across the inputs, as can be seen in Figure 5. These components should be placed close to the ADC because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter the input. The two 18Ω resistors and the 25 pF capacitors form a low-pass filter with a -3 dB frequency of 177 Mhz. 1.0 ANALOG INPUTS The ADC10065 has two analog signal inputs, VIN+ and VIN−. These two pins form a differential input pair. There is one common mode pin VCOM that may be used to set the common mode input voltage. 1.1 REFERENCE PINS The ADC10065 is designed to operate with a 1.2V reference. The voltages at VCOM, VREFT, and VREFB are derived from the reference voltage. It is very important that all grounds associated with the reference voltage and the input signal make connection to the analog ground plane at a single point to minimize the effects of noise currents in the ground path. The three Reference Bypass Pins VREF, VREFT and VREFB, are made available for bypass purposes only. These pins should each be bypassed to ground with a 0.1 µF capacitor. DO NOT LOAD these pins. 1.4 CLK PIN The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the range of 20 MHz to 65 MHz with rise and fall times of less than 2 ns. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90˚. The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency is too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the lowest sample rate to 20 MSPS. The duty cycle of the clock signal can affect the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the ADC10065 is designed to maintain performance over a range of duty cycles. While it is specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over a clock duty cycle range of 40% to 60%. 1.2 VCOM PIN This pin supplies a voltage for possible use to set the common mode input voltage. This pin may also be connected to VIN-, so that VIN+ may be used as a single ended input. This pin should be bypassed with at least a 0.1 uF capacitor. 1.3 SIGNAL INPUTS The signal inputs are VIN+ and VIN−. The input signal amplitude is defined as VIN+ − VIN− and is represented schematically in Figure 3: 1.5 STBY PIN The STBY pin, when high, holds the ADC10065 in a powerdown mode to conserve power when the converter is not being used. The power consumption in this state is 15 mW. The output data pins are undefined in this mode. Power consumption during power-down is not affected by the clock frequency, or by whether there is a clock signal present. The data in the pipeline is corrupted while in the power down. 1.6 DF PIN The DF pin, when high, forces the ADC10065 to output the 2’s complement data format. When DF is tied low, the output format is offset binary. 20077947 FIGURE 3. Input Voltage Waveforms for a 2VP-P differential Input 1.7 IRS PIN The IRS (Input Range Select) pin defines the input signal amplitude that will produce a full scale output. The table below describes the function of the IRS pin. A single ended input signal is shown in Figure 4. www.national.com 16 charging current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 10 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic performance. To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by connecting buffers between the ADC outputs and any other circuitry. Only one driven input should be ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. (Continued) TABLE 1. IRS Pin Functions IRS Pin Full-Scale Input VDDA 2.0VP-P VSSA 1.5VP-P Floating 1.0VP-P 1.8 OUTPUT PINS The ADC10065 has 10 TTL/CMOS compatible Data Output pins. The offset binary data is present at these outputs while the DF and STBY pins are low. While the tOD time provides information about output timing, a simple way to capture a valid output is to latch the data on the rising edge of the conversion clock. Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDDIO and VSSIO. These large 1.9 APPLICATION SCHEMATICS The following figures show simple examples of using the ADC10065. Figure 5 shows a typical differentially driven input. Figure 6 shows a single ended application circuit. 20077949 FIGURE 5. A Simple Application Using a Differential Driving Source 17 www.national.com ADC10065 Applications Information ADC10065 Applications Information (Continued) 20077950 FIGURE 6. A Simple Application Using a Single Ended Driving Source www.national.com 18 ADC10065 10-Bit 65 MSPS 3V A/D Converter Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead TSSOP Package Ordering Number ADC10065CIMT NS Package Number MTC28 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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