High Speed, Isolated RS-485 Transceiver with Integrated Transformer Driver ADM2485 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD1 D1 VDD2 D2 OSC ADM2485 GALVANIC ISOLATION RTS TxD RxD DE OUT A B RE GND2 GND1 06021-001 Half-duplex, isolated RS-485 transceiver Integrated oscillator driver for external transformer PROFIBUS® compliant Complies with ANSI/TIA/EIA RS-485-A-98 and ISO 8482:1987(E) Data rate: 16 Mbps 5 V or 3.3 V operation (VDD1) 50 nodes on bus High common-mode transient immunity: >25 kV/μs Isolated DE OUT status output Thermal shutdown protection Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Reinforced insulation, VIORM = 560 V peak Operating temperature range: –40°C to +85°C Wide-body, 16-lead SOIC package Figure 1. APPLICATIONS Isolated RS-485/RS-422 interfaces PROFIBUS networks Industrial field networks Multipoint data transmission systems GENERAL DESCRIPTION The ADM2485 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines and complies with ANSI/TIA/EIA RS-485-A-98 and ISO 8482:1987(E). The device employs Analog Devices, Inc., iCoupler® technology to combine a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. An on-chip oscillator outputs a pair of square waveforms that drive an external transformer to provide isolated power with an external transformer. The logic side of the device can be powered with either a 5 V or a 3.3 V supply, and the bus side is powered with an isolated 5 V supply. The ADM2485 driver has an active high enable. The driver differential outputs and the receiver differential inputs are connected internally to form a differential input/output port that imposes minimal loading on the bus when the driver is disabled or when VDD1 or VDD2 = 0 V. Also provided is an active high receiver disable that causes the receive output to enter a high impedance state. The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention might cause excessive power dissipation. The part is fully specified over the industrial temperature range and is available in a 16-lead, wide-body SOIC package. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADM2485 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 10 Applications....................................................................................... 1 Test Circuits..................................................................................... 13 Functional Block Diagram .............................................................. 1 Circuit Description......................................................................... 14 General Description ......................................................................... 1 Electrical Isolation...................................................................... 14 Revision History ............................................................................... 2 Truth Tables................................................................................. 14 Specifications..................................................................................... 3 Thermal Shutdown .................................................................... 14 Timing Specifications .................................................................. 5 Receiver Fail-Safe Inputs ........................................................... 14 Package Characteristics ............................................................... 6 Magnetic Field Immunity.......................................................... 15 Regulatory Information............................................................... 6 Applications Information .............................................................. 16 Insulation and Safety-Related Specifications............................ 6 PCB Layout ................................................................................. 16 VDE 0884-2 Insulation Characteristics..................................... 7 Transformer Suppliers ............................................................... 16 Absolute Maximum Ratings............................................................ 8 Applications Diagram................................................................ 16 ESD Caution.................................................................................. 8 Outline Dimensions ....................................................................... 17 Pin Configuration and Function Descriptions............................. 9 Ordering Guide .......................................................................... 17 REVISION HISTORY 12/07—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Features Section............................................................ 1 Changes to Table 4............................................................................ 6 Changes to VDE 0884-2 Insulation Characteristics Section ...... 7 Changes to PCB Section and Figure 34 ....................................... 16 Updated Outline Dimensions ....................................................... 17 1/07—Revision 0: Initial Version Rev. A | Page 2 of 20 ADM2485 SPECIFICATIONS 2.7 V ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DRIVER Differential Outputs Differential Output Voltage, VOD Min Typ Max Unit Test Conditions/Comments 5 5 5 5 0.2 3 0.2 200 200 V V V V V V V mA mA R = ∞, see Figure 21 R = 50 Ω (RS-422), see Figure 21 R = 27 Ω (RS-485), see Figure 21 VTST = –7 V to +12 V, VDD1 ≥ 4.75 V, see Figure 22 R = 27 Ω or 50 Ω, see Figure 21 R = 27 Ω or 50 Ω, see Figure 21 R = 27 Ω or 50 Ω, see Figure 21 −7 V ≤ VOUT ≤ +12 V −7 V ≤ VOUT ≤ +12 V 0.1 0.2 0.1 0.3 0.4 V V V V V V IODE = 20 μA IODE = 1.6 mA IODE = 4 mA IODE = −20 μA IODE = −1.6 mA IODE = −4 mA +0.01 0.25 VDD1 +10 V V μA TxD, RTS, RE TxD, RTS, RE TxD, RTS, RE = VDD1 or 0 V 0.6 −0.35 mV mV kΩ mA mA −7 V ≤ VCM ≤ +12V −7 V ≤ VCM ≤ +12V −7 V ≤ VCM ≤ +12V VIN = +12 V VIN = −7 V 0.1 0.4 85 ±1 V V V V mA μA IOUT = +20 μA, VA − VB = +0.2 V IOUT = +1.5 mA, VA − VB = +0.2 V IOUT = −20 μA, VA − VB = −0.2 V IOUT = −4 mA, VA − VB = −0.2 V VOUT = GND or VCC 0.4 V ≤ VOUT ≤ 2.4 V 600 430 1.5 2.5 kHz kHz Ω V VDD1 = 5.5 V VDD1 = 3.3 V 2.1 2.1 2.1 Δ|VOD| for Complementary Output States Common-Mode Output Voltage, VOC Δ|VOC| for Complementary Output States Output Short-Circuit Current, VOUT = High Output Short-Circuit Current, VOUT = Low Bus Enable Output Output High Voltage 60 60 VDD2 − 0.1 VDD2 − 0.3 VDD2 − 0.4 VDD2 − 0.1 VDD2 − 0.2 Output Low Voltage Logic Inputs Input High Voltage Input Low Voltage CMOS Logic Input Current (TxD, RTS, RE) RECEIVER Differential Inputs Differential Input Threshold Voltage, VTH Input Hysteresis Input Resistance (A, B) Input Current (A, B) RxD Logic Output Output High Voltage 0.7 VDD1 −10 −200 20 VDD1 − 0.1 VDD1 − 0.4 +200 70 30 VDD1 − 0.2 Output Low Voltage 0.2 Output Short-Circuit Current Tristate Output Leakage Current TRANSFORMER DRIVER Oscillator Frequency Switch-On Resistance Start-Up Voltage 7 400 230 500 330 0.5 2.2 Rev. A | Page 3 of 20 ADM2485 Parameter POWER SUPPLY CURRENT Logic Side Min Typ 2.3 5.0 1.26 1.5 2.9 1.7 49.0 Bus Side 55.0 COMMON-MODE TRANSIENT IMMUNITY 1 HIGH FREQUENCY COMMON-MODE NOISE IMMUNITY 1 Max Unit Test Conditions/Comments 2.5 mA mA mA mA mA mA mA mA RTS = 0 V, VDD1 = 5.5 V 2.5 Mbps, VDD1 = 5.5 V, see Figure 23 16 Mbps, VDD1 = 5.5 V, see Figure 23 RTS = 0 V, VDD1 = 3.3 V 2.5 Mbps, VDD1 = 3.3 V, see Figure 23 16 Mbps, VDD1 = 3.3 V, see Figure 23 RTS = 0 V 2.5 Mbps, RTS = VDD1, see Figure 23 for load conditions 16 Mbps, RTS = VDD1, see Figure 23 for load conditions Transient magnitude = 800 V, VCM = 1 kV VHF = +5 V, −2 V < VTEST2 < +7 V, 1 MHz < fTEST < 50 MHz, see Figure 24 6.5 2.5 75.0 25 100 mA kV/μs mV CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. A | Page 4 of 20 ADM2485 TIMING SPECIFICATIONS 2.7 V ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DRIVER Maximum Data Rate Propagation Delay Input-to-Output tPLH, tPHL RTS-to-DE OUT Propagation Delay Driver Output-to-Output, tSKEW Rise/Fall Time, tR, tF Enable Time Disable Time Enable Skew, |tAZH − tBZL|, |tAZL − tBZH| Disable Skew, |tAHZ − tBLZ|, |tALZ − tBHZ| RECEIVER Propagation Delay, tPLH, tPHL Differential Skew, tSKEW Enable Time Disable Time Min Typ Max 16 25 20 25 Unit Test Conditions/Comments Mbps 45 35 2 55 55 5 ns ns ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 25 See Figure 26 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 2 and Figure 25 5 43 43 1 2 15 53 55 3 5 ns ns ns ns ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 2 and Figure 25 See Figure 4 and Figure 27 See Figure 4 and Figure 27 See Figure 4 and Figure 27 See Figure 4 and Figure 27 45 55 5 13 13 ns ns ns ns CL = 15 pF, see Figure 3 and Figure 28 CL = 15 pF, see Figure 3 and Figure 28 RL = 1 kΩ, CL = 15 pF, see Figure 5 and Figure 29 RL = 1 kΩ, CL = 15 pF, see Figure 5 and Figure 29 3 3 Timing Diagrams 3V 1.5V 1.5V 0V tPLH 0.7VDD1 tPHL RTS B 0.5VDD1 0.5VDD1 1/2VOUT VOUT tZL A 10% POINT tR tF VOH + 0.5V VOL tHZ tZH 10% POINT –VOUT 2.3V A–B 90% POINT 90% POINT VOH – 0.5V 2.3V A–B VOH 0V Figure 2. Driver Propagation Delay, Rise/Fall Timing Figure 4. Driver Enable/Disable Timing 0.7VDD1 RE 0.5VDD1 0.5VDD1 0.3VDD1 0V 0V tPLH tPHL tLZ tZL 1.5V RxD VOH VOH + 0.5V OUTPUT LOW VOL tHZ tZH OUTPUT HIGH 1.5V tSKEW = |tPLH – tPHL| 1.5V VOL 06021-013 RxD Figure 3. Receiver Propagation Delay RxD 1.5V VOH – 0.5V 0V Figure 5. Receiver Enable/Disable Timing Rev. A | Page 5 of 20 VOH 06021-015 A–B 06021-014 0V tSKEW = |tPLH – tPHL | 06021-012 +VOUT 0.3VDD1 tLZ ADM2485 PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 Input IC Junction-to-Case Thermal Resistance Symbol RI-O CI-O CI θJCI Output IC Junction-to-Case Thermal Resistance θJCO 1 2 Min Typ 1012 3 4 33 Max 28 Unit Ω pF pF °C/W °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside Thermocouple located at center of package underside Device considered a 2-terminal device: Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION Table 4. ADM2485 Approvals Organization UL Approval Type Recognized under the Component Recognition Program of Underwriters Laboratories, Inc. VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Notes In accordance with UL 1577, each ADM2485 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second (current leakage detection limit = 5 μA). In accordance with DIN V VDE V 0884-10, each ADM2485 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 5. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (External Clearance) Symbol Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group L(I01) Value 2500 5.15 min Unit V rms mm L(I02) 5.5 min mm CTI 0.017 min >175 IIIa mm V Rev. A | Page 6 of 20 Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance along body Insulation distance through insulation DIN IEC 112/VDE 0303-1 Material Group (DIN VDE 0110: 1989-01, Table 1) ADM2485 VDE 0884-2 INSULATION CHARACTERISTICS This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits. An asterisk (*) on packages denotes DIN V VDE V 0884-10 approval. Table 6. Description Installation Classification per DIN VDE 0110 for Rated Mains Voltage ≤150 V rms ≤300 V rms ≤400 V rms Climatic Classification Pollution Degree (DIN VDE 0110: 1989-01, Table 1) Maximum Working Insulation Voltage Input-to-Output Test Voltage Method B1: VIORM × 1.875 = VPR, 100% Production Tested, tm = 1 sec, Partial Discharge < 5 pC Method A (After Environmental Tests, Subgroup 1): VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge <5 pC Method A (After Input and/or Safety Test, Subgroup 2/3): VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge <5 pC Highest Allowable Overvoltage 1 Safety-Limiting Values 2 Case Temperature Input Current Output Current Insulation Resistance at TS 3 1 Symbol Characteristic Unit I to IV I to III I to II 40/85/21 2 560 V peak 1050 V peak 896 V peak VTR 672 4000 V peak V peak TS IS, INPUT IS, OUTPUT RS 150 265 335 >109 °C mA mA Ω VIORM VPR Transient overvoltage, tTR = 10 sec. The safety-limiting value is the maximum value allowed in the event of a failure. See Figure 14 for the thermal derating curve. 3 VIO = 500 V. 2 Rev. A | Page 7 of 20 ADM2485 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective grounds. Table 7. Parameter VDD1 VDD2 Digital Input Voltage (RTS, RE, TxD) Digital Output Voltage RxD DE OUT D1, D2 Driver Output/Receiver Input Voltage Operating Temperature Range Storage Temperature Range Average Output Current per Pin θJA Thermal Impedance Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating −0.5 V to +6 V −0.5 V to +6 V −0.5 V to VDD1 + 0.5 V −0.5 V to VDD1 + 0.5 V −0.5 V to VDD2 + 0.5 V 13 V −9 V to +14 V −40°C to +85°C −55°C to +150°C −35 mA to +35 mA 73°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 300°C 215°C 220°C Rev. A | Page 8 of 20 ADM2485 D1 1 16 VDD2 D2 2 15 GND2 14 GND2 13 B 12 A RE 6 11 GND2 RTS 7 10 DE OUT TxD 8 9 GND2 GND1 3 VDD1 4 RxD 5 ADM2485 TOP VIEW (Not to Scale) 06021-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 6. Pin Configuration Table 8. Pin Function Description Pin No. 1 2 3 4 Mnemonic D1 D2 GND1 VDD1 5 RxD 6 RE 7 8 9, 11, 14, 15 10 12 RTS TxD GND2 DE OUT A 13 B 16 VDD2 Function Transformer Driver Terminal 1. Transformer Driver Terminal 2. Ground, Logic Side. Power Supply, Logic Side (3.3 V or 5 V). Decoupling capacitor to GND1 required; capacitor value should be between 0.01 μF and 0.1 μF. Receiver Output Data. This output is high when (A − B) > 200 mV and low when (A − B) < −200 mV. The output is tristated when the receiver is disabled, that is, when RE is driven high. Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver; driving it high disables the receiver. Driver Enable Input. Driving this input high enables the driver; driving it low disables the driver. Driver Input. Data to be transmitted by the driver is applied to this input. Ground, Bus Side. Driver Enable Status Output. Noninverting Driver Output/Receiver Input. When the driver is disabled or VDD1 or VDD2 is powered down, Pin A is put in a high impedance state to avoid overloading the bus. Inverting Driver Output/Receiver Input. When the driver is disabled or VDD1 or VDD2 is powered down, Pin B is put in a high impedance state to avoid overloading the bus. Power Supply, Bus Side (Isolated 5 V Supply). Decoupling capacitor to GND2 required; capacitor value should be between 0.01 μF and 0.1 μF. Rev. A | Page 9 of 20 ADM2485 TYPICAL PERFORMANCE CHARACTERISTICS 60 DRIVER PROPAGATION DELAY (ns) 2.35 IDD1 _RE_ENABLE_V DD1 = 5.5V 2.25 2.20 2.15 2.10 IDD2 _DE_ENABLE_V DD1 = 5.5V 2.00 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 40 20 10 IDD1 _NO LOAD_TxD = 16Mbps_V DD1 = 5.00V IDD1 _PROFIBUS LOAD_TxD = 2Mbps_VDD1 = 5.00V 2.0 1.5 IDD1 _NO LOAD_TxD = 2Mbps_VDD1 = 5.00V 1.0 –20 0 20 40 60 80 40 60 80 TEMPERATURE (°C) Rx PROP DELAY, tPLH_VDD2 = 5.00V 50 40 Rx PROP DELAY, tPHL _VDD2 = 5.00V 30 20 10 0 –40 06021-017 0.5 0 –40 20 60 IDD1 _PROFIBUS LOAD_TxD = 16Mbps_V DD1 = 5.00V RECEIVER PROPAGATION DELAY (ns) IDD1 SUPPLY CURRENT (mA) 2.5 0 Figure 10. Driver Propagation Delay vs. Temperature 4.0 3.0 –20 TEMPERATURE (°C) 5.0 3.5 tPHLA tPLHB 30 Figure 7. Unloaded Supply Current vs. Temperature 4.5 tPHLB tPLHA 0 –40 06021-016 2.05 50 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 8. Logic Side Supply Current (IDD1 = 1 mA) vs. Temperature 06021-020 SUPPLY CURRENT (mA) 2.30 06021-019 2.40 Figure 11. Receiver Propagation Delay vs. Temperature 60 IDD2 _ PROFIBUS LOAD_TxD = 16Mbps_VDD2 = 5.00V 40 IDD2 _PROFIBUS LOAD_TxD = 2Mbps_VDD2 = 5.00V DI 3 30 B 20 IDD2 _NO LOAD_TxD = 16Mbps_VDD2 = 5.00V 2 IDD2 _NO LOAD_TxD = 2Mbps_VDD2 = 5.00V 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 9. Bus Side Supply Current (IDD2 = 2 mA) vs. Temperature A CH1 2.0V Ω CH2 2.0V Ω M20.0ns 1.25GS/s A CH3 CH3 2.0V Ω IT 8.0ps/pt 2.60V Figure 12. Driver/Receiver Propagation Delay, Low to High (RLDIFF = 54 Ω, CL1 = CL2 = 100 pF) Rev. A | Page 10 of 20 06021-021 10 06021-018 IDD2 SUPPLY CURRENT (mA) 50 ADM2485 60 OUTPUT CURRENT (mA) 50 1 40 30 20 10 0 M10.0ns A CH1 T 19.8000ns 0 06021-022 CH1 1.0V Ω CH2 1.0V Ω CH3 2.0V Ω 120mV 4 5 4.75 4.74 OUTPUT VOLTAGE (V) 300 250 SIDE 2 200 150 SIDE 1 100 50 4.73 4.72 4.71 4.70 4.69 0 50 100 150 CASE TEMPERATURE (°C) 200 4.67 –40 Figure 14. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per VDE 0884-2 –20 0 20 40 60 80 TEMPERATURE (°C) 06021-031 4.68 06021-023 Figure 17. Receiver Output High Voltage vs. Temperature (IDD2 = –4 mA) 0 0.32 –10 0.30 OUTPUT VOLTAGE (V) –20 –30 –40 –50 0.28 0.26 0.24 0.22 –60 0 1 2 3 4 OUTPUT VOLTAGE (V) Figure 15. Output Current vs. Receiver Output High Voltage 5 0.20 –40 06021-024 –70 –20 0 20 40 TEMPERATURE (°C) 60 80 06021-032 SAFETY-LIMITING CURRENT (mA) 3 Figure 16. Output Current vs. Receiver Output Low Voltage 350 OUTPUT CURRENT (mA) 2 OUTPUT VOLTAGE (V) Figure 13. Driver/Receiver Propagation Delay, High to Low (RLDIFF = 54 Ω, CL1 = CL2 = 100 pF) 0 1 06021-025 3 Figure 18. Receiver Output Low Voltage vs. Temperature (IDD2 = –4 mA) Rev. A | Page 11 of 20 ADM2485 D1 D1 1 1 D2 D2 A CH2 1.52V CH1 2.0V Ω CH2 2.0V Ω M80ns 625MS/s 1.6ns/pt Figure 19. Switching Waveforms (50 Ω Pull-Up to VDD1 on D1 and D2) A CH2 1.52V Figure 20. Switching Waveforms (Break-Before-Make, 50 Ω Pull-Up to VDD1 on D1 and D2) Rev. A | Page 12 of 20 06021-034 CH1 2.0V Ω CH2 2.0V Ω M400ns 125MS/s 8.0ns/pt 06021-033 2 ADM2485 TEST CIRCUITS R CL1 A VOD R B 06021-003 VOC Figure 21. Driver Voltage Measurement 06021-007 RLDIFF CL2 Figure 25. Driver Propagation Delay 375Ω DE OUT TxD Figure 22. Driver Voltage Measurement RxD 150Ω GALVANIC ISOLATION GND2 Figure 26. RTS to DE OUT Propagation Delay VDD2 A B 195Ω RE GND1 VDD2 VCC A 110Ω GND2 110Ω S1 TxD 195Ω GND2 VDD1 VDD2 GND1 50pF B S2 VOUT 06021-009 RxD A B VDD1 06021-005 TxD 50pF RE DE OUT RTS 150Ω 06021-008 375Ω GALVANIC ISOLATION RTS VTEST 60Ω 06021-004 VOD3 RTS Figure 27. Driver Enable/Disable Figure 23. Supply-Current Measurement Test Circuit DE OUT GALVANIC ISOLATION RxD 2.2kΩ GND2 A B 195Ω 110Ω 195Ω RE GND2 GND1 VDD2 VDD1 100nF GND2 VOUT RE CL Figure 28. Receiver Propagation Delay VDD2 FTEST , VHF 50Ω 470nF 50Ω +1.5V 110nF –1.5V 22kΩ VTEST2 100nF VCC S1 06021-006 TxD VCM (HF) B Figure 24. High Frequency, Common-Mode Noise Test Circuit RL RE CL VOUT RE IN Figure 29. Receiver Enable/Disable Rev. A | Page 13 of 20 S2 06021-011 RTS 06021-010 A ADM2485 CIRCUIT DESCRIPTION ELECTRICAL ISOLATION Table 10. Transmitting In the ADM2485, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 30). Driver input and data enable, applied to the TxD and RTS pins, respectively, and referenced to logic ground (GND1), are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (GND2). Similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground. Supply Status VDD1 VDD2 On On On On On On On Off Off On Off Off iCoupler Technology VDD1 D1 OSC VDD1 On On On On On On Off Off VDD2 D2 Inputs TxD H L X X X X A H L Z Z Z Z Outputs B DE OUT L H H H Z L Z L Z L Z L Table 11. Receiving Supply Status The digital signals are transmitted across the isolation barrier using iCoupler technology. This technique uses chip-scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted. RTS H H L X X X VDD2 On On On On On Off On Off Input A−B >+0.2 V <–0.2 V −0.2 V < A − B < +0.2 V Inputs open X X X X Outputs RE L or NC L or NC L or NC L or NC H L or NC L or NC L or NC RxD H L I H Z H H L ISOLATION BARRIER THERMAL SHUTDOWN ENCODE DECODE RTS ENCODE DECODE RxD DECODE ENCODE B DE OUT R TRANSCEIVER DIGITAL ISOLATION RE GND1 A D 06021-026 TxD GND2 Figure 30. ADM2485 Digital Isolation and Transceiver Sections RECEIVER FAIL-SAFE INPUTS TRUTH TABLES Table 10 and Table 11 use the abbreviations found in Table 9. Table 9. Truth Table Abbreviations Letter H I L X Z NC The ADM2485 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150°C is reached. As the device cools, the drivers are re-enabled at a temperature of 140°C. The receiver input includes a fail-safe feature that guarantees a Logic high RxD output when the A and B inputs are floating or open-circuited. Description High level Indeterminate Low level Irrelevant High impedance (off ) Disconnected Rev. A | Page 14 of 20 ADM2485 The limitation on the iCoupler ac magnetic field immunity is set by the condition in which the induced error voltage in the receiving coil (the bottom coil, in this case) is made sufficiently large, either to falsely set or reset the decoder. The voltage induced across the bottom coil is given by ⎛ −dβ ⎞ 2 V =⎜ ⎟ ∑ πrn ; n = 1, 2 … N ⎝ dt ⎠ (1) where, if the pulses at the transformer output are greater than 1.0 V in amplitude: β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of nth turn in the receiving coil (cm). The decoder has a sensing threshold of about 0.5 V; therefore, there is a 0.5 V margin where induced voltages can be tolerated. Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 31. 1000 0.1 06021-027 0.01 100M DISTANCE = 100mm 0 0.1 0.01 1 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) DISTANCE = 5mm 10 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M At combinations of strong magnetic field and high frequency, any loops formed by printed circuit board (PCB) traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care must be taken in the layout of such traces to avoid this possibility. 10 0.001 1k DISTANCE = 1m 100 Figure 32. Maximum Allowable Current for Various Current-to-ADM2485 Spacings 100 MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGAUSS) Figure 32 shows the magnetic flux density values in terms of more familiar quantities, such as maximum allowable current flow at given distances from the ADM2485 transformers. 06021-028 Because iCouplers use a coreless technology, no magnetic components are present and the problem of magnetic saturation of the core material does not exist. Therefore, iCouplers have essentially infinite dc field immunity. The following analysis defines the conditions under which this can occur. The ADM2485 3.3 V operating condition is examined because it represents the most susceptible mode of operation. For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kGauss induces a voltage of 0.25 V at the receiving coil, which is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and it is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. MAXIMUM ALLOWABLE CURRENT (kA) MAGNETIC FIELD IMMUNITY Figure 31. Maximum Allowable External Magnetic Flux Density vs. Magnetic Field Frequency Rev. A | Page 15 of 20 ADM2485 APPLICATIONS INFORMATION PCB LAYOUT APPLICATIONS DIAGRAM The ADM2485 isolated RS-485 transceiver requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 33). The ADM2485 integrates a transformer driver that, when used with an external transformer and LDO, generates an isolated 5 V power supply, to be supplied between VDD2 and GND2. Bypass capacitors are most conveniently connected between Pin 3 and Pin 4 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value must be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin must not exceed 20 mm. D1 and D2 of the ADM2485 drive the center-tapped Transformer T1. A pair of Schottky diodes and a smoothing capacitor is used to create a rectified signal from the secondary winding. The ADP3330 linear voltage regulator provides a regulated 5 V power supply to the ADM2485 bus-side circuitry (VDD2), as shown in Figure 34. Bypassing between Pin 9 and Pin 16 is also recommended unless the ground wires on the VDD2 side are connected close to the package. If ADM2485 is powered by 5 V on the logic side, a 1CT:1.5CT Transformer T1 is required, ensuring enough headroom for the ADP3330 LDO to output a regulated 5 V output. ISOLATION BARRIER Figure 33. Recommended Printed Circuit Board Layout 1N5817 In applications involving high common-mode transients, care must be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout must be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the device absolute maximum ratings, thereby leading to latch-up or permanent damage. VCC ADP3330 SD 5V 10µF GND ISO 5V VCC 100nF 100nF VDD1 D1 D2 VDD2 ADM2485 The transformer primarily used with the ADM2485 must be a center-tapped transformer winding. The turns ratio of the transformer must be set to provide the minimum required output voltage at the maximum anticipated load with the minimum input voltage. Table 12 shows ADM2485 transformer suppliers. Table 12. Transformer Suppliers Primary Voltage 3.3 V DA2304-AL 782485/35C NR OUT T1 1N5817 TRANSFORMER SUPPLIERS Manufacturer Coilcraft C&D Technologies 22µF 10µF MLC ERR IN Primary Voltage 5 V DA2303-AL 782485/55C Rev. A | Page 16 of 20 GND1 GND2 06021-030 ADM2485 VDD2 GND2 GND2 B A GND2 DE OUT GND2 06021-029 D1 D2 GND1 VDD1 RxD RE RTS TxD When the ADM2485 is powered by 3.3 V on the logic side, a 1CT:2.2CT Transformer T1 is required to step up the 3.3 V to 6 V, ensuring enough headroom for the ADP3330 LDO to output a regulated 5 V output. Figure 34. Applications Diagram ADM2485 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 45° 8° 0° 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 032707-B 1 Figure 35. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADM2485BRWZ 1 ADM2485BRWZ-REEL71 1 Data Rate (Mbps) 16 16 Temperature Range −40°C to +85°C −40°C to +85°C Z = RoHS Compliant Part. Rev. A | Page 17 of 20 Package Description 16-Lead SOIC_W 16-Lead SOIC_W Package Option RW-16 RW-16 ADM2485 NOTES Rev. A | Page 18 of 20 ADM2485 NOTES Rev. A | Page 19 of 20 ADM2485 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06021-0-12/07(A) Rev. A | Page 20 of 20