AD ADP3300ART-27

a
High Accuracy anyCAP®
50 mA Low Dropout Linear Regulator
ADP3300
FEATURES
High Accuracy (Over Line and Load Regulations
at 25ⴗC): ⴞ0.8%
Ultralow Dropout Voltage: 80 mV Typical @ 50 mA
Requires Only CO = 0.47 ␮F for Stability
anyCAP™ = Stable with All Types of Capacitors
(Including MLCC)
Current and Thermal Limiting
Low Noise
Dropout Detector
Low Shutdown Current: 1 ␮A
3.0 V to 12 V Supply Range
–40ⴗC to +85ⴗC Ambient Temperature Range
Several Fixed Voltage Options
Ultrasmall SOT-23 6-Lead Package
Excellent Line and Load Regulations
APPLICATIONS
Cellular Telephones
Notebook, Palmtop Computers
Battery Powered Systems
PCMCIA Regulators
Bar Code Scanners
Camcorders, Cameras
FUNCTIONAL BLOCK DIAGRAM
ADP3300
Q1
IN
THERMAL
PROTECTION
ERR
CC
DRIVER
Q2
OUT
R1
Gm
SD
R2
BANDGAP
REF
GND
NR 2
ADP3300-5
VIN
5
IN
OUT 4
C1
0.47 F
6
VOUT = +5V
R1
330kΩ
EOUT
C2
0.47 F
GENERAL DESCRIPTION
The ADP3300 is a member of the ADP330x family of precision
low dropout anyCAP™ voltage regulators. The ADP3300
stands out from conventional LDOs with a novel architecture
and an enhanced process. Its patented design requires only a
0.47 µF output capacitor for stability. This device is stable with
any capacitor, regardless of its ESR (Equivalent Series Resistance)
value, including ceramic types (MLCC) for space restricted applications. The ADP3300 achieves exceptional accuracy of ±0.8%
at room temperature and ± 1.4% overall accuracy over temperature, line and load regulations. The dropout voltage of the
ADP3300 is only 80 mV (typical) at 50 mA.
The ADP3300 operates with a wide input voltage range from
3.0 V to 12 V and delivers a load current in excess of 50 mA. It
features an error flag that signals when the device is about to
lose regulation or when the short circuit or thermal overload
protection is activated. Other features include shutdown and
optional noise reduction capabilities. The ADP330x anyCAP™
1
3
ON
OFF
GND
Figure 1. Typical Application Circuit
LDO family offers a wide range of output voltages and output
current levels from 50 mA to 200 mA:
ADP3301 (100 mA)
ADP3302 (100 mA, Dual Output)
ADP3303 (200 mA)
anyCAP is a registered trademark of Analog Devices Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
ADP3300–SPECIFICATIONS (@noted)T = –40ⴗC to +85ⴗC, V
A
IN
= 7 V, CIN = 0.47 ␮F, COUT = 0.47 ␮F, unless otherwise
Parameter
Symbol
Conditions
Min
OUTPUT VOLTAGE
ACCURACY
VOUT
VIN = VOUT(NOM) +0.3 V to 12 V
IL = 0.1 mA to 50 mA
TA = +25°C
VIN = VOUT(NOM) +0.3 V to 12 V
IL = 0.1 mA to 50 mA
Typ
Max
Units
–0.8
+0.8
%
–1.4
+1.4
%
∆VO
∆VIN
VIN = VOUT(NOM) +0.3 V to 12 V
TA = +25°C
0.02
mV/V
∆VO
∆IL
IL = 0.1 mA to 50 mA
TA = +25°C
0.06
mV/mA
GROUND CURRENT
IGND
IL = 50 mA
IL = 0.1 mA
0.55
0.19
1.7
0.3
mA
mA
GROUND CURRENT
IN DROPOUT
IGND
VIN = 2.5 V
IL = 0.1 mA
0.6
1.2
mA
DROPOUT VOLTAGE
VDROP
VOUT = 98% of VOUT(NOM)
IL = 50 mA
IL = 10 mA
IL = 1 mA
0.08
0.025
0.004
0.17
0.07
0.03
V
V
V
0.75
0.75
0.3
V
V
1
22
µA
µA
0.005
1
µA
0.01
3
µA
LINE REGULATION
LOAD REGULATION
SHUTDOWN THRESHOLD
VTHSD
ON
OFF
2.0
SHUTDOWN PIN
INPUT CURRENT
ISDIN
0 < VSD ≤ 5 V
5 < VSD ≤ 12 V @ VIN = 12 V
GROUND CURRENT IN
SHUTDOWN MODE
IQ
VSD = 0, VIN = 12 V
TA = +25°C
VSD = 0, VIN = 12 V
TA = +85°C
IOSD
TA = +25°C @ VIN = 12 V
TA = +85°C @ VIN = 12 V
2
4
µA
µA
ERROR PIN OUTPUT
LEAKAGE
IEL
VEO = 5 V
13
µA
ERROR PIN OUTPUT
“LOW” VOLTAGE
VEOL
ISINK = 400 µA
0.12
0.3
V
PEAK LOAD CURRENT
ILDPK
VIN = VOUT(NOM) + 1 V
100
mA
OUTPUT NOISE
@ 5 V OUTPUT
VNOISE
f = 10 Hz–100 kHz
CNR = 0
CNR = 10 nF, CL = 10 µF
100
30
µV rms
µV rms
OUTPUT CURRENT IN
SHUTDOWN MODE
NOTE
Ambient temperature of +85°C corresponds to a typical junction temperature of +125°C under typical full load test conditions.
Specifications subject to change without notice.
–2–
REV. A
ADP3300
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
Input Supply Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Error Flag Output Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Noise Bypass Pin Voltage . . . . . . . . . . . . . . . . . –0.3 V to +5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . –55°C to +125°C
Operating Junction Temperature Range . . . . –55°C to +125°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
Vapor Phase (60 sec ) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Pin Mnemonic
Function
1
GND
Ground Pin.
2
NR
Noise Reduction Pin. Used for further
reduction of the output noise (see text for
details). No connection if not used.
3
SD
Active Low Shutdown Pin. Connect to
ground to disable the regulator output.
When shutdown is not used, this pin should
be connected to the input pin.
4
OUT
Output of the Regulator, fixed 2.7, 3.0, 3.2,
3.3 or 5 volts output voltage. Bypass to
ground with a 0.47 µF or larger capacitor.
5
IN
Regulator Input.
6
ERR
Open Collector Output which goes low to
indicate that the output is about to go out
of regulation.
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
PIN CONFIGURATION
6 ERR
GND 1
ADP3300
5 IN
TOP VIEW
SD 3 (Not to Scale) 4 OUT
NR 2
ORDERING GUIDE
Model
Voltage Output
Package Description
Package Options
Branding Information
ADP3300ART-2.7
ADP3300ART-3
ADP3300ART-3.2
ADP3300ART-3.3
ADP3300ART-5
2.7 V
3.0 V
3.2 V
3.3 V
5.0 V
Surface Mount
Surface Mount
Surface Mount
Surface Mount
Surface Mount
SOT-23-6
SOT-23-6
SOT-23-6
SOT-23-6
SOT-23-6
LAB
LBB
LCB
LDB
LEB
Contact the factory for the availability of other output voltage options.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
ADP3300–Typical Performance Characteristics
3.202
3.202
800
IL = 10mA
3.199
VOUT = 3.2V
3.198
IL = 50mA
3.197
A
3.200
3.199
3.198
3.197
\
GROUND CURRENT –
3.200
3.196
3.3 4
VOUT = 3.2V
VIN = 7V
3.201
3.201
OUTPUT VOLTAGE – Volts
OUTPUT VOLTAGE – Volts
IL = 0mA
VOUT = 3.2V
IL = 0mA
640
480
320
160
3.196
3.195
5
0
6 7 8 9 10 11 12 13 14
INPUT VOLTAGE – Volts
Figure 2. Line Regulation Output
Voltage vs. Supply Voltage
8
16
0
24 32 40 48 56 64 72 80
OUTPUT LOAD – mA
Figure 3. Output Voltage vs. Load
Current
0
Figure 4. Quiescent Current vs.
Supply Voltage
0.2
820
1.2 2.4 3.6 4.8 6.0 7.2 8.4 9.6 10.8 12.0
INPUT VOLTAGE – Volts
700
560
430
IL = 0 TO 80mA
VIN = 7V
300
170
A
0.0
IL = 0 – 50mA
–0.1
–0.2
–0.3
0
20
40
60
OUTPUT LOAD – mA
80
Figure 5. Quiescent Current vs. Load
Current
Figure 6. Output Voltage Variation %
vs. Temperature
48
24
0
20
40
60
OUTPUT LOAD – mA
80
Figure 8. Dropout Voltage vs. Output
Current
IL = 0mA
200
15 35 55 75 95 115 135
TEMPERATURE – C
8.0
VOUT = 3.2V
RL = 64Ω
VIN
4
3
2
RL = 33Ω
1
0
300
Figure 7. Quiescent Current vs.
Temperature
INPUT/OUTPUT VOLTAGE – Volts
INPUT/OUTPUT VOLTAGE – Volts
INPUT/OUTPUT VOLTAGE – mV
72
400
0
–45 –25 –5
15 35 55 75 95 115 135
TEMPERATURE – C
5
96
IL = 50mA
500
100
–0.4
–45 –25 –5
120
0
GROUND CURRENT –
690
OUTPUT VOLTAGE – %
GROUND CURRENT – µA
VIN = 7V
600
0.1
0
1
2
4
3
2
3
INPUT VOLTAGE – Volts
1
0
Figure 9. Power-Up/Power-Down
–4–
7.0
6.0
5.0
4.0
VOUT
3.0
VSD = VIN
CL = 0.47µF
RL = 66Ω
VOUT = 3.3V
2.0
1.0
0
0
20
40 60
80 100 120 140 160 180 200
TIME – µs
Figure 10. Power-Up Overshoot
REV. A
ADP3300
3.220
3.220
3.220
VOUT = 3.2V
VOUT = 3.2V
3.210
3.200
3.200
3.180
Volts
3.180
3.190
7.5
7.5
VIN
0
20 40
Figure 11. Line Transient Response
1mA
1
0
60 80 100 120 140 160 180 200
TIME – µs
IOUT = 50mA
50
7.0
7.0
20
40 60
0
80 100 120 140 160 180 200
TIME – µs
200
400
600
TIME – µs
800
1000
Figure 13. Load Transient
Figure 12. Line Transient Response
Volts
4
3.220
VOUT = 3.2V
CL = 4.7µF
3.205
Volts
RL = 64Ω
CL = 0.47µF
mA
Volts
RL = 3.2kΩ
CL = 0.47µF
3.200
3.195
3.190
3.190
VOUT = 3.2V
CL = 0.47µF
3.205
Volts
3.210
VOUT = 3.0V
3.0
VOUT
0
VOUT
CL = 0.47µF
3
3.2V
3.200
2
3.190
150
IOUT = 50mA
400
600
TIME – µs
800
0
1000
–10
RIPPLE REJECTION – dB
Volts
2
3
TIME – sec
4
1
0
3
V
0
–20
–30
VOUT = 3.3V
a. 0.47µF, RL = 33kΩ
b. 0.47µF, RL = 64Ω
b
c. 4.7µF, RL = 33kΩ
d. 4.7µF, RL = 64Ω
–40
–50
d
a
–60
–70
c
b d
–80
–90
0
20
40
60
TIME – µs
80
Figure 17. Turn Off
REV. A
0
5
0
VOUT = 3.2V
RL = 64Ω
CL = 0.47µF
2
Volts
1
100
–100
10
a c
100
1k
10k 100k
FREQUENCY – Hz
1M
10M
Figure 18. Power Supply Ripple
Rejection
–5–
20
40
60
TIME – s
80
100
Figure 16. Turn On
Figure 15. Short Circuit Current
4
3
V
+3V
0
0
Figure 14. Load Transient
3.2V
VOUT = 3.2V
RL = 64Ω
1
0
+3
VOLTAGE NOISE SPECTRAL DENSITY – µV/ Hz
1
200
100
VIN = 7V
1mA
0
IOUT
50
mA
50
CL = 4.7µF
Volts
200
mA
3.195
10
0.47µF BYPASS
PIN 5 TO PIN 1
VOUT = 5V, CL = 0.47µF,
IL = 1mA, CNR = 0
1
VOUT = 3.3V, CL = 0.47µF,
IL = 1mA, CNR = 0
0.1
VOUT = 2.7-5.0V, CL = 0.47µF,
IL = 1mA, CNR = 10nF
VOUT = 2.7-5.0V, CL = 0.47µF,
IL = 1mA, CNR = 10nF
0.01
100
10k
1k
FREQUENCY – Hz
100k
Figure 19. Output Noise Density
ADP3300
be stable with just a small 0.47 µF capacitor on the output.
Additional advantages of the pole splitting scheme include superior
line noise rejection and very high regulator gain, which leads to
excellent line and load regulation. An impressive ±1.4% accuracy is
guaranteed over line, load and temperature.
THEORY OF OPERATION
The new anyCAP™ LDO ADP3300 uses a single control loop
for regulation and reference functions. The output voltage is
sensed by a resistive voltage divider consisting of R1 and R2
which is varied to provide the available output voltage option.
Feedback is taken from this network by way of a series diode
(D1) and a second resistor divider (R3 and R4) to the input of
an amplifier.
Additional features of the circuit include current limit, thermal
shutdown and noise reduction. Compared to the standard
solutions that give warning after the output has lost regulation, the ADP3300 provides improved system performance by
enabling the ERR pin to give warning before the device loses
regulation.
OUTPUT
INPUT
Q1
NONINVERTING
WIDEBAND
DRIVER
COMPENSATION
CAPACITOR
Gm
R1
ATTENUATION
(VBANDGAP/VOUT)
PTAT
VOS
R4
R3
As the chip’s temperature rises above 165°C, the circuit
activates a soft thermal shutdown, indicated by a signal low
on the ERR pin, to reduce the current to a safe level.
D1
(a)
PTAT
CURRENT
R2
RLOAD
To reduce the noise gain of the loop, the node of the main
divider network (a) is made available at the noise reduction (NR)
pin, which can be bypassed with a small capacitor (10 nF–100 nF).
CLOAD
ADP3300
APPLICATION INFORMATION
Capacitor Selection: anyCAP™
Figure 20. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it
produces a large, temperature proportional input “offset voltage”
that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complimentary
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values are chosen to produce a temperature stable output. This unique arrangement specifically corrects
for the loading of the divider so that the error resulting from
base current loading in conventional circuits is avoided.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type and ESR of the
load capacitance.
Most LDOs place strict requirements on the range of ESR
values for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional
LDOs stable, changes depending on load and temperature.
These ESR limitations make designing with LDOs more
difficult because of their unclear specifications and extreme
variations over temperature.
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3300 is stable with a wide range of capacitor values, types
and ESR (anyCAP™). A capacitor as low as 0.47 µF is all that is
needed for stability. However, larger capacitors can be used if
high output current surges are anticipated. The ADP3300 is
stable with extremely low ESR capacitors (ESR ≈ 0), such as
multilayer ceramic capacitors (MLCC) or OSCON.
Input Bypass Capacitor: an input bypass capacitor is not
required; however, for applications where the input source is
high impedance or far from the input pins, a bypass capacitor is
recommended. Connecting a 0.47 µF capacitor from the input
to ground reduces the circuit’s sensitivity to PC board layout. If
a bigger output capacitor is used, the input capacitor should be
1 µF minimum.
Noise Reduction
A noise reduction capacitor (CNR) can be used to further reduce
the noise by 6 dB–10 dB (Figure 21). Low leakage capacitors in
the 10 nF–100 nF range provide the best performance. For load
current less than 200 µA, a 4.7 µF output capacitor provides the
lowest noise and the best overall performance. Since the noise
reduction pin (NR) is internally connected to a high impedance
node, any connection to this node should be carefully done to
avoid noise pickup from external sources. The pad connected to
this pin should be as small as possible. Long PC board traces
are not recommended.
NR 2
CNR
10nF
ADP3300-5
VIN
OUT 4
5 IN
C1 +
1.0 F
VOUT = +5V
330kΩ
6
3
EOUT
+
C2
4.7 F
1
ON
OFF
This is no longer true with the ADP3300 anyCAP™ LDO. It
can be used with virtually any capacitor, with no constraint on
the minimum ESR. The innovative design allows the circuit to
GND
Figure 21. Noise Reduction Circuit
–6–
REV. A
ADP3300
Thermal Overload Protection
Error Flag Dropout Detector
The ADP3300 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit,
which limits the die temperature to a maximum of 165°C.
Under extreme conditions (i.e., high ambient temperature and
high power dissipation), where die temperature starts to rise
above 165°C, the output current is reduced until die temperature has dropped to a safe level. Output current is restored when
the die temperature is reduced.
The ADP3300 will maintain its output voltage over a wide
range of load, input voltage and temperature conditions. If the
output is about to lose regulation, for example, by reducing the
supply voltage below the combined regulated output and dropout
voltages, the ERR pin will be activated. The ERR output is an
open collector that will be driven low.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 125°C.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
PD = (VIN – VOUT) ILOAD + (VIN) IGND
Where ILOAD and IGND are load current and ground current, VIN
and VOUT are input and output voltages respectively.
Once set, the ERRor flag’s hysteresis will keep the output low
until a small margin of operating range is restored either by
raising the supply voltage or reducing the load.
APPLICATION CIRCUITS
Crossover Switch
The circuit in Figure 22 shows that two ADP3300s can be used
to form a mixed supply voltage system. The output switches
between two different levels selected by an external digital input.
Output voltages can be any combination of voltages from the
Ordering Guide.
Assuming ILOAD = 50 mA, IGND = 0.5 mA, VIN = 8 V and
VOUT = 3.3 V, device power dissipation is:
VIN = 5.5V TO 12V
VOUT = 5V/3.3V
ADP3300-5.0
OUTPUT SELECT
5.0V
0V
PD = (8 – 3.3) 0.05 + 8 × 0.5 mA = 0.239 W
OUT
IN
GND
∆T = TJ – TA = PD × θJA = 0.239 × 165 = 39.4°C
With a maximum junction temperature of 125°C, this yields a
maximum ambient temperature of 85°C.
OUT
IN
C1
1.0 F
C2
0.47 F
ADP3300-3.3
Printed Circuit Board Layout Consideration
GND
Surface mount components rely on the conductive traces or
pads to transfer heat away from the device. Appropriate PC
board layout techniques should be used to remove heat from the
immediate vicinity of the package.
The following general guidelines will be helpful when designing
a board layout:
Figure 22. Crossover Switch
Higher Output Current
If higher current is needed, an appropriate pass transistor can be
used, as in Figure 23, to increase the output current to 1 A.
1. PC board traces with larger cross section areas will remove
more heat. For optimum results, use PC boards with thicker
copper and wider traces.
MJE253*
VIN = 6V TO 8V
C1
47 F
2. Increase the surface area exposed to open air so heat can be
removed by convection or forced air flow.
VOUT = 5V @ 1A
R1
50Ω
IN
3. Do not use solder mask or silkscreen on the heat dissipating
traces because it will increase the junction to ambient thermal
resistance of the package.
OUT
ADP3300-5
C2
10 F
Shutdown Mode
GND
Applying a TTL high signal to the shutdown pin or tying it to
the input pin will turn the output ON. Pulling the shutdown pin
down to 0.3 V or below, or tying it to ground, will turn the
output OFF. In shutdown mode, quiescent current is reduced
to less than 1 µA.
REV. A
*AAVID531002 HEAT SINK IS USED
Figure 23. High Output Current Linear Regulator
–7–
ADP3300
dropout voltage, which limits the power dissipation of the
LDO to 15 mW. The ADP3000 used in this circuit is a
switching regulator in the step-up configuration.
Constant Dropout Post Regulator
The circuit in Figure 24 provides high precision with low dropout
for any regulated output voltage. It significantly reduces the
ripple from a switching regulator while providing a constant
D1
1N5817
ADP3300-5
IN
C1
100 F
10V
R1
120Ω
ILIM
C2
100µF
10V
VIN
5V @ 50mA
GND
C3
2.2 F
SW1
ADP3000-ADJ
GND
R2
30.1kΩ
1%
OUT
SW2
Q1
2N3906
FB
Q2
2N3906
R3
124kΩ
1%
R4
274kΩ
Figure 24. Constant Dropout Post Regulator
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6-Lead Surface Mount Package
(SOT-23)
0.122 (3.10)
0.106 (2.70)
0.071 (1.80)
0.059 (1.50)
6
5
4
1
2
3
0.118 (3.00)
0.098 (2.50)
PIN 1
0.037 (0.95) BSC
0.075 (1.90)
BSC
0.051 (1.30)
0.035 (0.90)
0.059 (0.15)
0.000 (0.00)
0.057 (1.45)
0.035 (0.90)
0.020 (0.50) SEATING
0.010 (0.25) PLANE
10°
0.009 (0.23) 0°
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
PRINTED IN U.S.A.
VIN = 2.5V TO 3.5V
C00132–0–7/00 (rev .A)
L1
6.8 H
–8–
REV. A