a High Accuracy Ultralow IQ, 500 mA anyCAP® Adjustable Low Dropout Regulator ADP3336 FEATURES High Accuracy Over Line and Load: ⴞ0.9% @ 25ⴗC, ⴞ1.8% Over Temperature Ultralow Dropout Voltage: 200 mV (Typ) @ 500 mA Requires Only CO = 1.0 F for Stability anyCAP = Stable with Any Type of Capacitor (Including MLCC) Current and Thermal Limiting Low Noise Low Shutdown Current: < 1.0 A 2.6 V to 12 V Supply Range 1.5 V to 10 V Output Range –40ⴗC to +85ⴗC Ambient Temperature Range Ultrasmall Thermally-Enhanced 8-Lead MSOP Package FUNCTIONAL BLOCK DIAGRAM Q1 IN ADP3336 THERMAL PROTECTION CC FB SD BANDGAP REF GND ADP3336 OUT OUT IN VIN VOUT OUT R1 IN FB CIN 1F The ADP3336 is a member of the ADP333x family of precision low dropout anyCAP voltage regulators. The ADP3336 operates with an input voltage range of 2.6 V to 12 V and delivers a continuous load current up to 500 mA. The ADP3336 stands out from conventional LDOs with the lowest thermal resistance of any MSOP-8 package and an enhanced process that enables it to offer performance advantages beyond its competition. Its patented design requires only a 1.0 µF output capacitor for stability. This device is insensitive to output capacitor Equivalent Series Resistance (ESR), and is stable with any good quality capacitor, including ceramic (MLCC) types for spacerestricted applications. The ADP3336 achieves exceptional accuracy of ± 0.9% at room temperature and ± 1.8% over temperature, line, and load. The dropout voltage of the ADP3336 is only 200 mV (typical) at 500 mA. This device also includes a safety current limit, thermal overload protection and a shutdown feature. In shutdown mode, the ground current is reduced to less than 1 µA. The ADP3336 has ultralow quiescent current 80 µA (typical) in light load situations. gm DRIVER APPLICATIONS PCMCIA Card Cellular Phones Camcorders, Cameras Networking Systems, DSL/Cable Modems Cable Set-Top Box MP3/CD Players DSP Supply GENERAL DESCRIPTION OUT SD COUT 1F GND R2 ON OFF Figure 1. Typical Application Circuit anyCAP is a registered trademark of Analog Devices Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 ADP3336–SPECIFICATIONS1, 2(V IN = 6.0 V, CIN = COUT = 1.0 F, TJ = –40ⴗC to +125ⴗC unless otherwise noted.) Parameter Symbol Conditions Min OUTPUT Voltage Accuracy3, 4 VOUT VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TJ = 25°C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TJ = –40°C to +125°C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TJ = 150°C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA TA = 25°C IL = 0.1 mA to 500 mA TA = 25°C VOUT = 98% of VOUT(NOM) IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) + 1 V f = 10 Hz–100 kHz, CL = 10 µF IL = 500 mA, CNR = 10 nF, VOUT = 2.5 f = 10 Hz–100 kHz, CL = 10 µF IL = 500 mA, CNR = 0 nF, VOUT = 2.5 Line Regulation3 Load Regulation Dropout Voltage Peak Load Current Output Noise GROUND CURRENT5 In Regulation VDROP ILDPK VNOISE IGND In Dropout IGND In Shutdown IGNDSD SHUTDOWN Threshold Voltage SD Input Current Output Current In Shutdown VTHSD ISD IOSD Max Unit –0.9 +0.9 % –1.8 +1.8 % –2.3 +2.3 % 0.04 mV/V 0.04 mV/mA 200 140 60 10 800 27 400 235 130 mV mV mV mV mA µV rms µV rms 45 IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) – 100 mV IL = 0.1 mA SD = 0 V, VIN = 12 V ON OFF 0 ≤ SD ≤ 12 V TA = 25°C, VIN = 12 V TA = 85°C, VIN = 12 V Typ 4.5 2.6 0.5 80 120 10 6 1.5 110 400 mA mA mA µA µA 0.01 1 µA 1.2 0.01 0.01 0.4 5 1 1 V V µA µA µA 2.0 NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. 2 Application stable with no load. 3 VIN = 2.6 V to 12 V for models with V OUT(NOM) ≤ 2.2 V. 4 Over the VOUT range of 1.5 V to 10 V. 5 Ground current includes current through external resistors. Specifications subject to change without notice. –2– REV. 0 ADP3336 PIN FUNCTION DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS* Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited Operating Ambient Temperature Range . . . . –40°C to +85°C Operating Junction Temperature Range . . . –40°C to +150°C θJA 2-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153°C/W θJA 4-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Pin No. Mnemonic 1, 2, 3 OUT 4 5 GND FB 6 SD 7, 8 IN *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. ORDERING GUIDE Model Output Voltage ADP3336 ADJ Package Package Description Option Branding Information mini_SO LHA RM-8 Function Output of the Regulator. Bypass to ground with a 1.0 µF or larger capacitor. All pins must be connected together for proper operation. Ground Pin. Feedback Input. Connect to an external resistor divider which sets the output voltage. Can also be used for further reduction of output noise (see text for detail). Capacitor required if COUT > 3.3 µF. Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin. Regulator Input. All pins must be connected together for proper operation. PIN CONFIGURATION OUT 1 OUT 2 8 ADP3336 IN 7 IN TOP VIEW OUT 3 (Not to Scale) 6 SD GND 4 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3336 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– 5 FB WARNING! ESD SENSITIVE DEVICE ADP3336–Typical Performance Characteristics 2.201 2.202 IL = 0 2.200 2.199 150mA 2.198 2.197 300mA 2.196 2.195 2.199 2.197 2.196 2.195 80 40 2.193 2 4 0 0 12 6 8 10 INPUT VOLTAGE – Volts 100 200 300 400 OUTPUT LOAD – mA 500 TPC 2. Output Voltage vs. Load Current TPC 1. Line Regulation Output Voltage vs. Supply Voltage OUTPUT CHANGE – % 2.0 0.3 0.2 0.1 500mA 0 1.0 –0.1 0 –0.2 100 200 300 400 OUTPUT LOAD – mA 500 TPC 4. Ground Current vs. Load Current GROUND CURRENT – mA 300mA 4.0 4 6 8 10 INPUT VOLTAGE – Volts IL = 500mA 7 0.4 3.0 2 12 8 0 VIN = 6V VOUT = 2.2V 0 TPC 3. Ground Current vs. Supply Voltage 0.5 5.0 IL = 0 60 20 2.194 500mA VOUT = 2.2V 100 2.198 2.194 0 IL = 100A 120 GROUND CURRENT – A 2.200 OUTPUT VOLTAGE – Volts OUTPUT VOLTAGE – Volts 2.201 GROUND CURRENT – mA 140 VOUT = 2.2V VIN = 6V VOUT = 2.2V VIN = 6V VOUT = 2.2V 6 5 300mA 4 3 100mA 2 500mA 50mA 1 0 0 0 –40 –15 5 25 65 85 105 125 45 JUNCTION TEMPERATURE – ⴗC TPC 5. Output Voltage Variation % vs. Junction Temperature 25 45 65 85 105 125 –40 –15 5 JUNCTION TEMPERATURE – ⴗC TPC 6. Ground Current vs. Junction Temperature 200 150 100 50 VOUT = 2.2V SD = VIN RL = 4.4⍀ 3.0 2.5 2.0 0 100 200 300 400 OUTPUT LOAD – mA TPC 7. Dropout Voltage vs. Output Current 3 2 COUT = 10F 0 1.0 4 0.5 0 2 3 TIME – Sec 4 COUT = 1F 1 1.5 1 0 VOUT – Volts DROPOUT VOLTAGE – mV VOUT = 2.2V VIN – Volts INPUT/OUTPUT VOLTAGE – Volts 250 VOUT = 2.2V SD = VIN RL = 4.4⍀ 2 0 200 400 600 TIME – s 800 500 TPC 8. Power-Up/Power-Down –4– TPC 9. Power-Up Response REV. 0 VOUT = 2.2V RL = 4.4⍀ CL = 1F 2.189 2.190 2.179 3.500 3.000 40 80 140 TIME – s 3.500 180 200 3 0 2 2.1 VIN = 6V VOUT = 2.2V RL = 4.4⍀ 1F 1 10F 10F 0 0 200 VIN = 4V 1 VSD A 0 400 600 TIME – s 200 800 400 600 TIME – s 1F –30 100 120 CL = 1F IL = 50A –50 VOUT = 2.0V CNR = 10nF 140 RMS NOISE – V CL = 1F IL = 500mA –40 CL = 10F IL = 500mA –60 –70 IL = 500mA WITHOUT NOISE REDUCTION 100 IL = 500mA WITH NOISE REDUCTION 80 IL = 0mA WITHOUT NOISE REDUCTION 60 40 CL = 10F IL = 50A –80 100 1k 10k 100k FREQUENCY – Hz 1M TPC 16. Power Supply Ripple Rejection REV. 0 800 10 VOUT = 2.2V IL = 1mA CL = 10F CL = 10F CNR = 10nF CNR = 0 1 CL = 1F CNR = 0 0.1 CL = 1F CNR = 10nF 0.01 20 –90 10 400 600 TIME – s TPC 15. Turn On–Turn Off Response 160 VOUT = 2.2V 0 200 TPC 14. Short Circuit Current TPC 13 Load Transient Response 2 800 VOLTAGE NOISE SPECTRAL DENSITY – V/ Hz mA VOUT = 2.2V VIN = 6V CL = 10F 200 –20 800 2 400 RIPPLE REJECTION – dB FULL SHORT 800m⍀ SHORT 3 400 600 TIME – s TPC 12. Load Transient Response 2.2 Volts Volts 80 140 TIME – s TPC 11. Line Transient Response 2.3 VIN = 6V VOUT = 2.2V CL = 1F 200 0 40 2.2 400 3.000 180 TPC 10. Line Transient Response 2.2 2.1 VOUT = 2.2V RL = 4.4⍀ CL = 10F 2.189 VIN – Volts VIN – Volts 2.179 2.3 2.200 VOUT 2.190 2.210 Volts 2.200 mA 2.210 VOUT – Volts VOUT – Volts ADP3336 10M 0 0 IL = 0mA WITH NOISE REDUCTION 10 20 30 CL – F 40 TPC 17. RMS Noise vs. CL (10 Hz–100 kHz) –5– 50 0.001 10 100 1k 10k 100k FREQUENCY – Hz TPC 18. Output Noise Density 1M ADP3336 superior line noise rejection and very high regulator gain, which leads to excellent line and load regulation. An impressive ± 1.8% accuracy is guaranteed over line, load, and temperature. THEORY OF OPERATION The new anyCAP LDO ADP3336 uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider consisting of R1 and R2 which is varied to provide the available output voltage option. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier. Additional features of the circuit include current limit and thermal shutdown. APPLICATION INFORMATION Capacitor Selection Output Capacitors: as with any micropower device, output transient response is a function of the output capacitance. The ADP3336 is stable with a wide range of capacitor values, types and ESR (anyCAP). A capacitor as low as 1 µF is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. The ADP3336 is stable with extremely low ESR capacitors (ESR ≈ 0), such as multilayer ceramic capacitors (MLCC) or OSCON. Note that the effective capacitance of some capacitor types may fall below the minimum at cold temperature. Ensure that the capacitor provides more than 1 µF at minimum temperature. OUTPUT INPUT COMPENSATION CAPACITOR Q1 NONINVERTING WIDEBAND DRIVER gm ATTENUATION (VBANDGAP /VOUT) R3 D1 PTAT FB VOS R4 ADP3336 PTAT CURRENT R1 CLOAD (a) RLOAD R2 GND Figure 2. Functional Block Diagram Input Bypass Capacitor A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that equilibrium produces a large, temperature-proportional input, “offset voltage” that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary diode voltage to form a “virtual bandgap” voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise design. An input bypass capacitor is not strictly required but is advisable in any application involving long input wires or high source impedance. Connecting a 1 µF capacitor from IN to ground reduces the circuit's sensitivity to PC board layout. If a larger value output capacitor is used, then a larger value input capacitor is also recommended. Noise Reduction A noise reduction capacitor (CNR) can be placed between the output and the feedback pin to further reduce the noise by 6 dB–10 dB (TPC 18). Low leakage capacitors in 100 pF–500 pF range provide the best performance. Since the feedback pin (FB) is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible and long PC board traces are not recommended. The R1, R2 divider is chosen in the same ratio as the bandgap voltage to the output voltage. Although the R1, R2 resistor divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values can be chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider thus avoiding the error resulting from base current loading in conventional circuits. When adding a noise reduction capacitor, maintain a minimum load current of 1 mA when not in shutdown. It is important to note that as CNR increases, the turn-on time will be delayed. With CNR values greater than 1 nF, this delay may be on the order of several milliseconds. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type, and ESR of the load capacitance. ADP3336 IN VIN CIN 1F Most LDOs place very strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. IN SD ON OFF GND OUT OUT VOUT OUT FB CNR R1 COUT 1F R2 With the ADP3336 anyCAP LDO, this is no longer true. It can be used with virtually any good quality capacitor, with no constraint on the minimum ESR. This innovative design allows the circuit to be stable with just a small 1 µF capacitor on the output. Additional advantages of the pole-splitting scheme include Figure 3. Typical Application Circuit –6– REV. 0 ADP3336 Output Voltage The ADP3336 has an adjustable output voltage that can be set by an external resistor divider. The output voltage will be divided by R1 and R2, and then fed back to the FB pin. In order to have the lowest possible sensitivity of the output voltage to temperature variations, it is important that the parallel resistance of R1 and R2 is always 50 kΩ. DIE R1 × R2 = 50 kΩ R1 + R2 Also, for the best accuracy over temperature the feedback voltage should be set for 1.178 V: Figure 4. Thermally Enhanced Paddle-Under-Lead Package Thermal Overload Protection R2 VFB = VOUT × R1 + R2 where VOUT is the desired output voltage and VFB is the “virtual bandgap” voltage. Note that VFB does not actually appear at the FB pin due to loading by the internal PTAT current. Combining the above equations and solving for R1 and R2 gives the following formulas: The ADP3336 is protected against damage from excessive power dissipation by its thermal overload protection circuit which limits the die temperature to a maximum of 165°C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above 165°C, the output current is reduced until the die temperature has dropped to a safe level. The output current is restored when the die temperature is reduced. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 150°C. VOUT VFB 50 kΩ R2 = VFB 1 – VOUT R1 = 50 kΩ × Calculating Junction Temperature Device power dissipation is calculated as follows: PD = (VIN – VOUT) ILOAD + (VIN) IGND Table I. Feedback Resistor Selection Where ILOAD and IGND are load current and ground current, VIN and VOUT are input and output voltages respectively. VOUT R1 (1% Resistor) R2 (1% Resistor) 1.5 V 63.4 kΩ 232 kΩ 1.8 V 76.8 kΩ 147 kΩ PD = (5 – 3.3) 400 mA + 5.0(4 mA) = 700 mW 2.2 V 93.1 kΩ 107 kΩ 2.7 V 115 kΩ 88.7 kΩ The proprietary package used in the ADP3336 has a thermal resistance of 110°C/W, significantly lower than a standard MSOP-8 package. Assuming a 4-layer board, the junction temperature rise above ambient temperature will be approximately equal to: 3.3 V 140 kΩ 78.7 kΩ 5V 210 kΩ 64.9 kΩ 10 V 422 kΩ 56.2 kΩ Paddle-Under-Lead Package The ADP3336 uses a proprietary paddle-under-lead package design to ensure the best thermal performance in an MSOP-8 footprint. This new package uses an electrically isolated die attach that allows all pins to contribute to heat conduction. This technique reduces the thermal resistance to 110°C/W on a 4-layer board as compared to >160°C/W for a standard MSOP-8 leadframe. Figure 4 shows the standard physical construction of the MSOP-8 and the paddle-under-lead leadframe. REV. 0 Assuming ILOAD = 400 mA, IGND = 4 mA, VIN = 5.0 V and VOUT = 3.3 V, device power dissipation is: ∆TJA = 0.700 W × 110°C = 77.0°C To limit the maximum junction temperature to 150°C, maximum allowable ambient temperature will be: TAMAX = 150°C – 77.0°C = 73.0°C Printed Circuit Board Layout Consideration All surface mount packages rely on the traces of the PC board to conduct heat away from the package. –7– ADP3336 In standard packages the dominant component of the heat resistance path is the plastic between the die attach pad and the individual leads. In typical thermally enhanced packages one or more of the leads are fused to the die attach pad, significantly decreasing this component. To make the improvement meaningful, however, a significant copper area on the PCB must be attached to these fused pins. It is not recommended to use solder mask or silkscreen on the PCB traces adjacent to the ADP3336’s pins since it will increase the junction-to-ambient thermal resistance of the package. Applying a TTL high signal to the shutdown (SD) pin or tying it to the input pin, will turn the output ON. Pulling SD down to 0.4 V or below, or tying it to ground will turn the output OFF. In shutdown mode, quiescent current is reduced to much less than 1 µA. The proprietary paddle-under-lead frame design of the ADP3336 uniformly minimizes the value of the dominant portion of the thermal resistance. It ensures that heat is conducted away by all pins of the package. This yields a very low 110°C/W thermal resistance for an MSOP-8 package, without any special board layout requirements, relying only on the normal traces connected to the leads. This yields a 33% improvement in heat dissipation capability as compared to a standard MSOP-8 package. The thermal resistance can be decreased by, approximately, an additional 10% by attaching a few square cm of copper area to the IN pin of the ADP3336 package. C02174–2.5–10/00 (rev. 0) Shutdown Mode OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead mini_SO (RM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) 1 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 33ⴗ 27ⴗ 0.028 (0.71) 0.016 (0.41) PRINTED IN U.S.A. 0.011 (0.28) 0.003 (0.08) –8– REV. 0