ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 Single 12-Bit 750Msps Receiver and Feedback IC Check for Samples: ADS54T01 FEATURES 1 • • • • • • • • Single Channel 12-Bit Resolution Maximum Clock Rate: 750 Msps Low Swing Fullscale Input: 1.0 Vpp Analog Input Buffer with High Impedance Input Input Bandwidth (3dB): >1.2GHz Data Output Interface: DDR LVDS 196-Pin BGA Package (12x12mm) • • • • • Power Dissipation: 1.2W Performance at fin = 230 MHz IF – SNR: 60.7 dBFS – SFDR: 73 dBc Performance at fin = 700 MHz IF – SNR: 58.6 dBFS – SFDR: 64 dBc Receive Mode: 2x Decimation with Low Pass or High Pass Filter Feedback Mode: Burst Mode Output for Full Bandwidth DPD Feedback Device Part No. Number of Channels Speed Grade ADS54T02 2 750 Msps ADS54T01 1 750 Msps ADS54T04 2 500 Msps APPLICATIONS • • Telecommunications Receiver Power Amplifier Linearization DESCRIPTION The ADS54T01 is a high linearity single channel 12-bit, 750 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the onchip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output modes are available for the output data – it can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C). Digital Block 12bit 750Msps INA Burst Mode 2x Decimation DA[11:0] DACLK CLKIN Clk Buffer SYNC TRIGGER 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. OVRAP/N SRESET DETAILED BLOCK DIAGRAM SCLK OVERRANGE VREF VCM THRESHOLD SDIO CONTROL SDO VOLTAGE REFERENCE BUFFER INA_P/N PROGRAMMING DATA SDENB INTERLEAVING CORRECTION ADC Estimator DC or Fs/2 SYNCOUTP/M FIR FILTER Gain Correction DEC x2 SYNCOUTP/N CLKOUT GEN DACLKP/N SYNCP/N MULTICHIP SYNC BURST MODE PROCESSING DDR LVDS OUTPUT BUFFER CLKINP/N ... Offset Correction CLOCK DISTRIBUTION DA[11:0]P/N TRDYP/N BURST MODE TRIGGER HRESP/N TRIGGERP/N Figure 1. Detailed Block Diagram 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 PINOUT INFORMATION A B C D E F G H J K L M N P 14 VREF VCM GND NC NC GND AVDDC AVDDC GND INA_P INA_N GND GND CLKINP 14 13 SDENB TEST MODE GND GND GND GND GND GND GND GND GND GND GND CLKINN 13 12 SCLK SRESET GND AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 GND AVDD33 AVDD33 12 11 SDIO ENABLE GND AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 GND AVDD18 AVDD18 11 10 SDO IOVDD GND AVDD18 GND GND GND GND GND GND AVDD18 GND 9 DVDD DVDD GND GND GND GND GND GND GND GND GND GND SYNCN SYNCP 9 8 DVDD DVDD DVDD DVDD GND GND GND GND GND GND DVDD DVDD DVDD DVDD 8 7 NC NC DVDD LVDS DVDD LVDS GND GND GND GND GND GND DVDD LVDS DVDD LVDS TRDYN TRDYP 7 6 NC NC DVDD LVDS DVDD LVDS GND GND GND GND GND GND DVDD LVDS DVDD LVDS HRESN HRESP 6 5 NC NC NC NC GND GND GND GND GND GND OVRAN OVRAP SYNC OUTN SYNC OUTP 5 4 NC NC NC NC NC NC NC DA0P DA2P DA4P DA6P DA8P NC NC 4 3 NC NC NC NC NC NC NC DA0N DA2N DA4N DA6N DA8N DA11N DA11P 3 2 NC NC NC NC NC NC NC DACLKP DA1P DA3P DA5P DA7P DA10N DA10P 2 1 NC NC NC NC NC NC NC DACLKN DA1N DA3N DA5N DA7N DA9N DA9P 1 A B C D E F G H J K L M N P TRIGGER TRIGGER N P 10 Figure 2. Pinout in DDR Output Mode (top down view) PIN ASSIGNMENTS PIN NAME NUMBER I/O DESCRIPTION INPUT/REFERENCE INA_P/N K14, L14 I Analog ADC differential input signal. VCM B14 O Output of the analog input common mode (nominally 1.9V). A 0.1μF capacitor to AGND is recommended, but not required. VREF A14 I Reference voltage input. A 0.1μF capacitor to AGND is recommended. CLKINP/N P14, P13 I Differential input clock SYNCP/N P9, N9 I Synchronization input. Inactive if logic low. When clocked in a high state initially, this is used for resetting internal clocks and digital logic and starting the SYNCOUT signal. Internal 100Ω termination. SRESET B12 I Serial interface reset input. Active low. Initialized internal registers during high to low transition. Asynchronous. Internal 50kΩ pull up resistor to IOVDD. ENABLE B11 I Chip enable – active high. Power down function can be controlled through SPI register assignment. Internal 50kΩ pull up resistor to IOVDD. CLOCK/SYNC CONTROL/SERIAL Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 3 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com PIN ASSIGNMENTS (continued) PIN I/O DESCRIPTION NAME NUMBER SCLK A12 I SDIO A11 I/O SDENB A13 I Serial interface enable. Internal 50kΩ pull-down resistor. SDO A10 O Uni-directional serial interface data in 4 pin mode (register x00, D16). The SDO pin is tristated in 3-pin interface mode (default). Internal 50kΩ pull-down resistor. TESTMODE B13 – Factory internal test, do not connect DA[11:0]P/N P3, N3, P2, N2, P1, N1, M4, M3, M2, M1, L4, L3, L2, L1, K4, K3, K2, K1, J4, J3, J2, J1, H4, H3 O ADC A Data Bits 11 (MSB) to 0 (LSB) in DDR output mode. Standard LVDS output. DACLKP/N H2, H1 O DDR differential output data clock for Bus A. Register programmable to provide either rising or falling edge to center of stable data nominal timing. SYNCOUTP/N P5, N5 O Synchronization output signal for synchronizing multiple ADCs. Can be disabled via SPI. OVRAP/N M5, L5 O Bus A, Overrange indicator, LVDS output. A logic high signals an analog input in excess of the full-scale range. Optional SYNC output. Serial interface clock. Internal 50kΩ pull-down resistor. Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register x00, D16), the SDIO pin in an input only. Internal 50kΩ pull-down. DATA INTERFACE TRIGGERP/N TRDYP/N HRESP/N P10, N10 I Trigger used for High resolution output data in feedback mode. Internal 100Ω termination G4, G3, P7, N7 O Trigger ready output indicator P6, N6 O Indicator for high resolution output data– logic high signals 12bit output data. E3, E4, N4, P4 – Don’t connect to pin D12, E12, F12, G12, H12, J12, K12, L12, N12, P12 I 3.3V analog supply AVDDC G14, H14 I 1.8V supply for clock input AVDD18 D10, D11, E11, F11, G11, H11, J11, K11, L10, L11, N11, P11 I 1.8V analog supply DVDD A8, A9, B8, B9, C8, D8, L8, M8, N8, P8 I 1.8V supply for digital block DVDDLVDS C6, C7, D6, D7, L6, L7, M6, M7 I 1.8V supply for LVDS outputs B10 I 1.8V for digital I/Os I Ground NC POWER SUPPLY AVDD33 IOVDD GND 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 PACKAGE/ORDERING INFORMATION PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE ECO PLAN(2) ADS54T01 196-BGA ZAY –40°C to 85°C GREEN (RoHS & no Sb/Br) LEAD/BA LL FINISH ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS54T01IZAY Tray ADS54T01IZAYR Tape and Reel PACKAGE MARKING ADS54T01I ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE MIN MAX UNIT Supply voltage range, AVDD33 –0.5 4 V Supply voltage range, AVDDC –0.5 2.3 V Supply voltage range, AVDD18 –0.5 2.3 V Supply voltage range, DVDD –0.5 2.3 V Supply voltage range, DVDDLVDS –0.5 2.3 V Supply voltage range, IOVDD –0.5 4 V INA_P, INA_N –0.5 AVDD33 + 0.5 V CLKINP, CLKINN –0.5 AVDDC + 0.5 V SYNCP, SYNCN –0.5 AVDD33 + 0.5 V SRESET, SDENB, SCLK, SDIO, SDO, ENABLE –0.5 IOVDD + 0.5 V Voltage applied to input pins Operating free-air temperature range, TA –40 Operating junction temperature range, TJ Storage temperature range –65 ESD, Human Body Model 85 °C 150 °C 150 °C 2 kV THERMAL INFORMATION THERMAL METRIC (1) ADS54T01 QFN (196-PIN) θJA Junction-to-ambient thermal resistance (2) 37.6 θJCtop Junction-to-case (top) thermal resistance (3) 6.8 (4) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (5) 0.2 ψJB Junction-to-board characterization parameter (6) 16.4 16.8 UNITS °C/W spacer (1) (2) (3) (4) (5) (6) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 5 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN Recommended operating junction temperature TJ TA (1) NOM MAX 105 Maximum rated operating junction temperature (1) 125 Recommended free-air temperature –40 25 85 UNIT °C °C Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate. ELECTRICAL CHARACTERISTICS Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ADC Clock Frequency 40 750 MSPS Resolution 12 Bits SUPPLY AVDD33 3.15 3.3 3.45 V AVDDC, AVDD18, DVDD, DVDDLVDS 1.7 1.8 1.9 V IOVDD 1.7 1.8 3.45 V POWER SUPPLY IAVDD33 3.3V Analog supply current 154 170 mA IAVDD18 1.8V Analog supply current 66 80 mA IAVDDC 1.8V Clock supply current 42 60 mA IDVDD 1.8V Digital supply current Auto Correction Enabled 250 280 mA IDVDD 1.8V Digital supply current Auto Correction Disabled 215 mA IDVDD 1.8V Digital supply current Auto Correction Disabled, decimation filter enabled 234 mA IDVDDLVDS 1.8V LVDS supply current IIOVDD 1.8V I/O Voltage supply current Pdis Total power dissipation Auto Correction Enabled, decimation filter disabled Pdis Total power dissipation Auto Correction Disabled, decimation filter disabled PSRR 250kHz to 500MHz Shut-down power dissipation Shut-down wake up time Standby power dissipation Standby wake up time Deep-sleep mode power dissipation mA 2 mA 1.28 1.75 W 1.2 40 W dB 7 mW 2.5 ms 7 mW µs Auto correction disabled 350 mW Auto correction enabled 475 mW 20 µs Auto correction disabled 655 mW Auto correction enabled 780 mW Light-sleep mode wakeup time 6 90 1 100 Deep-sleep mode wakeup time Light-sleep mode power dissipation 66 2 Submit Documentation Feedback µs Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 ELECTRICAL CHARACTERISTICS Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD3V = 3.3V, AVDD/DRVDD/IOVDD = 1.8V, –1dBFS differential input (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ANALOG INPUTS Differential input full-scale 1.0 1.25 Input common mode voltage 1.9 ±0.1 Vpp V Input resistance Differential at DC 1 kΩ Input capacitance Each input to GND 2 pF VCM common mode voltage output 1.9 Analog input bandwidth (3dB) V 1200 MHz DYNAMIC ACCURACY Offset Error Auto Correction Disabled –20 –7.5 20 Auto Correction Enabled –1 0 1 Offset temperature coefficient –6.5 Gain error –5 Gain temperature coefficient mV mV µV/°C 5 0.005 %FS %FS/°C Differential nonlinearity fIN = 230 MHz –1 ±0.9 2 LSB Integral nonlinearity fIN = 230 MHz –5 ±1.5 5 LSB 750 MHz CLOCK INPUT Input clock frequency 40 Input clock amplitude 2 Input clock duty cycle 40% Internal clock biasing 50% Vpp 60% 0.9 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 V 7 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless otherwise noted). PARAMETER TEST CONDITIONS MIN Auto Correction TYP MAX Enabled MIN TYP MAX Disabled UNITS Vpp DYNAMIC AC CHARACTERISTICS (1) – Burst Mode Enabled: 12bit High Resolution Output Data SNR HD2,3 Signal to Noise Ratio Second and third harmonic distortion fIN = 10 MHz 61.1 61.2 fIN = 100 MHz 61.1 61.1 60.7 60.9 fIN = 450 MHz 59.9 60.5 fIN = 700 MHz 58.6 59.6 fIN = 10 MHz 81 83 fIN = 100 MHz 76 81 fIN = 230 MHz 78 79 fIN = 450 MHz 75 76 fIN = 700 MHz 74 76 78 79 75 77 fIN = 230 MHz 73 73 fIN = 450 MHz 68 69 fIN = 700 MHz 64 66 fIN = 10 MHz 90 87 fIN = 100 MHz 84 82 fIN = 230 MHz 59 fIN = 10 MHz Non HD2,3 IL Spur Free Dynamic Range (excluding second and third harmonic distortion) Fs/2-Fin interleaving spur SINAD THD IMD3 Signal to noise and distortion ratio Total Harmonic Distortion Inter modulation distortion fIN = 100 MHz fIN = 230 MHz 68 79 76 fIN = 450 MHz 72 72 fIN = 700 MHz 66 69 fIN = 10 MHz 61.0 61.1 fIN = 100 MHz 60.8 61.0 60.5 60.8 fIN = 450 MHz 59.8 60.3 fIN = 700 MHz 58.4 59.4 fIN = 10 MHz 76 76 fIN = 100 MHz 73 76 fIN = 230 MHz fIN = 230 MHz 65 57.5 66 (1) 8 Effective number of bits dBc dBc dBc dBc 74 74 fIN = 450 MHz 74 73 fIN = 700 MHz 72 74 Fin = 184.5 and 185.5MHz, –7dBFS 82 83 Fin = 549.5 and 550.5MHz, –7dBFS 76 77 90 90 dB fIN = 230 MHz 9.8 9.8 LSB Crosstalk ENOB dBFS dBc dBFS SFDR and SNR calculations do not include the DC or Fs/2 bins when Auto Correction is disabled. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 ELECTRICAL CHARACTERISTICS Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS OVER-DRIVE RECOVERY ERROR Input overload recovery Recovery to within 5% (of final value) for 6dB overload with sine wave input 2 ns SAMPLE TIMING CHARACTERISTICS rms Aperture Jitter Data Latency Over-range Latency Sample uncertainty 100 fs rms ADC sample to digital output, Auto correction disabled 38 ADC sample to digital output, Auto correction enabled 50 ADC sample to digital output, Decimation filter enabled, Auto correction disabled 74 Sampling clock Cycles ADC sample to over-range output 12 Clock Cycles Clock Cycles ELECTRICAL CHARACTERISTICS The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS – SRESET, SCLK, SDENB, SDIO, ENABLE High-level input voltage Low-level input voltage All digital inputs support 1.8V and 3.3V logic levels. 0.7 x IOVDD V 0.3 x IOVDD V High-level input current –50 200 µA Low-level input current –50 50 µA Input capacitance 5 pF DIGITAL OUTPUTS – SDO Iload = -100uA High-level output voltage Iload = -2mA IOVDD – 0.2 V 0.8 x IOVDD Iload = 100uA Low-level output voltage 0.2 0.22 x IOVDD Iload = 2mA V DIGITAL INPUTS – SYNCP/N, TRIGGERP/N VID Differential input voltage VCM Input common mode voltage 250 350 450 1.125 1.2 1.375 tSU 500 mV V ps DIGITAL OUTPUTS – DA[11:0]P/N, DACLKP/N, OVRAP/N, SYNCOUTP/N, TRDYP/N, HRESP/N VOD Output differential voltage Iout = 3.5mA 250 350 450 mV VOCM Output common mode voltage Iout = 3.5mA 1.125 1.25 1.375 tsu Fs = 750Msps Data valid to zero-crossing of DACLK 320 400 ps th Fs = 750Msps Zero-crossing of DACLK to data becoming invalid 250 320 ps tPD Fs = 750Msps V CLKIN falling edge to DACLK rising edge 3.36 3.69 3.92 ns tRISE 10% - 90% 100 150 200 ps tFALL 90% - 10% 100 150 200 ps Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 9 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com Data Latency 38 Clock Cycles SAMPLE N CLKINP tPD DACLKP DACLK edges are centered within the data valid window DA[11:0]P/N OVRAP/N TRDYP/N HRESP/N N-1 N N+1 CLKIN, DACLK are differential: Only the ‘P’ positive signal shown for clarity tsu th Figure 3. Timing Diagram for 12-bit DDR Output 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 TYPICAL CHARACTERISTICS Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input, unless otherwise noted. FFT FOR 10 MHz INPUT SIGNAL (auto on) FFT FOR 10 MHz INPUT SIGNAL (auto off) Figure 4. Figure 5. FFT FOR 230 MHz INPUT SIGNAL (auto on) FFT FOR 230 MHz INPUT SIGNAL (auto off) Figure 6. Figure 7. FFT FOR 450 MHz INPUT SIGNAL (auto on) FFT FOR 450 MHz INPUT SIGNAL (auto off) Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 11 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input, unless otherwise noted. 12 FFT FOR 700 MHz INPUT SIGNAL (auto on) FFT FOR 700 MHz INPUT SIGNAL (auto off) Figure 10. Figure 11. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input, unless otherwise noted. SFDR vs AMPLITUDE (fin = 230 MHz) SNR vs AMPLITUDE (fin = 230 MHz) Figure 14. Figure 15. Tow Tone Performance Across Input Amplitude (fin = 185MHz) SFDR vs Vref (auto on) Figure 16. Figure 17. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 13 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input, unless otherwise noted. 14 SFDR vs Vref (auto off) SNR vs Vref (auto on) Figure 18. Figure 19. SNR vs Vref (auto off) Performance Across Input Common Mode Voltage Figure 20. Figure 21. Performance Across Temperature (fin = 230MHz) Performance Across AVDD33 (fin = 230MHz) Figure 22. Figure 23. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input, unless otherwise noted. Performance Across AVDD18 (fin = 230MHz) Performance Across Clock Amplitude Figure 24. Figure 25. INL DNL Figure 26. Figure 27. CMRR Across Frequency PSRR Across Frequency Figure 28. Figure 29. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 15 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input, unless otherwise noted. Power Across Sampling Frequency Figure 30. 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input, unless otherwise noted. SFDR Across Input and Sampling Frequencies (auto on) Figure 31. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 17 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input, unless otherwise noted. SFDR Across Input and Sampling Frequencies (auto off) Figure 32. 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input, unless otherwise noted. SNR Across Input and Sampling Frequencies (auto on) Figure 33. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 19 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical values at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 750Msps, 50% clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input, unless otherwise noted. SNR Across Input and Sampling Frequencies (auto on) Figure 34. 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 FEATURES POWER DOWN MODES The ADS54T01 can be configured via SPI write (address x37) to a stand-by, light or deep sleep power mode which is controlled by the ENABLE pin. The sleep modes are active when the ENABLE pin goes low. Different internal functions stay powered up which results in different power consumption and wake up time between the two sleep modes. Sleep mode Wake up time Power Consumption Auto correction disabled Power Consumption Auto correction enabled Complete Shut Down 2.5 ms 7mW 7mW Stand-by 100µs 7mW 7mW Deep Sleep 20µs 350mW 475mW Light Sleep 2µs 655mW 780mW TEST PATTERN OUTPUT The ADS54T01 can be configured to output different test patterns that can be used to verify the digital interface is connected and working properly. To enable the test pattern mode, the high performance mode 1 has to be disabled first via SPI register write. Then different test patterns can be selected by configuring registers x3C, x3D and x3E. All three registers must be configured for the test pattern to work properly First set HP1 = 0 (Addr 0x01, D01) Register Address All 0s All 1s Toggle (0xAAA => 0x555) Toggle (0xFFF => 0x000) 0x3C 0x8000 0xBFFC 0x9554 0xBFFC 0x3D 0x0000 0x3FFC 0x2AA8 0x0000 0x3E 0x0000 0x3FFC 0x1554 0x3FFC Register Address x3C x3D x3E Custom Pattern D15 1 0 0 D14 0 0 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1 0 0 0 D0 0 0 0 For normal operation, set HP1 = 1 (Addr 0x01, D01) and 0x3C, 0x3D, 0x3E all to 0. CLOCK INPUTS The ADS54T01 clock input can be driven differentially with a sine wave, LVPECL or LVDS source with little or no difference in performance. The common mode voltage of the clock input is set to 0.9V using internal 2kΩ resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close as possible to the clock inputs in order to minimize signal reflections and jitter degradation. 0.1uF CLKINP CLKINP 2kΩ RT 0.9V 0.1uF 2kΩ RT CLKINN CLKINN 0.1uF Recommended differential clock driving circuit Figure 35. Recommended Differential Clock Driving Circuit Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 21 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com SNR AND CLOCK JITTER The signal to noise ratio of the ADC is limited by three different factors: the quantization noise is typically not noticeable in pipeline converters and is 72dB for a 12bit ADC. The thermal noise limits the SNR at low input frequencies while the clock jitter sets the SNR for higher input frequencies. SNRQuantization _ Noise æ SNR ADC [dBc] = -20 ´ log çç 10 20 è 2 2 2 ö æ SNRThermalNoise ö æ SNRJitter ö + 10 ÷÷ + ç 10 ÷ ç ÷ 20 20 ø è ø ø è The SNR limitation due to sample clock jitter can be calculated as following: SNRJitter [dBc] = -20 ´ log(2p ´ fin ´ TJitter ) (1) (2) The total clock jitter (TJitter) has three components – the internal aperture jitter (100fs for ADS54T01) which is set by the noise of the clock input buffer, the external clock jitter and the jitter from the analog input signal. It can be calculated as following: TJitter = (TJitter,Ext.Clock _ Input )2 + (TAperture _ ADC )2 + (TJitter,Analog_ input )2 (3) External clock jitter can be minimized by using high quality clock sources and jitter cleaners as well as bandpass filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The ADS54T01 has a thermal noise of 61.2 dBFS and internal aperture jitter of 100fs. The SNR depending on amount of external jitter for different input frequencies is shown in the following figure. SNR vs Input Frequency and External Clock Jitter 62 61 35 fs 50 fs 100 fs 150 fs 200 fs SNR (dBFS) 60 59 58 57 56 55 10 100 1000 Fin (MHz) 22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 ANALOG INPUTS The ADS54T01 analog signal input is designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high impedance input across a very wide frequency range to the external driving source which enables great flexibility in the external analog filter design as well as excellent 50Ω matching for RF applications. The buffer also helps to isolate the external driving circuit from the internal switching currents of the sampling circuit which results in a more constant SFDR performance across input frequencies. The common-mode voltage of the signal inputs is internally biased to 1.9V using 500Ω resistors which allows for AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.25V) and (VCM – 0.25V), resulting in a 1.0Vpp (default) differential input swing. The input sampling circuit has a 3dB bandwidth that extends up to 1.2GHz. 2nH 0.5Ω 20Ω INA_P 1.3pF 1.4pF 500Ω Vcm= 1.9V 2nH 500Ω 0.5Ω 20Ω INA_N 1.3pF 1.4pF OVER-RANGE INDICATION The ADS54T01 provides a fast over-range indication on the OVRA/B pins. The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and it gets presented after just 12 clock cycles enabling a quicker reaction to an overrange event. The OVR threshold can be configured using SPI register writes. The input voltage level at which the overload is detected is referred to as the threshold and is programmable using the Over-range threshold bits. The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the FAST OVR THRESH bits] /16). After reset, the default value of the over-range threshold is set to 15 (decimal) which corresponds to a threshold of 0.56dB below full scale (20*log(15/16)). OVR Detection Threshold 0 Thresholds set to dBFS -5 -10 -15 -20 -25 0 2 4 6 8 10 12 14 16 Programmed Value (1-15) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 23 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com INTERLEAVING CORRECTION The data converter channel consists of two interleaved ADCs each operating at half of the ADC sampling rate but 180º out of phase from each other. The front end track and hold circuitry is operating at the full ADC sampling rate which minimizes the timing mismatch between the two interleaved ADCs. In addition the ADS54T04 is equipped with internal interleaving correction logic that can be enabled via SPI register write. ADC ODD Input Track & Hold Fs Interleaving Correction Fs/2 0 deg ADC EVEN Estimator Fs/2 180 deg The interleaving operation creates 2 distinct and interleaving products: • Fs/2 – Fin: this spur is created by gain timing mismatch between the ADCs. Since internally the front end track and hold is operated at the full sampling rate, this component is greatly improved and mostly dependent on gain mismatch. • Fs/2 Spur: due to offset mismatch between ADCs Input Signal Fs/2 Spur Fs/2 - Fin Fs/2 The auto correction loop can be enabled via SPI register write in address 0x01. By default it is disabled for lowest possible power consumption. The default settings for the auto correction function should work for most applications. However please contact Texas Instruments if further fine tuning of the algorithm is required. The auto correction function yields best performance for input frequencies below 250MHz. For input frequencies greater than 250MHz it is recommended to disable the auto gain correction loop. 24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 RECEIVE MODE: DECIMATION FILTER Each channel has a digital filter in the data path as shown in Figure 36. The filter can be programmed as a lowpass or a high-pass filter and the normalized frequency response of both filters is shown in Figure 37. 750 MSPS Lowpass/ Highpass selection Low Latency Filter 375 MSPS ADC 2 Figure 36. The decimation filter response has a 0.1dB pass band ripple with approximately 41% pass-band bandwidth. The stop-band attenuation is approximately 40dB. Decimation Filter Response Decimation Filter Response 10 0.1 0.08 0 0.06 Low Pass Filter 0.04 High Pass Filter Attenuation (dB) Attenuation (dB) -10 -20 -30 0.02 0 -0.02 -0.04 -40 -0.06 -50 Low Pass Filter -0.08 -60 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.05 0.1 0.15 0.2 Frequency (MHz) 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (MHz) Figure 37. FEEDBACK MODE: BURST MODE In burst mode the output data is alternated between a high resolution 12 bit output of 2N samples and a low resolution 7 or 11bit output of 2N+3 samples. Burst mode is enabled through SPI register write and there are two basic operating modes available – a manual trigger mode where the high resolution output is initiated through external trigger and an auto trigger mode where the internal logic transitions to high resolution output immediately after transmitting the last low resolution sample. Upon enabling burst mode through a SPI register write, the ADS54T01 transmits 213 low resolution samples and the trigger command is locked out until completion. The parameter N can be changed via SPI at any time. It will go in effect with the next output cycle starting with transmission of low resolution samples. The default value for N after reset is N=10. N limit Number of low resolution samples per cycle (2N+3) N 10 (minimum) 25 (maximum) 8,192 268,435,456 Number of high resolution samples per cycle (2 ) 1,024 33,554,432 Total amount of samples per cycle 9,216 301,989,888 Maximum number of high resolution (12-bit) samples per 1 second 83.3M 83.3M Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 25 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com Manual Trigger Mode The control of the high resolution output is shown below along with the two output flags (TRDY and HRES). Enable Burst Mode Manual Trigger Trigger on rising edge of TRIGGER TRIGGER tTRIG_DELAY TRDY DA[11..0] High-Resolution 210 samples Low Resolution 213 samples Ready for new trigger High-Resolution 2N samples Low Resolution 2(N+3) samples Update value N Ready for new trigger HRES Figure 38. Triggering High Resolution Mode and Lockout Time After enabling burst mode, the output data DA[11..0] are forced to low resolution mode for 213 samples. During that period any trigger signal is ignored. The completion of the low resolution sample cycle is signaled by a logic high on the TRDY output pins indicating that a high resolution (12-bit) data output burst can be triggered by a low to high transition on the TRIGGER input. The ADC monitors the TRIGGER input at each rising edge of the input clock. The high resolution output data starts with a delay of tTRIG_DELAY = 1-2 DACLK clock cycles and is indicated through the HRES data flag which stays high for all 2N high resolution samples. At completion the register value for N is verified and transmission of 2(N+3) low resolution data immediately follows. Once the last low resolution sample is output on the output data bus, the flag TRDY is asserted high again indicating the end of the lockout period and the next 2N high resolution samples can be triggered again. Auto Trigger Mode This mode is enabled by setting the auto trigger bit via SPI register write and the DA data outputs start in low resolution for 213 samples. Immediately following completion of transmission of the last low resolution sample, the outputs automatically start transmitting 210 high resolution samples without the need for external trigger ensuring maximum efficiency. Any input signal on the TRIGGER pins is ignored and the TRDY flag will go high only for one clock cycle with the start of the high resolution data. The output flag HRES is aligned with the 2N high resolution output samples and the parameter N can be changed until the next output cycle starts again with low resolution output data. 26 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 Enable Burst Mode Auto Trigger High for one clock cycle TRDY DA[11..0] High-Resolution 210 samples Low Resolution 213 samples High-Resolution 2N samples Low Resolution 2(N+3) samples Update value N HRES High Resolution Output Data After trigger, the data outputs DA[11..0] are 12-bit resolution for 2N samples, where N is a programmable register with a range 10 ≤ N ≤ 25 (corresponding to 1024 to 33554432 samples). Sample M M+1 M+2 ... INA_P/N CLKINP/N tPDI Latency = X clock cycles DACLKP/N 12-bit data DA[11:0] Sample # M-6 M-5 M-4 M-3 M-2 M-1 M M+1 M+2 M+3 Figure 39. High Resolution Data Output Timing After the high resolution data, the data output returns to low resolution mode, the logic level of the HRES flag returns low and the trigger is locked out for 2(N+3) samples. N is the sample integer resulting in a maximum output duty cycle of 1/9. During the trigger lockout time, a low to high transition on TRIGGERP/N will be ignored. After the 2N+3 low resolution samples, the TRIGGERP/N is re-enabled for the next valid data burst. Low Resolution Output Data There are two different options for the low resolution output data and the selection is made through SPI register control. The data can either be output at full speed (ADC sampling rate) with the output resolution limited to 7bit (7 MSBs). Alternatively the output resolution can be selected to 11bit (11 MSBs) but at a reduced effective data rate where every 4th sample gets repeated four times. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 27 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com Full Speed – 7bit The output data rate and timing is exactly the same as the high resolution data – only the output resolution is limited to the 7 MSBs. Full Speed Low Resolution M Sample M+1 M+2 ... INA_P/N CLKINP/N tPDI Latency = X clock cycles DACLKP/N 7-bit data DA[11:5] Sample # M-6 M-5 M-4 M-3 M-2 M-1 M M+1 M+2 M+3 Figure 40. Full Rate Low Resolution Output Data Timing Decimated Low Resolution Output Data In decimated low resolution mode the output data is limited to 11-bits and every sample is repeated four times so the effective data rate is 1/4 of ADC sampling rate. The latency of the ADC sample to output sample is exactly the same as for high resolution data – there is no uncertainty in which conversion sample results in the valid output data. This is because the output continues to run at the ADC sample rate – only the resolution is changed and three out of four samples are deleted. Decimated Low Resolution Mode Sample M M+1 M+2 M+3 M+4 ... INA_P/N CLKINP/N Latency = X clock cycles tPDI DACLKP/N 11-bit data DA[11:1]] Sample M-8 M-4 M-4 M-4 M-4 M-8 repeat repeat repeat repeat repeat M M M M repeat repeat repeat M+4 Figure 41. Decimated Low Resolution Output Data Timing Diagram 28 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 MULTI DEVICE SYNCHRONIZATION The ADS54T01 simplifies the synchronization of data from multiple ADCs in one common receiver. Upon receiving the initial SYNC input signal, the ADS54T01 resets all the internal clocks and digital logic while also starting a SYNCOUT signal which operates on a 5bit counter (32 clock cycles). Therefore by providing a common SYNC signal to multiple ADCs their output data can be synchronized as the SYNCOUT signal marks a specific sample with the same latency in all ADCs. The SYNCOUT signal then can be used in the receiving device to synchronize the FIFO pointers across the different input data streams. Thus the output data of multiple ADCs can be aligned properly even if there are different trace lengths between the different ADCs. ADS54T01 DxCLK Sample x SYNCOUT Sample 1 Sample 2 DA[11:0] ChA FIFO Pointer Sample 3 Sample 4 Sample 5 Sample 6 ... FPGA ASIC SYNC ADS54T01 ChA DxCLK Sample x SYNCOUT Sample 1 DA[11:0] FIFO Pointer Sample 2 Sample 3 Sample 4 Sample 5 Sample 6 ... The SYNC input signal should be a periodic signal repeating every 32 CLKIN clock cycles. It gets registered on the rising edge of the ADC input clock (CLKIN). Upon registering the initial rising edge of the SYNC signal, the internal clocks and logic get reset which results in invalid output data for 36 samples (1 complete sync cycle and 4 additional samples). The SYNCOUT signal starts with the next output clock (DACLK) rising edge and operates on a 5-bit counter independent from the SYNC signal frequency and duty cycle. Since the ADS54T01 output interface operates with a DDR clock, the synchronization can happen on the rising edge or falling edge sample. Synchronization on the falling edge sample will result in a half cycle clock stretch of DACLK. For convenience the SYNCOUT signal is available on the ChA output LVDS bus. When using decimation the SYNCOUT signal still operates on 32 clock cycles of CLKIN but since the output data is decimated by 2, only the first 18 samples should be discarded. CLKIN 16 clock cycles SYNC 16 clock cycles DACLK 16 clock cycles SYNCOUT 16 clock cycles DA[11:0] Data invalid – 36 samples SYNC 16 clock cycles 16 clock cycles DACLK SYNCOUT 16 clock cycles 16 clock cycles DA[11:0] Data invalid – 36 samples Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 29 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com PROGRAMMING INTERFACE The serial interface (SIF) included in the ADS54T01 is a simple 3 or 4 pin interface. In normal mode, 3 pins are used to communicate with the device. There is an enable (SDENB), a clock (SCLK) and a bi-directional IO port (SDIO). If the user would like to use the 4 pin interface one write must be implemented in the 3 pin mode to enable 4 pin communications. In this mode, the SDO pin becomes the dedicated output. The serial interface has an 8-bit address word and a 16-bit data word. The first rising edge of SCLK after SDENB goes low will latch the read/write bit. If a high is registered then a read is requested, if it is low then a write is requested. SDENB must be brought high again before another transfer can be requested. The signal diagram is shown below: Register Initialization After power up, the internal registers must be initialized to the default values. This initialization can be accomplished in one of two ways: 1. Either through hardware reset by applying a low pulse on SRESET pin 2. By applying a software reset. When using the serial interface, a reset can be performed by addressing register x2C. This setting initializes the internal registers to the default values and then self-resets the RESET register to 0. In this case the SRESET pin can be kept high. Serial Register Write The internal register of the ADS54T01 can be programmed following these steps: 1. Drive SDENB pin low 2. Set the R/W bit to ‘0’ (bit A7 of the 8 bit address) 3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be written 4. Write 16bit data which is latched on the rising edge of SCLK SCLK SDENB SDIO RWB A6 A5 Read = 1 Write = 0 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 7 bit address space 16bit data: D15 is MSB, D0 is LSB Figure 42. Serial Register Write Timing Diagram PARAMETER MIN MAX UNIT 20 MHz fSCLK SCLK frequency (equal to 1/tSCLK) tSLOADS SDENB to SCLK setup time 25 ns tSLOADH SCLK to SDENB hold time 25 ns tDSU SDIO setup time 25 ns tDH SDIO hold time 25 ns (1) 30 >DC TYP (1) Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD3V = 3.3V, AVDD, DRVDD = 1.9V, unless otherwise noted. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 Serial Register Readout The device includes a mode where the contents of the internal registers can be read back using the SDO/SDIO pins. This read-back mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. 1. Drive SDENB pin low 2. Set the RW bit (A7) to '1'. This setting disables any further writes to the registers 3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be read. 4. The device outputs the contents (D15 to D0) of the selected register on the SDO/SDIO pin 5. The external controller can latch the contents at the SCLK rising edge. 6. To enable register writes, reset the RW register bit to '0'. SCLK SDENB SDIO RWB A6 Read = 1 Write = 0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 7 bit address space 16bit data: D15 is MSB, D0 is LSB Figure 43. Serial Register Read Timing Diagram Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 31 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com SERIAL REGISTER MAP (2) (2) Multiple functions in a register can be programmed in a single write operation. Register Address A7–A0 IN HEX Register Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 Burst rate 0 0 Auto Trigger 0 0 0 0 0 0 0 0 0 Data Format 0 Hp Mode1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 3/4 Wire SPI DecFil/ Burst 0 High/ Low Pass 1 Corr EN 0 0 0 0 2 0 1 0 0 0 0 DC Offset Corr 0 0 1 0 1 1 0 0 0 0 0 1 0 3 Over-range threshold E Sync Select F Sync Select 1A 0 0 0 0 1 0 1 2B 0 0 0 0 0 0 0 0 0 0 1 Reset Burst Mode N 37 Sleep Modes 38 3A VREF Set 0 Temp Sensor 2C 34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LP Mode TEMP EN BIAS EN SYNC EN TRIGEN 0 0 0 0 0 0 0 0 DACLK EN DBCLK EN 0 OVRA EN OVRB EN HP Mode2 LVDS Current Strength Internal LVDS Termination LVDS SW 66 LVDS Output Bus A EN DESCRIPTION OF SERIAL INTERFACE REGISTERS Register Address A7-A0 in hex 0 Register Data D15 3/4 Wire SPI D14 Dec Fil/ Burst D13 0 D12 High/ Low Pass D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 Burst rate D4 0 D3 0 D2 Auto Trigger D15 3/4 Wire SPI Default 0 0 3 wire SPI is used with SDIO pin operating as bi-directional I/O port 1 4 wire SPI is used with SDIO pin operating as data input and SDO pin as data output port. D14 DecFil/ Burst Default 0 0 Burst mode enable 1 2x decimation filter enabled D12 High/Low Pass Default 0 0 Low Pass 1 High Pass D5 Burst Rate Default 0 0 Low resolution (9bit) full output rate 1 Decimated low resolution output (4x decimation, 11bit resolution) 32 D1 0 D0 0 Enables 4-bit serial interface when set 2x decimation filter (Receive Mode) is enabled when bit is set (Decimation filter must be enabled first: set bit D14) Low resolution output data rate in burst mode Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com SLAS918 – DECEMBER 2012 D2 Auto Trigger Default 0 0 Manual trigger mode using the external trigger input pin 1 Auto trigger mode enabled Register Address A7-A0 in hex 1 Enables auto trigger mode in burst mode without the need to control the trigger pin. Register Data D15 Corr EN D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D15 Corr EN (should be enabled for maximum performance) Default 0 0 auto gain correction disabled 1 auto gain correction enabled D3 Data Format Default 0 0 Two's complement 1 Offset Binary D1 HP Mode 1 Default 0 1 Must be set to 1 for optimum performance Register Address A7-A0 in hex 2 D6 0 D5 0 D4 0 D3 Data Format D2 0 D1 HP Mode 1 D0 0 Register Data D15 D14 D13 D12 D11 0 1 0 0 0 D14 Read back 1. D10-D7 Over-range threshold D10 D9 D8 D7 Over-range threshold D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 The over-range detection is triggered 12 output clock cycles after the overload condition occurs. The threshold at which the OVR is triggered = 1.0V x [decimal value of <Over-range threshold>]/16. After power up or reset, the default value is 15 (decimal) which corresponds to a OVR threshold of 0.56dB below fullscale (20*log(15/16)). This OVR threshold is applicable to both channels. Default 1111 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 33 ADS54T01 SLAS918 – DECEMBER 2012 www.ti.com OVR Detection Threshold 0 Thresholds set to dBFS -5 -10 -15 -20 -25 0 2 4 6 8 10 12 14 16 Programmed Value (1-15) Register Address A7-A0 in hex 3 D14 Register Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 DC Offset Coff 0 0 1 0 1 1 0 0 0 1 1 0 0 0 D6 D5 D4 D3 D2 D1 D0 DC Offset Corr Starts DC offset correction loop Default 1 Starts offset correction loop DC offset correction loop is cleared 0 1 D11, 9, 8, 4, 3 Register Address A7-A0 in hex E Must be set to 1 for maximum performance Default 1 Register Data D15 D15-D2 0000 0000 0000 00 0101 0101 0101 01 1010 1010 1010 10 1111 1111 1111 11 34 D14 D13 D12 D11 D10 D9 D8 D7 Sync Select Sync Select Sync selection for the clock generator block (also Default 1010 1010 need to see address 0x0F) 1010 10 Sync is disabled Sync is set to one shot (one time synchronization only) Sync is derived from SYNC input pins not supported Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com Register Address A7-A0 in hex F D15-D12 0000 0101 1010 1111 D6-D4 000 001 010 011 100 Others Register Address A7-A0 in hex 1A SLAS918 – DECEMBER 2012 Register Data D15 D14 D13 D12 Sync Select D11 D10 D9 D8 D7 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 VREF Sel Sync Select Sync selection for the clock generator block Default 1010 1010 1010 10 Sync is disabled Sync is set to one shot (one time synchronization only) Sync is derived from SYNC input pins not supported VREF SEL Default 000 1.0V 1.25V 0.9V 0.8V 1.15V external reference Internal voltage reference selection Register Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 D14, 11, 9, 8, 4, Must be set to 1 for maximum performance 3 Default 1 Register Address A7-A0 in hex 2B D8-D0 Register Address A7-A0 in hex 2C D15-D0 Register Data D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 Temp Sensor D8 D7 Temp Sensor Internal temperature sensor value – read only Register Data D15 Reset Default 0000 1101001011110000 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 Reset This is a software reset to reset all SPI registers to their default value. Self clears to 0. Perform software reset Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 35 ADS54T01 SLAS918 – DECEMBER 2012 Register Address A7-A0 in hex 34 D13-D10 0000 0001 ... 1111 Register Address A7-A0 in hex 37 D15-D14 000000 100000 110000 110101 36 www.ti.com Register Data D15 D14 0 0 D13 D12 D11 D10 Burst Mode N Burst Mode N Default 0000 N = 10 N = 11 ... N = 25 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 This is the parameter that sets the amount of high resolution samples in burst mode Register Data D15 D14 D13 D12 D11 D10 Sleep Modes Sleep Modes Default 00 Complete shut down Stand-by mode Deep sleep mode Light sleep mode D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 Sleep mode selection which is controlled by the ENABLE pin. Sleep modes are active when ENABLE pin goes low. Wake Wake Wake Wake up up up up time 2.5 ms time 100 µs time 20 µs time 2 µs Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 ADS54T01 www.ti.com Register Address A7-A0 in hex 38 SLAS918 – DECEMBER 2012 Register Data D15 D14 D13 D12 D11 D10 D9 HP Mode 2 D8 D7 D6 D5 D4 LP TEMP FUSE SYNC TRIG Mode EN Bias EN EN EN D3 D2 D1 D0 0 0 0 0 D15-D9 HP Mode 2 Default 111111111 1 Set to 1 for normal operation D8 0 D7 1 D6 0 1 D5 0 1 D4 0 1 LP Mode Low power mode Default 1 Set to 0 to turn off unused output buffers TEMP EN Temperature sensor enable Default 1 Set to 1 to enable the temperature sensor FUSE BIAS EN Enables internal bias voltages. Can be disabled after power up for power savings. Default 1 Internal fuse bias powered down Internal fuse bias enabled SYNC EN Default 1 SYNC input buffer disabled SYNC input bffer enabled Enables the SYNC input buffer. TRIG EN Default 1 TRIGGER input buffer disabled TRIGGER input bffer enabled Enables the TRIGGER input buffer. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 37 ADS54T01 SLAS918 – DECEMBER 2012 Register Address A7-A0 in hex 3A D15-D13 000 001 010 011 D12-D11 01 11 D10-D9 00 01 10 11 D4 Register Data D15 D14 D13 LVDS Current Strength LVDS Current Strength Default 000 2 mA 2.25 mA 2.5 mA 2.75 mA D12 D11 LVDS SW D10 D9 Internal LVDS Termination D8 0 D7 0 D6 0 D5 0 D4 DACLK EN D3 0 D2 0 D1 OVRA EN D0 0 D2 D1 D0 LVDS output current strength. 100 101 110 111 3 mA 3.25 mA 3.5 mA 3.75 mA LVDS SW LVDS driver internal switch setting – correct range must be set for setting in D15-D13 Default 01 2 mA to 2.75 mA 3mA to 3.75mA Internal LVDS Internal termination Termination Default 00 2 kΩ 200 Ω 200 Ω 100 Ω DACLK EN Enable DACLK output buffer Default 1 DACLK output buffer powered down DACLK output buffer enabled 0 1 D1 OVRA EN Enable OVRA output buffer Default 1 OVRA output buffer powered down OVRA output buffer enabled 0 1 Register Address A7-A0 in hex 66 D15-D10 0 1 D15 D14 D13 D12 D11-D10 38 www.ti.com Register Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 LVDS Output Bus EN LVDS Output Bus EN Default FFFF Output is powered down Output is enabled Individual LVDS output pin power down corresponds to TRDYP/N (pins N7, P7) corresponds to HRESP/N (pins N6, P6) SYNCOUTP/N (pins N5, P5) Pins N4, P4 (no connect pins) which are not used and should be powered down for power savings corresponds to DA11-DA0 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS54T01 PACKAGE OPTION ADDENDUM www.ti.com 20-Dec-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Samples (3) (Requires Login) ADS54T01IZAY ACTIVE NFBGA ZAY 196 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR ADS54T01IZAYR ACTIVE NFBGA ZAY 196 1000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS54T01IZAYR Package Package Pins Type Drawing NFBGA ZAY 196 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 12.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.3 2.3 16.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS54T01IZAYR NFBGA ZAY 196 1000 336.6 336.6 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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