ADS8324 SBAS172A – AUGUST 2001 – REVISED MARCH 2004 14-Bit, High Speed, 1.8V MicroPower Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● The ADS8324 is a 14-bit, sampling Analog-to-Digital (A/D) converter with tested specifications using a 1.8V supply voltage. It requires very little power, even when operating at the full 50kHz data rate. At lower data rates, the high speed of the device enables it to spend most of its time in the power-down mode—the average power dissipation is less than 1mW at 10kHz data rate. The ADS8324 also features a synchronous serial (SPI/SSI compatible) interface, and a differential input. The reference voltage can be set to any level within the range of 500mV to VCC/2. Ultra-low power and small size make the ADS8324 ideal for portable and battery-operated systems. It is also a perfect fit for remote data acquisition modules, simultaneous multi-channel systems, and isolated data acquisition. The ADS8324 is available in an MSOP-8 package. BIPOLAR INPUT RANGE 1.8V OPERATION 50kHz SAMPLING RATE MICRO POWER: 5.0mW at 2.7V 2.5mW at 1.8V ● POWER DOWN: 3µA max ● MSOP-8 PACKAGE ● PIN-COMPATIBLE TO 12-BIT ADS7817 ● SERIAL (SPI/SSI) INTERFACE APPLICATIONS ● ● ● ● BATTERY OPERATED SYSTEMS REMOTE DATA ACQUISITION ISOLATED DATA ACQUISITION SIMULTANEOUS SAMPLING, MULTI-CHANNEL SYSTEMS ● INDUSTRIAL CONTROLS ● ROBOTICS ● VIBRATION ANALYSIS SAR VREF ADS8324 DOUT +In Serial Interface CDAC –In DCLOCK S/H Amp Comparator CS/SHDN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2001-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION VCC ....................................................................................................... +6V Analog Input ............................................................. –0.3V to (VCC + 0.3V) Logic Input .............................................................................. –0.3V to 6V Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +125°C External Reference Voltage .............................................................. +5.5V Top View MSOP VREF 1 +In 2 8 +VCC 7 DCLOCK ADS8324 NOTE: (1) Stresses above these ratings may permanently damage the device. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. –In 3 6 DOUT GND 4 5 CS/SHDN PIN ASSIGNMENTS PIN NAME DESCRIPTION 1 VREF Reference Input 2 +In Non Inverting Input 3 –In Inverting Input ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 4 GND 5 CS/SHDN Ground 6 DOUT The serial output data word is comprised of 16 bits of data. In operation, the data is valid on the rising edge of DCLOCK. The fifth falling edge of DCLOCK after the falling edge of CS enables the serial output. After one null bit, data is valid for the next 16 edges. 7 DCLOCK Data Clock synchronizes the serial data transfer and determines conversion speed. 8 +VCC Chip Select when LOW, Shutdown Mode when HIGH. Power Supply PACKAGE/ORDERING INFORMATION PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) NO MISSING CODES ERROR (LSB) ADS8324E PACKAGE PACKAGE DRAWING NUMBER(1) SPECIFICATION TEMPERATURE RANGE PACKAGE MARKING(2) ORDERING NUMBER(3) TRANSPORT MEDIA ADS8324E/250 ADS8324E/2K5 ADS8324EB/250 ADS8324EB/2K5 Tape and Reel Tape and Reel Tape and Reel Tape and Reel ±3 14 MSOP 337 –40°C to +85°C A24 " " " " " " " ADS8324EB ±2 14 MSOP 337 –40°C to +85°C A24 " " " " " " " NOTES: (1) For detail drawing and dimension table, please see end of data sheet or package drawing file on web. (2) Performance grade information is marked on the reel. (3) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “ADS8324EB/2K5” will get a single 2500-piece Tape and Reel. 2 ADS8324 www.ti.com SBAS172A ELECTRICAL CHARACTERISTICS: +VCC = +1.8V At –40°C to +85°C, VREF = 0.9V, –In = 0.9V, fSAMPLE = 50kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified. ADS8324E PARAMETER CONDITIONS MIN TYP RESOLUTION ANALOG INPUT Full-Scale Input Span Absolute Input Range +In – (–In) +In –In –VREF –0.1 0.8 REFERENCE INPUT Voltage Range Resistance Power Dissipation Power Down ✻ ✻ ✻ at DCC +1.8V < VCC < +3.6V ±3 ±8 ±2 ✻ ✻ ✻ ✻ ✻ ✻ ±8 50 1.8 ✻ 1.3 –0.3 1.4 80 3 ✻ ✻ ✻ ✻ ✻ ✻ ✻ 1.8 1400 250 2.5 0.3 Clk Cycles Clk Cycles kHz MHz dB dB dB dB ✻ ✻ 0.4 Binary Two’s Complement –40 ✻ Bits LSB LSB µV/°C LSB ppm/°C µVrms dB LSB(1) V GΩ GΩ µA µA µA ✻ VCC + 0.3 0.5 1.8 TEMPERATURE RANGE Specified Performance ±2 ±4 ✻ ✻ ✻ ✻ ✻ ✻ CMOS fSAMPLE = 10kHz(3, 4) VCC = 1.8V CS = VCC V V V pF nA –86 78 86 ✻ VCC/2 5 5 40 0.8 0.1 Specified Performance ✻ ✻ ✻ ✻ ✻ ✻ –84 77 85 78 0.5 IIH = +5µA IIL = +5µA IOH = –250µA IOL = 250µA Bits ✻ 0.024 CS = GND, fSAMPLE = 0Hz CS = VCC UNITS ✻ ✻ 16 4.5 VIN = 5Vp-p at 10kHz VIN = 5Vp-p at 10kHz VIN = 5Vp-p at 10kHz MAX 14 ±4 ±0.1 ±4 ±0.4 60 74 3 fSAMPLE = 10kHz CS = VCC POWER SUPPLY REQUIREMENTS VCC VCC Range(2) Quiescent Current TYP ✻ ✻ 14 Current Drain DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL Data Format +VREF VCC + 0.1 +1.0 25 1 SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Clock Frequency Range DYNAMIC CHARACTERISTICS Total Harmonic Distortion SINAD Spurious Free Dynamic Range SNR MIN 14 Capacitance Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Bipolar Zero Error Bipolar Zero Error Drift Gain Error Gain Temperature Drift Noise Common-Mode Rejection Ratio Power Supply Rejection Ratio ADS8324EB MAX 3.6 1700 ✻ ✻ ✻ ✻ ✻ 3.0 3.0 +85 ✻ V V V V ✻ ✻ V V µA µA mW µA ✻ °C ✻ ✻ ✻ Specifications same as ADS8324E. NOTES: (1) LSB means Least Significant Bit. (2) See Typical Performance Curves for more information. (3) fCLK = 1.2MHz, CS = VCC for 216 clock cycles out of every 240. (4) See the Power Dissipation section for more information regarding lower sample rates. ADS8324 SBAS172A www.ti.com 3 TYPICAL CHARACTERISTICS At TA = +25°C, VCC = 1.8V, VREF = 0.9V, fSAMPLE = 50kHz, fCLK = 24 • fSAMPLE, unless otherwise specified. FREQUENCY SPECTRUM (4096 point FFT, fIN = 0.989kHz, –0.2dB) –20 –20 –40 –40 –60 –80 –60 –80 –100 –100 –120 –120 –140 –140 0 0 5 10 15 20 25 0 5 10 15 20 Frequency (kHz) Frequency (kHz) FREQUENCY SPECTRUM (4096 point FFT, fIN = 20.001kHz, –0.2dB) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-(NOISE + DISTORTION) vs INPUT FREQUENCY 25 90 –20 SNR and SINAD (dB) 85 –40 Amplitude (dB) FREQUENCY SPECTRUM (4096 point FFT, fIN = 9.998kHz, –0.2dB) 0 Amplitude (dB) Amplitude (dB) 0 –60 –80 –100 SNR 80 75 SINAD 70 65 –120 –140 60 0 5 10 15 20 1 25 10 100 Frequency (kHz) Frequency (kHz) SIGNAL-TO-NOISE RATIO AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY COMMON-MODE REJECTION vs FREQUENCY 100 –100 80 95 –95 75 90 –90 70 80 –80 –75 75 THD(1) 70 60 1 60 55 –70 50 –65 45 10 –60 100 Frequency (kHz) 4 65 VCM = 400mVp-p sinewave centered around VREF NOTE: (1) First nine harmonics of the input frequency. 65 CMRR (dB) –85 THD (dB) SFDR (dB) SFDR 85 40 100 1k 10k 100k 1M Frequency (kHz) ADS8324 www.ti.com SBAS172A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VCC = 1.8V, VREF = 0.9V, fSAMPLE = 50kHz, fCLK = 24 • fSAMPLE, unless otherwise specified. DIFFERENTIAL LINEARITY ERROR vs CODE INTEGRAL LINEARITY ERROR vs CODE 2 2 ILE (LSBs) DLE (LSBs) 1 1 0 0 –1 –1 2000H 3000H 0000H 1000H –2 2000H 1FFFH 3000H Output Code QUIESCENT CURRENT vs VCC 1FFFH 10 Average Reference Current (µA) Quiescent Current (mA) 1000H REFERENCE CURRENT vs TEMPERATURE 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 9 8 7 6 5 4 3 2 1 0 –50 4 –30 –10 VCC (V) 1.8 9 1.6 8 Reference Current (µA) 10 1.4 1.2 1 0.8 0.6 50 70 90 7 6 5 4 3 0.4 2 0.2 1 0 –30 –10 10 30 50 70 90 0 Temperature (°C) 20 40 60 80 Sample Rate (kHz) ADS8324 SBAS172A 30 REFERENCE CURRENT vs SAMPLE RATE 2 0 –50 10 Temperature (°C) SUPPLY CURRENT vs TEMPERATURE Supply Current (µA) 0000H Output Code www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VCC = 1.8V, VREF = 0.9V, fSAMPLE = 50kHz, fCLK = 24 • fSAMPLE, unless otherwise specified. CHANGE IN GAIN vs TEMPERATURE 1 0.8 0.8 Change from +25°C (LSB) Change from +25°C (LSB) CHANGE IN BIPOLAR OFFSET vs TEMPERATURE 1 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –0.8 –1 –50 –30 –10 10 30 50 70 90 –1 –50 110 –30 –10 Temperature (°C) CHANGE IN BPZ vs REFERENCE VOLTAGE 30 50 70 90 110 CHANGE IN GAIN vs REFERENCE VOLTAGE 10 10 8 8 6 6 Change in GAIN (LSB) Change in BPZ (LSB) 10 Temperature (°C) 4 2 0 –2 –4 –6 4 2 0 –2 –4 –6 –8 –8 –10 –10 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0.4 0.5 0.6 Reference Voltage (V) 0.7 0.8 0.9 1 1.1 Reference Voltage (V) MAXIMUM SAMPLING RATE vs SUPPLY VOLTAGE NOISE vs REFERENCE VOLTAGE 1000 10 8 Sampling Rate (kHz) Peak-to-Peak Noise (LSB) 9 7 6 5 4 3 100 10 2 1 1 0 0.4 0.5 0.6 0.7 0.8 0.9 1 1.5 1.1 6 2 2.5 3 3.5 4 Supply (V) Reference Voltage (V) ADS8324 www.ti.com SBAS172A THEORY OF OPERATION 2 • VREF peak-to-peak Single-Ended Input VREF peak-to-peak ADS8324 Common Voltage VREF peak-to-peak Differential Input FIGURE 1. Methods of Driving the ADS8324—Single-Ended or Differential. 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 VCC = 1.8V Single-Ended Input 0.5 0.6 0.7 0.8 0.9 1 VREF (V) The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS8324: single-ended or differential, as shown in Figure 1. When the input is single-ended, the –In input is held at a fixed voltage. The +In input swings around the same voltage and the peak-to-peak amplitude is 2 • VREF. The value of VREF determines the range over which the common voltage may vary, as shown in Figure 2. When the input is differential, the amplitude of the input is the difference between the +In and –In input, or, +In – (–In). A voltage or signal is common to both of these inputs. The peak-to-peak amplitude of each input is VREF about this common voltage. However, since the inputs are 180° out-ofphase, the peak-to-peak amplitude of the difference voltage is 2 • VREF. The value of VREF also determines the range of the voltage that may be common to both inputs, as shown in Figure 3. In each case, care should be taken to ensure that the output impedance of the sources driving the +In and –In inputs are matched. If this is not observed, the two inputs could have Common Voltage Range (V) FIGURE 2. Single-Ended Input—Common Voltage Range vs VREF. ANALOG INPUT 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 Differential Input VCC = 1.8V 0.5 0.6 0.7 0.8 0.9 1 VREF (V) FIGURE 3. Differential Input—Common Voltage Range vs VREF. ADS8324 SBAS172A ADS8324 Common Voltage Common Voltage Range (V) The ADS8324 is a classic Successive Approximation Register (SAR) A/D converter. The architecture is based on capacitive redistribution that inherently includes a sampleand-hold function. The converter is fabricated on a 0.6µ CMOS process. The architecture and process allow the ADS8324 to acquire and convert an analog signal at up to 50,000 conversions per second while consuming less than 3.0mW from +VCC. The ADS8324 requires an external reference, an external clock, and a single power source (VCC). The external reference can be any voltage between 500mV and VCC /2. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS8324. The external clock can vary between 24kHz (1kHz throughput) and 1.2MHz (50kHz throughput). The duty cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 200ns. The minimum clock frequency is set by the leakage on the capacitors internal to the ADS8324. The analog input is provided to two input pins: +In and –In. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress—there is no pipeline delay. It is possible to continue to clock the ADS8324 after the conversion is complete and to obtain the serial data least significant bit first. See the digital timing section for more information. www.ti.com 7 different settling times. This may result in offset error, gain error, and linearity error that changes with both temperature and input voltage. If the impedance cannot be matched, the errors can be lessened by giving the ADS8324 additional acquisition time. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8324 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25pF) to the 14-bit settling level within 4.5 clock cycles. When the converter goes into the hold mode, or while it is in the power-down mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. The +In input should always remain within the range of GND – 100mV to VCC + 100mV. The –In input should always remain within the range of GND – 100mV to 2V. Outside of these ranges, the converter’s linearity may not meet specifications. NOISE The noise floor of the ADS8324 itself is extremely low, as can be seen from Figure 4, and is much lower than competing A/D converters. It was tested by applying a low noise DC input and a 0.9V reference to the ADS8324 and initiating 5,000 conversions. The digital output of the A/D converter will vary in output code due to the internal noise of the ADS8324. This is true for all 14-bit SAR-type A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped, with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6 and this will yield the ±3σ distribution or 99.7% of all codes. Statistically, up to 3 codes could fall outside the distribution when executing 1000 conversions. The ADS8324, with five output codes for the ±3σ distribution, will yield a ±0.8LSB transition noise. Remember, to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50µV. REFERENCE INPUT 3857 The external reference sets the analog input range. The ADS8324 will operate with a reference in the range of 500mV to VCC /2. There are several important implications of this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the Least Significant Bit (LSB) size and is equal to 2 • VREF divided by 16,384. This means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. The noise inherent in the converter will also appear to increase with lower LSB size. With a 0.9V reference, the internal noise of the converter typically contributes only 5LSB peak-to-peak of potential error to the output code. When the external reference is 500mV, the potential error contribution from the internal noise will be 7LSBs. The errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, consult the typical performance curve “Noise vs Reference Voltage.” Note that the Effective Number of Bits (ENOB) figure is calculated based on the converter’s signal-to-(noise + distortion) ratio with a 1kHz, 0dB input signal. SINAD is related to ENOB as follows: SINAD = 6.02 • ENOB + 1.76 With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter will also be more sensitive to external sources of error such as nearby digital signals and electromagnetic interference. 8 583 560 0 3FFEH 0 3FFFH 0000H 0001H 0002H Code FIGURE 4. Histogram of 5,000 Conversions of a DC Input at the Code Transition. AVERAGING The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise will be reduced by a factor of 1/√n, where n is the number of averages. For example, averaging 4 conversion results will reduce the transition noise by 1/2 to ±0.25LSBs. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging; for every decimation by 2, the signalto-noise ratio will improve 3dB. ADS8324 www.ti.com SBAS172A DIGITAL INTERFACE SYMBOL SIGNAL LEVELS The CMOS digital output (DOUT) will swing from 0V to VCC. If VCC is 3V, and this output is connected to a 5V CMOS logic input, then that IC may require more supply current than normal and may have a slightly longer propagation delay. DESCRIPTION MIN tSMPL Analog Input Sample Time 4.5 TYP MAX UNITS 5.0 Clk Cycles tCONV Conversion Time tCYC Throughput Rate 50 kHz tCSD CS Falling to 0 ns 16 Clk Cycles DCLOCK LOW CS Falling to tSUCS 50 ns DCLOCK Rising SERIAL INTERFACE The ADS8324 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as shown in Figure 5 and Table I. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. After the fifth falling DCLOCK edge, DOUT is enabled and will output a LOW value for one clock period. For the next 16 DCLOCK periods, DOUT will output the conversion result, most significant bit first followed by two zeros on clock cycles 15 and 16. After the two zero “dummy bits” have been output, subsequent clocks will repeat the output data but in a least significant bit first format starting with a zero. CS must be taken HIGH following a conversion in order to place DOUT in tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW. thDO DCLOCK Falling to Current DOUT Not Valid tdDO DCLOCK Falling to Next DOUT Valid tdis ten 5 20 ns 100 250 ns CS Rising to DOUT Tri-State 50 100 ns DCLOCK Falling to DOUT Enabled 100 200 ns tf DOUT Fall Time 50 150 ns tr DOUT Rise Time 75 200 ns TABLE I. Timing Specifications (VCC = 1.8V) –40°C to +85°C. See Figure 6 for test conditions. DATA FORMAT The output data from the ADS8324 is in Binary Two’s Complement format, as shown in Table II. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full-Scale Range 2 • VREF Least Significant Bit (LSB) 2 • VREF/16384 BINARY CODE HEX CODE +Full Scale +VREF – 1 LSB 0111 1111 1111 1100 7FFC 0V 0000 0000 0000 0000 0000 0V – 1 LSB 1111 1111 1111 1100 FFFC –VREF 1000 0000 0000 0000 8000 Midscale Midscale – 1LSB –Full Scale BINARY TWO’S COMPLEMENT TABLE II. Ideal Input Voltages and Output Codes. Complete Cycle CS/SHDN tSUCS Sample Power Down Conversion DCLOCK tCSD DOUT Use positive clock edge for data transfer Hi-Z 0 B13 B12 B11 B10 B9 (MSB) tSMPL B8 B7 B6 B5 B4 B3 B2 B1 B0 0 (LSB) 0 Hi-Z tCONV NOTE: Minimum 22 clock cycles required for 14-bit conversion. Shown are 24 clock cycles. If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again. FIGURE 5. ADS8324 Basic Timing Diagrams. ADS8324 SBAS172A www.ti.com 9 POWER DISSIPATION The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS8324 to convert at up to a 50kHz rate while requiring very little power. Still, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS8324 scales directly with the conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. In addition, the ADS8324 is in power-down mode under two conditions: when the conversion is complete and whenever CS is HIGH (see Figure 5). Ideally, each conversion should occur as quickly as possible, preferably at a 1.2MHz clock rate. This way, the converter spends the longest possible time in the power-down mode. This is very important as the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components) but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously, until the power-down mode is entered. 0.9V 3kΩ DOUT VOH DOUT VOL Test Point tr 30pF CLOAD tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Load Circuit for tdDO, tr, and tf Test Point DCLOCK VIL VCC DOUT tdDO VOH DOUT tdis Waveform 2, ten 3kΩ tdis Waveform 1 30pF CLOAD VOL thDO Load Circuit for tdis and ten Voltage Waveforms for DOUT Delay Times, tdDO VIH CS/SHDN DOUT Waveform 1(1) CS/SHDN 90% DCLOCK 5 6 tdis DOUT Waveform 2(2) VOL DOUT 10% B11 ten Voltage Waveforms for tdis Voltage Waveforms for ten NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. FIGURE 6. Timing Diagrams and Test Circuits for the Parameters in Table I. 10 ADS8324 www.ti.com SBAS172A 10000 TA = 25°C VCC = 1.8V VREF = 0.9V fCLK = 24 • fSAMPLE 1000 800 Supply Current (µA) Figure 7 shows the current consumption of the ADS8324 versus sample rate. For this graph, the converter is clocked at 1.2MHz regardless of the sample rate—CS is HIGH for the remaining sample period. Figure 8 also shows current consumption versus sample rate. However, in this case, the DCLOCK period is 1/24th of the sample period—CS is HIGH for one DCLOCK cycle out of every 16. There is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode that is enabled when CS is HIGH. CS LOW will shut down only the analog section. The digital section is completely shutdown only when CS is HIGH. Thus, if CS is left LOW at the end of a conversion and the converter is continually clocked, the power consumption will not be as low as when CS is HIGH, shown in Figure 9. 600 400 CS LOW (GND) 200 0.250 CS HIGH (VCC) 0.00 0.1 1 10 100 Sample Rate (kHz) Supply Current (µA) 10000 FIGURE 9. Shutdown Current with CS HIGH is 50nA Typically, Regardless of the Clock. Shutdown Current with CS LOW Varies with Sample Rate. TA = 25°C VCC = 1.8V VREF = 0.9V fCLK = 2.4MHz 1000 LAYOUT 100 10 0.1 1 10 100 Sample Rate (kHz) FIGURE 7. Maintaining fCLK at the Highest Possible Rate Allows Supply Current to Drop Linearly with Sample Rate. Supply Current (µA) 10000 1000 100 TA = 25°C VCC = 1.8V VREF = 0.9V fCLK = 24 • fSAMPLE 10 0.1 1 10 100 Sample Rate (kHz) FIGURE 8. Scaling fCLK Reduces Supply Current Only Slightly with Sample Rate. For optimum performance, care should be taken with the physical layout of the ADS8324 circuitry. This will be particularly true if the reference voltage is low and/or the conversion rate is high. At a 50kHz conversion rate, the ADS8324 makes a bit decision every 213ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 14-bit level all within one clock cycle. The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high power devices, to name a few. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter’s DCLOCK signal—as the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS8324 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the ADS8324 package as possible. In addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. The reference should be similarly bypassed with a 0.1µF capacitor. Again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, be careful that the op ADS8324 SBAS172A www.ti.com 11 amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). Keep in mind that while the ADS8324 draws very little current from the reference on average, there are still instantaneous current demands placed on the external input and reference circuitry. Texas Instruments OPA627 op amp provides optimum performance for buffering both the signal and reference inputs. For low-cost, low-voltage, single-supply applications, the OPA2350 or OPA2340 dual op amps are recommended. Also, keep in mind that the ADS8324 offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50Hz or 60Hz), can be difficult to remove. The GND pin on the ADS8324 should be placed on a clean ground point. In many cases, this will be the “analog” ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power supply connection point. The ideal layout will include an analog ground plane for the converter and associated analog circuitry. APPLICATION CIRCUITS Figure 10 shows a basic data acquisition system. The ADS8324 input range is 0V to VCC, as the reference input is connected directly to the power supply. The 5Ω resistor and 1µF to 10µF capacitor filter the microcontroller “noise” on the supply, as well as any high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of the noise. 1.8V 5Ω + 1µF to 10µF ADS8324 0.9V Reference VREF VCC + 1µF to 10µF 0.1µF 0V to 1.8V +In CS –In DOUT GND Microcontroller DCLOCK FIGURE 10. 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