Blackfin Embedded Processor ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 FEATURES PERIPHERALS Up to 600 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Accepts a wide range of supply voltages for internal and I/O operations. See Specifications on Page 28 Programmable on-chip voltage regulator (ADSP-BF523/ ADSP-BF525/ADSP-BF527 processors only) Qualified for Automotive Applications. See Automotive Products on Page 87 289-ball and 208-ball CSP_BGA packages USB 2.0 high speed on-the-go (OTG) with integrated PHY IEEE 802.3-compliant 10/100 Ethernet MAC Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats Host DMA port (HOSTDP) 2 dual-channel, full-duplex synchronous serial ports (SPORTs), supporting eight stereo I2S channels 12 peripheral DMAs, 2 mastered by the Ethernet MAC 2 memory-to-memory DMAs with external request lines Event handler with 54 interrupt inputs Serial peripheral interface (SPI) compatible port 2 UARTs with IrDA support 2-wire interface (TWI) controller Eight 32-bit timers/counters with PWM support 32-bit up/down counter with rotary support Real-time clock (RTC) and watchdog timer 32-bit core timer 48 general-purpose I/Os (GPIOs), with programmable hysteresis NAND flash controller (NFC) Debug/JTAG interface On-chip PLL capable of frequency multiplication MEMORY 132K bytes of on-chip memory (See Table 1 on Page 3 for L1 and L3 memory size details) External memory controller with glueless support for SDRAM and asynchronous 8-bit and 16-bit memories Flexible booting options from external flash, SPI, and TWI memory or from host devices including SPI, TWI, and UART Code security with Lockbox Secure Technology one-time-programmable (OTP) memory Memory management unit providing memory protection WATCHDOG TIMER OTP MEMORY RTC VOLTAGE REGULATOR* JTAG TEST AND EMULATION EAB COUNTER SPORT0 SPORT1 B L1 INSTRUCTION MEMORY PERIPHERAL ACCESS BUS INTERRUPT CONTROLLER UART1 GPIO PORT F UART0 L1 DATA MEMORY 16 DMA CONTROLLER DCB USB NFC DMA ACCESS BUS PPI SPI TIMER7-1 DEB TIMER0 BOOT ROM EXTERNAL PORT FLASH, SDRAM CONTROL GPIO PORT G GPIO PORT H EMAC HOST DMA *REGULATOR ONLY AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS TWI PORT J Figure 1. Processor Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TABLE OF CONTENTS Features ................................................................. 1 Clock Signals ...................................................... 16 Memory ................................................................ 1 Booting Modes ................................................... 18 Peripherals ............................................................. 1 Instruction Set Description .................................... 20 General Description ................................................. 3 Development Tools .............................................. 20 Portable Low Power Architecture ............................. 3 Additional Information ........................................ 21 System Integration ................................................ 3 Related Signal Chains ........................................... 22 Processor Peripherals ............................................. 3 Lockbox Secure Technology Disclaimer .................... 22 Blackfin Processor Core .......................................... 4 Signal Descriptions ................................................. 23 Memory Architecture ............................................ 5 Specifications ........................................................ 28 DMA Controllers .................................................. 9 Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors ...................................................... 28 Host DMA Port .................................................... 9 Real-Time Clock ................................................... 9 Watchdog Timer ................................................ 10 Operating Conditions for ADSP-BF523/ADSP-BF525/ ADSP-BF527 Processors .................................... 30 Timers ............................................................. 10 Electrical Characteristics ....................................... 32 Up/Down Counter and Thumbwheel Interface .......... 10 Absolute Maximum Ratings ................................... 37 Serial Ports ........................................................ 10 Package Information ............................................ 38 Serial Peripheral Interface (SPI) Port ....................... 11 ESD Sensitivity ................................................... 38 UART Ports ...................................................... 11 Timing Specifications ........................................... 39 TWI Controller Interface ...................................... 12 Output Drive Currents ......................................... 73 10/100 Ethernet MAC .......................................... 12 Test Conditions .................................................. 75 Ports ................................................................ 12 Environmental Conditions .................................... 79 Parallel Peripheral Interface (PPI) ........................... 13 289-Ball CSP_BGA Ball Assignment ........................... 80 USB On-The-Go Dual-Role Device Controller ........... 14 208-Ball CSP_BGA Ball Assignment ........................... 83 Code Security with Lockbox Secure Technology ......... 14 Outline Dimensions ................................................ 86 Dynamic Power Management ................................ 14 Surface-Mount Design .......................................... 87 ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation ........................................... 16 Automotive Products .............................................. 87 ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation ........................................... 16 Ordering Guide ..................................................... 88 REVISION HISTORY 7/13—Rev. C to Rev. D Updated Development Tools .................................... 20 Corrected footnote 9 and added footnote 11 in Operating Conditions for ADSP-BF523/ADSP-BF525/ ADSP-BF527 Processors .......................................... 30 Rev. D | Page 2 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 GENERAL DESCRIPTION The ADSP-BF52x processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin® processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The ADSP-BF52x processors are completely code compatible with other Blackfin processors. The ADSP-BF523/ ADSP-BF525/ADSP-BF527 processors offer performance up to 600 MHz. The ADSP-BF522/ADSP-BF524/ADSP-BF526 processors offer performance up to 400 MHz and reduced static power consumption. Differences with respect to peripheral combinations are shown in Table 1. Table 1. Processor Comparison Memory (bytes) 1 PORTABLE LOW POWER ARCHITECTURE Blackfin processors provide world-class power management and performance. They are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. This capability can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This allows longer battery life for portable appliances. ADSP-BF527 ADSP-BF525 ADSP-BF523 ADSP-BF526 ADSP-BF524 SYSTEM INTEGRATION ADSP-BF522 Feature Host DMA USB Ethernet MAC Internal Voltage Regulator TWI SPORTs UARTs SPI GP Timers GP Counter Watchdog Timers RTC Parallel Peripheral Interface GPIOs L1 Instruction SRAM L1 Instruction SRAM/Cache L1 Data SRAM L1 Data SRAM/Cache L1 Scratchpad L3 Boot ROM Maximum Instruction Rate1 Maximum System Clock Speed Package Options By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package. 1 1 1 1 1 1 – 1 1 – 1 1 – – 1 – – 1 – – – 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 8 8 8 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 48 48 48 48 48 48 48K 48K 48K 48K 48K 48K 16K 16K 16K 16K 16K 16K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 4K 4K 4K 4K 4K 4K 32K 32K 32K 32K 32K 32K 400 MHz 600 MHz 100 MHz 133 MHz 289-Ball CSP_BGA 208-Ball CSP_BGA Maximum instruction rate is not available with every possible SCLK selection. The ADSP-BF52x processors are highly integrated system-on-achip solutions for the next generation of embedded network connected applications. By combining industry-standard interfaces with a high performance signal processing core, costeffective applications can be developed quickly, without the need for costly external components. The system peripherals include an IEEE-compliant 802.3 10/100 Ethernet MAC, a USB 2.0 high speed OTG controller, a TWI controller, a NAND flash controller, two UART ports, an SPI port, two serial ports (SPORTs), eight general purpose 32-bit timers with PWM capability, a core timer, a real-time clock, a watchdog timer, a Host DMA (HOSTDP) interface, and a parallel peripheral interface (PPI). PROCESSOR PERIPHERALS The ADSP-BF52x processors contain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the block diagram on Page 1). These Blackfin processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. All of the peripherals, except for the general-purpose I/O, TWI, real-time clock, and timers, are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. The ADSP-BF523/ADSP-BF525/ADSP-BF527 processors include an on-chip voltage regulator in support of the processor’s dynamic power management capability. The voltage Rev. D | Page 3 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 BLACKFIN PROCESSOR CORE The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. As shown in Figure 2, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-, 16-, or 32-bit data from the register file. Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported. regulator provides a range of core voltage levels when supplied from VDDEXT. The voltage regulator can be bypassed at the user's discretion. ADDRESS ARITHMETIC UNIT L3 B3 M3 I2 L2 B2 M2 I1 L1 B1 M1 I0 L0 B0 M0 P5 DAG1 P4 P3 DAG0 P2 32 32 P1 P0 TO MEMORY DA1 DA0 SP FP I3 32 32 PREG RAB SD LD1 LD0 32 32 32 ASTAT 32 32 R7.H R6.H R7.L R6.L R5.H R5.L R4.H R4.L R3.H R3.L R2.H R2.L R1.H R1.L R0.H R0.L SEQUENCER 16 8 8 8 16 ALIGN 8 DECODE BARREL SHIFTER 40 40 A0 32 40 40 A1 LOOP BUFFER CONTROL UNIT 32 DATA ARITHMETIC UNIT Figure 2. Blackfin Processor Core The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). If the second ALU is used, quad 16-bit operations are possible. The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. Rev. D | Page 4 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The Blackfin processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. See Figure 3. The on-chip L1 memory system is the highest-performance memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory. The memory DMA controller provides high-bandwidth datamovement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces. CORE MMR REGISTERS (2M BYTES) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTES) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTES) 0xFFB0 0000 RESERVED 0xFFA1 4000 INSTRUCTION SRAM / CACHE (16K BYTES) 0xFFA1 0000 RESERVED 0xFFA0 C000 INSTRUCTION BANK B SRAM (16K BYTES) 0xFFA0 8000 INSTRUCTION BANK A SRAM (32K BYTES) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK B SRAM / CACHE (16K BYTES) 0xFF90 4000 DATA BANK B SRAM (16K BYTES) INTERNAL MEMORY MAP Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. 0xFFFF FFFF 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK A SRAM / CACHE (16K BYTES) 0xFF80 4000 DATA BANK A SRAM (16K BYTES) 0xFF80 0000 RESERVED 0xEF00 8000 BOOT ROM (32K BYTES) 0xEF00 0000 RESERVED 0x2040 0000 ASYNC MEMORY BANK 3 (1M BYTES) 0x2030 0000 ASYNC MEMORY BANK 2 (1M BYTES) 0x2020 0000 ASYNC MEMORY BANK 1 (1M BYTES) 0x2010 0000 ASYNC MEMORY BANK 0 (1M BYTES) 0x2000 0000 RESERVED 0x08 00 0000 SDRAM MEMORY (16M BYTES EXTERNAL MEMORY MAP length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). 128M BYTES) 0x0000 0000 Figure 3. Internal/External Memory Map Internal (On-Chip) Memory The processor has three blocks of on-chip memory providing high-bandwidth access to the core. The first block is the L1 instruction memory, consisting of 64K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed. The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed. The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory. External (Off-Chip) Memory External memory is accessed via the EBIU. This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM), as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. Rev. D | Page 5 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 The SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. A separate row can be open for each SDRAM internal bank and the SDRAM controller supports up to 4 internal SDRAM banks, improving overall performance. The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing requirements for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1M byte of memory. NAND Flash Controller (NFC) The ADSP-BF52x processors provide a NAND flash controller (NFC). NAND flash devices provide high-density, low-cost memory. However, NAND flash devices also have long random access times, invalid blocks, and lower reliability over device lifetimes. Because of this, NAND flash is often used for readonly code storage. In this case, all DSP code can be stored in NAND flash and then transferred to a faster memory (such as SDRAM or SRAM) before execution. Another common use of NAND flash is for storage of multimedia files or other large data segments. In this case, a software file system may be used to manage reading and writing of the NAND flash device. The file system selects memory segments for storage with the goal of avoiding bad blocks and equally distributing memory accesses across all address locations. Hardware features of the NFC include: • Support for page program, page read, and block erase of NAND flash devices, with accesses aligned to page boundaries. • Error checking and correction (ECC) hardware that facilitates error detection and correction. • A single 8-bit external bus interface for commands, addresses, and data. • Support for SLC (single level cell) NAND flash devices unlimited in size, with page sizes of 256 and 512 bytes. Larger page sizes can be supported in software. • Capability of releasing external bus interface pins during long accesses. • Support for internal bus requests of 16 bits. • DMA engine to transfer data between internal memory and NAND flash device. One-Time Programmable Memory The processor has 64K bits of one-time programmable nonvolatile memory that can be programmed by the developer only one time. It includes the array and logic to support read access and programming. Additionally, its pages can be write protected. OTP enables developers to store both public and private data on-chip. In addition to storing public and private key data for applications requiring security, it also allows developers to store completely user-definable data such as customer ID, product ID, MAC address, etc. Hence, generic parts can be shipped, which are then programmed and protected by the developer within this non-volatile memory. I/O Memory Space The processor does not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Booting The processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page 18. Event Handling The event controller on the processor handles all asynchronous and synchronous events to the processor. The processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The controller provides support for five different types of events: • Emulation — An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. • RESET — This event resets the processor. • Nonmaskable Interrupt (NMI) — The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. • Exceptions — Events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts — Events that occur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt Rev. D | Page 6 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processor. Table 2 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities. System Interrupt Controller (SIC) The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the processor provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (SIC_IARx). Table 3 describes the inputs into the SIC and the default mappings into the CEC. Table 2. Core Event Controller (CEC) Priority (0 is Highest) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Event Class Emulation/Test Control RESET Nonmaskable Interrupt Exception Reserved Hardware Error Core Timer General-Purpose Interrupt 7 General-Purpose Interrupt 8 General-Purpose Interrupt 9 General-Purpose Interrupt 10 General-Purpose Interrupt 11 General-Purpose Interrupt 12 General-Purpose Interrupt 13 General-Purpose Interrupt 14 General-Purpose Interrupt 15 EVT Entry EMU RST NMI EVX — IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15 Table 3. System Interrupt Controller (SIC) Peripheral Interrupt Event PLL Wakeup Interrupt DMA Error 0 (generic) DMAR0 Block Interrupt DMAR1 Block Interrupt DMAR0 Overflow Error DMAR1 Overflow Error PPI Error MAC Status SPORT0 Status SPORT1 Status Reserved Reserved UART0 Status UART1 Status RTC DMA Channel 0 (PPI/NFC) DMA Channel 3 (SPORT0 RX) DMA Channel 4 (SPORT0 TX) DMA Channel 5 (SPORT1 RX) DMA Channel 6 (SPORT1 TX) TWI DMA Channel 7 (SPI) DMA Channel 8 (UART0 RX) DMA Channel 9 (UART0 TX) DMA Channel 10 (UART1 RX) DMA Channel 11 (UART1 TX) General Purpose Interrupt (at RESET) IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 Peripheral Interrupt ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Rev. D | Page 7 of 88 | July 2013 Default Core Interrupt ID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 2 2 2 3 3 3 3 3 3 SIC Registers IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 3. System Interrupt Controller (SIC) (Continued) Peripheral Interrupt Event OTP Memory Interrupt GP Counter DMA Channel 1 (MAC RX/HOSTDP) Port H Interrupt A DMA Channel 2 (MAC TX/NFC) Port H Interrupt B Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Timer 7 Port G Interrupt A Port G Interrupt B MDMA Stream 0 MDMA Stream 1 Software Watchdog Timer Port F Interrupt A Port F Interrupt B SPI Status NFC Status HOSTDP Status Host Read Done Reserved USB_INT0 Interrupt USB_INT1 Interrupt USB_INT2 Interrupt USB_DMAINT Interrupt General Purpose Interrupt (at RESET) IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG13 IVG13 IVG13 IVG13 IVG13 IVG7 IVG7 IVG7 IVG7 IVG10 IVG10 IVG10 IVG10 IVG10 Peripheral Interrupt ID 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Default Core Interrupt ID 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 0 0 0 0 3 3 3 3 3 SIC Registers IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 Event Control The processor provides a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide. • CEC interrupt latch register (ILAT) — Indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared. • CEC interrupt mask register (IMASK) — Controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and is processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that generalpurpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) • CEC interrupt pending register (IPEND) — The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. The SIC allows further control of event processing by providing three pairs of 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 7. • SIC interrupt mask registers (SIC_IMASKx) — Control the masking and unmasking of each peripheral interrupt event. When a bit is set in these registers, that peripheral event is Rev. D | Page 8 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 unmasked and is processed by the system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event. Examples of DMA types supported by the processor DMA controller include: • A single, linear buffer that stops upon completion. • SIC interrupt status registers (SIC_ISRx) — As multiple peripherals can be mapped to a single event, these registers allow the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event. • A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer. • SIC interrupt wakeup enable registers (SIC_IWRx) — By enabling the corresponding bit in these registers, a peripheral can be configured to wake up the processor, should the core be idled or in sleep mode when the event is generated. For more information see Dynamic Power Management on Page 14. In addition to the dedicated peripheral DMA channels, there are two memory DMA channels provided for transfers between the various memories of the processor system. This enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC recognizes and queues the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor. DMA CONTROLLERS The processor has multiple, independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor's internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the Ethernet MAC, NFC, HOSTDP, USB, SPORTs, SPI port, UARTs, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The processor DMA controller supports both one-dimensional (1-D) and two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly. • 1-D or 2-D DMA using a linked list of descriptors. • 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page. The processor also has an external DMA controller capability via dual external DMA request pins when used in conjunction with the external bus interface unit (EBIU). This functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communications peripherals such as USB 2.0. It allows control of the number of data transfers for memory DMA. The number of transfers per edge is programmable. This feature can be programmed to allow memory DMA to have an increased priority on the external bus relative to the core. HOST DMA PORT The host port interface allows an external host to be a DMA master to transfer data in and out of the device. The host device masters the transactions and the Blackfin processor is the DMA slave. The host port is enabled through the PAB interface. Once enabled, the DMA is controlled by the external host, which can then program the DMA to send/receive data to any valid internal or external memory location. The host port interface controller has the following features. • Allows external master to configure DMA read/write data transfers and read port status. • Uses asynchronous memory protocol for external interface. • 8-/16-bit external data interface to host device. • Half duplex operation. • Little-/big-endian data transfer. • Acknowledge mode allows flow control on host transactions. • Interrupt mode guarantees a burst of FIFO depth host transactions. REAL-TIME CLOCK The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the Blackfin processor. Connect RTC pins RTXI and RTXO with external Rev. D | Page 9 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. components as shown in Figure 4. RTXO RTXI If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. R1 X1 C1 C2 The timer is clocked by the system clock (SCLK), at a maximum frequency of fSCLK. TIMERS SUGGESTED COMPONENTS: X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE) C1 = 22 pF C2 = 22 pF R1 = 10 M: There are nine general-purpose programmable timer units in the processors. Eight timers have an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the several other associated PF pins, an external clock input to the PPI_CLK input pin, or to the internal SCLK. NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF. Figure 4. External Components for RTC The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the processor from sleep mode upon generation of any RTC wake-up event. Additionally, an RTC wakeup event can wake up the processor from deep sleep mode or cause a transition from the hibernate state. WATCHDOG TIMER The processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an Rev. D | The timer units can be used in conjunction with the two UARTs to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. UP/DOWN COUNTER AND THUMBWHEEL INTERFACE A 32-bit up/down counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumb wheels. The counter can also operate in general-purpose up/down count modes. Then, count direction is either controlled by a level-sensitive input pin or by two edge detectors. A third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. All three pins have a programmable debouncing circuit. An internal signal forwarded to the timer unit enables one timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded. SERIAL PORTS The processors incorporate two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: • I2S capable operation. Page 10 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 • Bidirectional operation — Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio. The SPI port’s clock rate is calculated as: • Buffered (8-deep) transmit and receive ports — Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers. f SCLK SPI Clock Rate = ----------------------------------2 SPI_BAUD Where the 16-bit SPI_BAUD register contains a value of 2 to 65,535. • Clocking — Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines. • Word length – Each SPORT supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first. UART PORTS • Framing — Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. • Companding in hardware — Each SPORT can perform A-law or μ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. • DMA operations with single-cycle overhead — Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory. • Interrupts — Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer, or buffers, through DMA. • Multichannel capability — Each SPORT supports 128 channels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards. • PIO (programmed I/O) — The processor sends or receives data by writing or reading I/O mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (direct memory access) — The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. Each UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable: • Supporting bit rates ranging from (fSCLK/1,048,576) to (fSCLK/16) bits per second. • Supporting data formats from seven to 12 bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. SERIAL PERIPHERAL INTERFACE (SPI) PORT The processors have an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices. The UART port’s clock rate is calculated as: The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSI, and Master InputSlave Output, MISO) and a clock pin (serial clock, SCK). An SPI chip select input pin (SPISS) lets other SPI devices select the processor, and seven SPI chip select output pins (SPISEL7–1) let the processor select other SPI devices. The SPI select pins are reconfigured general-purpose I/O pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments. The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA channel, configurable to support transmit or receive data streams. The SPI’s DMA channel can only service unidirectional accesses at any given time. Rev. D | The processors provide two full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits, one or two stop bits, and none, even, or odd parity. Each UART port supports two modes of operation: f SCLK UART Clock Rate = ---------------------------------------------16 UART_Divisor Where the 16-bit UART_Divisor comes from the UART_DLH (most significant 8 bits) and UART_DLL (least significant 8 bits) registers. In conjunction with the general-purpose timer functions, autobaud detection is supported. The capabilities of the UARTs are further extended with support for the infrared data association (IrDA®) serial infrared physical layer link specification (SIR) protocol. Page 11 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TWI CONTROLLER INTERFACE The processors include a 2-wire interface (TWI) module for providing a simple exchange method of control data between multiple devices. The TWI is compatible with the widely used I2C® bus standard. The TWI module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock (SCL) and data (SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface pins are compatible with 5 V logic levels. Additionally, the TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices. • Convenient frame alignment modes support even 32-bit alignment of encapsulated Rx or Tx IP packet data in memory after the 14-byte MAC header. • Programmable Ethernet event interrupt supports any combination of: • Any selected Rx or Tx frame status conditions. • PHY interrupt condition. • Wake-up frame detected. • Any selected MAC management counter(s) at halffull. • DMA descriptor error. 10/100 ETHERNET MAC The ADSP-BF526 and ADSP-BF527 processors offer the capability to directly connect to a network by way of an embedded Fast Ethernet Media Access Controller (MAC) that supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec) operation. The 10/100 Ethernet MAC peripheral on the processor is fully compliant to the IEEE 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system. Some standard features are: • 47 MAC management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value. • Programmable Rx address filters, including a 64-bin address hash table for multicast and/or unicast frames, and programmable filter modes for broadcast, multicast, unicast, control, and damaged frames. • Advanced power management supporting unattended transfer of Rx and Tx frames and status to/from external memory via DMA during low power sleep mode. • System wakeup from sleep operating mode upon magic packet or any of four user-definable wakeup frame filters. • Support of MII and RMII protocols for external PHYs. • Support for 802.3Q tagged VLAN frames. • Full duplex and half duplex modes. • Programmable MDC clock rate and preamble suppression. • Data framing and encapsulation: generation and detection of preamble, length padding, and FCS. • In RMII operation, seven unused pins may be configured as GPIO pins for other purposes. • Media access management (in half-duplex operation): collision and contention handling, including control of retransmission of collision frames and of back-off timing. • Flow control (in full-duplex operation): generation and detection of PAUSE frames. • Station management: generation of MDC/MDIO frames for read-write access to PHY registers. PORTS Because of the rich set of peripherals, the processor groups the many peripheral signals to four ports—Port F, Port G, Port H, and Port J. Most of the associated pins are shared by multiple signals. The ports function as multiplexer controls. General-Purpose I/O (GPIO) • Operating range for active and sleep operating modes, see Table 58 on Page 68 and Table 59 on Page 68. • Internal loopback from Tx to Rx. Some advanced features are: • Buffered crystal output to external PHY for support of a single crystal system. • Automatic checksum computation of IP header and IP payload fields of Rx frames. The processor has 48 bidirectional, general-purpose I/O (GPIO) pins allocated across three separate GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associated with Port F, Port G, and Port H, respectively. Port J does not provide GPIO functionality. Each GPIO-capable pin shares functionality with other processor peripherals via a multiplexing scheme; however, the GPIO functionality is the default state of the device upon power-up. Neither GPIO output nor input drivers are active by default. • Independent 32-bit descriptor-driven Rx and Tx DMA channels. • Frame status delivery to memory via DMA, including frame completion semaphores, for efficient buffer queue management in software. • Tx DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations. Rev. D | Page 12 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: • GPIO direction control register — Specifies the direction of each individual GPIO pin as input or output. • GPIO control and status registers — The processor employs a “write one to modify” mechanism that allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. Four control registers are provided. One register is written in order to set pin values, one register is written in order to clear pin values, one register is written in order to toggle pin values, and one register is written in order to specify a pin value. Reading the GPIO status register allows software to interrogate the sense of the pins. • GPIO interrupt mask registers — The two GPIO interrupt mask registers allow each individual GPIO pin to function as an interrupt to the processor. Similar to the two GPIO control registers that are used to set and clear individual pin values, one GPIO interrupt mask register sets bits to enable interrupt function, and the other GPIO interrupt mask register clears bits to disable interrupt function. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. • GPIO interrupt sensitivity registers — The two GPIO interrupt sensitivity registers specify whether individual pins are level- or edge-sensitive and specify—if edge-sensitive— whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity. PARALLEL PERIPHERAL INTERFACE (PPI) The processor provides a parallel peripheral interface (PPI) that can connect directly to parallel analog-to-digital and digital-toanalog converters, video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate, and the synchronization signals can be configured as either inputs or outputs. The PPI supports a variety of general-purpose and ITU-R 656 modes of operation. In general-purpose mode, the PPI provides half-duplex, bidirectional data transfer with up to 16 bits of data. Up to three frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex bidirectional transfer of 8- or 10-bit video data. Additionally, on-chip decode of embedded start-of-line (SOL) and start-offield (SOF) preamble packets is supported. 2. Frame capture mode — Frame syncs are outputs from the PPI, but data are inputs. 3. Output mode — Frame syncs and data are outputs from the PPI. Input Mode Input mode is intended for ADC applications, as well as video communication with hardware signaling. In its simplest form, PPI_FS1 is an external frame sync input that controls when to read data. The PPI_DELAY MMR allows for a delay (in PPI_CLK cycles) between reception of this frame sync and the initiation of data reads. The number of input data samples is user programmable and defined by the contents of the PPI_COUNT register. The PPI supports 8-bit and 10-bit through 16-bit data, programmable in the PPI_CONTROL register. Frame Capture Mode Frame capture mode allows the video source(s) to act as a slave (for frame capture for example). The ADSP-BF52x processors control when to read from the video source(s). PPI_FS1 is an HSYNC output, and PPI_FS2 is a VSYNC output. Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs. Typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hardware signaling. ITU-R 656 Mode Descriptions The ITU-R 656 modes of the PPI are intended to suit a wide variety of video capture, processing, and transmission applications. Three distinct submodes are supported: 1. Active video only mode 2. Vertical blanking only mode 3. Entire field mode Active Video Mode Active video only mode is used when only the active video portion of a field is of interest and not any of the blanking intervals. The PPI does not read in any data between the end of active video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. After synchronizing to the start of Field 1, the PPI ignores incoming samples until it sees an SAV code. The user specifies the number of active video lines per frame (in PPI_COUNT register). Vertical Blanking Interval Mode General-Purpose Mode Descriptions The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. Three distinct submodes are supported: In this mode, the PPI only transfers vertical blanking interval (VBI) data. 1. Input mode — Frame syncs and data are inputs into the PPI. Rev. D | Page 13 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Entire Field Mode DYNAMIC POWER MANAGEMENT In this mode, the entire incoming bit stream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after synchronization to Field 1. Data is transferred to or from the synchronous channels through eight DMA engines that work autonomously from the processor core. The processor provides five operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. When configured for a 0 V core supply voltage, the processor enters the hibernate state. Control of clocking to each of the processor peripherals also reduces power consumption. See Table 4 for a summary of the power settings for each mode. USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER The USB OTG dual-role device controller (USBDRC) provides a low-cost connectivity solution for consumer mobile devices such as cell phones, digital still cameras, and MP3 players, allowing these devices to transfer data using a point-to-point USB connection without the need for a PC host. The USBDRC module can operate in a traditional USB peripheral-only mode as well as the host mode presented in the On-the-Go (OTG) supplement to the USB 2.0 specification. In host mode, the USB module supports transfers at high speed (480 Mbps), full speed (12 Mbps), and low speed (1.5 Mbps) rates. Peripheral-only mode supports the high- and full-speed transfer rates. The USB clock (USB_XI) is provided through a dedicated external crystal or crystal oscillator. See Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing on Page 60 for related timing requirements. If using a crystal to provide the USB clock, use a parallel-resonant, fundamental mode, microprocessor-grade crystal. The USB on-the-go dual-role device controller includes a phase locked loop with programmable multipliers to generate the necessary internal clocking frequency for USB. The multiplier value should be programmed based on the USB_XI frequency to achieve the necessary 480 MHz internal clock for USB high speed operation. For example, for a USB_XI crystal frequency of 24 MHz, the USB_PLLOSC_CTRL register should be programmed with a multiplier value of 20 to generate a 480 MHz internal clock. Table 4. Power Settings PLL Mode/State PLL Bypassed Full-On Enabled No Active Enabled/ Yes Disabled Sleep Enabled — Deep Sleep Disabled — Hibernate Disabled — Core Clock (CCLK) Enabled Enabled System Clock (SCLK) Enabled Enabled Core Power On On Disabled Enabled On Disabled Disabled On Disabled Disabled Off Full-On Operating Mode—Maximum Performance In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed. Active Operating Mode—Moderate Dynamic Power Savings In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. DMA access is available to appropriately configured L1 memories. In the active mode, it is possible to disable the control input to the PLL by setting the PLL_OFF bit in the PLL control register. This register can be accessed with a user-callable routine in the on-chip ROM called bfrom_SysControl(). If disabled, the PLL control input must be re-enabled before transitioning to the full-on or sleep modes. CODE SECURITY WITH LOCKBOX SECURE TECHNOLOGY A security system consisting of a blend of hardware and software provides customers with a flexible and rich set of code security features with LockboxTM Secure Technology. Key features include: For more information about PLL controls, see the “Dynamic Power Management” chapter in the ADSP-BF52x Blackfin Processor Hardware Reference. • OTP memory • Unique chip ID • Code authentication Sleep Operating Mode—High Dynamic Power Savings • Secure mode of operation The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically, an external event or RTC activity wakes up the processor. When in the sleep mode, asserting a wakeup enabled in the SIC_IWRx registers causes the processor to sense the value of the BYPASS bit in the PLL control register (PLL_CTL). If BYPASS is disabled, the processor transitions to the full-on mode. If BYPASS is enabled, the processor transitions to the active mode. The security scheme is based upon the concept of authentication of digital signatures using standards-based algorithms and provides a secure processing environment in which to execute code and protect assets. See Lockbox Secure Technology Disclaimer on Page 22. Rev. D | Page 14 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 System DMA access to L1 memory is not supported in sleep mode. Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, such as the RTC, may still be running but cannot access internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt (RESET) or by an asynchronous interrupt generated by the RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the Active mode. Assertion of RESET while in deep sleep mode causes the processor to transition to the full on mode. Hibernate State—Maximum Static Power Savings The hibernate state maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all of the synchronous peripherals (SCLK). The internal voltage regulator (ADSP-BF523/ADSP-BF525/ADSP-BF527 only) for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register, using the bfrom_SysControl() function. This setting sets the internal power supply voltage (VDDINT) to 0 V to provide the lowest static power dissipation. Any critical information stored internally (for example, memory contents, register contents, and other information) must be written to a non volatile storage device prior to removing power if the processor state is to be preserved. Writing b#00 to the FREQ bits also causes EXT_WAKE0 and EXT_WAKE1 to transition low, which can be used to signal an external voltage regulator to shut down. Since VDDEXT and VDDMEM can still be supplied in this mode, all of the external pins three-state, unless otherwise specified. This allows other devices that may be connected to the processor to still have power applied without drawing unwanted current. The Ethernet or USB modules can wake up the internal supply regulator (ADSP-BF525 and ADSP-BF527 only) or signal an external regulator to wake up using EXT_WAKE0 or EXT_WAKE1. If PG15 does not connect as a PHYINT signal to an external PHY device, PG15 can be pulled low by any other device to wake the processor up. The processor can also be woken up by a real-time clock wakeup event or by asserting the RESET pin. All hibernate wake-up events initiate the hardware reset sequence. Individual sources are enabled by the VR_CTL register. The EXT_WAKEx signals are provided to indicate the occurrence of wake-up events. As long as VDDEXT is applied, the VR_CTL register maintains its state during hibernation. All other internal registers and memories, however, lose their content in the hibernate state. State variables may be held in external SRAM or SDRAM. The SCKELOW bit in the VR_CTL register controls whether or not SDRAM operates in self-refresh mode, which allows it to retain its content while the processor is in hibernate and through the subsequent reset sequence. Rev. D | As shown in Table 5, the processor supports six different power domains, which maximizes flexibility while maintaining compliance with industry standards and conventions. By isolating the internal logic of the processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of dynamic power management without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate Specifications table for processor Operating Conditions; even if the feature/peripheral is not used. Table 5. Power Domains Power Domain All internal logic, except RTC, Memory, USB, OTP RTC internal logic and crystal I/O Memory logic USB PHY logic OTP logic All other I/O VDD Range VDDINT VDDRTC VDDMEM VDDUSB VDDOTP VDDEXT The dynamic power management feature of the processor allows both the processor’s input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled. The power dissipated by a processor is largely a function of its clock frequency and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic, as shown in the following equations. Power Savings Factor f CCLKRED V DDINTRED 2 T RED = -------------------------- -------------------------------- --------------- f CCLKNOM V DDINTNOM T NOM % Power Savings = 1 – Power Savings Factor 100% where the variables in the equations are: fCCLKNOM is the nominal core clock frequency fCCLKRED is the reduced core clock frequency VDDINTNOM is the nominal internal supply voltage VDDINTRED is the reduced internal supply voltage TNOM is the duration running at fCCLKNOM TRED is the duration running at fCCLKRED Page 15 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ADSP-BF523/ADSP-BF525/ADSP-BF527 VOLTAGE REGULATION The ADSP-BF523/ADSP-BF525/ADSP-BF527 provides an onchip voltage regulator that can generate processor core voltage levels from an external supply. Figure 5 shows the typical external components required to complete the power management system. 2.25V TO 3.6V INPUT VOLTAGE RANGE VDDEXT (LOW-INDUCTANCE) SET OF DECOUPLING CAPACITORS + ADSP-BF522/ADSP-BF524/ADSP-BF526 VOLTAGE REGULATION VDDEXT 100μF 100μF 10μH 100nF VDDINT + + FDS9431A 10μ F LOW ESR ZHCS1000 100μF SS/PG VROUT SHORT AND LOWINDUCTANCE WIRE EXT_WAKE1 SEE H/W REFERENCE, SYSTEM DESIGN CHAPTER, TO DETERMINE VALUE regulator, it is Power Good. The Soft Start feature is recommended to reduce the inrush currents and to reduce VDDINT voltage overshoot when coming out of hibernate or changing voltage levels. The Power Good (PG) input signal allows the processor to start only after the internal voltage has reached a chosen level. In this way, the startup time of the external regulator is detected after hibernation. For a complete description of Soft Start and Power Good functionality, refer to the ADSP-BF52x Blackfin Processor Hardware Reference. VRSEL GND NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A. Figure 5. ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulator Circuit The regulator controls the internal logic voltage levels and is programmable with the voltage regulator control register (VR_CTL) in increments of 50 mV. This register can be accessed using the bfrom_SysControl() function in the on-chip ROM. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power supplied. While in the hibernate state, all external supplies (VDDEXT, VDDMEM, VDDUSB, VDDOTP) can still be applied, eliminating the need for external buffers. VDDRTC must be applied at all times for correct hibernate operation. The voltage regulator can be activated from this power-down state either through an RTC wakeup, a USB wakeup, an Ethernet wake-up, or by asserting the RESET pin, each of which then initiates a boot sequence. The regulator can also be disabled and bypassed at the user’s discretion. The voltage regulator has two modes set by the VRSEL pin—the normal pulse width control of an external FET and the external supply mode which can signal a power down during hibernate to an external regulator. Set VRSEL to VDDEXT to use an external regulator or set VRSEL to GND to use the internal regulator. In the external mode VROUT becomes EXT_WAKE1. If the internal regulator is used, EXT_WAKE0 can control other power sources in the system during the hibernate state. Both signals are high-true for power-up and may be connected directly to the low-true shutdown input of many common regulators. The mode of the SS/PG (Soft Start/Power Good) signal also changes according to the state of VRSEL. When using an internal regulator, the SS/PG pin is Soft Start, and when using an external Rev. D | The ADSP-BF522/ADSP-BF524/ADSP-BF526 processor requires an external voltage regulator to power the VDDINT domain. To reduce standby power consumption, the external voltage regulator can be signaled through EXT_WAKE0 or EXT_WAKE1 to remove power from the processor core. These identical signals are high-true for power-up and may be connected directly to the low-true shut down input of many common regulators. While in the hibernate state, all external supplies (VDDEXT, VDDMEM, VDDUSB, VDDOTP) can still be applied, eliminating the need for external buffers. VDDRTC must be applied at all times for correct hibernate operation. The external voltage regulator can be activated from this power down state either through an RTC wakeup, a USB wakeup, an Ethernet wakeup, or by asserting the RESET pin, each of which then initiates a boot sequence. EXT_WAKE0 or EXT_WAKE1 indicate a wakeup to the external voltage regulator. The Power Good (PG) input signal allows the processor to start only after the internal voltage has reached a chosen level. In this way, the startup time of the external regulator is detected after hibernation. For a complete description of the Power Good functionality, refer to the ADSP-BF52x Blackfin Processor Hardware Reference. CLOCK SIGNALS The processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor’s CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. For fundamental frequency operation, use the circuit shown in Figure 6. A parallel-resonant, fundamental frequency, microprocessorgrade crystal is connected across the CLKIN and XTAL pins. The on-chip resistance between CLKIN and the XTAL pin is in the 500 kΩ range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor shown in Figure 6 fine tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 6 are typical values only. The capacitor values are dependent upon the crystal manufacturers’ load capacitance recommendations and the PCB physical layout. The resistor value depends on the drive level Page 16 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 specified by the crystal manufacturer. The user should verify the customized values based on careful investigations on multiple devices over temperature range. BLACKFIN permitted to run up to the frequency specified by the part’s maximum instruction rate. The CLKOUT pin reflects the SCLK frequency to the off-chip world. It is part of the SDRAM interface, but it functions as a reference signal in other timing specifications as well. While active by default, it can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL registers. CLKOUT TO PLL CIRCUITRY “FINE” ADJUSTMENT REQUIRES PLL SEQUENCING EN “COARSE” ADJUSTMENT ON-THE-FLY CLKBUF 560 ⍀ EN PLL 5u to 64u CLKIN XTAL CLKIN 330 ⍀* 18 pF * ÷ 1, 2, 4, 8 CCLK ÷ 1 to 15 SCLK VCO FOR OVERTONE OPERATION ONLY: 18 pF * SCLK d CCLK Figure 7. Frequency Modification Methods NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀. Figure 6. External Crystal Connections A third-overtone crystal can be used for frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone by adding a tuned inductor circuit as shown in Figure 6. A design procedure for third-overtone operation is discussed in detail in application note (EE-168) Using Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices website (www.analog.com)—use site search on “EE-168.” The CLKBUF pin is an output pin, which is a buffered version of the input clock. This pin is particularly useful in Ethernet applications to limit the number of required clock sources in the system. In this type of application, a single 25 MHz or 50 MHz crystal may be applied directly to the processor. The 25 MHz or 50 MHz output of CLKBUF can then be connected to an external Ethernet MII or RMII PHY device. If, instead of a crystal, an external oscillator is used at CLKIN, CLKBUF will not have the 40/60 duty cycle required by some devices. The CLKBUF output is active by default and can be disabled for power savings reasons using the VR_CTL register. The Blackfin core runs at a different clock rate than the on-chip peripherals. As shown in Figure 7, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a programmable multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier can be modified by a software instruction sequence. This sequence is managed by the bfrom_SysControl() function in the on-chip ROM. On-the-fly CCLK and SCLK frequency changes can be applied by using the bfrom_SysControl() function in the on-chip ROM. The maximum allowed CCLK and SCLK rates depend on the applied voltages VDDINT, VDDEXT, and VDDMEM; the VCO is always Rev. D | All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 6 illustrates typical system clock ratios. Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be dynamically changed without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV) using the bfrom_SysControl() function in the on-chip ROM. Table 6. Example System Clock Ratios Signal Name SSEL3–0 0001 0110 1010 Divider Ratio VCO/SCLK 1:1 6:1 10:1 Example Frequency Ratios (MHz) VCO SCLK 100 100 300 50 500 50 The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1–0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 7. This programmable core clock capability is useful for fast core frequency modifications. Table 7. Core Clock Ratios Signal Name CSEL1–0 00 01 10 11 Page 17 of 88 | July 2013 Divider Ratio VCO/CCLK 1:1 2:1 4:1 8:1 Example Frequency Ratios (MHz) VCO CCLK 300 300 300 150 500 125 200 25 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 The maximum CCLK frequency not only depends on the part's maximum instruction rate (see Page 88). This frequency also depends on the applied VDDINT voltage. See Table 12 and Table 15 for details. The maximal system clock rate (SCLK) depends on the chip package and the applied VDDINT, VDDEXT, and VDDMEM voltages (see Table 14 and Table 17). BOOTING MODES The processor has several mechanisms (listed in Table 8) for automatically loading internal and external memory after a reset. The boot mode is defined by four BMODE input pins dedicated to this purpose. There are two categories of boot modes. In master boot modes the processor actively loads data from parallel or serial memories. In slave boot modes the processor receives data from external host devices. The boot modes listed in Table 8 provide a number of mechanisms for automatically loading the processor’s internal and external memories after a reset. By default, all boot modes use the slowest meaningful configuration settings. Default settings can be altered via the initialization code feature at boot time or by proper OTP programming at pre-boot time. The BMODE pins of the reset configuration register, sampled during poweron resets and software-initiated resets, implement the modes shown in Table 8. Table 8. Booting Modes BMODE3–0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 • Boot from 16-bit asynchronous FIFO (BMODE = 0x2) — In this mode, the boot kernel starts booting from address 0x2030 0000. Every 16-bit word that the boot kernel has to read from the FIFO must be requested by placing a low pulse on the DMAR1 pin. • Boot from serial SPI memory, EEPROM or flash (BMODE = 0x3) — 8-, 16-, 24-, or 32-bit addressable devices are supported. The processor uses the PG1 GPIO pin to select a single SPI EEPROM/flash device and submits a read command and successive address bytes (0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device is detected. Pull-up resistors are required on the SPISEL1 and MISO pins. By default, a value of 0x85 is written to the SPI_BAUD register. • Boot from serial TWI memory, EEPROM/flash (BMODE = 0x5) — The processor operates in master mode and selects the TWI slave connected to the TWI with the unique ID 0xA0. • Idle/no boot mode (BMODE = 0x0) — In this mode, the processor goes into idle. The idle boot mode helps recover from illegal operating modes, such as when the OTP memory has been misconfigured. • Boot from 8-bit or 16-bit external flash memory (BMODE = 0x1) — In this mode, the boot kernel loads the first block header from address 0x2000 0000, and (depending on instructions contained in the header) the boot | The ARDY is not enabled by default, but it can be enabled through OTP programming. Similarly, all interface behavior and timings can be customized through OTP programming. This includes activation of burst-mode or page-mode operation. In this mode, all asynchronous interface signals are enabled at the port muxing level. • Boot from SPI host device (BMODE = 0x4) — The processor operates in SPI slave mode and is configured to receive the bytes of the LDR file from an SPI host (master) agent. The HWAIT signal must be interrogated by the host before every transmitted byte. A pull-up resistor is required on the SPISS input. A pull-down on the serial clock (SCK) may improve signal quality and booting robustness. Description Idle — No boot Boot from 8- or 16-bit external flash memory Boot from 16-bit asynchronous FIFO Boot from serial SPI memory (EEPROM or flash) Boot from SPI host device Boot from serial TWI memory (EEPROM/flash) Boot from TWI host Boot from UART0 Host Boot from UART1 Host Reserved Boot from SDRAM Boot from OTP memory Boot from 8-bit NAND flash via NFC using PORTF data pins Boot from 8-bit NAND flash via NFC using PORTH data pins Boot from 16-Bit Host DMA Boot from 8-Bit Host DMA Rev. D kernel performs an 8- or 16-bit boot or starts program execution at the address provided by the header. By default, all configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle R/W access times, 4-cycle setup). The processor submits successive read commands to the memory device starting at internal address 0x0000 and begins clocking data into the processor. The TWI memory device should comply with the Philips I2C® Bus Specification version 2.1 and should be able to auto-increment its internal address counter such that the contents of the memory device can be read sequentially. By default, a PRESCALE value of 0xA and a TWI_CLKDIV value of 0x0811 are used. Unless altered by OTP settings, an I2C memory that takes two address bytes is assumed. The development tools ensure that data booted to memories that cannot be accessed by the Blackfin core is written to an intermediate storage location and then copied to the final destination via memory DMA. • Boot from TWI host (BMODE = 0x6) — The TWI host selects the slave with the unique ID 0x5F. The processor replies with an acknowledgement and the host then downloads the boot stream. The TWI host agent should comply with the Philips I2C Bus Specification Page 18 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 version 2.1. An I2C multiplexer can be used to select one processor at a time when booting multiple processors from a single TWI. • Boot from UART0 host on Port G (BMODE = 0x7) — Using an autobaud handshake sequence, a boot-stream formatted program is downloaded by the host. The host selects a bit rate within the UART clocking capabilities. When performing the autobaud, the UART expects a “@” (0x40) character (eight bits data, one start bit, one stop bit, no parity bit) on the UART0RX pin to determine the bit rate. The UART then replies with an acknowledgement composed of 4 bytes (0xBF, the value of UART0_DLL, the value of UART0_DLH, then 0x00). The host can then download the boot stream. To hold off the host the Blackfin processor signals the host with the boot host wait (HWAIT) signal. Therefore, the host must monitor HWAIT before every transmitted byte. —Software-configurable boot mode for booting from boot streams spanning multiple blocks, including bad blocks —Software-configurable boot mode for booting from multiple copies of the boot stream, allowing for handling of bad blocks and uncorrectable errors —Configurable timing via OTP memory Small page NAND flash devices must have a 512-byte page size, 32 pages per block, a 16-byte spare area size, and a bus configuration of 8 bits. By default, all read requests from the NAND flash are followed by four address cycles. If the NAND flash device requires only three address cycles, the device must be capable of ignoring the additional address cycles. The small page NAND flash device must comply with the following command set: • Boot from UART1 host on Port F (BMODE = 0x8). Same as BMODE = 0x7 except that the UART1 port is used. —Reset: 0xFF • Boot from SDRAM (BMODE = 0xA) This is a warm boot scenario, where the boot kernel starts booting from address 0x0000 0010. The SDRAM is expected to contain a valid boot stream and the SDRAM controller must be configured by the OTP settings. —Read upper half of page: 0x01 • Boot from OTP memory (BMODE = 0xB) — This provides a stand-alone booting method. The boot stream is loaded from on-chip OTP memory. By default, the boot stream is expected to start from OTP page 0x40 and can occupy all public OTP memory up to page 0xDF. This is 2560 bytes. Since the start page is programmable, the maximum size of the boot stream can be extended to 3072 bytes. • Boot from 8-bit external NAND flash memory (BMODE = 0xC and BMODE = 0xD) — In this mode, auto detection of the NAND flash device is performed. —Read spare area: 0x50 For large-page NAND-flash devices, the four-byte electronic signature is read in order to configure the kernel for booting, which allows support for multiple large-page devices. The fourth byte of the electronic signature must comply with the specification in Table 9 on Page 20. Any NAND flash array configuration from Table 9, excluding 16-bit devices, that also complies with the command set listed below are directly supported by the boot kernel. There are no restrictions on the page size or block size as imposed by the small-page boot kernel. For devices consisting of a five-byte signature, only four are read. The fourth must comply as outlined above. Large page devices must support the following command set: BMODE = 0xC, the processor configures PORTF GPIO pins PF7:0 for the NAND data pins and PORTH pins PH15:10 for the NAND control signals. —Reset: 0xFF BMODE = 0xD, the processor configures PORTH GPIO pins PH7:0 for the NAND data pins and PORTH pins PH15:10 for the NAND control signals. —Read Electronic Signature: 0x90 —Read: 0x00, 0x30 (confirm command) For correct device operation pull-up resistors are required on both ND_CE (PH10) and ND_BUSY (PH13) signals. By default, a value of 0x0033 is written to the NFC_CTL register. The booting procedure always starts by booting from byte 0 of block 0 of the NAND flash device. NAND flash boot supports the following features: —Device Auto Detection —Error Detection & Correction for maximum reliability —No boot stream size limitation —Peripheral DMA providing efficient transfer of all data (excluding the ECC parity data) Rev. D | —Read lower half of page: 0x00 Large-page devices must not support or react to NAND flash command 0x50. This is a small-page NAND flash command used for device auto detection. By default, the boot kernel will always issue five address cycles; therefore, if a large page device requires only four cycles, the device must be capable of ignoring the additional address cycles. • Boot from 16-Bit Host DMA (BMODE = 0xE) — In this mode, the host DMA port is configured in 16-bit Acknowledge mode, with little endian data formatting. Unlike other modes, the host is responsible for interpreting the boot stream. It writes data blocks individually into the Host DMA port. Before configuring the DMA settings for each block, the host may either poll the ALLOW_CONFIG bit in HOST_STATUS or wait to be interrupted by the HWAIT Page 19 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 signal. When using HWAIT, the host must still check ALLOW_CONFIG at least once before beginning to configure the Host DMA Port. After completing the configuration, the host is required to poll the READY bit in HOST_STATUS before beginning to transfer data. When the host sends an HIRQ control command, the boot kernel issues a CALL instruction to address 0xFFA0 0000. It is the host's responsibility to ensure that valid code has been placed at this address. The routine at 0xFFA0 0000 can be a simple initialization routine to configure internal resources, such as the SDRAM controller, which then returns using an RTS instruction. The routine may also by the final application, which will never return to the boot kernel. • Boot from 8-Bit Host DMA (BMODE = 0xF) — In this mode, the Host DMA port is configured in 8-bit interrupt mode, with little endian data formatting. Unlike other modes, the host is responsible for interpreting the boot stream. It writes data blocks individually into the Host DMA port. Before configuring the DMA settings for each block, the host may either poll the ALLOW_CONFIG bit in HOST_STATUS or wait to be interrupted by the HWAIT signal. When using HWAIT, the host must still check ALLOW_CONFIG at least once before beginning to configure the Host DMA Port. The host will receive an interrupt from the HOST_ACK signal every time it is allowed to send the next FIFO depths worth (sixteen 32-bit words) of information. When the host sends an HIRQ control command, the boot kernel issues a CALL instruction to address 0xFFA0 0000. It is the host's responsibility to ensure valid code has been placed at this address. The routine at 0xFFA0 0000 can be a simple initialization routine to configure internal resources, such as the SDRAM controller, which then returns using an RTS instruction. The routine may also by the final application, which will never return to the boot kernel. INSTRUCTION SET DESCRIPTION The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources. The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages: • Seamlessly integrated DSP/MCU features are optimized for both 8-bit and 16-bit operations. • A multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle. • All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model. • Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers. • Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits. DEVELOPMENT TOOLS Table 9. Fourth Byte for Large Page Devices Bit Parameter Analog Devices supports its processors with a complete line of software and hardware development tools, including integrated development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products, emulators, and a wide variety of software add-ins. Value Meaning 00 01 10 11 1K byte 2K byte 4K byte 8K byte Spare Area Size 00 01 8 byte/512 byte 16 byte/512 byte For C/C++ software writing and editing, code generation, and debug support, Analog Devices offers two IDEs. D5:D4 Block Size (excluding spare area) 00 01 10 11 64K byte 128K byte 256K byte 512K byte D6 00 01 x8 not supported The newest IDE, CrossCore Embedded Studio, is based on the EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors, including multicore devices. CrossCore Embedded Studio seamlessly integrates available software add-ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, algorithmic software modules, and evaluation hardware board support packages. For more information, visit www.analog.com/cces. D1:D0 Page Size (excluding spare area) D2 Bus width Integrated Development Environments (IDEs) D3, D7 Not Used for configuration Rev. D | Page 20 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore Embedded Studio. This IDE includes the Analog Devices VDK real time operating system and an open source TCP/IP stack. For more information visit www.analog.com/visualdsp. Note that VisualDSP++ will not support future Analog Devices processors. Middleware Packages Analog Devices separately offers middleware add-ins such as real time operating systems, file systems, USB stacks, and TCP/ IP stacks. For more information see the following web pages: • www.analog.com/ucos3 • www.analog.com/ucfs EZ-KIT Lite Evaluation Board • www.analog.com/ucusbd For processor evaluation, Analog Devices provides wide range of EZ-KIT Lite® evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. Also available are various EZ-Extenders®, which are daughter cards delivering additional specialized functionality, including audio and video processing. For more information visit www.analog.com and search on “ezkit” or “ezextender”. • www.analog.com/lwip EZ-KIT Lite Evaluation Kits For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT Lite evaluation board, directions for downloading an evaluation version of the available IDE(s), a USB cable, and a power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user’s PC, enabling the chosen IDE evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also supports in-circuit programming of the on-board Flash device to store user-specific boot code, enabling standalone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices processors. Software Add-Ins for CrossCore Embedded Studio Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities and reduce development time. Add-ins include board support packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through the CrossCore Embedded Studio IDE once the add-in is installed. Algorithmic Modules To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are available for use with both CrossCore Embedded Studio and VisualDSP++. For more information visit www.analog.com and search on “Blackfin software modules” or “SHARC software modules”. Designing an Emulator-Compatible DSP Board (Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports connection of the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the Engineer-to-Engineer Note “Analog Devices JTAG Emulation Technical Reference” (EE-68) on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION The following publications that describe the ADSP-BF52x processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website: Board Support Packages for Evaluation Hardware • Getting Started With Blackfin Processors Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called Board Support Packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download area of the product web page. • ADSP-BF52x Blackfin Processor Hardware Reference (volumes 1 and 2) Rev. D | • Blackfin Processor Programming Reference • ADSP-BF522/ADSP-BF524/ADSP-BF526 Blackfin Processor Anomaly List • ADSP-BF523/ADSP-BF525/ADSP-BF527 Blackfin Processor Anomaly List Page 21 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in Wikipedia or the Glossary of EE Terms on the Analog Devices website. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The Application Signal Chains page in the Circuits from the LabTM site (http:\\www.analog.com\signalchains) provides: • Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications • Drill down links for components in each chain to selection guides and application information • Reference designs applying best practice design techniques LOCKBOX SECURE TECHNOLOGY DISCLAIMER Analog Devices products containing Lockbox Secure Technology are warranted by Analog Devices as detailed in the Analog Devices Standard Terms and Conditions of Sale. To our knowledge, the Lockbox Secure Technology, when used in accordance with the data sheet and hardware reference manual specifications, provides a secure method of implementing code and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE LOCKBOX SECURE TECHNOLOGY CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY. Rev. D | Page 22 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SIGNAL DESCRIPTIONS Signal definitions for the ADSP-BF52x processors are listed in Table 10. In order to maintain maximum function and reduce package size and ball count, some balls have dual, multiplexed functions. In cases where ball function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics. All pins are three-stated during and immediately after reset, with the exception of the external memory interface, asynchronous and synchronous memory control, and the buffered XTAL output pin (CLKBUF). On the external memory interface, the control and address lines are driven high, with the exception of CLKOUT, which toggles at the system clock rate. During hibernate, all outputs are three-stated unless otherwise noted in Table 10. All I/O pins have their input buffers disabled with the exception of the pins that need pull-ups or pull-downs, as noted in Table 10. It is strongly advised to use the available IBIS models to ensure that a given board design meets overshoot/undershoot and signal integrity requirements. If no IBIS simulation is performed, it is strongly recommended to add series resistor terminations for all Driver Types A, C and D. The termination resistors should be placed near the processor to reduce transients and improve signal integrity. The resistance value, typically 33 Ω or 47 Ω, should be chosen to match the average board trace impedance. Additionally, adding a parallel termination to CLKOUT may prove useful in further enhancing signal integrity. Be sure to verify overshoot/undershoot and signal integrity specifications on actual hardware. Table 10. Signal Descriptions Type Function Driver Type1 ADDR19–1 O Address Bus A DATA15–0 I/O Data Bus A ABE1–0/SDQM1–0 O Byte Enables/Data Mask A Signal Name EBIU AMS3–0 O Asynchronous Memory Bank Selects (Require pull-ups if hibernate is used.) A ARDY I Hardware Ready Control AOE O Asynchronous Output Enable A ARE O Asynchronous Read Enable A AWE O Asynchronous Write Enable A SRAS O SDRAM Row Address Strobe A SCAS O SDRAM Column Address Strobe A SWE O SDRAM Write Enable A SCKE O SDRAM Clock Enable (Requires a pull-down if hibernate with SDRAM selfrefresh is used.) A CLKOUT O SDRAM Clock Output B SA10 O SDRAM A10 Signal A SMS O SDRAM Bank Select A Rev. D | Page 23 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Signal Name Type Function Driver Type1 USB 2.0 HS OTG USB_DP I/O Data + (This ball should be pulled low when USB is unused or not present.) F USB_DM I/O Data – (This ball should be pulled low when USB is unused or not present.) F USB_XI I USB Crystal Input (This ball should be pulled low when USB is unused or not present.) USB_XO O USB Crystal Output (This ball should be left unconnected when USB is unused F or not present.) USB_ID I USB OTG mode (This ball should be pulled low when USB is unused or not present.) USB_VREF A USB voltage reference (Connect to GND through a 0.1 μF capacitor or leave unconnected when not used.) USB_RSET A USB resistance set. (This ball should be left unconnected.) USB_VBUS I/O 5V USB VBUS. USB_VBUS is an output only in peripheral mode during SRP F signaling. Host mode requires that an external voltage source of 5 V at 8 mA or more (per the OTG specification) be applied to VBUS. The voltage source needs to be able to charge and discharge VBUS, thus an ON/OFF switch is required to control the voltage source. A GPIO can be used for this purpose (This ball should be pulled low when USB is unused or not present.) Port F: GPIO and Multiplexed Peripherals PF0/PPI D0/DR0PRI /ND_D0A I/O GPIO/PPI Data 0/SPORT0 Primary Receive Data /NAND Alternate Data 0 C PF1/PPI D1/RFS0/ND_D1A I/O GPIO/PPI Data 1/SPORT0 Receive Frame Sync /NAND Alternate Data 1 C PF2/PPI D2/RSCLK0/ND_D2A I/O GPIO/PPI Data 2/SPORT0 Receive Serial Clock /NAND Alternate Data 2/Alternate Capture Input 0 D PF3/PPI D3/DT0PRI/ND_D3A I/O GPIO/PPI Data 3/SPORT0 Transmit Primary Data /NAND Alternate Data 3 C PF4/PPI D4/TFS0/ND_D4A/TACLK0 I/O GPIO/PPI Data 4/SPORT0 Transmit Frame Sync /NAND Alternate Data 4/Alternate Timer Clock 0 C PF5/PPI D5/TSCLK0/ND_D5A/TACLK1 I/O GPIO/PPI Data 5/SPORT0 Transmit Serial Clock /NAND Alternate Data 5/Alternate Timer Clock 1 D PF6/PPI D6/DT0SEC/ND_D6A/TACI0 I/O GPIO/PPI Data 6/SPORT0 Transmit Secondary Data /NAND Alternate Data 6/Alternate Capture Input 0 C PF7/PPI D7/DR0SEC/ND_D7A/TACI1 I/O GPIO/PPI Data 7/SPORT0 Receive Secondary Data /NAND Alternate Data 7/Alternate Capture Input 1 C PF8/PPI D8/DR1PRI I/O GPIO/PPI Data 8/SPORT1 Primary Receive Data C PF9/PPI D9/RSCLK1/SPISEL6 I/O GPIO/PPI Data 9/SPORT1 Receive Serial Clock/SPI Slave Select 6 D PF10/PPI D10/RFS1/SPISEL7 I/O GPIO/PPI Data 10/SPORT1 Receive Frame Sync/SPI Slave Select 7 C PF11/PPI D11/TFS1/CZM I/O GPIO/PPI Data 11/SPORT1 Transmit Frame Sync/Counter Zero Marker C PF12/PPI D12/DT1PRI/SPISEL2/CDG I/O GPIO/PPI Data 12/SPORT1 Transmit Primary Data/SPI Slave Select 2/Counter Down Gate C PF13/PPI D13/TSCLK1/SPISEL3/CUD I/O GPIO/PPI Data 13/SPORT1 Transmit Serial Clock/SPI Slave Select 3/Counter Up D Direction PF14/PPI D14/DT1SEC/UART1TX I/O GPIO/PPI Data 14/SPORT1 Transmit Secondary Data/UART1 Transmit C PF15/PPI D15/DR1SEC/UART1RX/TACI3 I/O GPIO/PPI Data 15/SPORT1 Receive Secondary Data /UART1 Receive /Alternate Capture Input 3 C Rev. D | Page 24 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Signal Name Type Function Driver Type1 Port G: GPIO and Multiplexed Peripherals PG0/HWAIT I/O GPIO/Boot Host Wait2 C PG1/SPISS/SPISEL1 I/O GPIO/SPI Slave Select Input/SPI Slave Select 1 C PG2/SCK I/O GPIO/SPI Clock D PG3/MISO/DR0SECA I/O GPIO/SPI Master In Slave Out/Sport 0 Alternate Receive Data Secondary C PG4/MOSI/DT0SECA I/O GPIO/SPI Master Out Slave In/Sport 0 Alternate Transmit Data Secondary C PG5/TMR1/PPI_FS2 I/O GPIO/Timer1/PPI Frame Sync2 C PG6/DT0PRIA/TMR2/PPI_FS3 I/O GPIO/SPORT0 Alternate Primary Transmit Data / Timer2 / PPI Frame Sync3 C PG7/TMR3/DR0PRIA/UART0TX I/O GPIO/Timer3/Sport 0 Alternate Receive Data Primary/UART0 Transmit C PG8/TMR4/RFS0A/UART0RX/TACI4 I/O GPIO/Timer 4/Sport 0 Alternate Receive Clock/Frame Sync /UART0 Receive/Alternate Capture Input 4 C PG9/TMR5/RSCLK0A/TACI5 I/O GPIO/Timer5/Sport 0 Alternate Receive Clock /Alternate Capture Input 5 D PG10/TMR6/TSCLK0A/TACI6 I/O GPIO/Timer 6 /Sport 0 Alternate Transmit /Alternate Capture Input 6 D PG11/TMR7/HOST_WR I/O GPIO/Timer7/Host DMA Write Enable C PG12/DMAR1/UART1TXA/HOST_ACK I/O GPIO/DMA Request 1/Alternate UART1 Transmit/Host DMA Acknowledge C PG13/DMAR0/UART1RXA/HOST_ADDR/TACI2 I/O GPIO/DMA Request 0/Alternate UART1 Receive/Host DMA Address/Alternate Capture Input 2 C PG14/TSCLK0A1/MDC/HOST_RD I/O GPIO/SPORT0 Alternate 1 Transmit/Ethernet Management Channel Clock /Host DMA Read Enable D PG153/TFS0A/MII PHYINT/RMII MDINT/HOST_CE I/O GPIO/SPORT0 Alternate Transmit Frame Sync/Ethernet/MII PHY Interrupt/RMII C Management Channel Data Interrupt/Host DMA Chip Enable Port H: GPIO and Multiplexed Peripherals PH0/ND_D0/MIICRS/RMIICRSDV/HOST_D0 I/O GPIO/NAND D0/Ethernet MII or RMII Carrier Sense/Host DMA D0 C PH1/ND_D1/ERxER/HOST_D1 I/O GPIO/NAND D1/Ethernet MII or RMII Receive Error/Host DMA D1 C PH2/ND_D2/MDIO/HOST_D2 I/O GPIO/NAND D2/Ethernet Management Channel Serial Data/Host DMA D2 C PH3/ND_D3/ETxEN/HOST_D3 I/O GPIO/NAND D3/Ethernet MII Transmit Enable/Host DMA D3 C PH4/ND_D4/MIITxCLK/RMIIREF_CLK/HOST_D4 I/O GPIO/NAND D4/Ethernet MII or RMII Reference Clock/Host D4 C PH5/ND_D5/ETxD0/HOST_D5 I/O GPIO/NAND D5/Ethernet MII or RMII Transmit D0/Host DMA D5 C PH6/ND_D6/ERxD0/HOST_D6 I/O GPIO/NAND D6/Ethernet MII or RMII Receive D0/Host DMA D6 C PH7/ND_D7/ETxD1/HOST_D7 I/O GPIO/NAND D7/Ethernet MII or RMII Transmit D1/Host DMA D7 C PH8/SPISEL4/ERxD1/HOST_D8/TACLK2 I/O GPIO/Alternate Timer Clock 2/Ethernet MII or RMII Receive D1/Host DMA D8 /SPI Slave Select 4 C PH9/SPISEL5/ETxD2/HOST_D9/TACLK3 I/O GPIO/SPI Slave Select 5/Ethernet MII Transmit D2/Host DMA D9 /Alternate Timer Clock 3 C PH10/ND_CE/ERxD2/HOST_D10 I/O GPIO/NAND Chip Enable/Ethernet MII Receive D2/Host DMA D10 C PH11/ND_WE/ETxD3/HOST_D11 I/O GPIO/NAND Write Enable/Ethernet MII Transmit D3/Host DMA D11 C PH12/ND_RE/ERxD3/HOST_D12 I/O GPIO/NAND Read Enable/Ethernet MII Receive D3/Host DMA D12 C PH13/ND_BUSY/ERxCLK/HOST_D13 I/O GPIO/NAND Busy/Ethernet MII Receive Clock/Host DMA D13 C PH14/ND_CLE/ERxDV/HOST_D14 I/O GPIO/NAND Command Latch Enable/Ethernet MII or RMII Receive Data Valid/ C Host DMA D14 PH15/ND_ALE/COL/HOST_D15 I/O GPIO/NAND Address Latch Enable/Ethernet MII Collision/Host DMA Data 15 Rev. D | Page 25 of 88 | July 2013 C ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Type Function Driver Type1 I/O PPI Frame Sync1/Timer0 C PJ1: PPI_CLK/TMRCLK I PPI Clock/Timer Clock PJ2: SCL I/O 5V TWI Serial Clock (This pin is an open-drain output and requires a pull-up resistor.4) E PJ3: SDA I/O 5V TWI Serial Data (This pin is an open-drain output and requires a pull-up resistor.4) E Signal Name Port J: Multiplexed Peripherals PJ0: PPI_FS1/TMR0 Real Time Clock RTXI I RTC Crystal Input (This ball should be pulled low when not used.) RTXO O RTC Crystal Output (Does not three-state during hibernate.) TCK I JTAG Clock TDO O JTAG Serial Data Out TDI I JTAG Serial Data In TMS I JTAG Mode Select TRST I JTAG Reset (This ball should be pulled low if the JTAG port is not used.) EMU O Emulation Output I Clock/Crystal Input JTAG Port C C Clock CLKIN XTAL O Crystal Output (If CLKBUF is enabled, does not three-state during hibernate.) CLKBUF O Buffered XTAL Output (If enabled, does not three-state during hibernate.) I Reset C Mode Controls RESET NMI I Nonmaskable Interrupt (This ball should be pulled high when not used.) BMODE3–0 I Boot Mode Strap 3-0 VRSEL I Internal/External Voltage Regulator Select VROUT/EXT_WAKE1 O External FET Drive/Wake up Indication 1 (Does not three-state during hibernate.) G EXT_WAKE0 O Wake up Indication 0 (Does not three-state during hibernate.) C SS/PG A Soft Start/Power Good EXT_WAKE1 O Wake up Indication 1 (Does not three-state during hibernate.) C EXT_WAKE0 O Wake up Indication 0 (Does not three-state during hibernate.) C PG A Power Good (This signal should be pulled low when not used.) ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation I/F ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation I/F Rev. D | Page 26 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 10. Signal Descriptions (Continued) Signal Name Type Function Driver Type1 ALL SUPPLIES MUST BE POWERED See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page 30, and see Operating Conditions for ADSP-BF522/ ADSP-BF524/ADSP-BF526 Processors on Page 28. Power Supplies VDDEXT P I/O Power Supply VDDINT P Internal Power Supply VDDRTC P Real Time Clock Power Supply VDDUSB P 3.3 V USB Phy Power Supply VDDMEM P MEM Power Supply VDDOTP P OTP Power Supply VPPOTP P OTP Programming Voltage GND G Ground for All Supplies 1 See Output Drive Currents on Page 73 for more information about each driver type. HWAIT must be pulled high or low to configure polarity. It is driven as an output and toggle during processor boot. See Booting Modes on Page 18. 3 When driven low, this ball can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as MII PHYINT. If the ball is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the ball with a resistor. 4 Consult version 2.1 of the I2C specification for the proper resistor value. 2 Rev. D | Page 27 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SPECIFICATIONS Specifications are subject to change without notice. OPERATING CONDITIONS FOR ADSP-BF522/ADSP-BF524/ADSP-BF526 PROCESSORS Parameter VDDINT VDDEXT VDDEXT VDDEXT VDDRTC VDDMEM VDDMEM VDDMEM VDDOTP VPPOTP Conditions VDDUSB VIH VIH VIH VIHTWI9 VIL VIL VIL VILTWI TJ Internal Supply Voltage External Supply Voltage1 External Supply Voltage1 External Supply Voltage1 RTC Power Supply Voltage2 MEM Supply Voltage1, 3 MEM Supply Voltage1, 3 MEM Supply Voltage1, 3 OTP Supply Voltage1 OTP Programming Voltage1 For Reads For Writes4 USB Supply Voltage5 High Level Input Voltage6, 7 High Level Input Voltage6, 8 High Level Input Voltage6, 8 High Level Input Voltage Low Level Input Voltage6, 7 Low Level Input Voltage6, 8 Low Level Input Voltage6, 8 Low Level Input Voltage Junction Temperature TJ Junction Temperature TJ Junction Temperature Min 1.235 1.7 2.25 3 2.25 1.7 2.25 3 2.25 2.25 6.9 3.0 VDDEXT/VDDMEM = 1.90 V 1.1 VDDEXT/VDDMEM = 2.75 V 1.7 VDDEXT/VDDMEM = 3.6 V 2.0 VDDEXT = 1.90 V/2.75 V/3.6 V 0.7 × VBUSTWI VDDEXT/VDDMEM = 1.7 V VDDEXT/VDDMEM = 2.25 V VDDEXT/VDDMEM = 3.0 V VDDEXT = Minimum 0 289-Ball CSP_BGA @ TAMBIENT = 0°C to +70°C 0 208-Ball CSP_BGA @ TAMBIENT = 0°C to +70°C –40 208-Ball CSP_BGA @ TAMBIENT = –40°C to +85°C 1 Nominal 1.8 2.5 3.3 2.5 Max 1.47 1.9 2.75 3.6 3.6 1.9 2.75 3.6 2.75 Unit V V V V V V V V V 2.5 7.0 3.3 2.75 7.1 3.6 VBUSTWI 0.6 0.7 0.8 0.3 × VBUSTWI10 +105 V V V V V V V V V V V °C +105 °C +105 °C 1.8 2.5 3.3 Must remain powered (even if the associated function is not used). If not used, power with VDDEXT. 3 Balls that use VDDMEM are DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AOE, AMS3–0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls are not tolerant to voltages higher than VDDMEM. 4 The VPPOTP voltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent on voltage and junction temperature) over the lifetime of the part. Please see Table 30 on Page 38 for details. 5 When not using the USB peripheral on the ADSP-BF524/ADSP-BF526 or terminating VDDUSB on the ADSP-BF522, VDDUSB must be powered by VDDEXT. 6 Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL. 7 Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are 2.5 V tolerant (always accept up to 2.7 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 8 Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are 3.3 V tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 9 The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 11. 10 SDA and SCL are pulled up to VBUSTWI. See Table 11. 2 Rev. D | Page 28 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 11 shows settings for TWI_DT in the NONGPIO_DRIVE register. Set this register prior to using the TWI port. Table 11. TWI_DT Field Selections and VDDEXT/VBUSTWI TWI_DT 000 (default)1 001 010 011 100 101 110 111 (reserved) 1 VDDEXT Nominal 3.3 1.8 2.5 1.8 3.3 1.8 2.5 – VBUSTWI Min 2.97 1.7 2.97 2.97 4.5 2.25 2.25 – VBUSTWI Nominal 3.3 1.8 3.3 3.3 5 2.5 2.5 – VBUSTWI Max 3.63 1.98 3.63 3.63 5.5 2.75 2.75 – Unit V V V V V V V – Designs must comply with the VDDEXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset. Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Table 12 describes the core clock timing requirements for the ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table 14). Table 13 describes phase-locked loop operating conditions. Table 12. Core Clock (CCLK) Requirements (All Instruction Rates1) for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Parameter fCCLK fCCLK 1 2 Core Clock Frequency (VDDINT =1.33 V minimum) Core Clock Frequency (VDDINT = 1.235 V minimum) Nominal Voltage Setting 1.40 V 1.30 V Max 4002 300 Unit MHz MHz See the Ordering Guide on Page 88. Applies to 400 MHz models only. See the Ordering Guide on Page 88. Table 13. Phase-Locked Loop Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Parameter fVCO 1 Voltage Controlled Oscillator (VCO) Frequency Min 70 Max Instruction Rate1 Unit MHz VDDEXT/VDDMEM 2.5 V or 3.3 V Nominal Max 100 80 Unit MHz MHz See the Ordering Guide on Page 88. Table 14. SCLK Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors VDDEXT/VDDMEM 1.8 V Nominal1 Parameter fSCLK fSCLK 1 2 CLKOUT/SCLK Frequency (VDDINT ≥ 1.33 V)2 CLKOUT/SCLK Frequency (VDDINT < 1.33 V) Max 80 80 If either VDDEXT or VDDMEM are operating at 1.8 V nominal, fSCLK is constrained to 80 MHz. fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 37 on Page 47. Rev. D | Page 29 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 OPERATING CONDITIONS FOR ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS Parameter VDDINT VDDINT Internal Supply Voltage1 Internal Supply Voltage1 VDDINT VDDEXT Internal Supply Voltage1 External Supply Voltage4, 5 VDDEXT VDDEXT VDDEXT VDDRTC VDDRTC VDDMEM VDDMEM VDDMEM VDDMEM VDDOTP VPPOTP VDDUSB VIH VIH VIH VIHTWI VIL VIL VIL VILTWI TJ External Supply Voltage4, 5 External Supply Voltage4, 5 External Supply Voltage4, 5 RTC Power Supply Voltage6 RTC Power Supply Voltage6 MEM Supply Voltage4, 7 MEM Supply Voltage4, 7 MEM Supply Voltage4, 7 MEM Supply Voltage4, 7 OTP Supply Voltage4 OTP Programming Voltage4 USB Supply Voltage8 High Level Input Voltage9, 10 High Level Input Voltage10, 11 High Level Input Voltage10, 11 High Level Input Voltage12 Low Level Input Voltage9, 10 Low Level Input Voltage10, 11 Low Level Input Voltage10, 11 Low Level Input Voltage Junction Temperature TJ Junction Temperature TJ Junction Temperature TJ Junction Temperature Conditions Min Nonautomotive models2 0.95 Automotive 533 MHz models3 1.093 Automotive 400 MHz models3 Nonautomotive models, Internal Voltage Regulator Disabled Nonautomotive models Nonautomotive models Automotive models Nonautomotive models Automotive models Nonautomotive models Nonautomotive models Nonautomotive models Automotive models VDDEXT/VDDMEM = 1.90 V VDDEXT/VDDMEM = 2.75 V VDDEXT/VDDMEM = 3.6 V VDDEXT = 1.90 V/2.75 V/3.6 V VDDEXT/VDDMEM = 1.7 V VDDEXT/VDDMEM = 2.25 V VDDEXT/VDDMEM = 3.0 V VDDEXT = Minimum 289-Ball CSP_BGA @ TAMBIENT = 0°C to +70°C 289-Ball CSP_BGA @ TAMBIENT = –40°C to +70°C 208-Ball CSP_BGA @ TAMBIENT = 0°C to +70°C 208-Ball CSP_BGA @ TAMBIENT = –40°C to +85°C 1.15 Max 1.26 1.26 1.045 1.7 1.10 1.8 1.20 1.9 V V 2.25 3 2.7 2.25 2.7 1.7 2.25 3 2.7 2.25 2.25 3.0 1.1 1.7 2.0 0.7 × VBUSTWI 2.5 3.3 3.3 2.75 3.6 3.6 3.6 3.6 1.9 2.75 3.6 3.6 2.75 2.75 3.6 0 VBUSTWI 0.6 0.7 0.8 0.3 × VBUSTWI13 +105 V V V V V V V V V V V V V V V V V V V V °C –40 +105 °C 0 +105 °C –40 +105 °C 1 Nominal 3.3 1.8 2.5 3.3 3.3 2.5 2.5 3.3 Unit V V The voltage regulator can generate VDDINT at levels of 1.00 V to 1.20 V with –5% to +5% tolerance when VRCTL is programmed with the bfrom_SysControl() API. This specification is only guaranteed when the API is used. See Ordering Guide on Page 88. 3 See Automotive Products on Page 87. 4 Must remain powered (even if the associated function is not used). 5 VDDEXT is the supply to the voltage regulator and GPIO. 6 If not used, power with VDDEXT. 7 Balls that use VDDMEM are DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AOE, AMS3–0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls are not tolerant to voltages higher than VDDMEM. 8 When not using the USB peripheral on the ADSP-BF525/ADSP-BF527 or terminating VDDUSB on the ADSP-BF523, VDDUSB must be powered by VDDEXT. 9 Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are 2.5 V tolerant (always accept up to 2.7 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 10 Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL. 11 Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are 3.3 V tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 12 The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 11 on Page 29. 13 SDA and SCL are pulled up to VBUSTWI. See Table 11 on Page 29. 2 Rev. D | Page 30 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Table 15 describes the core clock timing requirements for the ADSP-BF523/ADSP-BF525/ADSP-BF527 processors. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table 17). Table 16 describes phase-locked loop operating conditions. Use the nominal voltage setting (Table 15) for internal and external regulators. Table 15. Core Clock (CCLK) Requirements (All Instruction Rates1) for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter fCCLK fCCLK fCCLK fCCLK Core Clock Frequency (VDDINT =1.14 V minimum) Core Clock Frequency (VDDINT =1.093 V minimum) Core Clock Frequency (VDDINT = 1.045 V minimum)4 Core Clock Frequency (VDDINT = 0.95 V minimum) Nominal Voltage Setting 1.20 V 1.15 V 1.10 V 1.0 V Max 6002 5333 400 400 Unit MHz MHz MHz MHz 1 See the Ordering Guide on Page 88. Applies to 600 MHz models only. See the Ordering Guide on Page 88. 3 Applies to 533 MHz and 600 MHz models only. See the Ordering Guide on Page 88. 4 Applies only to automotive products. See Automotive Products on Page 87. 2 Table 16. Phase-Locked Loop Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter fVCO fVCO 1 Voltage Controlled Oscillator (VCO) Frequency (Commercial/Industrial Models) Voltage Controlled Oscillator (VCO) Frequency (Automotive Models) Min 60 Max Instruction Rate1 Unit MHz 70 Instruction Rate1 MHz VDDEXT/VDDMEM 2.5 V or 3.3 V Nominal Max 1333 100 Unit MHz MHz See the Ordering Guide on Page 88. Table 17. SCLK Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors VDDEXT/VDDMEM 1.8 V Nominal1 Parameter fSCLK fSCLK 2 CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V) CLKOUT/SCLK Frequency (VDDINT < 1.14 V)2 Max 100 100 1 If either VDDEXT or VDDMEM are operating at 1.8 V nominal, fSCLK is constrained to 100 MHz. fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 38 on Page 47. 3 Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 38 on Page 47. 2 Rev. D | Page 31 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ELECTRICAL CHARACTERISTICS Table 18. Common Electrical Characteristics for All ADSP-BF52x Processors Parameter Test Conditions Min Typical Max Unit VOH High Level Output Voltage VDDEXT /VDDMEM = 1.7 V, IOH = –0.5 mA 1.35 V VOH High Level Output Voltage VDDEXT /VDDMEM = 2.25 V, IOH = –0.5 mA 2.0 V VOH High Level Output Voltage VDDEXT /VDDMEM = 3.0 V, IOH = –0.5 mA 2.4 V VOL Low Level Output Voltage VDDEXT /VDDMEM = 1.7 V/2.25 V/ 3.0 V, IOL = 2.0 mA 0.4 V IIH High Level Input Current1 VDDEXT /VDDMEM =3.6 V, VIN = 3.6 V 10.0 μA IIL Low Level Input Current1 VDDEXT /VDDMEM =3.6 V, VIN = 0 V 10.0 μA 75.0 μA IIHP 2 High Level Input Current JTAG VDDEXT = 3.6 V, VIN = 3.6 V 3 IOZH Three-State Leakage Current VDDEXT /VDDMEM= 3.6 V, VIN = 3.6 V 10.0 μA IOZHTWI Three-State Leakage Current4 VDDEXT =3.0 V, VIN = 5.5 V 10.0 μA 10.0 μA 8 pF 15 pF IOZL 3 Three-State Leakage Current VDDEXT /VDDMEM= 3.6 V, VIN = 0 V CIN Input Capacitance 5,6 fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V CINTWI Input Capacitance4,6 fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V 1 Applies to input balls. Applies to JTAG input balls (TCK, TDI, TMS, TRST). 3 Applies to three-statable balls. 4 Applies to bidirectional balls SCL and SDA. 5 Applies to all signal balls, except SCL and SDA. 6 Guaranteed, but not tested. 2 Rev. D | Page 32 of 88 | July 2013 5 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 19. Electrical Characteristics for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Parameter 1 Test Conditions Min Typical Max Unit VDDINT Current in VDDINT = 1.3 V, fCCLK = 0 MHz, fSCLK = 0 MHz, Deep Sleep Mode TJ = 25°C, ASF = 0.00 2 mA IDDSLEEP VDDINT Current in Sleep Mode VDDINT = 1.3 V, fSCLK = 25 MHz, TJ = 25°C 13 mA IDD-IDLE VDDINT Current in Idle VDDINT = 1.3 V, fCCLK = 300 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 0.4 44 mA IDD-TYP VDDINT Current VDDINT = 1.3 V, fCCLK = 300 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 1.00 83 mA IDD-TYP VDDINT Current VDDINT = 1.4 V, fCCLK = 400 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 1.00 114 mA IDDHIBERNATE1, 2 Hibernate State Current VDDEXT =VDDMEM =VDDRTC =VDDUSB = 3.30 V, VDDOTP =VPPOTP =2.5 V, TJ = 25°C, CLKIN = 0 MHz with voltage regulator off (VDDINT = 0 V) 40 μA IDDRTC VDDRTC Current VDDRTC = 3.3 V, TJ = 25°C 20 μA IDDUSB-FS VDDUSB Current in Full/Low Speed Mode VDDUSB = 3.3 V, TJ = 25°C, Full Speed USB Transmit 9 mA IDDUSB-HS VDDUSB Current in VDDUSB = 3.3 V, TJ = 25°C, High Speed USB Transmit High Speed Mode 25 mA IDDSLEEP1, 3 VDDINIT Current in Sleep Mode IDDDEEPSLEEP1, 3 VDDINT Current in fCCLK = 0 MHz, fSCLK = 0 MHz Deep Sleep Mode Table 22 IDDINT3, 5 VDDINT Current fCCLK > 0 MHz, fSCLK ≥ 0 MHz mA Table 22 + (Table 23 × ASF) + (0.52 × VDDINT × fSCLK) IDDOTP VDDOTP Current VDDOTP = 2.5 V, TJ = 25°C, OTP Memory Read 2 mA IDDOTP VDDOTP Current VDDOTP = 2.5 V, TJ = 25°C, OTP Memory Write 2 mA IPPOTP VPPOTP Current VPPOTP = 2.5 V, TJ = 25°C, OTP Memory Read 100 μA IPPOTP VPPOTP Current VPPOTP = see Table 30, TJ = 25°C, OTP Memory Write 3 mA IDDDEEPSLEEP Table 22 + mA4 4 (0.52 × VDDINT × fSCLK) fCCLK = 0 MHz, fSCLK > 0 MHz 1 See the ADSP-BF52x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. Includes current on VDDEXT, VDDUSB, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low. 3 Guaranteed maximum specifications. 4 Unit for VDDINT is V (Volts). Unit for fSCLK is MHz. Example: 1.4 V, 75 MHz would be 0.52 × 1.4 × 75 = 54.6 mA adder. 5 See Table 21 for the list of IDDINT power vectors covered. 2 Rev. D | Page 33 of 88 | July 2013 mA ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 20. Electrical Characteristics for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Parameter 1 Test Conditions Min Typical Max Unit VDDINT Current in VDDINT = 1.0 V, fCCLK = 0 MHz, fSCLK = 0 MHz, Deep Sleep Mode TJ = 25°C, ASF = 0.00 10 mA IDDSLEEP VDDINT Current in Sleep Mode VDDINT = 1.0 V, fSCLK = 25 MHz, TJ = 25°C 20 mA IDD-IDLE VDDINT Current in Idle VDDINT = 1.0 V, fCCLK = 400 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 0.44 53 mA IDD-TYP VDDINT Current VDDINT = 1.0 V, fCCLK = 400 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 1.00 94 mA IDD-TYP VDDINT Current VDDINT = 1.15 V, fCCLK = 533 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 1.00 144 mA IDD-TYP VDDINT Current VDDINT = 1.2 V, fCCLK = 600 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 1.00 170 mA IDDHIBERNATE1, 2 Hibernate State Current VDDEXT =VDDMEM =VDDRTC = VDDUSB = 3.30 V, VDDOTP =VPPOTP =2.5 V, TJ = 25°C, CLKIN = 0 MHz with voltage regulator off (VDDINT = 0 V) 40 μA IDDRTC VDDRTC Current VDDRTC = 3.3 V, TJ = 25°C 20 μA IDDUSB-FS VDDUSB Current in Full/Low Speed Mode VDDUSB = 3.3 V, TJ = 25°C, Full Speed USB Transmit 9 mA IDDUSB-HS VDDUSB Current in VDDUSB = 3.3 V, TJ = 25°C, High Speed USB High Speed Mode Transmit 25 mA IDDSLEEP1, 3 VDDINT Current in Sleep Mode IDDDEEPSLEEP1, 3 IDDDEEPSLEEP Table 24 + (0.61 × VDDINT × fSCLK)4 mA4 VDDINT Current in fCCLK = 0 MHz, fSCLK = 0 MHz Deep Sleep Mode Table 24 mA IDDINT3, 5 VDDINT Current fCCLK > 0 MHz, fSCLK ≥ 0 MHz Table 24 + (Table 25 mA × ASF) + (0.61 × VDDINT × fSCLK) IDDOTP VDDOTP Current VDDOTP = 2.5 V, TJ = 25°C, OTP Memory Read IDDOTP VDDOTP Current VDDOTP = 2.5 V, TJ = 25°C, OTP Memory Write 25 mA IPPOTP VPPOTP Current VPPOTP = 2.5 V, TJ = 25°C, OTP Memory Read 0 mA IPPOTP VPPOTP Current VPPOTP = 2.5 V, TJ = 25°C, OTP Memory Write 0 mA fCCLK = 0 MHz, fSCLK > 0 MHz 1 1 See the ADSP-BF52x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. Includes current on VDDEXT, VDDUSB, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low. 3 Guaranteed maximum specifications. 4 Unit for VDDINT is V (Volts). Unit for fSCLK is MHz. Example: 1.2 V, 75 MHz would be 0.61 × 1.2 × 75 = 54.9 mA adder. 5 See Table 21 for the list of IDDINT power vectors covered. 2 Rev. D | Page 34 of 88 | July 2013 mA ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Total Power Dissipation Total power dissipation has two components: 1. Static, including leakage current 2. Dynamic, due to transistor switching characteristics Many operating conditions can also affect power dissipation, including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics on Page 32 shows the current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP specifies static power dissipation as a function of voltage (VDDINT) and temperature (see Table 22 or Table 24), and IDDINT specifies the total power specification for the listed test conditions, including the dynamic component as a function of voltage (VDDINT) and frequency (Table 23 or Table 25). There are two parts to the dynamic component. The first part is due to transistor switching in the core clock (CCLK) domain. This part is subject to an Activity Scaling Factor (ASF) which represents application code running on the processor core and L1 memories (Table 21). The ASF is combined with the CCLK Frequency and VDDINT dependent data in Table 23 or Table 25 to calculate this part. The second part is due to transistor switching in the system clock (SCLK) domain, which is included in the IDDINT specification equation. Table 21. Activity Scaling Factors (ASF)1 IDDINT Power Vector IDD-PEAK IDD-HIGH IDD-TYP IDD-APP IDD-NOP IDD-IDLE 1 Activity Scaling Factor (ASF) 1.29 1.26 1.00 0.88 0.72 0.44 See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors (EE-297). The power vector information also applies to the ADSP-BF52x processors. Table 22. Static Current — IDD-DEEPSLEEP (mA) for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors 1 TJ (°C) –40 –20 0 25 40 55 70 85 100 105 1 1.2 V 1.47 1.67 1.97 2.49 3.12 4.07 5.77 8.32 12.11 13.78 1.25 V 1.42 1.81 2.07 2.66 3.37 4.47 6.28 8.88 12.93 14.72 1.3 V 1.50 1.89 2.15 2.79 3.57 4.82 6.71 9.56 13.94 15.74 Voltage (VDDINT)1 1.35 V 1.4 V 1.64 1.85 1.95 2.01 2.22 2.30 2.92 3.07 3.75 3.96 5.11 5.41 7.17 7.61 10.25 10.94 14.76 15.76 16.81 17.91 1.45 V 2.12 2.07 2.39 3.20 4.18 5.73 8.09 11.63 16.77 19.06 1.5 V 2.09 2.12 2.47 3.36 4.40 6.06 8.60 12.36 17.83 20.27 Valid temperature and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page 28. Table 23. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1 for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors fCCLK (MHz)2 400 350 300 250 200 100 1 2 1.2 V N/A N/A 63.31 53.36 43.49 23.6 1.25 V N/A N/A 66.51 56.10 45.76 24.93 1.3 V 91.41 80.56 69.78 58.88 48.08 26.29 Voltage (VDDINT)2 1.35 V 1.4 V 95.7 100.11 84.37 88.26 73.09 76.51 61.72 64.64 50.44 52.86 27.68 29.12 1.45 V 104.51 92.17 79.93 67.56 55.28 30.56 1.5 V 109.01 96.17 83.42 70.55 57.77 32.04 The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 32. Valid frequency and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page 28. Rev. D | Page 35 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 24. Static Current — IDD-DEEPSLEEP (mA) for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors 1 TJ (°C) –40 –20 0 25 40 55 70 85 100 105 115 125 1 0.95 V 6.5 9.0 13.2 22.3 30.8 42.9 59.1 80.4 109.3 120.8 144.4 173.9 1.00 V 7.8 10.6 15.2 25.4 34.8 47.9 65.6 88.6 118.7 132.1 157.5 189.1 Voltage (VDDINT)1 1.10 V 1.15 V 11.1 13.1 14.6 17.0 20.4 23.5 32.8 37.2 44.1 49.6 59.9 66.9 80.8 89.7 107.8 119.2 143.2 157.4 158.8 174.2 188.4 206.0 224.9 245.4 1.05 V 9.3 12.4 17.7 28.9 39.2 53.6 72.9 97.9 130.5 144.7 172.3 206.4 1.20 V 15.4 19.8 27.0 42.1 55.7 74.6 99.4 131.5 172.8 190.9 225.3 267.8 1.25 V 18.0 22.9 30.9 47.6 62.5 83.2 110.2 145.1 189.7 209.3 246.4 292.2 1.30 V 21.0 26.4 35.3 53.7 70.0 92.6 122.0 159.8 208.1 229.2 269.2 318.7 Valid temperature and voltage ranges are model-specific. See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page 30. Table 25. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1 for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors fCCLK (MHz)2 600 533 500 400 300 200 100 1 2 0.95 V N/A N/A N/A 69.8 53.4 36.9 20.5 1.00 V N/A N/A N/A 74.3 56.9 39.4 22.0 Voltage (VDDINT)2 1.10 V 1.15 V N/A 130.4 110.3 116.7 103.1 109.1 83.6 88.5 64.1 68.0 44.6 47.4 25.3 27.0 1.05 V N/A N/A 97.3 78.9 60.4 41.9 23.6 1.20 V 137.6 123.3 115.0 93.5 71.8 50.1 28.8 1.25 V 145.1 129.8 121.3 98.6 75.8 53.0 30.6 1.30 V 152.5 136.4 127.7 103.9 80.0 56.0 32.5 The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 32. Valid frequency and voltage ranges are model-specific. See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page 30. Rev. D | Page 36 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 26 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 26. Absolute Maximum Ratings Parameter Rating Internal Supply Voltage (VDDINT) for ADSP-BF523/ADSP-BF525/ADSP-BF527 processors –0.3 V to +1.26 V Internal Supply Voltage (VDDINT) for ADSP-BF522/ADSP-BF524/ADSP-BF526 processors –0.3 V to +1.47 V External (I/O) Supply Voltage (VDDEXT/VDDMEM) –0.3 V to +3.8 V Real-Time Clock Supply Voltage (VDDRTC) –0.5 V to +3.8 V OTP Supply Voltage (VDDOTP) –0.5 V to +3.0 V OTP Programming Voltage (VPPOTP)1 –0.5 V to +3.0 V OTP Programming Voltage (VPPOTP)2 –0.5 V to +7.1 V USB PHY Supply Voltage (VDDUSB) –0.5 V to +3.8 V Input Voltage3, 4, 5 –0.5 V to +3.8 V Input Voltage3, 4, 6 –0.5 V to +5.5 V Input Voltage 3, 4, 7 –0.5 V to +5.25 V Output Voltage Swing –0.5 V to VDDEXT /VDDMEM + 0.5 V IOH/IOL Current per Pin Group 3, 8 82 mA (max) Storage Temperature Range –65°C to +150°C Junction Temperature While Biased +110°C 1 Applies to OTP memory reads and writes for ADSP-BF523/ADSP-BF525/ADSP-BF527 processors and to OTP memory reads for ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Applies only to OTP memory writes for ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. 3 Applies to 100% transient duty cycle. 4 Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT ±0.2 V. 5 For other duty cycles see Table 27. 6 Applies to balls SCL and SDA. 7 Applies to balls USB_DP, USB_DM, and USB_VBUS. 8 For pin group information, see Table 28. For other duty cycles see Table 29. 2 Table 27. Maximum Duty Cycle for Input Transient Voltage1, 2 Maximum Duty Cycle3 VIN Min (V)4 VIN Max (V)6 100% –0.50 +3.80 40% –0.70 +4.00 25% –0.80 +4.10 15% –0.90 +4.20 10% –1.00 +4.30 1 Applies to all signal balls with the exception of CLKIN, XTAL, VROUT/ EXT_WAKE1, SCL, SDA, USB_DP, USB_DM, and USB_VBUS. 2 Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT ±0.2 V. 3 Duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. The is equivalent to the measured duration of a single instance of overshoot or undershoot as a percentage of the period of occurrence. 4 The individual values cannot be combined for analysis of a single instance of overshoot or undershoot. The worst case observed value must fall within one of the voltages specified, and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle. Rev. D | Table 26 specifies the maximum total source/sink (IOH/IOL) current for a group of pins. Permanent damage can occur if this value is exceeded. To understand this specification, if pins PH4, PH3, PH2, PH1, and PH0 from group 1 in Table 28 were sourcing or sinking 2 mA each, the total current for those pins would be 10 mA. This would allow up to 72 mA total that could be sourced or sunk by the remaining pins in the group without damaging the device. For a list of all groups and their pins, see the Table 28 table. For duty cycles that are less than 100%, see Table 29. Note that the VOH and VOL specifications have separate per-pin maximum current requirements (see Table 19 on Page 33 and Table 20 on Page 34). Table 28. Total Current Pin Groups Group 1 2 3 4 5 Pins in Group PH4, PH3, PH2, PH1, PH0, PF15, PF14, PF13 PF12, SDA, SCL, PF11, PF10, PF9, PF8, PF7 PF6, PF5, PF4, PF3, PF2, PF1, PF0, PPI_FS1 PPI_CLK, PG15, PG14, PG13, PG12, PG11, PG10, PG9 PG8, PG7, PG6, PG5, PG4, BMODE3, BMODE2, BMODE1 Page 37 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 PACKAGE INFORMATION Table 28. Total Current Pin Groups (Continued) Group 6 7 8 9 10 11 12 13 14 15 16 17 18 The information presented in Figure 8 and Table 31 provides details about the package branding for the ADSP-BF52x processors. For a complete listing of product availability, see Ordering Guide on Page 88. Pins in Group BMODE0, PG3, PG2, PG1, PG0, TDI, TDO, EMU TCK, TRST, TMS PH12, PH11, PH10, PH9, PH8, PH7, PH6, PH5 PH15, PH14, PH13, CLKBUF, NMI, RESET DATA15, DATA14, DATA13, DATA12, DATA11, DATA10 DATA9, DATA8, DATA7, DATA6, DATA5, DATA4 DATA3, DATA2, DATA1, DATA0, ADDR19, ADDR18 ADDR17, ADDR16, ADDR15, ADDR14, ADDR13 ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7 ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1 ABE1, ABE0, SA10, SWE, SCAS, SRAS SMS, SCKE, ARDY, AWE, ARE, AOE AMS3, AMS2, AMS1, AMS0, CLKOUT a ADSP-BF52x tppZccc vvvvvv.x n.n #yyww country_of_origin B Figure 8. Product Information on Package Table 31. Package Brand Information1 Table 29. Maximum Duty Cycle for IOH/IOL Current Per Pin Group Brand Key Field Description ADSP-BF52x Product Name2 Maximum Duty Cycle RMS Current (mA) t Temperature Range 100% 82 pp Package Type 80% 92 Z Lead Free Option 60% 106 ccc See Ordering Guide 40% 130 vvvvvv.x Assembly Lot Code 25% 165 n.n Silicon Revision 261 # RoHS Compliance Designator yyww Date Code 10% When programming OTP memory on the ADSP-BF522/ ADSP-BF524/ADSP-BF526 processors, the VPPOTP ball must be set to the write value specified in the Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page 28. There is a finite amount of cumulative time that the write voltage may be applied (dependent on voltage and junction temperature) to VPPOTP over the lifetime of the part. Therefore, maximum OTP memory programming time for the ADSP-BF522/ADSP-BF524/ADSP-BF526 processors is shown in Table 30. The ADSP-BF523/ADSP-BF525/ADSP-BF527 processors do not have a similar restriction. 1 Non Automotive only. For branding information specific to Automotive products, contact Analog Devices Inc. 2 See product names in the Ordering Guide on Page 88. ESD SENSITIVITY Table 30. Maximum OTP Memory Programming Time for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Temperature (TJ) VPPOTP Voltage (V) 25°C 85°C 105°C 6.9 6000 sec 100 sec 25 sec 7.0 2400 sec 44 sec 12 sec 7.1 1000 sec 18 sec 4.5 sec Rev. D | Page 38 of 88 | July 2013 ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TIMING SPECIFICATIONS Specifications are subject to change without notice. Clock and Reset Timing Table 32 and Figure 9 describe clock and reset operations. Per the CCLK and SCLK timing specifications in Table 12 to Table 17, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of the processor's maximum instruction rate. Table 32. Clock and Reset Timing Parameter Min Max Unit 50 MHz 50 MHz Timing Requirements fCKIN CLKIN Frequency (Commercial/ Industrial Models) 1, 2, 3, 4 12 CLKIN Frequency (Automotive Models) 1 tCKINL CLKIN Low Pulse tCKINH CLKIN High Pulse1 tWRST 1, 2, 3, 4 RESET Asserted Pulse Width Low 5 14 10 ns 10 ns 11 × tCKIN ns Switching Characteristic tBUFDLAY CLKIN to CLKBUF Delay 10 ns 1 Applies to PLL bypass mode and PLL nonbypass mode. Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 12 on Page 29 through Table 14 on Page 29 and Table 15 on Page 31 through Table 17 on Page 31. 3 The tCKIN period (see Figure 9) equals 1/fCKIN. 4 If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models. 5 Applies after power-up sequence is complete. See Table 33 and Figure 10 for power-up reset timing. 2 tCKIN CLKIN tCKINL tBUFDLAY tCKINH CLKBUF tWRST RESET Figure 9. Clock and Reset Timing Rev. D | Page 39 of 88 | July 2013 tBUFDLAY ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 33. Power-Up Reset Timing Parameter Min Max Unit Timing Requirement tRST_IN_PWR RESET Deasserted after the VDDINT, VDDEXT, VDDRTC, VDDUSB, VDDMEM, VDDOTP, and CLKIN 3500 × tCKIN Pins are Stable and Within Specification tRST_IN_PWR RESET CLKIN V DD_SUPPLIES In Figure 10, VDD_SUPPLIES is VDDINT, VDDEXT, VDDRTC, VDDUSB, VDDMEM, and VDDOTP. Figure 10. Power-Up Reset Timing Rev. D | Page 40 of 88 | July 2013 ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Asynchronous Memory Read Cycle Timing Table 34. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements tSDAT DATA15–0 Setup Before CLKOUT tHDAT DATA15–0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDO Output Delay After CLKOUT1 tHO Output Hold After CLKOUT1 1 ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDMEM VDDMEM 1.8 V Nominal 2.5 V or 3.3 V Nominal Min Max Min Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDMEM VDDMEM 1.8 V Nominal 2.5 V or 3.3 V Nominal Min Max Min Max Unit 2.1 1.2 4.0 0.2 2.1 0.9 4.0 0.2 ns ns ns ns 2.1 0.8 4.0 0.2 6.0 0.8 6.0 0.8 2.1 0.8 4.0 0.2 6.0 0.8 6.0 0.8 Output balls include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE. SETUP 2 CYCLES PROGRAMMED READ ACCESS 4 CYCLES ACCESS EXTENDED 3 CYCLES HOLD 1 CYCLE CLKOUT tDO tHO AMSx ABE1–0 ADDR19–1 AOE tDO tHO ARE tSARDY tHARDY ARDY tSARDY tHARDY DATA 15–0 Figure 11. Asynchronous Memory Read Cycle Timing Rev. D | Page 41 of 88 | July 2013 tSDAT tHDAT ns ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Asynchronous Memory Write Cycle Timing Table 35. Asynchronous Memory Write Cycle Timing ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDMEM 1.8 V Nominal Parameter Min Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDMEM 2.5 V or 3.3 V Nominal Min Max VDDMEM 1.8 V Nominal Min Max VDDMEM 2.5 V or 3.3 V Nominal Min Max Unit Timing Requirements tSARDY ARDY Setup Before CLKOUT 4.0 4.0 4.0 4.0 ns tHARDY ARDY Hold After CLKOUT 0.2 0.2 0.2 0.2 ns Switching Characteristics tDDAT DATA15–0 Disable After CLKOUT tENDAT DATA15–0 Enable After CLKOUT tDO Output Delay After CLKOUT1 tHO 1 6.0 0.0 6.0 6.0 1 Output Hold After CLKOUT 6.0 0.0 0.8 0.0 6.0 6.0 0.8 0.8 Output balls include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AWE. PROGRAMMED WRITE ACCESS ACCESS EXTEND HOLD 2 CYCLES 1 CYCLE 1 CYCLE SETUP 2 CYCLES CLKOUT tDO tHO AMSx ABE1–0 ADDR19–1 tHO tDO AWE tSARDY tHARDY ARDY tENDAT tHARDY tSARDY tDDAT DATA 15–0 Figure 12. Asynchronous Memory Write Cycle Timing Rev. D | 6.0 0.0 Page 42 of 88 | July 2013 6.0 0.8 ns ns ns ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 NAND Flash Controller Interface Timing Table 36 and Figure 13 on Page 44 through Figure 17 on Page 46 describe NAND Flash Controller Interface operations. Table 36. NAND Flash Controller Interface Timing VDDEXT 1.8 V Nominal Parameter VDDEXT 2.5 V or 3.3 V Nominal Min Min Unit ns Write Cycle Switching Characteristics tCWL ND_CE Setup Time to AWE Low 1.0 × tSCLK – 4 1.0 × tSCLK – 4 tCH ND_CE Hold Time From AWE High 3.0 × tSCLK – 4 3.0 × tSCLK – 4 ns tCLEWL ND_CLE Setup Time to AWE Low 0.0 0.0 ns tCLH ND_CLE Hold Time From AWE high 2.5 × tSCLK – 4 2.5 × tSCLK – 4 ns tALEWL ND_ALE Setup Time to AWE Low 0.0 0.0 ns tALH ND_ALE Hold Time From AWE High 2.5 × tSCLK – 4 2.5 × tSCLK – 4 ns tWP1 AWE Low to AWE high (WR_DLY +1.0) × tSCLK – 4 (WR_DLY +1.0) × tSCLK – 4 ns tWHWL AWE High to AWE Low 4.0 × tSCLK – 4 4.0 × tSCLK – 4 ns tWC1 AWE Low to AWE Low (WR_DLY +5.0) × tSCLK – 4 (WR_DLY +5.0) × tSCLK – 4 ns tDWS1 Data Setup Time for a Write Access (WR_DLY +1.5) × tSCLK – 4 (WR_DLY +1.5) × tSCLK – 4 ns tDWH Data Hold Time for a Write Access 2.5 × tSCLK – 4 2.5 × tSCLK – 4 ns Read Cycle Switching Characteristics tCRL ND_CE Setup Time to ARE Low 1.0 × tSCLK – 4 1.0 × tSCLK – 4 ns tCRH ND_CE Hold Time From ARE High 3.0 × tSCLK – 4 3.0 × tSCLK – 4 ns 1 ARE Low to ARE High (RD_DLY +1.0) × tSCLK – 4 (RD_DLY +1.0) × tSCLK – 4 ns tRHRL ARE High to ARE Low 4.0 × tSCLK – 4 4.0 × tSCLK – 4 ns tRC1 ARE Low to ARE Low (RD_DLY +5.0) × tSCLK – 4 (RD_DLY +5.0) × tSCLK – 4 ns tRP Timing Requirements (ADSP-BF522/ADSP-BF524/ADSP-BF526) tDRS Data Setup Time for a Read Transaction 14.0 10.0 ns tDRH Data Hold Time for a Read Transaction 0.0 0.0 ns Timing Requirements (ADSP-BF523/ADSP-BF525/ADSP-BF527) tDRS Data Setup Time for a Read Transaction 11.0 8.0 ns tDRH Data Hold Time for a Read Transaction 0.0 0.0 ns 5.0 × tSCLK – 4 5.0 × tSCLK – 4 ns Write Followed by Read Switching Characteristic tWHRL 1 AWE High to ARE Low WR_DLY and RD_DLY are defined in the NFC_CTL register. Rev. D | Page 43 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 tCWL tCH ND_CE ND_CLE tCLEWL tCLH tALEWL tALH ND_ALE tWP AWE tDWH tDWS ND_DATA In Figure 13, ND_DATA is ND_D0–D7. Figure 13. NAND Flash Controller Interface Timing — Command Write Cycle tCWL ND_CE tCLEWL ND_CLE ND_ALE tALH tALEWL tALH tALEWL tWP tWHWL tWP AWE tWC tDWS tDWH tDWS ND_DATA In Figure 14, ND_DATA is ND_D0–D7. Figure 14. NAND Flash Controller Interface Timing — Address Write Cycle Rev. D | Page 44 of 88 | July 2013 tDWH ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 tCWL ND_CE tCLEWL ND_CLE tALEWL ND_ALE tWP tWC AWE tWP tDWS tWHWL tDWH tDWS tDWH ND_DATA In Figure 15, ND_DATA is ND_D0–D7. Figure 15. NAND Flash Controller Interface Timing — Data Write Operation tCRL tCRH ND_CE ND_CLE ND_ALE tRP tRC ARE tRHRL tRP tDRS tDRH tDRS ND_DATA In Figure 16, ND_DATA is ND_D0–D7. Figure 16. NAND Flash Controller Interface Timing — Data Read Operation Rev. D | Page 45 of 88 | July 2013 tDRH ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 tCLWL ND_CE ND_CLE tCLEWL tCLH tWP AWE tWHRL tRP ARE tDWS tDWH tDRS tDRH ND_DATA In Figure 17, ND_DATA is ND_D0–D7. Figure 17. NAND Flash Controller Interface Timing — Write Followed by Read Operation Rev. D | Page 46 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SDRAM Interface Timing Table 37. SDRAM Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors VDDMEM 1.8V Nominal Parameter Min Max VDDMEM 2.5 V or 3.3V Nominal Min Max Unit Timing Requirements tSSDAT Data Setup Before CLKOUT 1.5 1.5 ns tHSDAT Data Hold After CLKOUT 1.3 0.8 ns Switching Characteristics tSCLK CLKOUT Period1 12.5 10 ns tSCLKH CLKOUT Width High 5.0 4.0 ns tSCLKL CLKOUT Width Low 5.0 4.0 ns tDCAD Command, Address, Data Delay After CLKOUT tHCAD Command, Address, Data Hold After CLKOUT2 tDSDAT Data Disable After CLKOUT tENSDAT Data Enable After CLKOUT 1 2 2 5.0 1.0 4.0 1.0 ns 5.5 0.0 ns 5.0 0.0 ns ns The tSCLK value is the inverse of the fSCLK specification discussed in Table 14 and Table 17. Package type and reduced supply voltages affect the best-case values listed here. Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Table 38. SDRAM Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors VDDMEM 1.8V Nominal Parameter Min Max VDDMEM 2.5 V or 3.3V Nominal Min Max Unit Timing Requirements tSSDAT Data Setup Before CLKOUT 1.5 1.5 ns tHSDAT Data Hold After CLKOUT 1.0 0.8 ns Switching Characteristics tSCLK CLKOUT Period1 10 7.5 ns tSCLKH CLKOUT Width High 2.5 2.5 ns tSCLKL CLKOUT Width Low 2.5 2.5 ns tDCAD Command, Address, Data Delay After CLKOUT tHCAD Command, Address, Data Hold After CLKOUT2 tDSDAT Data Disable After CLKOUT tENSDAT Data Enable After CLKOUT 1 2 2 4.0 1.0 4.0 1.0 5.0 0.0 ns 4.0 0.0 ns ns ns The tSCLK value is the inverse of the fSCLK specification discussed in Table 14 and Table 17. Package type and reduced supply voltages affect the best-case values listed here. Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Rev. D | Page 47 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 tSCLK CLKOUT tSSDAT tHSDAT tSCLKL tSCLKH DATA (IN) tENSDAT tDCAD tHCAD DATA (OUT) tDCAD tHCAD COMMAND, ADDRESS (OUT) NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Figure 18. SDRAM Interface Timing Rev. D | Page 48 of 88 | July 2013 tDSDAT ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 External DMA Request Timing Table 39, Table 40, and Figure 19 describe the External DMA Request operations. Table 39. External DMA Request Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors1 VDDEXT/VDDMEM 1.8 V Nominal Parameter Min Max VDDEXT/VDDMEM 2.5 V or 3.3 V Nominal Min Max Unit Timing Requirements 1 tDS DMARx Asserted to CLKOUT High Setup 9.0 6.0 ns tDH CLKOUT High to DMARx Deasserted Hold Time 0.0 0.0 ns tDMARACT DMARx Active Pulse Width 1.0 × tSCLK 1.0 × tSCLK ns tDMARINACT DMARx Inactive Pulse Width 1.75 × tSCLK 1.75 × tSCLK ns Because the external DMA control pins are part of the VDDEXT power domain and the CLKOUT signal is part of the VDDMEM power domain, systems in which VDDEXT and VDDMEM are NOT equal may require level shifting logic for correct operation. Table 40. External DMA Request Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors1 VDDEXT/VDDMEM 1.8 V Nominal Parameter Min Max VDDEXT/VDDMEM 2.5 V or 3.3 V Nominal Min Max Unit Timing Requirements 1 tDS DMARx Asserted to CLKOUT High Setup 8.0 6.0 ns tDH CLKOUT High to DMARx Deasserted Hold Time 0.0 0.0 ns tDMARACT DMARx Active Pulse Width 1.0 × tSCLK 1.0 × tSCLK ns tDMARINACT DMARx Inactive Pulse Width 1.75 × tSCLK 1.75 × tSCLK ns Because the external DMA control pins are part of the VDDEXT power domain and the CLKOUT signal is part of the VDDMEM power domain, systems in which VDDEXT and VDDMEM are NOT equal may require level shifting logic for correct operation. CLKOUT tDS tDH DMAR0/1 (ACTIVE LOW) tDMARACT tDMARINACT DMAR0/1 (ACTIVE HIGH) Figure 19. External DMA Request Timing Rev. D | Page 49 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Parallel Peripheral Interface Timing Table 41 and Figure 20 on Page 51, Figure 24 on Page 55, and Figure 27 on Page 57 describe parallel peripheral interface operations. Table 41. Parallel Peripheral Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.3 V Nominal Min Max Unit Timing Requirements tPCLKW PPI_CLK Width1 6.4 6.4 ns tPCLK PPI_CLK Period1 25.0 20.0 ns Timing Requirements - GP Input and Frame Capture Modes tSFSPE External Frame Sync Setup Before PPI_CLK (Nonsampling Edge for Rx, Sampling Edge for Tx) 6.7 6.7 ns tHFSPE External Frame Sync Hold After PPI_CLK 1.2 1.2 ns tSDRPE Receive Data Setup Before PPI_CLK 4.1 3.5 ns tHDRPE Receive Data Hold After PPI_CLK 2.0 1.6 ns Switching Characteristics - GP Output and Frame Capture Modes tDFSPE Internal Frame Sync Delay After PPI_CLK tHOFSPE Internal Frame Sync Hold After PPI_CLK tDDTPE Transmit Data Delay After PPI_CLK tHDTPE Transmit Data Hold After PPI_CLK 1 8.0 1.7 8.0 ns 8.0 ns 1.7 8.2 2.3 ns 1.9 ns PPI_CLK frequency cannot exceed fSCLK/2. Table 42. Parallel Peripheral Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.3V Nominal Min Max Unit Timing Requirements tPCLKW PPI_CLK Width1 6.0 6.0 ns tPCLK PPI_CLK Period1 20.0 15.0 ns 6.7 6.7 ns Timing Requirements - GP Input and Frame Capture Modes tSFSPE External Frame Sync Setup Before PPI_CLK (Nonsampling Edge for Rx, Sampling Edge for Tx) tHFSPE External Frame Sync Hold After PPI_CLK 1.0 1.0 ns tSDRPE Receive Data Setup Before PPI_CLK 3.5 3.5 ns tHDRPE Receive Data Hold After PPI_CLK 2.0 1.6 ns Switching Characteristics - GP Output and Frame Capture Modes tDFSPE Internal Frame Sync Delay After PPI_CLK tHOFSPE Internal Frame Sync Hold After PPI_CLK tDDTPE Transmit Data Delay After PPI_CLK tHDTPE Transmit Data Hold After PPI_CLK 1 8.0 1.7 2.3 Rev. D | Page 50 of 88 | July 2013 ns 8.0 ns 1.7 8.0 PPI_CLK frequency cannot exceed fSCLK/2. 8.0 1.9 ns ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 DATA SAMPLED / FRAME SYNC SAMPLED DATA SAMPLED / FRAME SYNC SAMPLED PPI_CLK tSFSPE tPCLKW tHFSPE tPCLK PPI_FS1/2 tSDRPE tHDRPE PPI_DATA Figure 20. PPI GP Rx Mode with External Frame Sync Timing DATA DRIVEN / FRAME SYNC SAMPLED PPI_CLK tSFSPE tHFSPE tPCLKW PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 21. PPI GP Tx Mode with External Frame Sync Timing FRAME SYNC DRIVEN DATA SAMPLED PPI_CLK tHOFSPE tDFSPE tPCLKW tPCLK PPI_FS1/2 tSDRPE tHDRPE PPI_DATA Figure 22. PPI GP Rx Mode with Internal Frame Sync Timing Rev. D | Page 51 of 88 | July 2013 tPCLK ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 FRAME SYNC DRIVEN DATA DRIVEN tPCLK PPI_CLK tHOFSPE tDFSPE tPCLKW PPI_FS1/2 tDDTPE PPI_DATA Figure 23. PPI GP Tx Mode with Internal Frame Sync Timing Rev. D | Page 52 of 88 | July 2013 tHDTPE DATA DRIVEN ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Serial Ports Table 43 through Table 47 on Page 57 and Figure 24 on Page 55 through Figure 27 on Page 57 describe serial port operations. Table 43. Serial Ports—External Clock ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Parameter Min Max Min Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Min Max Min Max Unit Timing Requirements tSFSE TFSx/RFSx Setup Before TSCLKx RSCLKx1 3.0 1 3.0 3.0 3.0 ns tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx 3.0 3.0 3.0 3.0 ns tSDRE Receive Data Setup Before RSCLKx1 3.0 3.0 3.0 3.0 ns 3.5 3.0 3.5 3.0 ns 7.0 4.5 7.0 4.5 ns tHDRE Receive Data Hold After RSCLKx 1 tSCLKEW TSCLKx/RSCLKx Width tSCLKE 2.0 × tSCLK 2.0 × tSCLK 2.0 × tSCLK 2.0 × tSCLK ns tSUDTE Start-Up Delay From SPORT Enable To First External TFSx2 TSCLKx/RSCLKx Period 4.0 × tSCLKE 4.0 × tSCLKE 4.0 × tSCLKE 4.0 × tSCLKE ns tSUDRE Start-Up Delay From SPORT Enable To First External RFSx2 4.0 × tSCLKE 4.0 × tSCLKE 4.0 × tSCLKE 4.0 × tSCLKE ns Switching Characteristics tDFSE TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3 tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3 tDDTE tHDTE 10.0 0.0 Transmit Data Delay After TSCLKx3 Transmit Data Hold After TSCLKx 3 10.0 0.0 10.0 0.0 0.0 10.0 0.0 1 Referenced to sample edge. Verified in design but untested. 3 Referenced to drive edge. 2 Rev. D | 10.0 Page 53 of 88 | July 2013 10.0 0.0 10.0 0.0 ns 10.0 0.0 ns ns ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 44. Serial Ports—Internal Clock for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors VDDEXT 1.8V Nominal Min Parameter VDDEXT 2.5 V or 3.3V Nominal Max Min Max Unit Timing Requirements tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1 11.0 9.6 ns tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1 –1.5 –1.5 ns 11.0 9.6 ns –1.5 –1.5 ns tSDRI tHDRI Receive Data Setup Before RSCLKx Receive Data Hold After RSCLKx 1 1 Switching Characteristics tSCLKIW TSCLKx/RSCLKx Width tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 –2.0 tDDTI Transmit Data Delay After TSCLKx2 tHDTI Transmit Data Hold After TSCLKx2 1 2 10.0 8.0 3.0 ns 3.0 ns 3.0 ns –1.0 3.0 –1.8 ns –1.5 ns Referenced to sample edge. Referenced to drive edge. Table 45. Serial Ports—Internal Clock for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.3V Nominal Min Max Unit Timing Requirements tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1 tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx tSDRI Receive Data Setup Before RSCLKx1 tHDRI Receive Data Hold After RSCLKx 1 1 11.0 9.6 ns –1.5 –1.5 ns 11.0 9.6 ns –1.5 –1.5 ns 4.5 4.5 ns Switching Characteristics tSCLKIW TSCLKx/RSCLKx Width tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tDDTI Transmit Data Delay After TSCLKx2 tHDTI 1 2 Transmit Data Hold After TSCLKx 3.0 –1.0 –1.0 3.0 2 –1.8 Referenced to sample edge. Referenced to drive edge. Rev. D 3.0 | Page 54 of 88 | July 2013 ns 3.0 –1.5 ns ns ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE DRIVE EDGE SAMPLE EDGE SAMPLE EDGE tSCLKE tSCLKEW tSCLKIW RSCLKx RSCLKx tDFSE tDFSI tHOFSI tHOFSE RFSx (OUTPUT) RFSx (OUTPUT) tSFSI tHFSI RFSx (INPUT) tSFSE tHFSE tSDRE tHDRE RFSx (INPUT) tSDRI tHDRI DRx DRx DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE t SCLKEW TSCLKx tSCLKE TSCLKx tD FSI tDFSE tHOFSI tHOFSE TFSx (OUTPUT) TFSx (OUTPUT) tSFSI tHFSI tSFSE TFSx (INPUT) TFSx (INPUT) tDDTI tDDTE tHDTI tHDTE DTx DTx Figure 24. Serial Ports TSCLKx (INPUT) tSUDTE TFSx (INPUT) RSCLKx (INPUT) tSUDRE RFSx (INPUT) FIRST TSCLKx/RSCLKx EDGE AFTER SPORT ENABLED Figure 25. Serial Port Start Up with External Clock and Frame Sync Rev. D | Page 55 of 88 | July 2013 tHFSE ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 46. Serial Ports—Enable and Three-State ADSP-BF522/ADSP-BF524/ADSP-BF526 VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.3V Nominal Min Max ADSP-BF523/ADSP-BF525/ADSP-BF527 VDDEXT 1.8V Nominal Min Max VDDEXT 2.5 V or 3.3V Nominal Min Max Unit Switching Characteristics tDTENE Data Enable Delay from External TSCLKx1 tDDTTE Data Disable Delay from External TSCLKx1 tDTENI Data Enable Delay from Internal TSCLKx1 tDDTTI Data Disable Delay from Internal TSCLKx1 1 0.0 0.0 tSCLK +1 –2.0 0.0 tSCLK +1 –2.0 tSCLK +1 tSCLK +1 –2.0 tSCLK +1 DRIVE EDGE TSCLKx tDTENE/I tDDTTE/I DTx Figure 26. Serial Ports — Enable and Three-State Rev. D | Page 56 of 88 | July 2013 ns tSCLK +1 –2.0 tSCLK +1 Referenced to drive edge. DRIVE EDGE 0.0 ns ns tSCLK +1 ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 47. Serial Ports — External Late Frame Sync ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Min Parameter Max Min Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Min Max Min Max Unit 10.0 ns Switching Characteristics tDDTLFSE Data Delay from Late External TFSx or External RFSx in multi-channel mode with MFD = 01, 2 tDTENLFSE Data Enable from External RFSx in multi- 0.0 channel mode with MFD = 01, 2 1 2 12.0 10.0 0.0 12.0 0.0 When in multi-channel mode, TFSx enable and TFSx valid follow tDTENLFSE and tDDTLFSE. If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFSE apply. EXTERNAL RFSx IN MULTI-CHANNEL MODE SAMPLE DRIVE EDGE EDGE DRIVE EDGE RSCLKx RFSx tDDTLFSE tDTENLFSE 1ST BIT DTx LATE EXTERNAL TFSx DRIVE EDGE SAMPLE EDGE DRIVE EDGE TSCLKx TFSx tDDTLFSE 1ST BIT DTx Figure 27. Serial Ports — External Late Frame Sync Rev. D | Page 57 of 88 | July 2013 0.0 ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Serial Peripheral Interface (SPI) Port—Master Timing Table 48 and Figure 28 describe SPI port master operations. Table 48. Serial Peripheral Interface (SPI) Port—Master Timing ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Min Parameter Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 Min VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Max Min Max Min Max Unit Timing Requirements tSSPIDM Data Input Valid to SCK Edge (Data 11.6 Input Setup) 9.6 11.6 9.6 ns tHSPIDM SCK Sampling Edge to Data Input Invalid –1.5 –1.5 –1.5 –1.5 ns Switching Characteristics tSDSCIM SPISELx low to First SCK Edge 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 ns tSPICHM Serial Clock High Period 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 ns tSPICLM Serial Clock Low Period 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 ns tSPICLK Serial Clock Period 4 × tSCLK –1.5 4 × tSCLK –1.5 4 × tSCLK –1.5 4 × tSCLK –1.5 ns tHDSM Last SCK Edge to SPISELx High 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 ns tSPITDM Sequential Transfer Delay 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 ns tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay) tHDSPIDM SCK Edge to Data Out Invalid (Data –1.0 Out Hold) 6 6 6 –1.0 6 –1.0 –1.0 SPIxSELy (OUTPUT) tSDSCIM tSPICLM tSPICHM tSPICLK tHDSM SPIxSCK (OUTPUT) tDDSPIDM tHDSPIDM SPIxMOSI (OUTPUT) tSSPIDM CPHA = 1 tHSPIDM SPIxMISO (INPUT) tHDSPIDM tDDSPIDM SPIxMOSI (OUTPUT) CPHA = 0 tSSPIDM tHSPIDM SPIxMISO (INPUT) Figure 28. Serial Peripheral Interface (SPI) Port—Master Timing Rev. D | Page 58 of 88 | July 2013 tSPITDM ns ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Serial Peripheral Interface (SPI) Port—Slave Timing Table 49 and Figure 29 describe SPI port slave operations. Table 49. Serial Peripheral Interface (SPI) Port—Slave Timing ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Min Parameter ADSP-BF523/ADSP-BF525/ ADSP-BF527 Max Min VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Max Min Max Min Max Unit Timing Requirements tSPICHS Serial Clock High Period 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 ns tSPICLS Serial Clock Low Period 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 ns tSPICLK Serial Clock Period 4× tSCLK –1.5 4 × tSCLK –1.5 4× tSCLK –1.5 4 × tSCLK –1.5 ns tHDS Last SCK Edge to SPISS Not Asserted 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 ns tSPITDS Sequential Transfer Delay 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 ns tSDSCI SPISS Assertion to First SCK Edge 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 2 × tSCLK –1.5 ns tSSPID Data Input Valid to SCK Edge (Data Input Setup) 1.6 1.6 1.6 1.6 ns tHSPID SCK Sampling Edge to Data Input Invalid 2.0 1.6 1.6 1.6 ns Switching Characteristics tDSOE SPISS Assertion to Data Out Active 0 12.0 0 10.3 0 12.0 0 10.3 ns tDSDHI SPISS Deassertion to Data High Impedance 0 11.0 0 8.5 0 8.5 8 ns tDDSPID SCK Edge to Data Out Valid (Data Out Delay) 10 10 10 ns tHDSPID SCK Edge to Data Out Invalid (Data Out Hold) 0 0 0 10 0 0 ns SPIxSS (INPUT) tSDSCI tSPICLS tSPICHS tHDS tSPICLK SPIxSCK (INPUT) tDSOE tDDSPID tDDSPID tHDSPID tDSDHI SPIxMISO (OUTPUT) CPHA = 1 tSSPID tHSPID SPIxMOSI (INPUT) tDSOE tHDSPID tDDSPID tDSDHI SPIxMISO (OUTPUT) CPHA = 0 tSSPID SPIxMOSI (INPUT) Figure 29. Serial Peripheral Interface (SPI) Port—Slave Timing Rev. D | Page 59 of 88 | July 2013 tHSPID tSPITDS ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Table 50 describes the USB On-The-Go receive and transmit operations. Table 50. USB On-The-Go—Receive and Transmit Timing ADSP-BF522/ADSP-BF524/ADSP-BF526 VDDEXT 1.8V Nominal Parameter ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDEXT 1.8V Nominal VDDEXT 2.5 V or 3.3V Nominal VDDEXT 2.5 V or 3.3V Nominal Min Max Min Max Min Max Min Max Unit Timing Requirements fUSBS USB_XI Frequency 12 33.3 12 33.3 9 33.3 9 33.3 MHz FSUSB USB_XI Clock Frequency Stability –50 +50 –50 +50 –50 +50 –50 +50 ppm Rev. D | Page 60 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing For information on the UART port receive and transmit operations, see the ADSP-BF52x Hardware Reference Manual. General-Purpose Port Timing Table 51 and Figure 30 describe general-purpose port operations. Table 51. General-Purpose Port Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.3V Nominal Min Max Unit Timing Requirement tWFI General-Purpose Port Ball Input Pulse Width tSCLK + 1 tSCLK + 1 ns Switching Characteristic tGPOD General-Purpose Port Ball Output Delay from CLKOUT 0 Low 11.0 0 8.2 ns Table 52. General-Purpose Port Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors VDDEXT 1.8V Nominal Parameter Min Max VDDEXT 2.5 V or 3.3V Nominal Min Max Unit Timing Requirement tWFI General-Purpose Port Ball Input Pulse Width tSCLK + 1 tSCLK + 1 ns Switching Characteristic tGPOD General-Purpose Port Ball Output Delay from CLKOUT Low 0 CLKOUT tGPOD GPIO OUTPUT tWFI GPIO INPUT Figure 30. General-Purpose Port Timing Rev. D | Page 61 of 88 | July 2013 8.2 0 6.5 ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Timer Cycle Timing Table 53 and Figure 31 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz. Table 53. Timer Cycle Timing ADSP-BF522/ADSP-BF524/ADSP-BF526 VDDEXT 1.8V Nominal Min Parameter ADSP-BF523/ADSP-BF525/ADSP-BF527 VDDEXT 1.8V Nominal VDDEXT 2.5 V or 3.3V Nominal Max Min Max Min Max VDDEXT 2.5 V or 3.3V Nominal Min Max Unit Timing Requirements tWL Timer Pulse Width Input tSCLK Low (Measured In SCLK Cycles)1 tSCLK tSCLK tSCLK ns tWH Timer Pulse Width Input tSCLK High (Measured In SCLK Cycles)1 tSCLK tSCLK tSCLK ns tTIS Timer Input Setup Time Before CLKOUT Low2 10 7 8.1 6.2 ns tTIH Timer Input Hold Time After CLKOUT Low2 –2 –2 –2 –2 ns Switching Characteristics tHTO Timer Pulse Width Output tSCLK –1.5 (Measured In SCLK Cycles) (232– 1)tSCLK tSCLK – 1 (232– 1)tSCLK tSCLK – 1 (232– 1)tSCLK tSCLK – 1 (232 – 1)tSCLK ns tTOD Timer Output Update Delay After CLKOUT High 6 6 6 6 1 2 ns The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode. Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs. CLKOUT tTOD TMRx OUTPUT tTIS tTIH TMRx INPUT tWH,tWL Figure 31. Timer Cycle Timing Rev. D | Page 62 of 88 | July 2013 tHTO ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Timer Clock Timing Table 54 and Figure 32 describe timer clock timing. Table 54. Timer Clock Timing VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.3V Nominal Min Max Unit 12.0 ns Switching Characteristic tTODP Timer Output Update Delay After PPI_CLK High 12.0 PPI_CLK tTODP TMRx OUTPUT Figure 32. Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Table 55. Up/Down Counter/Rotary Encoder Timing VDDEXT 1.8V Nominal Parameter Min Max VDDEXT 2.5 V or 3.3V Nominal Min Max Unit Timing Requirements tWCOUNT Up/Down Counter/Rotary Encoder Input Pulse Width tSCLK + 1 tCIS Counter Input Setup Time Before CLKOUT High tCIH Counter Input Hold Time After CLKOUT High1 1 1 tSCLK + 1 ns 9.0 7.0 ns 0 0 ns Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs. CLKOUT tCIS tCIH CUD/CDG/CZM tWCOUNT Figure 33. Up/Down Counter/Rotary Encoder Timing Rev. D | Page 63 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOSTDP A/C Timing- Host Read Cycle Table 56 describes the HOSTDP A/C Host Read Cycle timing requirements. Table 56. Host Read Cycle Timing Requirements Parameter Timing Requirements tSADRDL HOST_ADDR and HOST_CE Setup before HOST_RD falling edge tHADRDH HOST_ADDR and HOST_CE Hold after HOST_RD rising edge tRDWL HOST_RD pulse width low (ACK mode) ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT VDDEXT 2.5 V or 3.3V Nominal 1.8V Nominal Min Max Min Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDEXT VDDEXT 2.5 V or 3.3V Nominal 1.8V Nominal Min Max Min Max Unit 4 4 4 4 ns 2.5 2.5 2.5 2.5 ns tDRDYRDL + tRDYPRD + tDRDHRDY 1.5 × tSCLK + 8.7 2 × tSCLK tDRDYRDL + tRDYPRD + tDRDHRDY 1.5 × tSCLK + 8.7 2 × tSCLK tDRDYRDL + tRDYPRD + tDRDHRDY 1.5 × tSCLK + 8.7 2 × tSCLK ns 2.0 0 0 ns 3.5 4.5 3.5 ns tDRDYRDL + tRDYPRD + tDRDHRDY tRDWL HOST_RD pulse width low 1.5 × tSCLK (INT mode) + 8.7 tRDWH HOST_RD pulse width high or time 2 × tSCLK between HOST_RD rising edge and HOST_WR falling edge tDRDHRDY HOST_RD rising edge delay after 2.0 HOST_ACK rising edge (ACK mode) Switching Characteristics tSDATRDY Data valid prior HOST_ACK rising 4.5 edge (ACK mode) tDRDYRDL Host_ACK falling edge after HOST_CE (ACK mode) tRDYPRD HOST_ACK low pulse-width for Read access (ACK mode) tDDARWH Data disable after HOST_RD tACC Data valid after HOST_RD falling edge (INT mode) tHDARWH Data hold after HOST_RD rising 1.0 edge 1 ns ns 12.5 11.25 11.25 11.25 ns NM1 NM1 NM1 NM1 ns 11.0 1.5 × tSCLK 9.0 1.5 × tSCLK 9.0 1.5 × tSCLK 9.0 ns 1.5 × tSCLK ns 1.0 1.0 1.0 ns NM (Not Measured) — This parameter is based on tSCLK. It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO status and is system design dependent. Rev. D | Page 64 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOST_ADDR HOST_CE tSADRDL tHADRDH tRDWL HOST_RD tSDATRDY tACC tRDWH tDDARWH tHDARWH HOST_DATA tDRDYRDL tDRDHRDY tRDYPRD HOST_ACK In Figure 34, HOST_DATA is HOST_D0–D15. Figure 34. HOSTDP A/C- Host Read Cycle Rev. D | Page 65 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOSTDP A/C Timing- Host Write Cycle Table 57 describes the HOSTDP A/C Host Write Cycle timing requirements. Table 57. Host Write Cycle Timing Requirements Parameter Timing Requirements tSADWRL HOST_ADDR/HOST_CE Setup before HOST_WR falling edge tHADWRH HOST_ADDR/HOST_CE Hold after HOST_WR rising edge HOST_WR pulse width low tWRWL (ACK mode) ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V VDDEXT Nominal 1.8V Nominal Min Max Min Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDEXT VDDEXT 2.5 V or 3.3V Nominal 1.8V Nominal Min Max Min Max Unit 4 4 4 4 ns 2.5 2.5 2.5 2.5 ns tDRDYWRL + tRDYPRD + tDWRHRDY 1.5 × tSCLK + 8.7 2 × tSCLK tDRDYWRL + tRDYPRD + tDWRHRDY 1.5 × tSCLK + 8.7 2 × tSCLK tDRDYWRL + tRDYPRD + tDWRHRDY 1.5 × tSCLK + 8.7 2 × tSCLK tDRDYWRL + tRDYPRD + tDWRHRDY 1.5 × tSCLK + 8.7 2 × tSCLK ns 2.0 0 0 ns 2.5 2.5 2.5 2.5 2.5 2.5 ns ns HOST_WR pulse width low (INT mode) HOST_WR pulse width high tWRWH or time between HOST_WR rising edge and HOST_RD falling edge tDWRHRDY HOST_WR rising edge delay 2.0 after HOST_ACK rising edge (ACK mode) tHDATWH Data Hold after HOST_WR rising edge 2.5 3.5 tSDATWH Data Setup before HOST_WR rising edge Switching Characteristics tDRDYWRL HOST_ACK falling edge after HOST_CE asserted (ACK mode) tRDYPWR HOST_ACK low pulse-width for Write access (ACK mode) 1 ns ns 12.5 11.5 11.5 11.5 ns NM1 NM1 NM1 NM1 ns NM (Not Measured) — This parameter is based on tSCLK. It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO status and is system design dependent. Rev. D | Page 66 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 HOST_ADDR HOST_CE tSADWRL tHADWRH tWRWH tWRWL HOST_WR tSDATWH tHDATWH HOST_DATA tDRDYWRL tRDYPWR tDWRHRDY HOST_ACK In Figure 35, HOST_DATA is HOST_D0–D15. Figure 35. HOSTDP A/C- Host Write Cycle Rev. D | Page 67 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 10/100 Ethernet MAC Controller Timing Table 58 through Table 63 and Figure 36 through Figure 41 describe the 10/100 Ethernet MAC Controller operations. Table 58. 10/100 Ethernet MAC Controller Timing: MII Receive Signal VDDEXT 1.8V Nominal Parameter1 VDDEXT 2.5 V or 3.3V Nominal Min Max Min Max Unit 25 + 1% None 25 + 1% MHz Timing Requirements tERXCLKF ERxCLK Frequency (fSCLK = SCLK Frequency) None tERXCLKW ERxCLK Width (tERxCLK = ERxCLK Period) tERxCLK × 40% tERxCLK × 60% tERxCLK × 35% tERxCLK × 65% ns tERXCLKIS Rx Input Valid to ERxCLK Rising Edge (Data In Setup) 7.5 7.5 ns tERXCLKIH ERxCLK Rising Edge to Rx Input Invalid (Data In Hold) 7.5 7.5 ns 1 MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER. tERXCLK tERXCLKW ERx_CLK ERxD3–0 ERxDV ERxER tERXCLKIS tERXCLKIH Figure 36. 10/100 Ethernet MAC Controller Timing: MII Receive Signal Table 59. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal VDDEXT 1.8V Nominal Parameter1 VDDEXT 2.5 V or 3.3V Nominal Min Max Min Max Unit 25 + 1% None 25 + 1% MHz Switching Characteristics tETXCLKF ETxCLK Frequency (fSCLK = SCLK Frequency) None tETXCLKW ETxCLK Width (tETxCLK = ETxCLK Period) tETxCLK × 40% tETxCLK × 60% tETxCLK × 35% tETxCLK × 65% ns tETXCLKOV ETxCLK Rising Edge to Tx Output Valid (Data Out Valid) tETXCLKOH ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold) 1 20 0 MII outputs synchronous to ETxCLK are ETxD3–0. tETXCLK MIITxCLK tETXCLKW tETXCLKOH ETxD3–0 ETxEN tETXCLKOV Figure 37. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal Rev. D | Page 68 of 88 | July 2013 20 0 ns ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 60. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal VDDEXT 1.8V Nominal Parameter1 VDDEXT 2.5 V or 3.3V Nominal Min Max Min Max Unit 50 + 1% None 50 + 1% MHz Timing Requirements tEREFCLKF REF_CLK Frequency (fSCLK = SCLK Frequency) None tEREFCLKW EREF_CLK Width (tEREFCLK = EREFCLK Period) tEREFCLK × 40% tEREFCLK × 60% tEREFCLK × 35% tEREFCLK × 65% ns tEREFCLKIS Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup) 4 4 ns tEREFCLKIH RMII REF_CLK Rising Edge to Rx Input Invalid (Data In 2 Hold) 2 ns 1 RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER. tREFCLK tREFCLKW RMII_REF_CLK ERxD1–0 ERxDV ERxER tREFCLKIS tREFCLKIH Figure 38. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal Table 61. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Parameter1 Min Max Min Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Min Max Min Max Unit 7.5 ns Switching Characteristics tEREFCLKOV RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid) tEREFCLKOH RMII REF_CLK Rising Edge 2 to Tx Output Invalid (Data Out Hold) 1 8.1 8.1 2 7.5 2 RMII outputs synchronous to RMII REF_CLK are ETxD1–0. tREFCLK RMII_REF_CLK tREFCLKOH ETxD1–0 ETxEN tREFCLKOV Figure 39. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal Rev. D | Page 69 of 88 | July 2013 2 ns ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 62. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal VDDEXT 1.8V Nominal Min Parameter VDDEXT 2.5 V or 3.3V Nominal Max Min Max Unit Timing Requirements tECOLH COL Pulse Width High1 tETxCLK × 1.5 tERxCLK × 1.5 tETxCLK × 1.5 tERxCLK × 1.5 ns tECOLL COL Pulse Width Low1 tETxCLK × 1.5 tERxCLK × 1.5 tETxCLK × 1.5 tERxCLK × 1.5 ns tECRSH CRS Pulse Width High2 tETxCLK × 1.5 tETxCLK × 1.5 ns tETxCLK × 1.5 tETxCLK × 1.5 ns tECRSL CRS Pulse Width Low 2 1 MII/RMII asynchronous signals are COL and CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both the ETxCLK and the ERxCLK, and the COL input must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks. 2 The asynchronous CRS input is synchronized to the ETxCLK, and the CRS input must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK. MIICRS, COL tECRSH tECOLH tECRSL tECOLL Figure 40. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal Table 63. 10/100 Ethernet MAC Controller Timing: MII Station Management ADSP-BF522/ADSP-BF524/ ADSP-BF526 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Parameter1 Min Max Min Max ADSP-BF523/ADSP-BF525/ ADSP-BF527 VDDEXT 2.5 V or 3.3V Nominal VDDEXT 1.8V Nominal Min Max Min Max Unit Timing Requirements tMDIOS MDIO Input Valid to MDC Rising Edge (Setup) 11.5 11.5 10 10 ns tMDCIH MDC Rising Edge to MDIO Input Invalid 11.5 (Hold) 11.5 10 10 ns Switching Characteristics tMDCOV MDC Falling Edge to MDIO Output Valid tMDCOH MDC Falling Edge to MDIO Output Invalid (Hold) 1 25 –1 25 –1 25 –1 25 –1 ns ns MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple of the system clock SCLK. MDIO is a bidirectional data line. Rev. D | Page 70 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 MDC (OUTPUT) tMDCOH MDIO (OUTPUT) tMDCOV MDIO (INPUT) tMDIOS tMDCIH Figure 41. 10/100 Ethernet MAC Controller Timing: MII Station Management Rev. D | Page 71 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 JTAG Test And Emulation Port Timing Table 64 and Figure 42 describe JTAG port operations. Table 64. JTAG Port Timing VDDEXT 1.8V Nominal Min Parameter Max VDDEXT 2.5 V or 3.3V Nominal Min Max Unit Timing Requirements tTCK TCK Period 20 20 ns tSTAP TDI, TMS Setup Before TCK High 4 4 ns tHTAP TDI, TMS Hold After TCK High 4 4 ns 12 12 ns 5 5 ns 4 4 TCK tSSYS System Inputs Setup Before TCK High 1 1 tHSYS System Inputs Hold After TCK High tTRSTW TRST Pulse Width2 (measured in TCK cycles) Switching Characteristics TDO Delay from TCK Low tDTDO System Outputs Delay After TCK Low tDSYS 3 1 10 10 ns 12 12 ns System Inputs = DATA15–0, ARDY, SCL, SDA, PF15–0, PG15–0, PH15–0, RESET, NMI, BMODE3–0. 50 MHz Maximum. 3 System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, PF15–0, PG15–0, PH15–0. 2 tTCK TCK tSTAP tHTAP TMS TDI tDTDO TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 42. JTAG Port Timing Rev. D | Page 72 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 OUTPUT DRIVE CURRENTS Figure 43 through Figure 57 show typical current-voltage characteristics for the output drivers of the ADSP-BF52x processors. The curves represent the current drive capability of the output drivers. See Table 10 on Page 23 for information about which driver type corresponds to a particular ball. 200 160 240 200 VDDEXT = 3.0V @ 105°C 120 80 0 –40 –80 VOL –120 VDDEXT = 3.0V @ 105°C 120 VOH 40 VDDEXT = 3.6V @ – 40°C VDDEXT = 3.3V @ 25°C 160 SOURCE CURRENT (mA) SOURCE CURRENT (mA) VDDEXT = 3.6V @ – 40°C VDDEXT = 3.3V @ 25°C –160 80 VOH 40 0 –40 –80 –120 VOL –160 –200 –200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 –240 0 SOURCE VOLTAGE (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V) Figure 43. Driver Type A Current (3.3V VDDEXT/VDDMEM) Figure 46. Driver Type B Current (3.3V VDDEXT/VDDMEM) 160 VDDEXT = 2.75V @ – 40°C 120 160 VDDEXT = 2.5V @ 25°C VDDEXT = 2.75V @ – 40°C VDDEXT = 2.25V @ 105°C 120 VDDEXT = 2.5V @ 25°C 80 VDDEXT = 2.25V @ 105°C 40 VOH 0 –40 –80 VOL –120 SOURCE CURRENT (mA) SOURCE CURRENT (mA) 80 40 VOH 0 –40 –80 VOL –120 –160 –160 0 0.5 1.0 1.5 2.0 2.5 –200 0 SOURCE VOLTAGE (V) 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) Figure 44. Driver Type A Current (2.5V VDDEXT/VDDMEM) Figure 47. Driver Type B Current (2.5V VDDEXT/VDDMEM) 80 60 VDDEXT = 1.9V @ – 40°C 80 VDDEXT = 1.8V @ 25°C VDDEXT = 1.7V @ 105°C 60 VDDEXT = 1.9V @ – 40°C VDDEXT = 1.8V @ 25°C VDDEXT = 1.7V @ 105°C 40 VOH 20 0 –20 VOL –40 –60 SOURCE CURRENT (mA) SOURCE CURRENT (mA) 40 VOH 20 0 –20 –40 VOL –60 –80 –80 0 0.5 1.0 1.5 –100 0.5 0 SOURCE VOLTAGE (V) 1.0 1.5 SOURCE VOLTAGE (V) Figure 45. Driver Type A Current (1.8V VDDEXT/VDDMEM) Figure 48. Driver Type B Current (1.8V VDDEXT/VDDMEM) Rev. D | Page 73 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 100 160 120 VDDEXT = 3.3V @ 25°C 60 VDDEXT = 3.0V @ 105°C 40 VOH 20 0 –20 –40 VOL –60 VDDEXT = 3.3V @ 25°C VDDEXT = 3.0V @ 105°C 80 SOURCE CURRENT (mA) SOURCE CURRENT (mA) VDDEXT = 3.6V @ – 40°C VDDEXT = 3.6V @ – 40°C 80 VOH 40 0 –40 –80 VOL –120 –80 –100 –160 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 49. Driver Type C Current (3.3V VDDEXT/VDDMEM) 3.0 3.5 120 VDDEXT = 2.75V @ – 40°C VDDEXT = 2.75V @ – 40°C 100 VDDEXT = 2.5V @ 25°C VDDEXT = 2.5V @ 25°C 80 VDDEXT = 2.25V @ 105°C 40 VDDEXT = 2.25V @ 105°C 60 20 VOH 0 –20 –40 VOL SOURCE CURRENT (mA) SOURCE CURRENT (mA) 2.5 Figure 52. Driver Type D Current (3.3V VDDEXT/VDDMEM) 80 60 2.0 SOURCE VOLTAGE (V) 40 VOH 20 0 –20 –40 –60 VOL –80 –60 –100 –80 –120 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 SOURCE VOLTAGE (V) Figure 50. Drive Type C Current (2.5V VDDEXT/VDDMEM) 2.5 60 VDDEXT = 1.9V @ – 40°C VDDEXT = 1.9V @ – 40°C VDDEXT = 1.8V @ 25°C VDDEXT = 1.7V @ 105°C VDDEXT = 1.8V @ 25°C VDDEXT = 1.7V @ 105°C 40 VOH 10 0 –10 VOL –20 SOURCE CURRENT (mA) 20 SOURCE CURRENT (mA) 2.0 Figure 53. Driver Type D Current (2.5V VDDEXT/VDDMEM) 40 30 1.5 SOURCE VOLTAGE (V) 20 VOH 0 –20 VOL –40 –30 –40 0 0.5 1.0 –60 1.5 0 0.5 SOURCE VOLTAGE (V) 1.0 1.5 SOURCE VOLTAGE (V) Figure 51. Driver Type C Current (1.8V VDDEXT/VDDMEM) Rev. D Figure 54. Driver Type D Current (1.8V VDDEXT/VDDMEM) | Page 74 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TEST CONDITIONS 60 VDDEXT = 3.6V @ – 40°C 50 VDDEXT = 3.3V @ 25°C 40 VDDEXT = 3.0V @ 105°C SOURCE CURRENT (mA) 30 20 10 0 All Timing Requirements appearing in this data sheet were measured under the conditions described in this section. Figure 58 shows the measurement point for AC measurements (except output enable/disable). The measurement point VMEAS is VDDEXT/2 or VDDMEM/2 for VDDEXT/VDDMEM (nominal) = 1.8 V/ 2.5 V/3.3 V. –10 –20 –30 INPUT OR OUTPUT VOL –40 VMEAS VMEAS –50 –60 0 0.5 1.0 1.5 2.0 2.5 3.0 Figure 58. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) 3.5 SOURCE VOLTAGE (V) Output Enable Time Measurement Figure 55. Driver Type E Current (3.3V VDDEXT/VDDMEM) 40 VDDEXT = 2.75V @ – 40°C 30 VDDEXT = 2.5V @ 25°C VDDEXT = 2.25V @ 105°C SOURCE CURRENT (mA) 20 10 0 Output balls are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of Figure 59. –10 REFERENCE SIGNAL VOL –20 –30 tDIS_MEASURED tDIS –40 0 0.5 1.0 1.5 2.0 3.0 2.5 3.5 VOH (MEASURED) SOURCE VOLTAGE (V) VOL (MEASURED) Figure 56. Driver Type E Current (2.5V VDDEXT/VDDMEM) tENA_MEASURED tENA VOH (MEASURED) ⴚ ⌬V VOH(MEASURED) VTRIP(HIGH) VOL (MEASURED) + ⌬V VTRIP(LOW) VOL (MEASURED) tDECAY tTRIP 20 VDDEXT = 1.9V @ – 40°C 15 VDDEXT = 1.8V @ 25°C VDDEXT = 1.7V @ 105°C OUTPUT STOPS DRIVING HIGH IMPEDANCE STATE 10 SOURCE CURRENT (mA) OUTPUT STARTS DRIVING Figure 59. Output Enable/Disable 5 0 –5 VOL –10 –15 –20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V) Figure 57. Driver Type E Current (1.8V VDDEXT/VDDMEM) The time tENA_MEASURED is the interval from when the reference signal switches to when the output voltage reaches VTRIP(high) or VTRIP(low). For VDDEXT/VDDMEM (nominal) = 1.8 V, VTRIP (high) is 1.05 V, and VTRIP (low) is 0.75 V. For VDDEXT/VDDMEM (nominal) = 2.5 V, VTRIP (high) is 1.5 V and VTRIP (low) is 1.0 V. For VDDEXT/VDDMEM (nominal) = 3.3 V, VTRIP (high) is 1.9 V, and VTRIP (low) is 1.4 V. Time tTRIP is the interval from when the output starts driving to when the output reaches the VTRIP(high) or VTRIP(low) trip voltage. Time tENA is calculated as shown in the equation: t ENA = t ENA_MEASURED – t TRIP If multiple balls (such as the data bus) are enabled, the measurement value is that of the first ball to start driving. Rev. D | Page 75 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Output Disable Time Measurement TESTER PIN ELECTRONICS Output balls are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The output disable time tDIS is the difference between tDIS_MEASURED and tDECAY as shown on the left side of Figure 59. t DIS = t DIS_MEASURED – t DECAY The time for the voltage on the bus to decay by ΔV is dependent on the capacitive load CL and the load current IL. This decay time can be approximated by the equation: 50Ω VLOAD T1 DUT OUTPUT 45Ω 70Ω ZO = 50Ω (impedance) TD = 4.04 ± 1.18 ns 50Ω 0.5pF 4pF 2pF 400Ω t DECAY = C L V I L The time tDECAY is calculated with test loads CL and IL, and with V equal to 0.25 V for VDDEXT/VDDMEM (nominal) = 2.5 V/3.3 V and 0.15 V for VDDEXT/VDDMEM (nominal) = 1.8V. The time tDIS_MEASURED is the interval from when the reference signal switches, to when the output voltage decays ΔV from the measured output high or output low voltage. NOTES: THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. Figure 60. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Example System Hold Time Calculation Capacitive Loading Output delays and holds are based on standard capacitive loads of an average of 6 pF on all balls (see Figure 60). VLOAD is equal to (VDDEXT/VDDMEM) /2. The graphs of Figure 61 through Figure 72 show how output rise time varies with capacitance. The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown. Rev. D | 12 RISE AND FALL TIME (10% TO 90%) To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose ΔV to be the difference between the processor’s output voltage and the input threshold for the device requiring the hold time. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the various output disable times as specified in the Timing Specifications on Page 39 (for example tDSDAT for an SDRAM write cycle as shown in SDRAM Interface Timing on Page 47). 10 tRISE 8 tFALL 6 4 2 tRISE = 1.8V @ 25°C tFALL = 1.8V @ 25°C 0 0 50 100 150 200 LOAD CAPACITANCE (pF) Figure 61. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (1.8V VDDEXT/VDDMEM) Page 76 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 7 7 6 tRISE 5 tFALL 4 3 2 1 tRISE = 2.5V @ 25°C RISE AND FALL TIME (10% TO 90%) RISE AND FALL TIME (10% TO 90%) 8 6 5 tRISE 4 tFALL 3 2 1 tRISE = 2.5V @ 25°C tFALL = 2.5V @ 25°C tFALL = 2.5V @ 25°C 0 0 50 100 0 200 150 0 50 LOAD CAPACITANCE (pF) 200 150 LOAD CAPACITANCE (pF) Figure 62. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM) Figure 65. Driver Type B Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM) 6 6 5 tRISE 4 tFALL 3 2 1 tRISE = 3.3V @ 25°C RISE AND FALL TIME (10% TO 90%) RISE AND FALL TIME (10% TO 90%) 100 5 tRISE 4 tFALL 3 2 1 tRISE = 3.3V @ 25°C tFALL = 3.3V @ 25°C 0 tFALL = 3.3V @ 25°C 0 0 50 100 200 150 0 50 LOAD CAPACITANCE (pF) 100 200 150 LOAD CAPACITANCE (pF) Figure 63. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3.3V VDDEXT/VDDMEM) Figure 66. Driver Type B Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3.3V VDDEXT/VDDMEM) 9 25 tRISE 7 6 tFALL 5 4 3 2 tRISE = 1.8V @ 25°C 1 RISE AND FALL TIME (10% TO 90%) RISE AND FALL TIME (10% TO 90%) 8 20 tRISE 15 tFALL 10 5 tRISE = 1.8V @ 25°C tFALL = 1.8V @ 25°C 0 tFALL = 1.8V @ 25°C 0 0 50 100 150 200 0 LOAD CAPACITANCE (pF) 50 100 150 200 LOAD CAPACITANCE (pF) Figure 64. Driver Type B Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (1.8V VDDEXT/VDDMEM) Rev. D | Figure 67. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (1.8V VDDEXT/VDDMEM) Page 77 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 10 9 14 12 tRISE 10 tFALL 8 6 4 2 tRISE = 2.5V @ 25°C RISE AND FALL TIME (10% TO 90%) RISE AND FALL TIME (10% TO 90%) 16 100 tFALL 5 4 3 2 tRISE = 2.5V @ 25°C tFALL = 2.5V @ 25°C 0 200 150 tRISE 6 0 0 50 7 1 tFALL = 2.5V @ 25°C 0 8 50 14 8 12 tRISE 10 8 tFALL 6 4 2 tRISE = 3.3V @ 25°C RISE AND FALL TIME (10% TO 90%) RISE AND FALL TIME (10% TO 90%) 200 150 Figure 71. Driver Type D Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM) Figure 68. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM) 7 6 tRISE 5 tFALL 4 3 2 1 tRISE = 3.3V @ 25°C tFALL = 3.3V @ 25°C 0 tFALL = 3.3V @ 25°C 0 0 50 100 200 150 0 50 LOAD CAPACITANCE (pF) 100 200 150 LOAD CAPACITANCE (pF) Figure 69. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3.3V VDDEXT/VDDMEM) Figure 72. Driver Type D Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3.3V VDDEXT/VDDMEM) 9 12 tRISE 10 tFALL 8 6 4 2 tRISE = 1.8V @ 25°C RISE AND FALL TIME (10% TO 90%) 14 RISE AND FALL TIME (10% TO 90%) 100 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) 8 tRISE 7 6 tFALL 5 4 3 2 tRISE = 1.8V @ 25°C 1 tFALL = 1.8V @ 25°C tFALL = 1.8V @ 25°C 0 0 0 50 100 150 0 200 50 100 150 200 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) Figure 70. Driver Type D Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (1.8V VDDEXT/VDDMEM) Rev. D | Figure 73. Driver Type G Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (1.8V VDDEXT/VDDMEM) Page 78 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Values of JA are provided for package comparison and printed circuit board design considerations. JA can be used for a first order approximation of TJ by the equation: 9 RISE AND FALL TIME (10% TO 90%) 8 7 6 T J = T A + JA P D tRISE 5 tFALL where: 4 TA = Ambient temperature (°C) 3 2 tRISE = 2.5V @ 25°C 1 tFALL = 2.5V @ 25°C 0 0 50 100 200 150 LOAD CAPACITANCE (pF) Figure 74. Driver Type G Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM) 9 RISE AND FALL TIME (10% TO 90%) 8 Values of JC are provided for package comparison and printed circuit board design considerations when an external heat sink is required. Values of JB are provided for package comparison and printed circuit board design considerations. In Table 66, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board measurement complies with JESD51-8. The junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Table 65. Thermal Characteristics for BC-208-1 Package 7 tRISE 6 5 tFALL 4 3 2 tRISE = 3.3V @ 25°C 1 tFALL = 3.3V @ 25°C 0 0 50 100 150 200 LOAD CAPACITANCE (pF) Figure 75. Driver Type G Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3.3V VDDEXT/VDDMEM) ENVIRONMENTAL CONDITIONS To determine the junction temperature on the application printed circuit board use: T J = T CASE + JT P D Parameter Condition Typical Unit JA 0 linear m/s air flow 23.20 °C/W JMA 1 linear m/s air flow 20.20 °C/W JMA 2 linear m/s air flow 19.20 °C/W JB 13.05 °C/W JC 6.92 °C/W JT 0 linear m/s air flow 0.18 °C/W JT 1 linear m/s air flow 0.27 °C/W JT 2 linear m/s air flow 0.32 °C/W Table 66. Thermal Characteristics for BC-289-2 Package Parameter Condition Typical Unit JA 0 linear m/s air flow 34.5 °C/W JMA 1 linear m/s air flow 31.1 °C/W JMA 2 linear m/s air flow 29.8 °C/W JB 20.3 °C/W JC 8.8 °C/W where: JT 0 linear m/s air flow 0.24 °C/W TJ = Junction temperature (°C) JT 1 linear m/s air flow 0.44 °C/W JT 2 linear m/s air flow 0.53 °C/W TCASE = Case temperature (°C) measured by customer at top center of package. JT = From Table 66 PD = Power dissipation — For a description, see Total Power Dissipation on Page 35. Rev. D | Page 79 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 289-BALL CSP_BGA BALL ASSIGNMENT Table 67 lists the CSP_BGA balls by signal mnemonic. Table 68 on Page 81 lists the CSP_BGA by ball number. Table 67. 289-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Ball Ball Ball Ball Ball Ball Ball Signal No. Signal No. Signal No. Signal No. Signal No. Signal No. Signal No. T2 GND M10 NC D23 PH0 A11 USB_XO AA23 VDDINT R8 ABE0/SDQM0 AB9 DATA6 T1 GND M11 NC E22 PH1 A12 VDDEXT G7 VDDINT R16 ABE1/SDQM1 AC9 DATA7 ADDR1 AB8 DATA8 R1 GND M12 NC E23 PH2 A13 VDDEXT G8 VDDINT T8 G9 VDDINT T9 ADDR2 AC8 DATA9 P1 GND M13 NC F22 PH3 B14 VDDEXT G10 VDDINT T10 ADDR3 AB7 DATA10 P2 GND M14 NC F23 PH4 A14 VDDEXT ADDR4 AC7 DATA11 R2 GND M15 NC G22 PH5 K23 VDDEXT G11 VDDINT T11 G12 VDDINT T12 ADDR5 AC6 DATA12 N1 GND N9 NC H23 PH6 K22 VDDEXT G13 VDDINT T13 ADDR6 AB6 DATA13 N2 GND N10 NC J23 PH7 L23 VDDEXT ADDR7 AB4 DATA14 M2 GND N11 NMI U22 PH8 L22 VDDEXT G14 VDDINT T14 G15 VDDINT T15 ADDR8 AB5 DATA15 M1 GND N12 VPPOTP AB11 PH9 T23 VDDEXT H7 VDDINT T16 ADDR9 AC5 EMU J2 GND N13 PF0 A7 PH10 M22 VDDEXT ADDR10 AC4 EXT_WAKE0 AC19 GND N14 PF1 B8 PH11 R22 VDDEXT J17 VDDMEM J7 K17 VDDMEM K7 ADDR11 AB3 GND A1 GND N15 PF2 A8 PH12 M23 VDDEXT L17 VDDMEM L7 ADDR12 AC3 GND A23 GND P9 PF3 B9 PH13 N22 VDDEXT ADDR13 AB2 GND B6 GND P10 PF4 B11 PH14 N23 VDDEXT M17 VDDMEM M7 G16 GND P11 PF5 B10 PH15 P22 VDDEXT N17 VDDMEM N7 ADDR14 AC2 GND1 P17 VDDMEM P7 ADDR15 AA2 GND G17 GND P12 PF6 B12 PPI_CLK/TMRCLK A6 VDDEXT ADDR16 W2 GND1 H17 GND P13 PF7 B13 PPI_FS1/TMR0 B7 VDDEXT R17 VDDMEM R7 V22 VDDEXT T17 VDDMEM T7 ADDR17 Y2 GND H22 GND P14 PF8 B16 RESET ADDR18 AA1 GND1 J22 GND P15 PF9 A20 RTXI U23 VDDEXT U17 VDDMEM U7 B5 VDDMEM U8 ADDR19 AB1 GND J9 GND R9 PF10 B15 RTXO V23 VDDINT AC17 GND J10 GND R10 PF11 B17 SA10 AC10 VDDINT H8 VDDMEM U9 AMS0 AMS1 AB16 GND J11 GND R11 PF12 B18 SCAS AC11 VDDINT H9 VDDMEM U10 AC16 GND J12 GND R12 PF13 B19 SCKE AB13 VDDINT H10 VDDMEM U11 AMS2 AB15 GND J13 GND R13 PF14 A9 SCL B22 VDDINT H11 VDDMEM U12 AMS3 AOE AC15 GND J14 GND R14 PF15 A10 SDA C22 VDDINT H12 VDDMEM U13 AC13 VDDINT H13 VDDMEM U14 ARDY AC14 GND J15 GND R15 PG0 H2 SMS AB17 GND K9 GND T22 PG1 G1 SRAS AB12 VDDINT H14 VDDMEM U15 ARE AWE AB14 GND K10 GND AC1 PG2 H1 SS/PG AC20 VDDINT H15 VDDMEM U16 AB10 VDDINT H16 VDDOTP AC12 BMODE0 G2 GND K11 GND AC23 PG3 F1 SWE J8 VDDRTC W23 BMODE1 F2 GND K12 NC A15 PG4 D1 TCK L1 VDDINT BMODE2 E1 GND K13 NC A16 PG5 D2 TDI J1 VDDINT J16 VDDUSB W22 K8 VDDUSB Y23 BMODE3 E2 GND K14 NC A17 PG6 C2 TDO K1 VDDINT K16 NC G23 CLKBUF AB19 GND K15 NC A18 PG7 B1 TMS L2 VDDINT CLKIN R23 GND L9 NC A19 PG8 C1 TRST K2 VDDINT L8 VROUT/EXT_WAKE1 AC18 L16 VRSEL/VDDEXT AB22 CLKOUT AB18 GND L10 NC A21 PG9 B2 USB_DM AB21 VDDINT M8 XTAL P23 DATA0 Y1 GND L11 NC A22 PG10 B4 USB_DP AA22 VDDINT DATA1 V2 GND L12 NC B20 PG11 B3 USB_ID Y22 VDDINT M16 N8 DATA2 W1 GND L13 NC B21 PG12 A2 USB_RSET AC21 VDDINT N16 DATA3 U2 GND L14 NC B23 PG13 A3 USB_VBUS AB20 VDDINT DATA4 V1 GND L15 NC C23 PG14 A4 USB_VREF AC22 VDDINT P8 P16 DATA5 U1 GND M9 NC D22 PG15 A5 USB_XI AB23 VDDINT NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. 1 For ADSP-BF52xC compatibility, connect this ball to VDDEXT. Rev. D | Page 80 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 68. 289-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball Ball Ball Ball Ball Ball Ball No. Signal No. Signal No. Signal No. Signal No. Signal No. Signal No. Signal A1 GND B20 NC H12 VDDINT L9 GND P2 DATA10 T22 GND AB10 SWE A2 PG12 B21 NC H13 VDDINT L10 GND P7 VDDMEM T23 PH9 AB11 VPPOTP L11 GND P8 VDDINT U1 DATA5 AB12 SRAS A3 PG13 B22 SCL H14 VDDINT A4 PG14 B23 NC H15 VDDINT L12 GND P9 GND U2 DATA3 AB13 SCKE L13 GND P10 GND U7 VDDMEM AB14 AWE A5 PG15 C1 PG8 H16 VDDINT A6 PPI_CLK/TMRCLK C2 PG6 H17 GND1 L14 GND P11 GND U8 VDDMEM AB15 AMS3 A7 PF0 C22 SDA H22 GND L15 GND P12 GND U9 VDDMEM AB16 AMS1 A8 PF2 C23 NC H23 NC L16 VDDINT P13 GND U10 VDDMEM AB17 ARE A9 PF14 D1 PG4 J1 TDI L17 VDDEXT P14 GND U11 VDDMEM AB18 CLKOUT A10 PF15 D2 PG5 J2 EMU L22 PH8 P15 GND U12 VDDMEM AB19 CLKBUF L23 PH7 P16 VDDINT U13 VDDMEM AB20 USB_VBUS A11 PH0 D22 NC J7 VDDMEM M1 DATA15 P17 VDDEXT U14 VDDMEM AB21 USB_DM A12 PH1 D23 NC J8 VDDINT A13 PH2 E1 BMODE2 J9 GND M2 DATA14 P22 PH15 U15 VDDMEM AB22 VRSEL/VDDEXT A14 PH4 E2 BMODE3 J10 GND M7 VDDMEM P23 XTAL U16 VDDMEM AB23 USB_XI R1 DATA8 U17 VDDEXT AC1 GND A15 NC E22 NC J11 GND M8 VDDINT A16 NC E23 NC J12 GND M9 GND R2 DATA11 U22 NMI AC2 ADDR14 U23 RTXI AC3 ADDR12 A17 NC F1 PG3 J13 GND M10 GND R7 VDDMEM V1 DATA4 AC4 ADDR10 A18 NC F2 BMODE1 J14 GND M11 GND R8 VDDINT A19 NC F22 NC J15 GND M12 GND R9 GND V2 DATA1 AC5 ADDR9 A20 PF9 F23 NC J16 VDDINT M13 GND R10 GND V22 RESET AC6 ADDR5 M14 GND R11 GND V23 RTXO AC7 ADDR4 A21 NC G1 PG1 J17 VDDEXT A22 NC G2 BMODE0 J22 GND1 M15 GND R12 GND W1 DATA2 AC8 ADDR2 J23 NC M16 VDDINT R13 GND W2 ADDR16 AC9 ABE1/SDQM1 A23 GND G7 VDDEXT B1 PG7 G8 VDDEXT K1 TDO M17 VDDEXT R14 GND W22 VDDUSB AC10 SA10 K2 TRST M22 PH10 R15 GND W23 VDDRTC AC11 SCAS B2 PG9 G9 VDDEXT B3 PG11 G10 VDDEXT K7 VDDMEM M23 PH12 R16 VDDINT Y1 DATA0 AC12 VDDOTP B4 PG10 G11 VDDEXT K8 VDDINT N1 DATA12 R17 VDDEXT Y2 ADDR17 AC13 SMS B5 VDDINT G12 VDDEXT K9 GND N2 DATA13 R22 PH11 Y22 USB_ID AC14 ARDY K10 GND N7 VDDMEM R23 CLKIN Y23 VDDUSB AC15 AOE B6 GND G13 VDDEXT B7 PPI_FS1/TMR0 G14 VDDEXT K11 GND N8 VDDINT T1 DATA7 AA1 ADDR18 AC16 AMS2 B8 PF1 G15 VDDEXT K12 GND N9 GND T2 DATA6 AA2 ADDR15 AC17 AMS0 1 B9 PF3 G16 GND K13 GND N10 GND T7 VDDMEM AA22 USB_DP AC18 VROUT/EXT_WAKE1 B10 PF5 G17 GND K14 GND N11 GND T8 VDDINT AA23 USB_XO AC19 EXT_WAKE0 AB1 ADDR19 AC20 SS/PG B11 PF4 G22 NC K15 GND N12 GND T9 VDDINT B12 PF6 G23 NC K16 VDDINT N13 GND T10 VDDINT AB2 ADDR13 AC21 USB_RSET B13 PF7 H1 PG2 K17 VDDEXT N14 GND T11 VDDINT AB3 ADDR11 AC22 USB_VREF AB4 ADDR7 AC23 GND B14 PH3 H2 PG0 K22 PH6 N15 GND T12 VDDINT K23 PH5 N16 VDDINT T13 VDDINT AB5 ADDR8 B15 PF10 H7 VDDEXT B16 PF8 H8 VDDINT L1 TCK N17 VDDEXT T14 VDDINT AB6 ADDR6 L2 TMS N22 PH13 T15 VDDINT AB7 ADDR3 B17 PF11 H9 VDDINT L7 VDDMEM N23 PH14 T16 VDDINT AB8 ADDR1 B18 PF12 H10 VDDINT B19 PF13 H11 VDDINT L8 VDDINT P1 DATA9 T17 VDDEXT AB9 ABE0/SDQM0 NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. 1 For ADSP-BF52xC compatibility, connect this ball to VDDEXT. Rev. D | Page 81 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Figure 76 shows the top view of the BC-289-2 CSP_BGA ball configuration. Figure 77 shows the bottom view of the BC-289-2 CSP_BGA ball configuration. A1 BALL PAD CORNER A B C D E F G H J K L TOP VIEW M N P KEY: R V DDINT GND T NC U V V DDEXT I/O V W DDMEM Y AA AB AC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Figure 76. 289-Ball CSP_BGA Ball Configuration (Top View) A1 BALL PAD CORNER A B C D E BOTTOM VIEW F G H KEY: J K L V GND NC V I/O V DDINT M N P DDEXT R T U V W Y AA AB AC 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 77. 289-Ball CSP_BGA Ball Configuration (Bottom View) Rev. D | Page 82 of 88 | July 2013 DDMEM ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 208-BALL CSP_BGA BALL ASSIGNMENT Table 69 lists the CSP_BGA balls by signal mnemonic. Table 70 on Page 84 lists the CSP_BGA by ball number. Table 69. 208-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. ABE0/SDQM0 V19 CLKOUT K20 GND K11 PF13 A5 PPI_CLK/TMRCLK G2 VDDEXT J8 ABE1/SDQM1 V20 DATA0 Y8 GND K12 PF14 B6 PPI_FS1/TMR0 F2 VDDEXT K7 Signal Ball No. ADDR1 W20 DATA1 W8 GND K13 PF15 A6 RESET B18 VDDEXT K8 ADDR2 W19 DATA2 Y7 GND L9 PG0 R2 RTXI A14 VDDEXT L7 ADDR3 Y19 ADDR4 W18 DATA4 DATA3 DATA5 W7 GND L10 PG1 P1 RTXO A15 VDDINT G12 Y6 GND L11 PG2 P2 SA10 U19 VDDINT G13 ADDR5 Y18 W6 GND L12 PG3 N1 SCAS U20 VDDINT G14 ADDR6 W17 DATA6 Y5 GND L13 PG4 N2 SCKE P20 VDDINT H14 ADDR7 Y17 W5 GND M9 PG5 M1 SCL A4 VDDINT J14 ADDR8 W16 DATA8 Y4 GND M10 PG6 M2 SDA B4 VDDINT K14 ADDR9 Y16 W4 GND M11 PG7 L1 SMS R19 VDDINT L14 ADDR10 W15 DATA10 Y3 GND M12 PG8 L2 SRAS T19 VDDINT M14 ADDR11 Y15 W3 GND M13 PG9 K1 SS/PG G19 VDDINT N14 ADDR12 W14 DATA12 Y2 GND N9 K2 SWE T20 VDDINT P12 DATA7 DATA9 DATA11 PG10 ADDR13 Y14 DATA13 W2 GND N10 PG11 J1 TCK V2 VDDINT P13 ADDR14 W13 DATA14 W1 GND N11 PG12 J2 TDI R1 VDDINT P14 ADDR15 Y13 V1 GND N12 PG13 H1 TDO T1 VDDMEM L8 ADDR16 W12 EMU T2 GND N13 PG14 H2 TMS U2 VDDMEM M7 ADDR17 Y12 J20 GND Y1 PG15 G1 TRST U1 VDDMEM M8 ADDR18 W11 GND A1 GND Y20 PH0 A7 USB_DM F20 VDDMEM N7 ADDR19 Y11 GND A17 NMI B19 PH1 B7 USB_DP E20 VDDMEM N8 AMS0 J19 GND A20 VPPOTP L19 PH2 A8 USB_ID C20 VDDMEM P7 AMS1 K19 GND B20 PF0 F1 PH3 B8 USB_RSET D20 VDDMEM P8 AMS2 M19 GND H9 PF1 E1 PH4 A9 USB_VBUS E19 VDDMEM P9 AMS3 L20 GND H10 PF2 E2 PH5 B9 USB_VREF H19 VDDMEM P10 AOE N20 GND H11 PF3 D1 PH6 B10 USB_XI A19 VDDMEM P11 ARDY P19 GND H12 PF4 D2 PH7 B11 USB_XO A18 VDDOTP R20 ARE M20 GND H13 PF5 C1 PH8 A12 VDDEXT G7 VDDRTC A16 AWE N19 GND J9 PF6 C2 PH9 B12 VDDEXT G8 VDDUSB D19 BMODE0 Y10 GND J10 PF7 B1 PH10 A13 VDDEXT G9 VDDUSB G20 DATA15 EXT_WAKE0 BMODE1 W10 GND J11 PF8 B2 PH11 B13 VDDEXT G10 VROUT/EXT_WAKE1 H20 BMODE2 Y9 GND J12 PF9 A2 PH12 B14 VDDEXT G11 VRSEL/VDDEXT F19 BMODE3 W9 GND J13 PF10 B3 PH13 B15 VDDEXT H7 XTAL A10 CLKBUF C19 GND K9 PF11 A3 PH14 B16 VDDEXT H8 CLKIN A11 GND K10 PF12 B5 PH15 B17 VDDEXT J7 NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Rev. D | Page 83 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Table 70. 208-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal A1 GND B16 PH14 H7 VDDEXT L2 PG8 P1 PG1 W8 DATA1 A2 PF9 B17 PH15 H8 VDDEXT L7 VDDEXT P2 PG2 W9 BMODE3 A3 PF11 B18 RESET H9 GND L8 VDDMEM P7 VDDMEM W10 BMODE1 A4 SCL B19 NMI H10 GND L9 GND P8 VDDMEM W11 ADDR18 A5 PF13 B20 GND H11 GND L10 GND P9 VDDMEM W12 ADDR16 A6 PF15 C1 PF5 H12 GND L11 GND P10 VDDMEM W13 ADDR14 A7 PH0 C2 PF6 H13 GND L12 GND P11 VDDMEM W14 ADDR12 A8 PH2 C19 CLKBUF H14 VDDINT L13 GND P12 VDDINT W15 ADDR10 A9 PH4 C20 USB_ID H19 USB_VREF L14 VDDINT P13 VDDINT W16 ADDR8 A10 XTAL D1 PF3 H20 VROUT/EXT_WAKE1 L19 VPPOTP P14 VDDINT W17 ADDR6 A11 CLKIN D2 PF4 J1 PG11 L20 AMS3 P19 ARDY W18 ADDR4 A12 PH8 D19 VDDUSB J2 PG12 M1 PG5 P20 SCKE W19 ADDR2 A13 PH10 D20 USB_RSET J7 VDDEXT M2 PG6 R1 TDI W20 ADDR1 A14 RTXI E1 PF1 J8 VDDEXT M7 VDDMEM R2 PG0 Y1 GND A15 RTXO E2 PF2 J9 GND M8 VDDMEM R19 SMS Y2 DATA12 GND A16 VDDRTC E19 USB_VBUS J10 GND M9 R20 VDDOTP Y3 DATA10 A17 GND E20 USB_DP J11 GND M10 GND T1 TDO Y4 DATA8 A18 USB_XO F1 PF0 J12 GND M11 GND T2 EMU Y5 DATA6 A19 USB_XI F2 PPI_FS1/TMR0 J13 GND M12 GND T19 SRAS Y6 DATA4 A20 GND F19 VRSEL/VDDEXT J14 VDDINT M13 GND T20 SWE Y7 DATA2 B1 PF7 F20 USB_DM J19 AMS0 M14 VDDINT U1 TRST Y8 DATA0 B2 PF8 G1 PG15 J20 EXT_WAKE0 M19 AMS2 U2 TMS Y9 BMODE2 B3 PF10 G2 PPI_CLK/TMRCLK K1 PG9 M20 ARE U19 SA10 Y10 BMODE0 B4 SDA G7 VDDEXT K2 PG10 N1 PG3 U20 SCAS Y11 ADDR19 B5 PF12 G8 VDDEXT K7 VDDEXT N2 PG4 V1 DATA15 Y12 ADDR17 B6 PF14 G9 VDDEXT K8 VDDEXT N7 VDDMEM V2 TCK Y13 ADDR15 B7 PH1 G10 VDDEXT K9 GND N8 VDDMEM V19 ABE0/SDQM0 Y14 ADDR13 B8 PH3 G11 VDDEXT K10 GND N9 GND V20 ABE1/SDQM1 Y15 ADDR11 B9 PH5 G12 VDDINT K11 GND N10 GND W1 DATA14 Y16 ADDR9 B10 PH6 G13 VDDINT K12 GND N11 GND W2 DATA13 Y17 ADDR7 B11 PH7 G14 VDDINT K13 GND N12 GND W3 DATA11 Y18 ADDR5 B12 PH9 G19 SS/PG K14 VDDINT N13 GND W4 DATA9 Y19 ADDR3 B13 PH11 G20 VDDUSB K19 AMS1 N14 VDDINT W5 DATA7 Y20 GND B14 PH12 H1 PG13 K20 CLKOUT N19 AWE W6 DATA5 B15 PH13 H2 PG14 L1 PG7 N20 AOE W7 DATA3 NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Rev. D | Page 84 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 Figure 78 shows the top view of the CSP_BGA ball configuration. Figure 79 shows the bottom view of the CSP_BGA ball configuration. A1 BALL PAD CORNER A B C D E F G H J K L M N P R T U V W Y TOP VIEW KEY: VDDINT GND VDDEXT I/O VDDMEM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 78. 208-Ball CSP_BGA Ball Configuration (Top View) A1 BALL PAD CORNER A B C D E F G H J K L M N P R T U V W Y BOTTOM VIEW KEY: VDDINT GND VDDEXT I/O VDDMEM 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 79. 208-Ball CSP_BGA Ball Configuration (Bottom View) Rev. D | Page 85 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 OUTLINE DIMENSIONS Dimensions in the outline dimension figures (Figure 80 and Figure 81) are shown in millimeters. A1 BALL CORNER 12.00 BSC SQ 22 20 18 16 14 12 10 8 6 4 2 23 21 19 17 15 13 11 9 7 5 3 1 A C E G 11.00 BSC SQ J L N R 0.50 BSC U W B D F H K M P T V Y AA AB AC TOP VIEW BOTTOM VIEW DETAIL A 1.40 1.26 1.11 DETAIL A 0.20 MIN 0.35 COPLANARITY 0.08 0.30 0.25 BALL DIAMETER SEATING PLANE *COMPLIANT WITH JEDEC STANDARD MO-275-GGCE-1 Figure 80. 289-Ball CSP_BGA (BC-289-2) A1 BALL CORNER 17.10 17.00 SQ 16.90 A B C D E F G H J K L M N P R T U V W Y 15.20 BSC SQ 0.80 BSC BOTTOM VIEW TOP VIEW *1.75 1.61 1.46 A1 BALL CORNER 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 DETAIL A DETAIL A 0.35 NOM 0.30 MIN SEATING PLANE 0.50 0.45 0.40 BALL DIAMETER *COMPLIANT TO JEDEC STANDARDS MO-275-MMAB-1 WITH EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. Figure 81. 208-Ball CSP_BGA (BC-208-2) Rev. D | Page 86 of 88 | July 2013 *1.36 1.26 1.16 COPLANARITY 0.12 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 SURFACE-MOUNT DESIGN Table 71 is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 71. Surface-Mount Design Supplement Package 289-Ball CSP_BGA 208-Ball CSP_BGA Package Ball Attach Type Solder Mask Defined Solder Mask Defined Package Solder Mask Opening 0.26 mm diameter 0.40 mm diameter Package Ball Pad Size 0.35 mm diameter 0.50 mm diameter AUTOMOTIVE PRODUCTS The ADBF525W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models and designers should review the product Specifications section of this data sheet carefully. Only the automotive grade products shown in Table 72 are available for use in automotive applications. Contact your local ADI account representative for specific product ordering information and to obtain the specific automotive Reliability reports for these models. Table 72. Automotive Products Automotive Models1, 2 ADBF525WBBCZ4xx ADBF525WBBCZ5xx ADBF525WYBCZxxx Temperature Range3 –40°C to +85°C –40°C to +85°C –40°C to +105°C Package Description 208-Ball CSP_BGA 208-Ball CSP_BGA 208-Ball CSP_BGA 1 Package Option BC-208-2 BC-208-2 BC-208-2 Instruction Rate (Max) 400 MHz 533 MHz For product details, please contact your ADI account representative. Z = RoHS Compliant Part. The information indicated by x in the model number will be provided by your ADI account representative. 3 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions for ADSP-BF523/ADSP-BF525/ ADSP-BF527 Processors on Page 30 for junction temperature (TJ) specification which is the only temperature specification. 2 Rev. D | Page 87 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 ORDERING GUIDE Model1 Temperature Range2 Instruction Rate (Max) Package Description Package Option ADSP-BF522BBCZ-3A –40°C to +85°C 300 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF522BBCZ-4A –40°C to +85°C 400 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF522KBCZ-3 0°C to +70°C 300 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF522KBCZ-4 0°C to +70°C 400 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF523BBCZ-5A –40°C to +85°C 533 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF523KBCZ-5 0°C to +70°C 533 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF523KBCZ-6 0°C to +70°C 600 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF523KBCZ-6A 0°C to +70°C 600 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF524BBCZ-3A –40°C to +85°C 300 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF524BBCZ-4A –40°C to +85°C 400 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF524KBCZ-3 0°C to +70°C 300 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF524KBCZ-4 0°C to +70°C 400 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF525ABCZ-5 –40°C to +70°C 500 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF525ABCZ-6 –40°C to +70°C 600 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF525BBCZ-5A –40°C to +85°C 533 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF525KBCZ-5 0°C to +70°C 533 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF525KBCZ-6 0°C to +70°C 600 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF525KBCZ-6A 0°C to +70°C 600 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF526BBCZ-3A –40°C to +85°C 300 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF526BBCZ-4A –40°C to +85°C 400 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF526KBCZ-3 0°C to +70°C 300 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF526KBCZ-4 0°C to +70°C 400 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF527BBCZ-5A –40°C to +85°C 533 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 ADSP-BF527KBCZ-5 0°C to +70°C 533 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF527KBCZ-6 0°C to +70°C 600 MHz 289-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-289-2 ADSP-BF527KBCZ-6A 0°C to +70°C 600 MHz 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-208-2 1 2 Z = RoHS Compliant Part. Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page 28 and Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors on Page 30 for junction temperature (TJ) specification which is the only temperature specification. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06675-0-7/13(D) Rev. D | Page 88 of 88 | July 2013