AIC1533 Triple-Output LCD Power Supply FEATURES DESCRIPTION One Low Dropout Linear Regulator AIC1533, composed of dual charge pumps and a Dropout Voltage 500mV at 0.3A Output Current regulator, provide three independent regulated Dual Adjustable Charge Pump voltages designed for using in thin-film transistor Up to +30V Positive Output (TFT) liquid crystal display (LCD). Down to -10V Negative Output Power Up Sequencing and Adjustable Delay The main regulator has an adjustable output time voltage and a low dropout voltage of 500mV at Power-Saving Shutdown Mode (0.1µA typical) 300mA load current is performed. Operating Supply Voltage: 12V The dual charge pumps independently regulate a 1MHz Operation Frequency Internal Current Limit and Thermal Protection built in LDO part Few External Components Required positive output and a negative output. AIC1533 has thermal shutdown capability and survives a continuous short circuit from output to ground. A unique control scheme minimizes output ripple as well as output capacitance for both charge pump. APPLICATIONS 1MHz-switching frequency of AIC1533 provides a LCD Monitor Panel Module low noise, low cost total solution. The device LCD TV Panel Module operates up to 15V supply voltage and is available in 14-lead SOP and 16-lead TSSOP package. Analog Integrations Corporation Si-Soft Research Center DS-1533P-02 010405 3A1, No.1, Li-Hsin Rd. I, Science Park, Hsinchu 300, Taiwan, R.O.C. TEL: 886-3-5772500 FAX: 886-3-5772510 www.analog.com.tw 1 AIC1533 TYPICAL APPLICATION CIRCUIT OUT3 10V/300mA 12VIN CIN 10µF + Cp 1nF C1 2.2µF BAT54S D1 CFLY1 OUT1 28V/30mA OUT SHDN ADJ TP 0.1µF TN GND SWN SUPP FBN SWP VREF + R3 910k Cn 4.7nF R4 CFLY3 0.1µF R1 470k C3 10pF R5 240k OUT2 -9V/30mA Co2 1µF D3 BAT54S R6 33k C4 0.22µF 0.1µF D2 BAT54S Co1 1µF Co3 10µF 130k FBP PGND AIC1533 CFLY2 C2 0.47uF VCC R2 22k CIN, CO3: HER-MEI Electrolysis Capacitor, LER100M1CD11 or TAIYO YUDEN Ceramic Capacitor, EMK325BJ106MN-B (10µF/16V) CFLY1, CFLY2: TAIYO YUDEN Ceramic Capacitor, UMK212BJ104KG (0.1µF/50V) CFLY3: TAIYO YUDEN Ceramic Capacitor, EMK107BJ104KA (0.1µF/16V) CO1: TAIYO YUDEN Ceramic Capacitor, UMK212F105ZG (1µF/50V) CO2: TAIYO YUDEN Ceramic Capacitor, EMK212F105KG (1µF/16V) D1~D3: WTE Schottky Diode, BAT54S Fig.1 TFT-LCD Power Application 2 AIC1533 ORDERING INFORMATION AIC1533XXXX PACKING TYPE TB: TUBE TR: TAPING & REEL PACKAGING TYPE S: SOP-14 L: TSSOP-16 C: COMMERCIAL P: LEAD FREE COMMERCIAL Exam ple: AIC1533CLTR PIN CONFIGURATION SOP-14 TOP VIEW ADJ 1 14 GND OUT 2 13 VREF FBP 3 12 FBN SHDN 4 11 TP VCC 5 10 TN SUPP 6 9 SW N SW P 7 8 PGND in TSSOP-16 Package & Taping & Reel Packing Type AIC1533PSTR in Lead Free SOP-14 Package & Taping & Reel Packing Type TSSOP-16 TOP VIEW ADJ 1 16 GND OUT 2 15 VREF FBP 3 14 FBN SHDN 4 13 TP VCC 5 12 TN SUPP 6 11 SW N SW P 7 10 PGND GND 8 9 GND 3 AIC1533 ABSOLUTE MAXIMUM RATINGS VCC, SHDN to GND -0.3V to 18V FBN, FBP, VREF, ADJ, TN, TP -0.3V to 8V SWN, SWP -0.3V to (Vcc+0.3V) PGND to GND ±0.3V Operating Temperature -40°C to 85°C Junction Temperature 125°C Storage Temperature Range -65°C to 150°C Lead Temperature (Soldering, 10 sec) 260°C Thermal Resistance Junction to Ambient SOP-14 100°C/W (Assume no ambient airflow, no heatsink) TSSOP-16 120°C/W Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. TEST CIRCUIT Refer to TYPICAL APPLICATION CIRCUIT. ELECTRICAL CHARACTERISTICS (VIN=12V, CO1=CO2=1µF, CO3=10µF, CFLY1=CFLY2=CFLY3=0.1µF, TA=25°C, unless otherwise specified.) (Note 1) PARAMETER TEST CONDITIONS Input Voltage Range Quiescent Current V SHDN =2.4V, IOUT= 0mA Standby Current V SHDN =0.6V,Output OFF MIN. TYP. MAX. UNIT 10 12 15 V 0.6 1.2 2.0 mA 1 µA Thermal Shutdown Temperature °C 155 LOW DROPOUT LINEAR REGULATOR TERMINAL SPECIFICATION Adjustable Voltage Line Regulation 1.225 1.25 VIN =12~15V, VOUT3=10V, 1 IOUT3=1mA Load Regulation VIN =12V, IOUT3=0.1~300mA Continuous Output Current VIN =12V Current Limit VIN =12V, V OUT3=0V (Note2) Dropout Voltage IOUT3=300mA 1.275 1 % % mA 300 350 V 700 mA 500 mV 4 AIC1533 ELECTRICAL CHARACTERISTICS (Continued) MIN. TYP. MAX. UNIT FBP Threshold 1.225 1.25 1.275 V FBN Threshold -30 0 30 mV 1.231 1.25 1.269 V 30 mA PARAMETER TEST CONDITIONS CHARGE PUMP TERMINAL SPECIFICATION VREF Voltage IREF=250µA Continuous Output Current VIN =12V 3 5 7 µA TP/TN Input Threshold 1.225 1.25 1.275 V Switching Frequency 0.70 1 1.30 MHz SUPP switch 5 10 SWP switch 5 10 SWN switch 5 10 0.1 1 TP/TN Bias Current Internal Switch On-Resistance Ω SHUTDOWN TERMINAL SPECIFICATIONS SHDN Pin Current SHDN Pin Voltage V SHDN =2.4V Output ON Output OFF 2.4 0.6 µA V Note 1: Specifications are production tested at TA=25°C. Specifications over the -40°C to 85°C operating temperature range are assured by design, characterization and correlation with Statistical Quality Controls (SQC). Note 2: Current limit is measured by pulse testing. 5 AIC1533 SHDN 0 Shutdown exit Delay time LDO 0 Negative Charge Pump 0 90% 10% 90% T1 T2 Positive Charge Pump 0 T1 set by CN T2 set by CP Fig. 2 Power Up Sequencing TYPICAL PERFORMANCE CHARACTERISTICS VSHDN=0~3V V O2=-10V, I O2=30mA VCC=12V Vo1 Vo3 VO1=30V, IO1=30mA Vo2 Fig. 3 Power- Up Sequence Fig 4. Ripple Voltage Waveforms 6 AIC1533 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) 800 VCC=12V, VO3=10V, CO3=10µF, Io3=300mA VCC=12V VCC-VOUT (mV) 700 VO3 IO3 600 500 400 300 200 100 0 0 50 100 150 200 250 300 350 400 450 IOUT (mA) Fig. 5 LDO Load Transient Response Fig. 6 Dropout Voltage vs. LDO Load 800 800 600 500 400 300 200 -40 700 Current Limit (mA) VCC-VOUT (mV) 700 IOUT=300mA -20 0 20 40 60 80 100 600 500 400 300 120 -40 -20 0 Temperature (°C) 80 100 120 TN/TP Bias Current (µA) 7.0 IOUT=300mA 475 VCC-VOUT (mV) 60 Fig. 8 LDO Current Limit vs. Temperature 500 450 425 400 375 10 40 Temperature (°C) Fig. 7 LDO Dropout Voltage vs. Temperature 350 20 11 12 13 14 15 16 17 18 VCC (V) Fig. 9 LDO Dropout Voltage vs. Input Voltage 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Fig. 10 TN/TP Bias Current vs. Temperature 7 AIC1533 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) 1.260 -8.0 -8.4 1.255 -8.8 VREF (V) VNEG (V) 1.250 1.245 1.240 -9.2 VCC=11V -9.6 VCC=12V -10.0 -10.4 1.235 VCC=13V -10.8 1.230 -40 -20 0 20 40 60 80 100 120 Temperature (°C) 0 20 30 40 INEG (mA) Fig. 12 Negative Charge-Pump vs. Load Current Fig. 11 VREF vs. Temperature 32 100 VNEG=-10V 31 90 VCC=13V Efficiency (%) 30 VPOS (V) 10 29 VCC=12V 28 VCC=11V 27 26 VCC=12V VCC=11V 80 VCC=13V 70 60 50 40 25 0 10 20 30 40 IPOS (mA) Fig. 13 Positive Charge Pump vs. Load Current 30 0 10 20 30 40 INEG (mA) Fig. 14 Negative Charge-Pump vs. Load Current 100 VPOS=30V 90 Efficiency (%) VCC=11V 80 VCC=12V VCC=13V 70 60 50 40 30 0 10 30 40 IPOS (mA) Fig. 15 Positive Charge-Pump Efficiency vs. Load Current 8 AIC1533 BLOCK DIAGRAM 14 ADJ 1 + VCC OUT - Current Limit Thermal Shutdown Reference Voltage ADJ - FBP 13 EA 2 90%VREF 5V + 12 10%VREF - COMP 3 SHDN + 5µA VCC 5 Q6 OSC FBN COMP 5µA Shutdown VREF 5V 11 4 GND 1.25V TP Q7 TP 10 Q1 TN VCC SUPP 6 Q4 Q2 9 SWP 7 - EA + Q3 FBP FBN + VREF - SWN EA Q5 8 PGND 9 AIC1533 PIN DESCRIPTIONS PIN 1: ADJ - Providing VADJ=1.25V (typ.) for adjustable VOUT. PIN 2: OUT - Adjustable output. PIN 3: FBP - Positive charge pump feedback input. Regulates to 1.25V typical. PIN 4: SHDN - Active-Low logic level shutdown input. Connecting SHDN to VCC for typical operation. PIN 5: VCC - Supply input. PIN 6: SUPP - Positive charge pump supply pin. It monitors negative charge pump. LDO The capacitor on this pin sets negative charge pump to provide independent time control. Or TN connects to high level directly if it is not in use for programming delay time. regulator PIN 7: SWP - Positive charge pump driver output. Output high level is VCC, and low level is GND. PIN 8: PGND - Power ground. Connecting to GND. PIN 9: SWN - Negative charge pump driver output. Output high level is VCC, and low level is GND. PIN 10: TN - Programmable delay time pin. PIN 11: TP - Programmable delay time pin. The capacitor on this pin sets positive charge pump to provide independent time control. Or TP connects to high level directly if it is not in use for programming delay time. PIN 12: FBN - Negative charge pump feedback input. Regulates to 0V typical. PIN 13: VREF - Internal reference bypass terminal. Connecting a 0.22µF capacitor to ground. Providing a positive voltage greater than negative feedback voltage to obtain a positive voltage for FBN. PIN 14: GND - Ground. Tie GND pin directly to local ground plane to obtain best performance. APPLICATION INFORMATION an adjustable start-up delay time. In shutdown Introduction AIC1533 is composed of dual charge pumps and a regulator to provide three independent regulated voltages exclusively designed for thin-film transistor (TFT) liquid crystal display (LCD) applications. LDO regulator has an adjustable output voltage with a low dropout voltage of 500mV at 300mA load current. Two independent charge pumps regulate a positive output and a negative output by using a 1MHz switching frequency, and a pulse-width-modulation (PWM) architecture. AIC1533 provides a start-up sequence function with mode, it only consumes 0.1µA supply current. AIC1533 also features an internal current limit and thermal shutdown protection. Operation As Fig. 16 shows, two internal MOSFETs - Q2, Q3, and external components comprise a positive charge pump, whose output is three times as much as input voltage. After delay time, which determined by CP, Q1 turns on. During on state, which indicates Q2 is at off stage and Q3 at on stage, CFLY1 connects VCC and PGND and is charged by VCC. 10 AIC1533 During off state, Q2 at on stage and Q3 off stage, voltage of C2 is the addition of VCC and VCFLY1. And then go back to on state with voltage of CFLY2 AIC1533 VCC D3 equal to VC2, which is twice as much voltage as VCC. Lastly, the system goes to off state, voltage of SWN Q4 CFLY3 Co1 is the addition of VCC and CFLY2, that is, three times as much voltage as VCC. - 3 Q5 FBN 2 Fig.17 shows the structure of a negative charge R5 C5 Co2 + R6 VREF pump. During on state, which represents Q4 at on stage and Q5 at off stage, voltage of CFLY3 is equal Vn 1 PGND C4 to VCC. During off state, indicating Q4 at off stage and Q5 on stage, SWN pin connects to PGND Fig. 17 Structure of Negative Charge Pump directly, and voltage of Co2 equals to -VCC. AIC1533 12VIN VCC Q1 Power-Up Sequence And Adjustable Delay Time For thin-film transistor (TFT) liquid crystal display 1 SUPP D1 Q2 CFLY1 C1 3 2 SWP Q3 FBP C2 PGND 3 voltages is required. Fig. 3 indicates the power-up sequence of AIC1533. After shutdown exit delay time, output of LDO starts rising. When it reaches to D2 1 applications, power-up sequence of three output CFLY2 2 90% of normal voltage, which is determined by an external resistor divider, CN starts being charged from 5µA current source (referring to BLOCK DIAGRAM). The charging time of CN, defined as T1, Vp + Co1 R1 - can be calculated as R2 C3 Fig.16 Structure of Positive Charge Pump T1 = Cn × VTH,n In (1) where VTH,η = negative threshold voltage, 1.25V, In = negative bias current, 5µA Afterwards, while negative output voltage starts decreasing from 0V, VFBN decreases from 1.1V to 0V proportionally. As VFBN decreases to 10% of VREF, Q7 turns off and Cp starts being charged from 5µA current source (referring to BLOCK DIAGRAM). The charging time of CP, defined as T2, can be calculated as 11 AIC1533 T2 = Cp × VTH,P (2) IP Shutdown AIC1533 shuts off all devices and consumes only where VTH,P = positive threshold voltage, 1.25V IP= positive bias current, 5µA 0.1µA supple current when SHDN gets lower than 0.6V. This pin can be pulled high to 2.4V for normal operation. Due to high impedance of SHDN pin, it can’t be floating. Current Limit And Thermal Protection To protect devices from damage caused by short circuit, AIC1533 provides current limit and thermal protection. When short circuit occurs, output current is clamped at the current limit. Due to power dissipation of LDO is defined as PDISSIPATION = IOUT * (VIN-VOUT) (3) Under short circuit condition, the temperature rising, which is caused by power dissipation, gets to thermal shutdown temperature and shuts AIC1533 down. As the temperature gets lower than the thermal shutdown temperature, the device will Components Selection 1. Determining The Number Of Charge Pump Stages The number of charge pump stages to regulate is determined by output voltage, supply voltage, switching frequency, load current, forward voltage of diodes, on-resistor of internal MOSFET, and value of ceramic capacitor. resume. The pattern of temperature of the device For positive charge pump, the number of required recycles until the short circuit condition is removed. stages can be calculated as The waveform under short circuit condition is shown NPOS ≥ as Fig.18. VPOS − Vcc + R TH × Iout Vcc − 2VD (4) where VPOS = output of positive charge pump IOUT RTH = equivalent output impedance of charge pump Current VD Limit = forward voltage of diodes Vcc = input voltage Thermal Shutdown The following equation approximates RTH RTH = VOUT 2(R DS,ON(P ) + R DS,ON(N) ) + ( 1 1 ) )+( CO × FSW CFLY × FSW (5) Fig.18 Current Limit Waveform of AIC1533 where RDS, ON(P) is on-resistor of internal P-channel MOSFET, RDS, ON(N) means on-resistor of internal N-channel MOSFET, and FSW is switching frequency of AIC1533 (referring to ELECTRIVAL CHARACTERISTICS). 12 AIC1533 For negative charge pump, the number of negative VLDO = VADJ × (1 + charge pump can be determined by NNEG ≥ R TH × Iout − VNEG Vcc − 2VD (6) R3 ) R4 (10) where VLDO = output voltage of LDO VADJ = adjustable voltage of LDO, the where VNEG = output of negative charge pump recommended R4 is 130kΩ. Example To obtain VPOS=28V/30mA, VNEG=-9V/30mA from 2.2. Output Voltage Of Positive Charge Pump VCC=12V, CFLY=0.1µF, the number of positive and Output negative charge pumps can be calculated as determined by connecting a resistor divider to follows output terminal of positive charge pump, GND, and RTH FBP = 2(R DS,ON(P ) + R DS,ON(N) ) + ( = 2(10 + 10) + ( 1 1 )+( ) C FLY × FSW C O × FSW 1 0.1× 10 −6 × 1× 10 6 )+( 1 1× 10 −6 =51 × 1× 10 6 ) (7) voltage of (referred to positive charge TYPICAL pump is APPLICATION CIRCUIT). The values of resistor divider can be calculated as equation (11). VPOS = VFBP × (1 + R1 ) R2 (11) where VPOS = output voltage of positive charge pump VFBP = feedback voltage of positive charge pump, NPOS ≥ VPOS − Vcc + R TH × Iout 28 − 12 + (51 × 30 × 10 −3 ) = Vcc − 2VD 12 − 2 × 0.5 = 1.59 (8) NNEG R × Iout − VNEG (51 × 30 × 10 −3 ) − ( −9) ≥ TH = Vcc − 2VD 12 − 2 × 0.5 1.25V. The recommended R2 is 22kΩ 2.3 Output voltage of negative charge pump Since comparator input of negative charge pump, FBN, is referenced to 0V, a positive reference (9) = 0.96 Thus, the number of positive charge pump is two, and the negative one requires one charge pump. 2. Output Voltage Selection 2.1 Output voltage of LDO A resistor divider, determining output voltage of LDO, connects to OUT, GND, and ADJ (referred to voltage, which can be obtained by adding a 0.22µF bypass capacitor between VREF and GND, is needed (referred to TYPICAL APPLICATION CIRCUIT). The value of resistor dividers can be calculated as equation (12). VNEG = − VREF × R5 R6 (12) where VNEG represents output voltage of negative charge pump, and VREF means reference voltage, 1.25V. The recommended R6 is 33kΩ. TYPICAL APPLICATION CIRCUIT). Values of resistors can be calculated by equation (10). 13 AIC1533 3. Flying Capacitor Selection maintain stability. The recommended values for A flying capacitor plays an important role in charge pump strength. Increase of flying capacitor value results in a rise of output capability with smaller ripple voltage. Normal voltage of flying capacitor must comply with the following conditions, as both input and output capacitors are 10µF. Because of the material, X5R or X7R, ceramic capacitor has low ESR and excellent electrical characteristics in over temperature. That makes ceramic capacitor suitable for output and input capacitors of AIC1533. equation (13). 4.2 Charge Pump VCFLY (POS) = VCFLY (NEG) >1.5 x [VCC x (N)] .....(13) A ceramic capacitor of a value, which is 10 times of Where VCFLY(POS) is the normal voltage of positive flying capacitor, is suitable for the output capacitor charge VCFLY(NEG) of charge pump. In order to maintain a stable output represents the normal voltage of negative charge voltage, make sure to place the capacitor as close pump flying capacitor, and N means the number of to IC as possible. pump flying capacitor, charge pump stages Besides, ceramic capacitors composed by different 5. Rectifier Diode Selection materials, such as X7R, X5R, Z5U and Y5V, have A Schottky diode with a current rating equal to or different tolerance in temperature, and result in greater than two times of average charge pump different capacitance loss. A capacitor, which is input current, and a voltage rating at least 1.5 times made of X7R or X5R, is recommended for AIC1533 of VCC, is recommended. applications. Table 1 indicates the recommended components for AIC1533 applications. 4. Input-Output Capacitor Selection 4.1 LDO AIC1533 needs input and output capacitors to Table.1 Bill of Materials List Designator Part Type CIN 10µF/16V CFLY1 Vender Phone Ceramic capacitor, EMK325BJ106MN-B Taiyo Yuden 02-27972155-314 0.1µF/50V Ceramic capacitor, UMK212BJ104KG Taiyo Yuden 02-27972155-314 CFLY2 0.1µF/50V Ceramic capacitor, UMK212BJ104KG Taiyo Yuden 02-27972155-314 CFLY3 0.1µF/16V Ceramic capacitor, EMK107BJ104KA Taiyo Yuden 02-27972155-314 CO1 1µF/50V Ceramic capacitor, UMK212F105ZG Taiyo Yuden 02-27972155-314 CO2 1µF/16V Ceramic capacitor, EMK212F105KG Taiyo Yuden 02-27972155-314 CO3 10µF/16V Ceramic capacitor, EMK325BJ106MN-B Taiyo Yuden 02-27972155-314 D1~D3 BAT54SW Surface mount Schottky barrier diode U1 AIC1533 Description Triple Adjustable Output DC/DC Converter with a LDO WTE 07-8225408 AIC 03-5772500 14 AIC1533 Layout Consideration Due to the switching frequency of AIC1533, careful of trace for best performance. Make sure each PCB layout is necessary. Place components as device connect to its immediate ground plane. Fig close to one another as possible and maintain each 19, 20 and 21 represent recommended layouts. connection of minimum length and maximum width Fig. 19 Top Layer Fig. 20 Bottom Layer Fig. 21 Top-over Layer 15 AIC1533 PHYSICAL DIMENSIONS (unit: mm) SOP-14 D A A e MIN. MAX. 1.35 1.75 0.10 0.25 0.33 0.51 C 0.19 0.25 D 8.55 8.75 E 3.80 4.00 e h X 45° A A1 B SEE VIEW B A1 B 1.27 BSC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0° 8° WITH PLATING C θ 0.25 BASE METAL SECTION A-A GAUGE PLANE SEATING PLANE θ L VIEW B SOP-14 MILLIMETERS A H E S Y M B O L TSSOP-16 D S Y M B O L TSSOP-16 MILLIMETERS MAX. MIN. e/2 e A E E1 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 E A SEE VIEW B E1 4.30 A A2 e L A1 θ 5.10 6.40 BSC 4.50 0.65 BSC 0.45 0.75 0° 8° b c WITH PLATING 0.25 BASE METAL SECTION A-A GAUGE PLANE SEATING PLANE VIEW B θ L 16 AIC1533 Note: Information provided by AIC is believed to be accurate and reliable. However, we cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AIC product; nor for any infringement of patents or other rights of third parties that may result from its use. We reserve the right to change the circuitry and specifications without notice. Life Support Policy: AIC does not authorize any AIC product for use in life support devices and/or systems. Life support devices or systems are devices or systems which, (I) are intended for surgical implant into the body or (ii) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 17